Texas Instruments | TLV62085 High Efficiency 3-A Step-Down Converter in 2-mm × 2-mm VSON Package (Rev. B) | Datasheet | Texas Instruments TLV62085 High Efficiency 3-A Step-Down Converter in 2-mm × 2-mm VSON Package (Rev. B) Datasheet

Texas Instruments TLV62085 High Efficiency 3-A Step-Down Converter in 2-mm × 2-mm VSON Package (Rev. B) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
TLV62085 High Efficiency 3-A Step-Down Converter in 2-mm × 2-mm VSON Package
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TLV62085 device is a high-frequency
synchronous step-down converter optimized for small
solution size and high efficiency. With an input
voltage range of 2.5 V to 6.0 V, common battery
technologies are supported. The devices focus on
high-efficiency step-down conversion over a wide
output current range. At medium to heavy loads, the
converter operates in PWM mode and automatically
enters Power Save Mode operation at light load to
maintain high efficiency over the entire load current
range.
1
DCS-Control™ Topology
Up to 95% Efficiency
17-μA Operating Quiescent Current
31mΩ and 23mΩ Power MOSFET Switch
2.5-V to 6.0-V Input Voltage Range
0.8-V to VIN Adjustable Output Voltage
Power Save Mode for Light Load Efficiency
100% Duty Cycle for Lowest Dropout
Hiccup Short-Circuit Protection
Output Discharge
Power Good Output
Thermal Shutdown Protection
Available in 2-mm × 2-mm VSON Package
For Improved Feature Set, See TPS62085
Create a Custom Design using the TLV62085 with
the WEBENCH® Power Designer
To address the requirements of system power rails,
the internal compensation circuit allows a large
selection of external output capacitor values ranging
from 10 µF to 150 µF and above. Together with its
DCS-Control™ architecture, excellent load transient
performance and output voltage regulation accuracy
are achieved. The device is available in a 2-mm × 2mm VSON package.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
TLV62085
Battery-Powered Applications
Point-of-Load
Processor Supplies
Hard Disk Drives (HDD) / Solid State Drives
(SSD)
PACKAGE
VSON (7)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
spacer
spacer
Typical Application Schematic
TLV62085
VIN
2.5V to 6V C1
10µF
VIN
SW
EN
VOS
Efficiency at VIN = 5 V
L1
0.47µH
R1
138k
R3
1M
C2
22µF
100
VOUT
1.8V
FB
PG
90
R2
110k
POWER GOOD
Efficiency (%)
GND
80
70
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
60
1m
10m
100m
Load (A)
1
5
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
6
6
7
8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations ........................................ 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Development Support ...........................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision A (January 2017) to Revision B
•
Page
Added Figure 3 to power save mode section......................................................................................................................... 7
Changes from Original (October 2015) to Revision A
Page
•
Added WEBENCH™ information and hyperlinks to Features, Detailed Design Procedure, and Device Support sections .. 1
•
Added SW (AC) to the Absolute Maximum Rating table ....................................................................................................... 4
•
Added Table 1, PG Pin Logic ................................................................................................................................................. 8
2
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
5 Pin Configuration and Functions
RLT Package
7-Pin VSON
Top View
EN
1
PG
2
FB
3
VOS
4
7
VIN
6
SW
5
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
IN
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the
device. This pin has a pulldown resistor of typically 400 kΩ when the device is disabled.
FB
3
IN
Feedback pin. Connect a resistor divider to set the output voltage.
GND
5
PG
2
OUT
Power good open drain output pin. The pullup resistor can not be connected to any voltage higher than 6 V. If
unused, leave it floating.
SW
6
PWR
Switch pin of the power stage.
VIN
7
PWR
Input voltage pin.
VOS
4
IN
Ground pin.
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
3
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
Voltage at Pins (2)
Temperature
(1)
(2)
(3)
MIN
MAX
VIN, FB, VOS, EN, PG
– 0.3
7
SW (DC)
UNIT
– 0.3
VIN + 0.3
SW (AC, less than 100ns) (3)
–3
11
V
Operating Junction, TJ
– 40
150
°C
Storage, Tstg
– 65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
While switching.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
MIN
NOM
MAX
VIN
Input voltage range
2.5
6
VOUT
Output voltage range
0.8
VIN
UNIT
V
V
ISINK_PG Sink current at PG pin
1
mA
VPG
Pullup resistor voltage
6
V
TJ
Operating junction temperature
125
°C
(1)
–40
Refer to Application and Implementation for further information.
6.4 Thermal Information
TLV62085
THERMAL METRIC (1)
RLT [VSON]
UNIT
7 PINS
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.2
°C/W
RθJB
Junction-to-board thermal resistance
17.1
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
6.5
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
Electrical Characteristics
TJ = 25 °C, and VIN = 3.6 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN
No load, device not switching
17
ISD
Shutdown current into VIN
EN = Low
0.7
Under voltage lock out threshold
VIN falling
Under voltage lock out hysteresis
VIN rising
200
mV
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
VUVLO
TJSD
2.1
2.2
µA
µA
2.3
V
LOGIC INTERFACE EN
VIH
High-level input voltage
VIN = 2.5 V to 6.0 V
VIL
Low-level input voltage
VIN = 2.5 V to 6.0 V
1.0
V
IEN,LKG
Input leakage current into EN pin
EN = High
0.01
µA
RPD
Pull-down resistance at EN pin
EN = Low
400
kΩ
Time from EN high to 95% of VOUT nominal
0.8
ms
0.4
V
SOFT START, POWER GOOD
tSS
Soft start time
VPG
Power good threshold
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
VFB
Feedback regulation voltage
PWM mode, 2.5 V ≤ VIN ≤ 6 V
TJ = 0°C to 85 °C
IFB,LKG
Feedback input leakage current
VFB = 1 V
0.01
µA
RDIS
Output discharge resistor
EN = LOW, VOUT = 1.8 V
260
Ω
mΩ
VOUT rising, referenced to VOUT nominal
95%
VOUT falling, referenced to VOUT nominal
90%
0.4
0.01
V
µA
OUTPUT
792
800
808
mV
POWER SWITCH
RDS(on)
High-side FET on-resistance
ISW = 500 mA
31
Low-side FET on-resistance
ISW = 500 mA
23
ILIM
High-side FET switch current limit
fSW
PWM switching frequency
3.7
IOUT = 1 A
4.6
mΩ
5.5
2.4
A
MHz
6.6 Typical Characteristics
Switching Frequency (Hz)
5x106
106
105
104
103
1m
VIN = 2.5 V
VIN = 3.6 V
VIN = 6.0 V
10m
100m
Load (A)
1
5
D007
VOUT = 1.2 V
Figure 1. Switching Frequency
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
5
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TLV62085 synchronous step-down converter is based on the DCS-Control (Direct Control with Seamless
transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic, voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC's
current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. The device offers both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
7.2 Functional Block Diagram
PG
Hiccup
Counter
VFB
VREF
EN
400kΩ
(1)
VIN
High Side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
SW
MOSFET Driver
Control Logic
GND
Ramp
Direct Control
and
Compensation
Comparator
Timer
ton
VOS
FB
VREF
Error Amplifier
DCS - Control
TM
EN
260Ω
Output Discharge
Logic
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
Figure 2. Functional Block Diagram
6
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
7.3 Feature Description
7.3.1 Power Save Mode
As the load current decreases, the TLV62085 enters Power Save Mode (PSM) operation. During Power Save
Mode, the converter operates with reduced switching frequency and with a minimum quiescent current
maintaining high efficiency. Power Save Mode occurs when the inductor current becomes discontinuous. Power
Save Mode is based on a fixed on-time architecture, as related in Equation 1. The switching frequency over the
whole load current range is also shown in Figure 1 for a shown typical application.
V
t ON = 420 ns ´ OUT
VIN
fPFM =
t ON2
2 ´ IOUT
V - VOUT
VIN
´
´ IN
VOUT
L
(1)
In PSM, the output voltage rises slightly above the nominal output voltage, as shown in Figure 10. This effect is
minimized by increasing the output capacitor or inductor value.
During PAUSE period in PSM (shown in Figure 3), the device does not change the PG pin state nor does it
detect an UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light
loads.
VOUT
tPAUSE
IINDUCTOR
tON
Figure 3. Power Save Mode Waveform Diagram
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )
with
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
(2)
7.3.3 Soft Start
The TLV62085 has an internal soft-start circuitry which monotonically ramps up the output voltage and reaches
the nominal output voltage during a soft-start time of typically 0.8 ms. This avoids excessive inrush current and
creates a smooth output voltage slope. It also prevents excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance. The device is able to start into a prebiased output capacitor.
The device starts with the applied bias voltage and ramps the output voltage to its nominal value.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
7
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
Feature Description (continued)
7.3.4 Switch Current Limit and Hiccup Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET is turned on to ramp down the inductor current. When this switch current
limits is triggered 32 times, the device stops switching and enables the output discharge. The device then
automatically starts a new start-up after a typical delay time of 66 µs has passed. This is named HICCUP shortcircuit protection. The device repeats this mode until the high load condition disappears.
7.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 200 mV.
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 260 Ω discharges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, UVLO, or short-circuit protection are triggered.
An internal pulldown resistor of 400 kΩ is connected to the EN pin when the EN pin is LOW. The pulldown
resistor is disconnected when the EN pin is HIGH.
7.4.2 Power Good
The TLV62085 has a power good output. The power good goes high impedance once the output is above 95%
of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 1 shows
the PG pin logic.
Table 1. PG Pin Logic
DEVICE CONDITIONS
EN = High, VFB ≥ VPG
Enable
LOGIC STATUS
HIGH Z
LOW
√
EN = High, VFB ≤ VPG
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
0.5 V < VIN < VUVLO
Power Supply Removal
VIN ≤ 0.5 V
8
√
√
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62085 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using the typical applications as a reference.
8.2 Typical Application
TLV62085
VIN
2.5V to 6V C1
10µF
L1
0.47µH
SW
VIN
VOS
EN
R1
138k
R3
1M
C2
22µF
VOUT
1.8V
FB
GND
PG
R2
110k
POWER GOOD
Figure 4. 1.8-V Output Voltage Application
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 6 V
Output voltage
1.8 V
Output current
≤3A
Output ripple voltage
<30 mV
Table 3 lists the components used for the example.
Table 3. List of Components (1)
REFERENCE
(1)
DESCRIPTION
MANUFACTURER
C1
10 µF, Ceramic capacitor, 10 V, X7R, size 0805, GRM21BR71A106ME51L
Murata
C2
22 µF, Ceramic capacitor, 6.3 V, X5R, size 0805, GRM21BR60J226ME39L
Murata
L1
0.47 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4015-471ME
Coilcraft
R1
Depending on the output voltage, 1%, size 0603;
Std
R2
110 kΩ, Chip resistor, 1/16 W, 1%, size 0603;
Std
R3
1 MΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
See Third-Party Products discalimer.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
9
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TLV62085 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to Equation 3:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
÷ = 0.8 V ´ ç 1 + R2 ÷
è R2 ø
è
ø
(3)
R2 must not be higher than 180 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.
8.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process,
Table 4 outlines possible inductor and capacitor value combinations for most applications.
Table 4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL L [µH] (1)
NOMINAL COUT [µF] (2)
10
0.47
1
+
22
47
100
150
+ (3)
+
+
+
+
+
+
+
2.2
(1)
(2)
(3)
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and
–30%.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by
20% and –50%.
Typical application configuration. Other '+' mark indicates recommended filter combinations.
8.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 4 is given.
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where
•
•
10
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
•
•
fSW = Switching frequency
L = Inductor value
(4)
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of
Equation 4. A higher inductor value is also useful to lower ripple current but increases the transient response
time as well. The following inductors are recommended to be used in designs.
Table 5. List of Recommended Inductors (1)
(1)
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
L × W × H [mm3]
DC RESISTANCE
[mΩ typical]
0.47
0.47
6.6
4 × 4 × 1.5
7.6
Coilcraft XFL4015-471
4.7
3.2 × 2.5 × 1.2
21
TOKO DFE322512-R47N
1
5.1
4×4×2
10.8
Coilcraft XFL4020-102
PART NUMBER
See Third-Party Products disclaimer.
8.2.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those pins. For most applications, 10 μF is sufficient, though a larger value
reduces input current ripple.
The architecture of the TLV62085 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF; this capacitance can
vary over a wide range as outline in the output filter selection table. Output capacitors above 150uF may be used
with a reduced load current during startup to avoid triggering the short circuit protection.
A feed-forward capacitor is not required for device proper operation.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
11
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
8.2.3 Application Curves
100
100
90
90
Efficiency (%)
Efficiency (%)
VIN = 3.6 V, TA = 25 ºC, unless otherwise noted
80
70
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
10m
100m
Load (A)
1
80
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
5
10m
VOUT = 0.95 V
90
90
Efficiency (%)
100
80
70
D002
80
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
10m
100m
Load (A)
1
60
1m
5
10m
100m
Load (A)
D003
VOUT = 3.3 V
1
5
D004
VOUT = 1.8 V
Figure 7. Efficiency
Figure 8. Efficiency
1.212
1.212
1.206
1.206
Output Voltage (V)
Output Voltage (V)
5
Figure 6. Efficiency
100
60
1m
1
VOUT = 1.2 V
Figure 5. Efficiency
Efficiency (%)
100m
Load (A)
D001
1.200
1.194
1.200
1.194
TA = -40°C
TA = 25°C
TA = 85°C
1.188
2.5
3.0
3.5
TA = -40°C
TA = 25°C
TA = 85°C
4.0
4.5
Input Voltage (V)
5.0
5.5
6.0
1.188
1m
D005
10m
100m
Load (A)
1
5
D006
IOUT = 1 A
Figure 9. Line Regulation
12
Figure 10. Load Regulation
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
t -- 500ns/div
t -- 300ns/div
Vout (AC, 20mV/div)
Vout (AC, 20mV/div)
Icoil (DC, 1A/div)
Icoil (DC, 1A/div)
SW (DC, 5V/div)
SW (DC, 5V/div)
IOUT = 3 A
VOUT = 1.2 V
IOUT = 0.1 A
Figure 11. PWM Operation
VOUT = 1.2 V
Figure 12. PFM Operation
t -- 200μs/div
Load (DC, 2A/div)
t -- 200μs/div
EN (DC, 5V/div)
Vout (AC, 50mV/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
IOUT = 0 A to 3 A
VOUT = 1.2 V
ROUT = 0.47 Ω
Figure 13. Load Sweep
VOUT = 1.2 V
Figure 14. Start-Up with Load
t -- 200μs/div
t -- 5μs/div
EN (DC, 5V/div)
EN (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 0.5A/div)
VOUT = 1.2 V
ROUT = 0.47 Ω
Figure 15. Start-Up without Load
VOUT = 1.2 V
Figure 16. Shutdown with Load
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
13
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
t -- 5ms/div
EN (DC, 5V/div)
t -- 2μs/div
Load (DC, 2A/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 0.5A/div)
Icoil (DC, 2A/div)
VOUT = 1.2 V
IOUT = 0.5 A to 3 A
Figure 17. Shutdown without Load
VOUT = 1.2 V
Figure 18. Load Transient
t -- 3μs/div
Load (DC, 2A/div)
t -- 200μs/div
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
IOUT = 50mA to 3A
VOUT = 1.2 V
ROUT = 0.47 Ω
Figure 19. Load Transient
VOUT = 1.2 V
Figure 20. Output Short-Circuit Protection, Entry
t -- 200μs/div
ROUT = 0.47 Ω
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
VOUT = 1.2 V
ROUT = 0.47 Ω
Figure 21. Output Short-Circuit Protection, Recovery
14
t -- 5μs/div
PG (DC, 5V/div)
VOUT = 1.2 V
Figure 22. Output Short-Circuit Protection,
HICCUP Zoom In
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 6 V. Ensure that the input
power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TLV62085
device.
The input and output capacitors and the inductor must be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
The low side of the input and output capacitors must be connected directly to the GND pin to avoid a ground
potential shift. The sense traces connected to FB and VOS pins are signal traces. Special care must be taken to
avoid noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used
for shielding. Keep these traces away from SW nodes. See Figure 23 for the recommended PCB layout.
10.2 Layout Example
L1
VOUT
VIN
C1
GND
VOS
SW
FB
EN
VIN
C2
PG
Solution Size
2
62 mm
GND
R2
R1
Figure 23. PCB Layout Recommendation
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
The big copper planes connecting to the pads of the IC on the PCB improve the thermal performance of the
device. For more details on how to use the thermal parameters, see the Thermal Characteristics Application
Notes, SZZA017 and SPRA953.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
15
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
www.ti.com
11 Device and Documentation Support
11.1 Development Support
11.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TLV62085 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Thermal Characteristics Application Note, SZZA017
• Thermal Characteristics Application Note, SPRA953
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
DCS-Control, WEBENCH, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
16
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
TLV62085
www.ti.com
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TLV62085
17
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV62085RLTR
ACTIVE
VSON-HR
RLT
7
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12Q5
TLV62085RLTT
ACTIVE
VSON-HR
RLT
7
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
12Q5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV62085RLTR
VSONHR
RLT
7
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV62085RLTT
VSONHR
RLT
7
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV62085RLTR
VSON-HR
RLT
7
3000
182.0
182.0
20.0
TLV62085RLTT
VSON-HR
RLT
7
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
1
PIN 1
INDEX AREA
2.1
1.9
C
1 MAX
0.08
SEATING PLANE
0.05
0.00
3X 0.5
0.3
(0.2) TYP
(0.2) TYP
3X 0.5
4
5
1.2
1.5
4X 0.3
0.2
0.1
0.05
C A
C
2X 0.6
7
1
3X 1.4
1.2
B
0.5
0.3
PIN 1 ID
3X 0.35
0.25
0.1
0.05
C A
C
B
4220429/A 09/2014
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
℄
(0.6)
1
(0.25)
7
2X (0.6)
PKG
℄
3X (0.5)
3X (0.25)
5
4
3X (0.3)
3X (1.5)
3X (0.6)
(0.9)
(0.45)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
PADS 1 - 4
SOLDER MASK
DEFINED
PADS 5 - 7
SOLDER MASK DETAILS
NOTES: (continued)
3.
4.
5.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias should not be placed on soldering pads unless they are plugged or plated shut.
www.ti.com
4220429/A 09/2014
EXAMPLE STENCIL DESIGN
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
6X (0.65)
℄
(0.6)
(0.21)
1
7
EXPOSED METAL
TYP
2X (0.6)
PKG
℄
3X (0.5)
METAL UNDER
SOLDER MASK
TYP
3X (0.21)
6X (0.3)
4
5
3X (0.025)
3X (0.6)
(0.9)
(0.875)
3X
EXPOSED METAL
SOLDER MASK EDGE
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR ALL EXPOSED PADS
85% PRINTED SOLDER COVERAGE BY AREA
SCALE: 40X
4220429/A 09/2014
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising