Texas Instruments | TPS7A63-Q1, TPS7A6401-Q1 300-mA, 40-V, Low-Dropout Regulator With Ultra-Low IQ (Rev. F) | Datasheet | Texas Instruments TPS7A63-Q1, TPS7A6401-Q1 300-mA, 40-V, Low-Dropout Regulator With Ultra-Low IQ (Rev. F) Datasheet

Texas Instruments TPS7A63-Q1, TPS7A6401-Q1 300-mA, 40-V, Low-Dropout Regulator With Ultra-Low IQ (Rev. F) Datasheet
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TPS7A63-Q1, TPS7A6401-Q1
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
TPS7A63-Q1, TPS7A6401-Q1
300-mA, 40-V, Low-Dropout Regulator With Ultra-Low IQ
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C2
Low Dropout Voltage
– 300 mV at IOUT = 150 mA
11-V to 40-V Wide Input-Voltage Range
With up to 45-V Transients
300-mA Maximum Output Current
Ultralow Quiescent Current
– IQUIESCENT = 35 µA (Typical) at Light Loads
– ISLEEP < 2 µA When EN = Low
Fixed (3.3-V and 5-V) and Adjustable (2.5-V to
7-V) Output Voltages
Integrated Watchdog With Fault/Flag
Stable With Low-ESR Ceramic Output Capacitor
Integrated Power-On Reset
– Programmable Delay
– Open-Drain Reset Output
Integrated Fault Protection
– Short-Circuit and Overcurrent Protection
– Thermal Shutdown
Low Input-Voltage Tracking
Thermally Enhanced 14-Pin HTSSOP-PWP
Package and 10-Pin VSON-DRK Package
Infotainment Systems With Sleep Mode
Body Control Modules
Always-On Battery Applications
– Gateway Applications
– Remote Keyless Entry Systems
– Immobilizers
3 Description
The TPS7A63-Q1 and TPS7A6401-Q1 are a family of
low-dropout linear voltage regulators designed for low
power consumption and quiescent current less than
35 µA in light-load applications. These devices,
designed to achieve stable operation even with a lowESR ceramic output capacitor, feature an integrated
programmable window watchdog and overcurrent
protection. Designers can program the output voltage
using external resistors. A low-voltage tracking
feature allows for a smaller input capacitor and can
possibly eliminate the need of using a boost
converter during cold-crank conditions. The poweron-reset delay is fixed (250 µs typical), or an external
capacitor can program the delay. Because of such
features, these devices are well-suited in power
supplies for various automotive applications.
Device Information(1)
PART NUMBER
VIN
CIN
5.00 mm × 4.40 mm
TPS7A63-Q1
VSON (10)
4.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Adjustable Output Voltage Option
TPS7A6x01-Q1
TPS7A6333-Q1
VOUT
or
TPS7A6350-Q1
RDELAY
VOUT
COUT
VIN
VOUT
VIN
CIN
VOUT
COUT
R1
FB
RDELAY
RRST
CDLY
ROSC
RRST
R2
CDLY
ROSC
ROSC
RESET
nRST
ROSC
GND
nWD_EN
WD_FLT/
WD_FLG
WD
RESET
nRST
RFLT/FLAG
EN
BODY SIZE (NOM)
HTSSOP (14)
Fixed Output Voltage Option
VIN
PACKAGE
TPS7A63-Q1,
TPS7A6401-Q1
RFLT/FLAG
FAULT/
FLAG
GND
EN
nWD_EN
WD_FLT/
WD_FLG
WD
FAULT/
FLAG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A63-Q1, TPS7A6401-Q1
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagrams ..................................... 10
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ............................................... 21
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2015) to Revision F
Page
•
Changed device names to TPS7A63-Q1 TPS7A6401-Q1..................................................................................................... 1
•
Changed 4 V to 11 V in fourth Features bullet ...................................................................................................................... 1
•
Changed VIN, VEN parameter row in Recommended Operating Conditions table: separated VIN and VEN into different
rows, changed VIN minimum specification from 4 V to 11 V .................................................................................................. 5
•
Changed VIN minimum specification from VOUT + 0.3 V to 11 V in Electrical Characteristics table ....................................... 6
•
Changed 4 V to 11 V in Example values column of Input voltage range row of Design Parameters table ......................... 22
•
Changed 4 V to 11 V in Example values column of Input voltage range row of Design Parameters table ........................ 23
•
Changed 4 V to 11 V in first sentence of Power Supply Recommendations section .......................................................... 24
Changes from Revision D (July 2012) to Revision E
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
Changes from Revision C (April 2012) to Revision D
Page
•
Added new bullets at top of Features list ............................................................................................................................... 1
•
Corrected part number in numerous locations throughout the data sheet ............................................................................. 1
•
Deleted the NO. column from the electrical tables ................................................................................................................. 5
•
Deleted two Typical Characteristics graphs ........................................................................................................................... 8
Changes from Revision B (December 2011) to Revision C
•
2
Page
Changed regulated output voltage (6.1), added text to the test conditions (10mA to 200mA, VIN = VOUT + 1V to 16V) ....... 6
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Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
TPS7A63-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
Changes from Revision A (August 2011) to Revision B
•
Page
Deleted devices TPS7A64333-Q1 and TPSA6450-Q1 .......................................................................................................... 1
Changes from Original (June 2011) to Revision A
Page
•
Deleted the Ordering Information Table ................................................................................................................................. 4
•
Changed values for VIL and VIH in the Watchdog Enable Input (nWD_EN pin) section......................................................... 7
•
Changed values for VIL and VIH in the Watchdog Input Pulse (WD pin) section.................................................................... 7
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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3
TPS7A63-Q1, TPS7A6401-Q1
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
www.ti.com
5 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP With PowerPAD IC Package
Top View (Fixed Output Voltage Option)
VIN
nRST
NC
GND
EN
RDELAY
VOUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PWP Package
14-Pin HTSSOP With PowerPAD IC Package
Top View (Adjustable Output Voltage Option)
ROSC
NC
nWD_EN
NC
WD
WD_FLT/FLAG
NC
VIN
nRST
FB
GND
EN
RDELAY
VOUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ROSC
NC
nWD_EN
NC
WD
WD_FLT/FLAG
NC
DRK Package
10-Pin VSON With Exposed Thermal Pad
Top View (Fixed Output Voltage Option)
VIN
1
10
ROSC
nRST
2
9
nWD_EN
GND
3
8
RDELAY
EN
4
7
WD
VOUT
5
6
WD_FLT
Pin Functions
PIN
NAME
PWP
DRK
EN
5
4
FB
3
GND
4
NC
I/O
DESCRIPTION
I
Chip enable pin: This is a high-voltage-tolerant input pin with an internal pulldown. A high input to this pin
activates the device and turns the regulator ON. Connect this input to the VIN terminal for self-bias applications.
If this pin remains unconnected, the device stays disabled.
—
I
Feedback pin (only applicable for TPS7A6x01-Q1): Sense voltage for error amplifier
3
I/O
Ground pin: This is signal ground pin of the device.
3
—
—
Not connected (only applicable for TPS7A6333-Q1 and TPS7A6350-Q1)
NC
8
—
—
Not connected
NC
11
—
—
Not connected
NC
13
—
—
Not connected
nRST
2
2
O
Reset pin: This is an open-drain reset output pin with an external pullup resistor connected to the VOUT pin.
nWD_EN
12
9
I
Watchdog enable pin: A high input to this pin disables the watchdog, and vice versa. This is an active-low input
pin with an internal pulldown. Leaving this pin is unconnected and floating keeps the watchdog enabled. An
external microcontroller can pull this pin high momentarily to disable and reinitialize the watchdog.
RDELAY
6
8
O
Reset delay timer pin: This pin programs the reset delay timer using an external capacitor (CDLY) to ground.
ROSC
14
10
O
ROscillator pin: This pin programs the internal oscillator frequency (and hence the duration of the watchdog
window) by connecting an external resistor to ground.
WD
10
7
I
Watchdog service pin: This is an input pin to provide a service signal to the watchdog.
WD_FLAG
9
6
O
Watchdog flag pin (for TPS7A6401-Q1 only): This is an active-high latched fault (that is, flag) output pin with an
external pullup resistor connected to VOUT pin.
WD_FLT
9
6
O
Watchdog fault pin (for TPS7A63-Q1 only): This is an active-low fault output pin with an external pullup resistor
connected to the VOUT pin.
VIN
1
1
I
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor connected between
the VIN pin and GND pin dampens line transients on the input.
VOUT
7
5
O
Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V or a programmed value) pin
with a limitation on maximum output current. For devices with adjustable output voltage (TPS7A6x01-Q1),
connecting an external resistor network programs the output voltage. In order to achieve stable operation and
prevent oscillation, connect an external output capacitor (COUT) with low ESR between this pin and GND pin.
4
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Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
TPS7A63-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MAX
UNIT
VIN, VEN
Unregulated inputs (2) (3)
DESCRIPTION
45
V
VOUT
Regulated output
7
V
FB
Sense voltage for error amplifier (2)
7
V
ROSC
Constant-voltage reference (2)
7
V
nWD_EN,
WD,
WD_FLAG,
WD_FLT
Watchdog inputs and outputs (2)
7
V
nRST
Open-drain reset output (2)
7
V
RDELAY
Reset delay timer output (2)
7
V
TA
Operating ambient temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
MIN
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
Absolute negative voltage on these pins not to go below –0.3 V.
Absolute maximum voltage for duration less than 480 ms.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±4000
Charged device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
11
40
V
Enable pin voltage
4
40
V
Low voltage input or output
0
5.25
V
–40
150
°C
VIN
Unregulated input voltage
VEN
nRST, RDELAY, nWD_EN, WD_FLT
WD_FLAG (2), WD, FB (3)
(1)
,
TJ
(1)
(2)
(3)
Operating junction temperature range
UNIT
Applicable for TPS7A63-Q1 only
Applicable for TPS7A6401-Q1 only
Applicable for TPS7A6301-Q1 and TPS7A6401-Q1 only
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
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6.4 Thermal Information
THERMAL METRIC
TPS7A6401-Q1
TPS7A63-Q1
(1)
PWP (HTTSOP)
DRK (VSON)
14 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
46
36.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.6
36.6
°C/W
RθJB
Junction-to-board thermal resistance
27.4
11.6
°C/W
ψJT
Junction-to-top characterization parameter
1.2
0.5
°C/W
ψJB
Junction-to-board characterization parameter
27.2
11.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.5
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN PIN)
VIN
Input voltage
VOUT = 2.5 V to 7 V, IOUT = 1 mA
IQUIESCENT
Quiescent current
VIN = 8.2 V to 18 V, VEN = 5 V,
IOUT = 0.01 mA to 0.75 mA
11
40
ISLEEP
Sleep or shutdown current
VIN = 8.2 V to 18 V, VEN < 0.8 V,
IOUT = 0 mA (no load), TA = 125°C
VIN-UVLO
Undervoltage lockout
voltage
Ramp VIN down until output is turned OFF
3.16
V
VIN(POWERUP)
Power-up voltage
Ramp VIN up until output is turned ON
3.45
V
35
V
µA
3
µA
DEVICE ENABLE INPUT (EN PIN)
VIL
Logic-input low level
VIH
Logic-input high level
0
0.8
V
2.5
40
V
–2%
2%
REGULATED OUTPUT VOLTAGE (VOUT PIN)
Fixed VOUT value (3.3 V, 5 V or a programmed value),
IOUT = 10 mA to 200 mA, VIN = VOUT + 1 V to 16 V
VOUT
Regulated output voltage
ΔVLINE-REG
Line regulation
ΔVLOAD-REG
Load regulation
VDROPOUT
Dropout voltage
(VIN – VOUT)
IOUT = 200 mA
500
IOUT = 150 mA
300
RSW (1)
Switch resistance
VIN to VOUT resistance
IOUT
Output current
ICL
Output current limit
PSRR (3)
(1)
(2)
(3)
6
Power-supply ripple
rejection
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V
15
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V
20
IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 5 V
25
IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 3.3 V
35
2
VOUT in regulation
0
200
[VOUT in regulation, VOUT = 3.3 V, VIN = 6 V] (2)
0
300
350
1000
VOUT = 0 V (VOUT pin is shorted to ground)
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA,
frequency = 100 Hz, VOUT = 5 V and VOUT = 3.3 V
60
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA,
frequency = 150 kHz, VOUT = 5 V and VOUT = 3.3 V
30
mV
mV
mV
Ω
mA
mA
dB
This test is done with VOUT in regulation, measuring the VIN – VOUT parameter when VOUT drops by 100 mV from the programmed value
(of VOUT) at specified loads.
Design Information - not tested; specified by characterization.
Specified by design - not tested.
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SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
Electrical Characteristics (continued)
VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET (nRST PIN)
VOL
Reset pulled low
IOL = 5 mA
IOH
Leakage current
Reset pulled to VOUT through a 5-kΩ resistor
VTH(POR)
Power-on-reset threshold
UVTHRES
VOUT powered up above internally set tolerance,
VOUT = 5 V
Power-on-reset delay
tPOR-PRESET
Internally preset
Power-on-reset delay
tDEGLITCH
Reset deglitch time
4.65
V
1
µA
4.77
V
VOUT powered up above internally set tolerance,
VOUT = 3.3 V
3.07
VOUT falling below internally set tolerance,
VOUT = 5 V
Reset threshold
tPOR (2)
4.5
0.4
4.5
4.65
4.77
V
VOUT falling below internally set tolerance,
VOUT = 3.3 V
3.07
CDLY = 100 pF
300
µs
CDLY = 100 nF
300
ms
CDLY not connected, VOUT = 5 V and VOUT = 3.3 V
250
µs
5.5
µs
RESET DELAY (RDELAY PIN)
VTH(RDELAY)
Threshold to release nRST
high
IDLY
Delay capacitor
charging current
IOL
Delay capacitor
discharging current
Voltage at RDELAY pin is ramped up
0.75
Voltage at RDELAY pin = 1 V
3
3.3
V
1
1.25
µA
5
mA
CURRENT VOLTAGE REFERENCE (ROSC PIN)
VROSC
Voltage reference
0.95
1
1.05
V
0.4
V
1
µA
0.8
V
WATCHDOG FAULT / FLAG OUTPUT (WD_FLT / WD_FLAG Pin)
VOL
IOH
Logic output low level
IOL= 5 mA
Leakage current
WD_FLT/WD_FLG pulled to VOUT through 5-kΩ
resistor
WATCHDOG ENABLE INPUT (nWD_EN PIN)
VIL
Logic input low level
VIH
Logic input high level
3 V < VDD < 5.25 V
2.5
3 V < VDD < 5.25 V
2.5
V
WATCHDOG INPUT PULSE (WD PIN)
VIL
Logic input low level
VIH
Logic input high level
0.8
tWD
Watchdog window duration
tWD-tol
Tolerance of watchdog
period using external
resistor
Excludes tolerance of ROSC
(external resistor connected to ROSC pin)
tWD-DEFAULT
Default watchdog period
External resistor not connected, ROSC pin is floating
or open
tWD-HOLD
Minimum pulse width for
resetting watch dog timer
V
ROSC = 10 kΩ ± 1%
10
ROSC = 20kΩ ± 1%
20
–10%
108
V
ms
10%
164
254
1.65
ms
µs
OPERATING TEMPERATURE RANGE
TJ
Operating junction
temperature
TSHUTDOWN
Thermal shutdown trip
point
THYST
Thermal shutdown
hysteresis
–40
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
150
ºC
165
ºC
10
ºC
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6.6 Typical Characteristics
55
60
IOUT = 1mA
50
VIN =14V
45
IQUIESCENT (µA)
I QUIESCENT (µA)
50
40
30
VIN = 14V
TA = 25°C
VOUT = 5V, 3.3V
20
35
30
25
20
15
10
0.1
1
10
VOUT = 5V, 3.3V
40
100
-50
0
50
T A (°C)
IOUT (mA)
Figure 1. Quiescent Current vs Load Current
0.4
V OUT = 5V
VOUT = 5V, 3.3V
0.35
TA= 25°C
0.3
500
VDROP OUT (V)
I QUIESCENT (µA)
600
400
300
IOUT = 100mA
200
0.25
T A = 125°C
0.2
T A = 25°C
0.15
T A = -40°C
0.1
No Load
100
0.05
0
4
14
24
V IN (V)
34
40
Figure 3. Quiescent Current vs Input Voltage
5.1
0
50
100
IOUT (mA)
150
200
Measure dropout voltage when the output voltage drops by 100 mV
from the regulated output-voltage level. (For example, for an output
voltage programmed to be 5 V, measure the dropout voltage when
the output voltage drops down to 4.9 V from 5 V.)
Figure 4. Dropout Voltage vs Load Current
6
VIN = 14V
5.08
IOUT = 1mA
IOUT = 100mA
TA = 25°C
5
5.06
5.04
4
5.02
VOUT (V)
VOUT (V)
150
Figure 2. Quiescent Current vs Ambient Air Temperature
700
0
100
5
4.98
3
2
4.96
4.94
1
4.92
4.9
-50
0
50
TA (°C)
100
150
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2
3
4
5
6
7
V IN (V)
Figure 5. Output Voltage vs Ambient Air Temperature (VOUT
Set To 5 V)
8
0
Figure 6. Output Voltage vs Input Voltage
(VOUT Set To 5 V)
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
Typical Characteristics (continued)
0.12
0.1
0.08
650
TA= 125°C
TA = 25°C
0.06
TA = -40°C
0.04
500
0
0
10
20
30
40
450
-50
50
VIN (V)
50
TA (°C)
Figure 7. Output Voltage vs Input Voltage
Figure 8. Output Current Limit vs Ambient Air Temperature
12
10.5
10
9.5
9
150
2
1.5
1
0.5
8.5
8
-50
0
50
T A (°C)
100
120
VIN = 14V
IOUT = 200mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
100
60
0
50
T A (°C)
100
150
Figure 10. Line Regulation vs Ambient Air Temperature
120
VIN = 14V
IOUT = 1mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
100
PSRR (dB)
80
0
-50
150
Figure 9. Load Regulation vs Ambient Air Temperature
PSRR (dB)
100
IOUT = 10mA
VOUT = 5V, 3.3V
VIN step from
8V to 28V
2.5
Line Regulation (mV)
11
0
3
VIN = 14V
VOUT = 5V, 3.3V
IOUT step from
10mA to 200mA
11.5
Load Regulation (mV)
600
550
0.02
80
60
40
40
20
20
0
VIN = 14V
VOUT = 5V, 3.3V
700
ICL (mA)
IOUT (A)
750
ILOAD = 100mA
VOUT = 5V, 3.3V
0
10
100
10k
1k
Frequency (Hz)
100k
1M
Figure 11. PSRR at Heavy Load Current
10
100
10k
1k
Frequency (Hz)
100k
1M
Figure 12. PSRR at Light Load Current
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7 Detailed Description
7.1 Overview
The TPS7A63-Q1 and TPS7A6401-Q1 are a family of monolithic low-dropout linear voltage regulators with
integrated watchdog and reset functionality. These voltage regulators are designed for low power consumption
and quiescent current less than 25 µA in light-load applications. Because of a programmable reset delay (also
called power-on-reset delay), these devices are well-suited in power supplies for microprocessors and
microcontrollers.
These devices are available in two fixed and adjustable output-voltage versions as follows:
• Fault (WD_FLT) output version: TPS7A63-Q1
• Flag (WD_FLAG) output version: TPS7A6401-Q1
Feature Description describes the features of the TPS7A63-Q1 and TPS7A6401-Q1 voltage regulators in detail.
7.2 Functional Block Diagrams
VIN
Band Gap
VRef1
VIN
CIN
Temp. Sensor/
Thermal Shutdown
UVLO Comp.
with internal
reference
Q1
VRef1
EN
Regulator
Control
Logic
Control
Error
Amp.
VOUT
VOUT
Over
Current
Detection
RDELAY
CDLY
Charge Pump
Oscillator
COUT
RRST
Voltage
Supervisor with
Reset Delay
Q2
RESET
nRST
ROSC
Current
Regulator
ROSC
Watchdog
Oscillator
RFLT
Timer
WD_FLT
Q3
GND
FAULT
Watchdog
Fault Control
nWD_EN
WD
Figure 13. TPS7A6333-Q1 and TPS7A6350-Q1 (Fixed Output Voltage With Fault Output)
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Functional Block Diagrams (continued)
VIN
Band Gap
VRef1
Temp. Sensor/
Thermal Shutdown
VIN
CIN
UVLO Comp.
with internal
reference
Q1
VRef1
EN
Regulator
Control
Logic
Control
Error
Amp.
VOUT
VOUT
FB
R2
Over Current
Detection
RDELAY
COUT
R1
RRST
Voltage
Supervisor with
Reset Delay
CDLY
Charge Pump
Oscillator
Q2
RESET
nRST
ROSC
Current
Regulator
ROSC
Watchdog
Oscillator
RFLT
Timer
WD_FLT
Q3
GND
FAULT
Watchdog
Fault Control
nWD_EN
WD
Figure 14. TPS7A6301 (Adjustable Output Voltage With Fault Output)
VIN
Band Gap
VRef1
VIN
CIN
Temp. Sensor/
Thermal Shutdown
UVLO Comp.
with internal
reference
Q1
VRef1
EN
Regulator
Control
Logic
Control
Error
Amp.
VOUT
VOUT
FB
R2
Over Current
Detection
RDELAY
COUT
R1
RRST
Voltage
Supervisor with
Reset Delay
CDLY
Charge Pump
Oscillator
Current
Regulator
Watchdog
Oscillator
Q2
RESET
nRST
ROSC
ROSC
RFLAG
Timer
WD_FLAG
Q3
GND
FLAG
Watchdog
Fault Control
nWD_EN
WD
Figure 15. TPS7A6401-Q1 (Adjustable Output Voltage With Flag Output)
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7.3 Feature Description
7.3.1 Power Up, Reset Delay, and Reset Output
During power up, the regulator incorporates a protection scheme to limit the current through the pass element
and output capacitor. When the input voltage exceeds a certain threshold (VIN(POWERUP)) level, the output voltage
begins to ramp up as shown in Figure 16.
When starting up, and also when the output recovers from a negative voltage spike due to a load step or a dip in
the input voltage for a specified duration, the device implements reset delay to indicate that output voltage is
stable and in regulation.
When the output voltage reaches the power-on-reset threshold (VTH(POR)) level, that is, 93% of regulated output
voltage (3.3 V or 5 V, or a programmed value), a constant output current charges an external capacitor (CDLY) to
an internal threshold (VTH(RDELAY)) voltage level. Then, nRST asserts high and CDLY discharges through an
internal load. This allows CDLY to charge from approximately 0 V during the next power cycle.
Program the reset delay time by connecting an external capacitor (CDLY ,100 pF to 100 nF) to the RDELAY pin.
Equation 1 gives the delay time:
tPOR =
CDLY ´ 3
1´ 10-6
where
•
•
tPOR = reset delay time in seconds
CDLY = reset delay capacitor value in farads
(1)
VIN(POWERUP)
VIN t < tDEGLITCH
0
0
t>tDEGLITCH
VIN
VTH(POR)
VTH(POR)= 93% of VOUT
UVTHRES
0
0
VOUT
VOUT
VTH(RDELAY)
0
VTH(RDELAY)
0
VRDELAY
tPOR
VRDELAY
tDEGLITCH
tPOR
VnRST
VnRST
0
0
Figure 16. Power Up and Conditions for Activation
of Reset
Figure 17. Reset Delay and Deglitch Filter
As Figure 17 shows, if the regulated output voltage falls below 93% of the set level, nRST asserts low after a
short de-glitch time of approximately 5.5 µs (typical). In case of negative transients in the input voltage (VIN), the
reset signal asserts low only if the output (VOUT) drops and stays below the reset threshold level (VTH(POR)) for
more than the deglitch time (tDEGLITCH), as Figure 17 and Figure 20 illustrate. While nRST is low, if the input
voltage returns to the nominal operating voltage, the normal power-up sequence ensues. nRST asserts high only
if the output voltage exceeds the reset threshold voltage (VTH(POR)) and the reset delay time (tPOR) has elapsed.
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Feature Description (continued)
7.3.2 Adjustable Output Voltage
Program the regulated output voltage (VOUT) by connecting external resistors to FB pin. Calculate the feedback
resistor values using Equation 2.
R1 ù
é
VOUT = VREF ê1 +
R2 úû
ë
where
•
•
•
VOUT= desired output voltage
VREF = reference voltage (VREF= 1.23 V, typically)
R1, R2 = feedback resistors (see Figure 15)
(2)
Equation 3 gives the overall tolerance of the regulated output.
é R1 ù
tolVOUT = tolVREF + ê
ú éë tolR1 + tolR2 ùû
ë R1 + R2 û
where
•
•
•
tolVOUT = tolerance of the output voltage
tolVREF = tolerance of the internal reference voltage (tolVREF = ± 1.5% typically)
tolR1,tolR2 = tolerance of feedback resistors R1, R2
(3)
For a tighter tolerance on VOUT, select lower-value feedback resistors. TI recommends to select feedback
resistors such that the sum of R1 and R2 is from 20 kΩ to 200 kΩ.
7.3.3 Chip Enable
These devices have a high-voltage-tolerant EN pin that an external microcontroller or a digital control circuit can
use to enable and disable them. A high input to this pin activates the device and turns the regulator on. For self
bias applications, connect this input to the VIN terminal. An internal pulldown resistor is connected to this pin,
and therefore if this pin remains unconnected, the device stays disabled.
7.3.4 Charge Pump Operation
Charge Pump State
Charge Pump State
These devices have an internal charge pump which turns on or off depending on the input voltage and the output
current. The charge pump switching circuitry must not cause conducted emissions to exceed required thresholds
on the input voltage line. For a given output current, the charge pump stays on at lower input voltages and turns
off at higher input voltages. The charge pump switching thresholds are hysteretic. Figure 18 and Figure 19 show
typical switching thresholds for the charge pump at light (IOUT < approximately 2 mA) and heavy (IOUT >
approximately 2 mA) loads, respectively.
ON
Hysteresis
OFF
7.8
ON
Hysteresis
OFF
9.2
7.9
9.6
VIN (V)
VIN (V)
Figure 18. Charge Pump Operation at Light
Loads
Figure 19. Charge Pump Operation at Heavy
Loads
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7.3.5 Low-Power Mode
At light loads and high input voltages (VIN > approximately 8 V, such that the charge pump is off), the device
operates in low-power mode and the quiescent current consumption is reduced to 25 µA (typical) as shown in
Table 1.
Table 1. Typical Quiescent Current Consumption
IOUT
Charge Pump ON
Charge Pump OFF
IOUT < approximately 2 mA
(Light load)
250 µA
35 µA
(Low-power mode)
IOUT > approximately 2 mA
(Heavy load)
280 µA
70 µA
7.3.6 Undervoltage Shutdown
These devices have an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input
voltage (VIN) falls below an internally fixed UVLO threshold level (VIN-UVLO). This ensures that the regulator does
not latch into an unknown state during low input voltage conditions. The regulator powers up when the input
voltage exceeds the VIN(POWERUP) level, as Figure 20 shows.
7.3.7 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation, and the output voltage tracks the input minus a
voltage based on the load current (IOUT) and switch resistance (RSW), as Figure 20 shows. This feature allows for
a smaller input capacitor and can possibly eliminate the need of using a boost convertor during cold crank
conditions, as Figure 20 shows.
7.3.8 Integrated Fault Protection
These devices feature integrated fault protection to make them ideal for use in automotive applications. In order
to remain in a safe area of operation during certain fault conditions, the devices use internal current-limit
protection and current-limit foldback to limit the maximum output current. This protects them from excessive
power dissipation. For example, during a short-circuit condition on the output, fault protection limits the current
through the pass element to ICL to protect the device from excessive power dissipation.
7.3.9 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. The junction temperature
exceeding the TSD trip point causes the output to turn off. When the junction temperature falls below TSD trip
point, the output turns on again, as Figure 21 shows.
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Tracking
VIN-UVLO
VIN
0
UVTHRES
0
VOUT
0
VRDELAY
tDEGLITCH
VnRST
0
Figure 20. Low-Voltage Tracking and Undervoltage
Lockout
Figure 21. Thermal Cycling Waveform for
TPS7A6350-Q1 (VIN= 24 V, IOUT= 200 mA, VOUT= 5 V)
7.3.10 Integrated Window Watchdog
These devices have an integrated watchdog with fault (WD_FLT) and flag (WD_FLAG) output options. Both
device options are available in fixed- and adjustable-output versions. The watchdog operation, service fault
conditions, and difference between fault (TPS7A63-Q1) and flag (TPS7A6401-Q1) output versions are described
as follows.
7.3.10.1 Programmable-Window Watchdog
Program the duration of the watchdog window by connecting an external resistor (ROSC) to ground at the ROSC
pin. The current through the resistor sets the clock frequency of the internal oscillator. The user can adjust the
duration of the watchdog window (that is, the watchdog timer period) by changing the resistor value. The duration
of the watchdog window and the duration of the fault output are multiples of the internal oscillator frequency and
are given by the following equations:
tWD = 10–6 × ROSC = 5000 × 1 / fOSC
tWD_OUT = 1 / fOSC
tCW = tOW = 1 / 2 tWD
(4)
(5)
where
•
•
•
•
•
•
tWD = width of watchdog window
ROSC = resistor connected at ROSC pin
tWD_OUT = duration of fault output
fOSC = frequency of internal oscillator
tCW = duration of closed window
tOW = duration of open window
(6)
As shown in Figure 22, each watchdog window consists of an open window and a closed window, each having a
width approximately 50% of the watchdog window. However, there is an exception to this; the first open window
after watchdog initialization is eight times the duration of the watchdog window. All open windows except the one
after watchdog initialization are one-half the width of the watchdog window. On initialization, the watchdog must
receive service (by software, external microcontroller, and so forth) only during an open window. A watchdog
serviced during a closed window, or not serviced during a open window, creates a watchdog fault condition.
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CLOSED
OPEN
After watchdog initialization
(must be serviced to prevent fault)
WINDOW
(must not be serviced
to prevent fault)
WINDOW
(must be serviced to
prevent fault)
8 x tWD
tCW=½ tWD
tOW=½ tWD
OPEN WINDOW
Event causing
watchdog initialization
tWD = 5000 x tWD_OUT
Figure 22. Watchdog Window Duration
7.3.10.2 Watchdog Enable
An external microcontroller or a digital circuit can apply an appropriate signal to the nWD_EN pin to enable or
disable the watchdog. A low input to this pin turns the watchdog on. Because of an internal pulldown resistor
connected to this pin, leaving the pin unconnected keeps the watchdog enabled.
7.3.10.3 Watchdog Service Signal
In order for the watchdog service signal (WD) to service an open window correctly, the service signal must stay
high for a duration of at least tWD_HOLD. The recommended value of tWD_HOLD is given by Equation 7:
tWD_HOLD = 3 × tWD_OUT
(7)
7.3.10.4 Watchdog Fault Outputs
The WD_FLT pin and WD_FLAG pin are fault output terminals for the TPS7A63-Q1 and TPS7A6401-Q1
devices, respectively. Typically, one pulls these fault outputs high to a regulated output supply. In the case of a
watchdog fault condition, the TPS7A63-Q1 momentarily pulls WD_FLT low for a duration of tWD_OUT, whereas the
TPS7A6401-Q1 latches the WD_FLAG high and momentarily pulls nRST low for a duration of tWD_OUT.
7.3.10.5 Watchdog Initialization
On power up and during normal operation, the watchdog initializes under the conditions shown in Table 2. The
normal operation of the watchdog for the WD_FLT and WD_FLAG output device options is shown in Figure 23
and Figure 24, respectively.
Table 2. Conditions For Watchdog Initialization
Edge
16
TPS7A63-Q1
(FAULT Option)
TPS7A6401-Q1
(FLAG Option)
Rising edge of nRST (when VOUT exceeds VTH(POR)) while
the watchdog is in the enabled state, for example, during
soft power up
✓
✓
Falling edge of nWD_EN while the nRST is already high,
for example, when the microprocessor enables the
watchdog after the device is powered up
✓
✓
Rising edge of WD_FLT while the nRST is already high
and the watchdog is in the enabled state, for example, right
after a closed window is serviced
✓
X
What causes watchdog to initialize?
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7.3.10.6 Watchdog Operation
tPOR
tPOR
93% of VOUT
93% of VOUT
0
0
VOUT
VOUT
0
0
nRST
nRST
0
0
tWD_HOLD
nWD_EN
0
tWD_HOLD
nWD_EN
0
WD
WD
0
0
WD_FLT
WD
Window
Status
WD_FLAG
NA
OW
WD Initialization
CW
OW
<8 tWD
½ tWD
<½ tWD
CW
Figure 23. Power Up, Initialization, and Normal
Operation for TPS7A63-Q1
WD
Window
Status
NA
OW
WD Initialization
CW
OW
<8 tWD
½ tWD
<½ tWD
CW
Figure 24. Power Up, Initialization, and Normal
Operation for TPS7A6401-Q1
Figure 23 shows watchdog initialization and operation for the TPS7A63-Q1. After output voltage is in regulation
and reset asserts high (clearly the chip-enable pin is high), the watchdog becomes enabled when an external
signal pulls nWD_EN (the watchdog enable pin) low. This causes the watchdog to initialize and wait for a service
signal during the first open window for 8× the duration of tWD. A service signal applied to the WD pin during the
first open window resets the watchdog counter and a closed window starts. To prevent a fault condition from
occurring, watchdog service must not occur during the closed window. Watchdog service must occur during the
following open window to prevent fault condition from occurring. The fault output (WD_FLT), externally pulled up
to VOUT (typically), stays high as long as the watchdog receives proper serviced and there is no fault condition.
Figure 24 shows watchdog initialization and operation for FLAG output version (TPS7A6401-Q1). The fault
output (WD_FLAG), externally pulled up to VOUT (typically), stays low as long as the watchdog receives proper
service and there is no fault condition.
Likewise, enabling the watchdog before powering the device on (that is, pulling the nWD_EN pin low before
power up), the watchdog initializes as soon as the output voltage is in regulation and reset asserts high (see
Table 2 for Conditions for Watchdog Initialization).
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7.3.10.7 Watchdog Fault Conditions
0
0
VOUT
VOUT
0
0
nRST
nRST
0
tWD_OUT
tWD_OUT
tWD_OUT
tWD_OUT
0
nWD_EN
nWD_EN
0
0
WD
WD
0
tWD_OUT
WD_FLT
OW CW
<½ tWD
FLT
OW
0
tWD_OUT
WD Initialization
CW
OW
<8 tWD
½ tWD
½ tWD
WD_FLAG
OW
WD
FLT FLT
Init.
Figure 25. Watchdog Service Fault Conditions for
TPS7A63-Q1
OW CW
<½ tWD
FLT
OW
WD Init.
<8 tWD
OW
WD
NA FLT
Init.
CW
OW
½ tWD
½ tWD
FLT
Figure 26. Watchdog Service Fault Conditions for
TPS7A6401-Q1
For both device options, a watchdog fault condition occurs in following (non-exhaustive) cases:
• When the watchdog receives service during a closed window.
• When watchdog does not receive service during an open window (this open window could be the one after
watchdog initialization, or the one following a closed window).
As shown in Figure 25, for TPS7A63-Q1 the first watchdog fault registers when the watchdog receives service
during a closed window. This causes the watchdog fault pin (WD_FLT) to go low temporarily for a duration of
tWD_OUT. Following the fault, the watchdog reinitializes. Likewise, the second fault registers when the watchdog
does not receive service during an open window (following a closed window). Again, the fault pin (WD_FLT) is
asserts low for a duration of tWD_OUT.
As shown in Figure 26, for TPS7A6401-Q1 the first watchdog fault registers when watchdog receives service
during a closes window. This causes the watchdog flag pin (WD_FLAG) to become high and stay latched. At the
same time, nRST pin goes low temporarily for the duration of tWD_OUT. WD_FLAG remains high until toggling the
nWD_EN pin disables and re-enables the watchdog or the watchdog receives service properly (while nWD_EN is
low and nRST is high). The second fault registers when the watchdog does not receive service during an open
window (following a closed window). While WD_FLAG is high (that is, during a fault condition), if the watchdog
stays enabled, and reset is high; a watchdog service signal can also bring WD_FLAG low (about 5 µs after the
watchdog receives service).
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tPOR
tPOR
93% of VOUT
93% of VOUT
tDEGLITCH
tDEGLITCH
0
0
VOUT
VOUT
0
0
nRST
tWD_OUT
tWD_OUT
nRST
0
0
nWD_EN
nWD_EN
0
0
WD
WD
0
tWD_OUT
WD_FLT
OW
WD Initialization
8 tWD
FLT
OW
WD Init.
tWD_OUT
CW
<8 tWD < ½tWD
OW
CW
WD Initialization
F
N OW
L
A WD Init.
T
8 tWD
Figure 27. Watchdog Fault During Initialization,
and Reinitialization During Reset for TPS7A63-Q1
0
tWD_OUT
WD_FLAG
OW
WD Initialization
FLT
8 tWD
OW
WD Init.
<8 tWD
NA
OW
CW
WD
Initialization
F
N OW
L
A WD Init.
T
8 tWD
Figure 28. Watchdog Fault During Initialization,
and Reinitialization During Reset for TPS7A6401Q1
As shown in Figure 27 for the TPS7A6401-Q1, the watchdog fault condition also occurs if the watchdog does not
receive service during the open window after watchdog initialization. That is, if the watchdog does not receive
service during the first 8× tWD_OUT period after initialization, a fault condition occurs. This causes the watchdog
fault pin (WD_FLT) to go low temporarily for a duration of tWD_OUT. In case of a load transient, if the regulated
output voltage drops down causing reset (nRST) to go low, the rising edge on nRST causes the watchdog to
reinitialize (that is, when reset becomes high with the watchdog still enabled). During a fault condition (that is,
WD_FLT is low) with the watchdog disabled, the fault output continues to stay low until tWD_OUT is elapsed. A
falling edge on nWD_EN pin causes the watchdog to reinitialize while nRST is still high.
As shown in Figure 28 for the TPS7A6401-Q1, the watchdog fault condition also occurs if the watchdog does not
receive service during the open window after watchdog initialization. That is, if the watchdog does not receive
service in first 8× tWD_OUT period after initialization, a fault condition occurs. This causes the watchdog flag pin
(WD_FLAG) to become high and stay latched. At the same time, the nRST pin goes low temporarily for a
duration of tWD_OUT. In the case of a load transient, if the regulated output voltage drops down causing the reset
output to go low, the WD_FLAG asserts low, and the rising edge on nRST causes the watchdog to reinitialize
(while the watchdog remains enabled). During a fault condition (that is, WD_FLAG is high), and with a disabled
watchdog, the flag output continues to stay high as long as the watchdog remains enabled or receives proper
service. However, nRST stays low until tWD_OUT elapses. Re-enabling the watchdog causes watchdog to
reinitialize (while nRST is still high).
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7.4 Device Functional Modes
7.4.1 Operation With VIN Lower Than 4 V
The TPS7A63-Q1 and TPS7A6401-Q1 family devices operate with input voltage above 4 V. The typical UVLO
voltage is 3.16 V. The device can operate at input voltage lower than 4 V, but at input voltage below the actual
UVLO, the device will shut down.
7.4.2 Operation With VIN Larger Than 4 V
When VIN is greater than 4 V, if the input voltage is higher than VOUT plus the dropout voltage, the output voltage
is equal to the set value. Otherwise, the output voltage is equal to VIN minus the dropout voltage.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Typical application circuits for TPS76333-Q1/TPS76350-Q1 and TPS7A6401-Q1 are shown in Figure 29 and
Figure 32. Depending on the end application, one may use different values of external components. Carefully
select feedback resistors (R1 and R2), used to program the output voltage. Using smaller resistors results in
higher current consumption, whereas using very large resistors impacts the sensitivity of the regulator. Therefore,
TI recommends selecting feedback resistors such that the sum of R1 and R2 is from 20 kΩ to 200 kΩ.
8.1.1 Example
If the desired regulated output voltage is 5 V, after selecting R2 then one can calculate R1 using (or vice versa)
Equation 2. Knowing VREF = 1.23 V (typical), VOUT = 5 V, selecting R2 = 20 kΩ, the calculated value of R1 is 61.3
kΩ.
During fast load steps, an application may require a larger output capacitor to prevent the output from temporarily
dropping down. TI recommends a low-ESR ceramic capacitor with dielectric of type X5R or X7R. One can also
connect a bypass capacitor at the output to decouple high-frequency noise as per the end application.
8.2 Typical Applications
8.2.1 Typical Application Using the TPS7A6333-Q1 or TPS7A6350-Q1
TPS7A6333-Q1/
TPS7A6350-Q1
VIN
0.1μF
VOUT
VOUT
VIN
1μ F
to
10μF
10μF
to
22μF
0.1μF
1kΩ
to
5kΩ
RDELAY
100pF
to 100nF
ROSC
10kΩ
to
200kΩ
GND
EN
RESET
nRST
WD_FLT/
WD_FLG
nWD_EN WD
1kΩ
to
5kΩ
FAULT/
FLAG
Figure 29. Typical Application Schematic, TPS7A6333-Q1/6350-Q1
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Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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Typical Applications (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUES
Input voltage range
11 V - 40 V
Input capacitor range
10 µF - 22 µF
Output voltage
3.3 V, 5 V
Output current rating
300 mA maximum
Output capacitor range
1 µF-10 µF
8.2.1.2 Detailed Design Procedure
When using the TPS7A6333-Q1, TPS7A6350-Q1, TI recommends adding a 10-µF to 22-µF capacitor to the input
to keep the input voltage stable. TI also recommends adding a 1-µF to 10-µF low ESR ceramic capacitor to get a
stable output.
The reset delay time is set by an external capacitor (CDLY) to ground, capacitor value typical from 100 pF to
100 nF. Equation 1 provides the method for the calculation.
Connecting an external resistor to ground at the ROSC pin can set the duration of the watchdog window.
Equation 4 provides the method for the calculation. Usually a 10-kΩ to 200-kΩ resistor can be used to set the
time.
8.2.1.3 Application Curves
Figure 30. TPS7A6333-Q1 Power Up Waveform
22
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Figure 31. TPS7A6333-Q1 Load Transient Waveform
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
TPS7A63-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
8.2.2 Typical Application Using the TPS7A6401-Q1
TPS7A6401-Q1
VIN
0.1μF
VOUT
VOUT
VIN
10μF
to
22μF
R1
1kΩ
to
5kΩ
FB
RDELAY
1μ F
to
10μF
0.1μF
R2
100pF
to 100nF
ROSC
10kΩ
to
200kΩ
RESET
nRST
GND
EN
1kΩ
to
5kΩ
WD_FLT/
WD_FLG
nWD_EN WD
FAULT/
FLAG
Figure 32. Typical Application Schematic TPS7A6401-Q1
8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 4.
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUES
Input voltage range
11 V - 40 V
Input capacitor range
10 µF-22 µF
Output voltage
2.5 V - 7 V
Output current rating
300 mA maximum
Output capacitor range
1 µF-10 µF
8.2.2.2 Detailed Design Procedure
When using TPS7A6401-Q1, TI recommends adding a 10-µF to 22-µF capacitor to the input to keep the input
voltage stable. TI also recommends adding a 1-µF to 10-µF low ESR ceramic capacitor to get a stable output.
The output voltage is set by the R1 and R2 resistor network. Output voltage can be calculated by Equation 2.
The reset delay time is set by an external capacitor (CDLY) to ground, capacitor value typical from 100 pF to
100 nF. Equation 1 provides the method for the calculation. Connecting an external resistor to ground at the
ROSC pin can set the duration of the watchdog window. Equation 4 provides the method for the calculation.
Usually a 10-kΩ to 200-kΩ resistor can be used to set the time.
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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8.2.2.3 Application Curves
Figure 33. TPS7A6401-Q1 Power Up Waveform
Figure 34. TPS7A6401-Q1 Load Transient Waveform
9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range from 11 V to 40 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS7A63XX-Q1 or TPS7A64XXQ1 device, TI recommends adding an electrolytic capacitor with a value of 10 µF and a ceramic bypass capacitor
at the input.
10 Layout
10.1 Layout Guidelines
For the LDO power supply, especially these high voltage and large current ones, layout is an important step. If
layout is not carefully designed, the regulator could not deliver enough output current because of the thermal
limitation. To improve the thermal performance of the device, and maximize the current output at high ambient
temperature, it is recommended to spread the thermal pad as large as possible and put enough thermal vias on
the thermal pad. Figure 37 shows an example layout.
10.1.1 Power Dissipation and Thermal Considerations
Calculated the power dissipated in the device using Equation 8.
PD = IOUT × (VIN – VOUT)) + IQUIESCENT × VIN
where
•
•
•
•
•
PD = continuous power dissipation
IOUT = output current
VIN = input voltage
VOUT = output voltage
IQUIESCENT = quiescent current
(8)
As IQUIESCENT << IOUT, therefore, ignore the term IQUIESCENT × VIN in Equation 8.
For a device in operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) using
Equation 9.
TJ = TA + (RθJA × PD)
where
•
RθJA = junction-to-ambient-air thermal impedance
(9)
Calculate the rise in junction temperature due to power dissipation using Equation 10.
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SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
Layout Guidelines (continued)
ΔT = TJ – TA = (RθJA × PD)
(10)
For a given maximum junction temperature (TJ-Max), calculate the maximum ambient air temperature (TA-Max) at
which the device can operate using Equation 11.
TA-Max = TJ-Max – (RθJA × PD)
(11)
10.1.1.1 Example
If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT = 250 µA, and RθJA= 50°C/W, the continuous power
dissipated in the device is 0.9 W. The rise in junction temperature due to power dissipation is 45°C. For a
maximum junction temperature of 150°C, the maximum ambient air temperature at which the device can operate
is 105°C.
For adequate heat dissipation, TI recommends soldering the thermal pad (exposed heat sink) to the thermal land
pad on the PCB. Doing this provides a heat conduction path from the die to the PCB and reduces overall
package thermal resistance. Power derating curves for the TPS7A63-Q1 and TPS7A6401-Q1 PWP package and
TPS7A6333-Q1 DRK are comparable; see Figure 35.
2.5
Power Dissipated (W)
2
1.5
1
0.5
0
0
25
50
75
100
Junction Temperature (°C)
125
150
Figure 35. Power Derating Curve
For optimum thermal performance, TI recommends using a high-K PCB with thermal vias between the ground
plane and solder pad or thermal land pad; see Figure 36 (a) and (b). Further, use a thicker ground plane and a
thermal land pad with a larger surface area to inprove considerably the heat-spreading capabilities of a PCB. For
a two-layer PCB, a bat wing layout can enhance the heat-spreading capabilities.
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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Layout Guidelines (continued)
Thermal Via
Thermal Land Pad
PCB
Dedicated
Ground Plane
(a) Multilayer PCB with a dedicated ground plane
Thermal Via
Thermal Land Pad
PCB
Bat Wings
Ground Plane
(b) Dual layer PCB with Bat wings for enhanced heat spreading
Figure 36. Using Multilayer PCB and Thermal Vias for Adequate Heat Dissipation
Keeping other factors constant, surface area of the thermal land pad contributes to heat dissipation only to a
certain extent.
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TPS7A63-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
10.2 Layout Example
C1
Input
D1
VIN
1
14
ROSC
nRST
2
13
NC
FB
3
12
nWD_EN
11
NC
WD
GND
4
EN
5
10
RDELAY
6
9
WD_FLT/FLAG
VOUT
7
8
NC
C1
Figure 37. Layout Recommendation
Copyright © 2011–2018, Texas Instruments Incorporated
Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
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TPS7A63-Q1, TPS7A6401-Q1
SLVSAB1F – JUNE 2011 – REVISED JUNE 2018
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS7A63-Q1
Click here
Click here
Click here
Click here
Click here
TPS7A6401-Q1
Click here
Click here
Click here
Click here
Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Product Folder Links: TPS7A63-Q1 TPS7A6401-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jul-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A6301QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7A6301
TPS7A6333QDRKRQ1
ACTIVE
VSON
DRK
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
PRGQ
TPS7A6333QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7A6333
TPS7A6350QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7A6350
TPS7A6401QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7A6401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jul-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS7A6301QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TPS7A6333QDRKRQ1
VSON
DRK
10
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
TPS7A6333QPWPRQ1
HTSSOP
PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TPS7A6350QPWPRQ1
HTSSOP
PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TPS7A6401QPWPRQ1
HTSSOP
PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A6301QPWPRQ1
HTSSOP
PWP
14
2000
350.0
350.0
43.0
TPS7A6333QDRKRQ1
VSON
DRK
10
3000
367.0
367.0
35.0
TPS7A6333QPWPRQ1
HTSSOP
PWP
14
2000
350.0
350.0
43.0
TPS7A6350QPWPRQ1
HTSSOP
PWP
14
2000
350.0
350.0
43.0
TPS7A6401QPWPRQ1
HTSSOP
PWP
14
2000
350.0
350.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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