Texas Instruments | TPS7A65-Q1 300-mA, 40-V, Low-Dropout Regulator With 25-µA Quiescent Current (Rev. E) | Datasheet | Texas Instruments TPS7A65-Q1 300-mA, 40-V, Low-Dropout Regulator With 25-µA Quiescent Current (Rev. E) Datasheet

Texas Instruments TPS7A65-Q1 300-mA, 40-V, Low-Dropout Regulator With 25-µA Quiescent Current (Rev. E) Datasheet
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TPS7A65-Q1
SLVSA98E – MAY 2010 – REVISED MAY 2018
TPS7A65-Q1 300-mA, 40-V, Low-Dropout Regulator With 25-µA Quiescent Current
1 Features
3 Description
•
The TPS7A65-Q1 low-dropout linear voltage
regulator is designed for low power consumption and
quiescent current less than 25 µA in light-load
applications. This device features integrated
overcurrent protection and a design to achieve stable
operation even with low-ESR ceramic output
capacitors. A low-voltage tracking feature allows for a
smaller input capacitor and can possibly eliminate the
need of using a boost converter during cold crank
conditions. Because of these features, this device is
well-suited in power supplies for various automotive
applications.
1
•
•
•
•
•
•
•
•
Low Dropout Voltage
– 300 mV at IOUT = 150 mA
11-V to 40-V Wide Input Voltage Range
With up to 45-V Transients
300-mA Maximum Output Current
25-µA (Typical) Ultralow Quiescent Current at
Light Loads
3.3-V and 5-V Fixed Output Voltage With ±2%
Tolerance
Low-ESR Ceramic Output Stability Capacitor
Integrated Fault Protection
– Short-Circuit and Overcurrent Protection
– Thermal Shutdown
Low Input-Voltage Tracking
Thermally Enhanced Power Package
– 3-Pin TO-252 (KVU, DPAK)
Device Information(1)
PART NUMBER
TPS7A65-Q1
PACKAGE
TO-252 (3)
BODY SIZE (NOM)
6.60 mm × 6.10 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
•
Qualified for Automotive Applications
Infotainment Systems With Sleep Mode
Body Control Modules
Always-On Battery Applications
– Gateway Applications
– Remote Keyless Entry Systems
– Immobilizers
Typical Application Schematic
Typical Regulator Stability
10
VIN = 14V
COUT = 10µF, 47µF
TA = 27°C
VOUT = 5V, 3.3V
TPS7A65-Q1
VIN
VOUT
VOUT
COUT
CIN
GND
ESR of COUT (Ω)
VIN
1
Stable Operation
Over Entire Region
0.1
0.01
0.01
0.1
1
10
100 300
IOUT (mA)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A65-Q1
SLVSA98E – MAY 2010 – REVISED MAY 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2015) to Revision E
Page
•
Changed 4 V to 11 V in Input Voltage Range Features bullet .............................................................................................. 1
•
Changed VIN parameter min specifications to 11 V from 5.3 V and 3.6 V ............................................................................ 5
•
Changed 4 V to 11 V in Input voltage range row in Design Parameters table..................................................................... 13
•
Changed 4 V to 40 V in first sentence of Power Supply Recommendations section........................................................... 15
Changes from Revision C (December 2011) to Revision D
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
Changes from Revision B (November 2011) to Revision C
Page
•
Deleted the TPS7A6533QKVURQ1 device............................................................................................................................ 1
•
Changed the Regulated Output Voltage (5.1). Added to Test Conditions "10mA to 300mA, VIN = VOUT + 1V to 16V" ......... 5
Changes from Revision A (November 2011) to Revision B
•
Changed the θJP value in the Abs Max Table From: 12.7 To: 1.2°C/W ................................................................................. 4
Changes from Original (May 2010) to Revision A
•
2
Page
Page
Removed all KKT information................................................................................................................................................. 4
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5 Pin Configuration and Functions
KVU Package
3-Pin TO-252
Top View
1
2
3
GND
VIN
VOUT
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected
between VIN pin and GND pin to dampen input line transients.
1
VIN
I
2
GND
I/O
Ground pin: This is signal ground pin of the IC.
3
VOUT
O
Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V, as applicable) pin
with a limitation on maximum output current. To achieve stable operation and prevent oscillation, an
external output capacitor (COUT) with low ESR is connected between this pin and the GND pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
45
V
Unregulated input (2) (3)
VIN
VOUT Regulated output
7
V
θJP
Thermal impedance junction to exposed pad
1.2
°C/W
TA
Operating ambient temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute negative voltage on these pins not to go below –0.3 V.
Absolute maximum voltage for duration less than 480 ms.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
VALUE
UNIT
±2000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
VIN
Unregulated input voltage
VEN
Enable pin voltage
TJ
Operating junction temperature
MIN
MAX
UNIT
11
40
4
40
V
–40
150
°C
V
6.4 Thermal Information
TPS7A65-Q1
THERMAL METRIC (1)
KVU (TO-252)
UNIT
3 PINS
High-K profile (2)
29.3
°C/W
Low-K profile (3)
38.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
N/A
°C/W
RθJB
Junction-to-board thermal resistance
8.2
°C/W
ψJT
Junction-to-top characterization parameter
3.4
°C/W
ψJB
Junction-to-board characterization parameter
8.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The thermal data is based on JEDEC standard high-K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated.
The thermal data is based on JEDEC standard low-K profile – JESD 51-3. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated.
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6.5 Electrical Characteristics
VIN = 14 V, TJ = –40ºC to +150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN PIN)
Fixed 5-V output, IOUT = 1 mA
11
40
Fixed 3.3-V output, IOUT = 1 mA
11
40
VIN
Input voltage
IQUIESCENT
Quiescent current
VIN = 8.2 V to 18 V, IOUT = 0.01 mA to 0.75 mA
VIN-UVLO
Undervoltage lockout voltage
Ramp VIN down until output is turned OFF
3.16
V
VIN(POWERUP)
Power-up voltage
Ramp VIN up until output is turned ON
3.45
V
25
40
V
µA
REGULATED OUTPUT VOLTAGE (VOUT PIN)
Fixed VOUT value (3.3 V or 5 V as applicable),
IOUT = 10 mA, 10 mA to 300 mA,
VIN = VOUT + 1 V to 16 V
VOUT
Regulated output voltage
∆VLINE-REG
Line regulation
∆VLOAD-REG
Load regulation
VDROPOUT (1)
Dropout voltage
(VIN – VOUT)
IOUT = 250 mA
500
IOUT = 150 mA
300
RSW (2)
Switch resistance
VIN to VOUT resistance
IOUT
Output current
VOUT in regulation
ICL
Output current limit
VOUT = 0 V (VOUT pin is shorted to ground)
PSRR (2)
Power-supply ripple rejection
–2%
2%
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V
15
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V
20
IOUT = 10 mA to 300 mA, VIN= 14 V, VOUT = 5 V
25
IOUT = 10 mA to 300 mA, VIN = 14 V, VOUT = 3.3
V
35
2
mV
mV
mV
Ω
0
300
mA
350
1000
mA
VIN-RIPPLE = 0.5 Vpp, IOUT = 300 mA,
frequency = 100 Hz, VOUT = 5 V, VOUT = 3.3 V
60
VIN-RIPPLE = 0.5 Vpp, IOUT = 300 mA,
frequency = 150 kHz, VOUT = 5 V, VOUT = 3.3 V
30
dB
TEMPERATURE
TSHUTDOWN
Thermal shutdown trip point
THYST
Thermal shutdown hysteresis
(1)
(2)
165
ºC
10
ºC
This test is done with VOUT in regulation and VIN – VOUT parameter is measured when VOUT (3.3 V or 5 V) drops by 100 mV at specified
loads.
Specified by design; not tested.
6.6 Dissipation Ratings
JEDEC STANDARD
PACKAGE
TA < 25°C POWER
RATING (W)
DERATING FACTOR
ABOVE TA = 25°C (°C/W)
TA = 85°C POWER
RATING (W)
JEDEC Standard PCB low K, JESD 51-3
3-pin KVU
3.24
38.6
1.68
JEDEC Standard PCB high K, JESD 51-5
3-pin KVU
4.27
29.3
2.22
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6.7 Typical Characteristics
10
VIN = 14V
COUT = 1µF
TA = 27°C
VOUT = 5V
VIN = 14V
COUT = 1µF
TA = 27°C
VOUT = 3.3V
ESR of COUT (Ω)
ESR of COUT (Ω)
10
1
Stable Operation
0.1
0.06
1
Stable Operation
0.1
Unstable
Operation
0.06
0.03
0.01
0.01
Unstable
Operation
0.1
1
IOUT (mA)
10
30
100
300
0.03
0.01
0.01
0.1
Figure 1. ESR vs Load Current
80
55
IQUIESCENT (µA)
I QUIESCENT (µA)
50
40
30
30
10
20
10
100
15
1000
IOUT = 250mA
35
25
1
IOUT (mA)
IOUT = 1mA
-50
0
50
T A (°C)
0.4
VOUT = 5V, 3.3V
TA= 25°C
VDROP OUT (V)
500
400
300
150
V OUT = 5V
0.35
0.3
I QUIESCENT (µA)
100
Figure 4. Quiescent Current vs Ambient Air Temperature
Figure 3. Quiescent Current vs Load Current
700
600
300
40
20
0.1
100
VOUT =5V, 3.3V
45
0.01
30
VIN =14V
50
60
0
0.001
10
Figure 2. ESR vs Load Current
VIN = 14V
TA = 25°C
VOUT = 5V, 3.3V
70
1
IOUT (mA)
IOUT = 100mA
T A = 125°C
0.25
T A = 25°C
0.2
T A = -40°C
0.15
0.1
200
No Load
100
0.05
0
0
4
14
24
V IN (V)
34
Figure 5. Quiescent Current vs Input Voltage
(1)
6
40
0
50
100
150
IOUT (mA)
200
250
Figure 6. Dropout Voltage vs Load Current
300
(1)
Dropout voltage is measured when the output voltage drops by 100 mV from the regulated output voltage level. (For example, the drop
out voltage for TPS7A6550 is measured when the output voltage drops down to 4.9 V from 5 V.)
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Typical Characteristics (continued)
5.1
6
VIN = 14V
5.08
IOUT = 1mA
TA = 25°C
5
5.06
5.04
4
VOUT (V)
5.02
VOUT (V)
IOUT = 100mA
5
4.98
3
2
4.96
4.94
1
4.92
4.9
-50
0
50
TA (°C)
100
0
150
2
0.12
0.1
7
650
TA = 25°C
TA = -40°C
600
550
0.02
500
0
10
20
30
40
VIN (V)
50
TA (°C)
Figure 9. Output Current vs Input Voltage
Figure 10. Output Current Limit vs Ambient Air Temperature
12
11
0
3
VIN = 14V
VOUT = 5V, 3.3V
IOUT step from
10mA to 300mA
11.5
10
9.5
9
100
150
IOUT = 10mA
VOUT = 5V, 3.3V
VIN step from
8V to 28V
2.5
10.5
2
1.5
1
0.5
8.5
8
-50
450
-50
50
Line Regulation (mV)
0
Load Regulation (mV)
6
VIN = 14V
VOUT = 5V, 3.3V
700
ICL (mA)
IOUT (A)
750
TA= 125°C
0.04
5
Figure 8. Output Voltage vs Input Voltage
ILOAD = 100mA
VOUT = 5V, 3.3V
0.06
4
V IN (V)
Figure 7. Output Voltage vs Ambient Air Temperature
0.08
3
0
50
T A (°C)
100
150
Figure 11. Load Regulation vs Ambient Air Temperature
0
-50
0
50
T A (°C)
100
150
Figure 12. Line Regulation vs Ambient Air Temperature
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Typical Characteristics (continued)
120
VIN = 14V
IOUT = 250mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
80
60
80
60
40
40
20
20
0
VIN = 14V
IOUT = 1mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
100
PSRR (dB)
PSRR (dB)
100
120
0
10
100
10k
1k
Frequency (Hz)
100k
1M
10
Figure 13. PSRR at Heavy Load Current
8
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100
10k
1k
Frequency (Hz)
100k
1M
Figure 14. PSRR at Light Load Current
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7 Detailed Description
7.1 Overview
The TPS7A65-Q1 is a monolithic low-dropout linear voltage regulator designed for low-power consumption and
quiescent current less than 25 µA in light-load applications. Because of an integrated fault protection, this device
is well-suited in power supplies for various automotive applications.
This device is available in two fixed-output-voltage versions as follows:
• 5-V output version (TPS7A6550-Q1)
• 3.3-V output version (TPS7A6533-Q1)
See Feature Description for full descriptions of the features of the TPS7A65-Q1 voltage regulator.
7.2 Functional Block Diagram
Band Gap
VIN
CIN
VIN
UVLO
Comp. with
Internal
Reference
VRef1
Temperature Sensor/
Thermal Shutdown
Q1
VRef1
Regulator
Control
Error
Amp
Logic
Control
VOUT
VOUT
COUT
Over Current Detection
Charge
Pump
Oscillator
GND
7.3 Feature Description
7.3.1 Power Up
During power up, the regulator incorporates a protection scheme to limit the current through the pass element
and output capacitor. When the input voltage exceeds a certain threshold (VIN(POWERUP)) level, the output voltage
begins to ramp up; see Figure 15.
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Feature Description (continued)
VIN
VIN(POWERUP)
0
VOUT
5V or 3.3V
0
Figure 15. Power-Up Sequence
7.3.2 Charge-Pump Operation
Charge Pump State
This device has an internal charge pump that turns on or off depending on the input voltage and the output
current. The charge pump switching circuitry does not cause conducted emissions to exceed required thresholds
on the input voltage line. For a given output current, the charge pump stays on at lower input voltages and turns
off at higher input voltages. The charge-pump switching thresholds are hysteretic. Figure 16 and Figure 17 show
typical switching thresholds for the charge pump at light (IOUT < approximately 2 mA) and heavy (IOUT >
approximately 2 mA) loads, respectively.
ON
Hysteresis
OFF
7.8
7.9
VIN (V)
Charge Pump State
Figure 16. Charge-Pump Operation at Light Loads
ON
Hysteresis
OFF
9.2
9.6
VIN (V)
Figure 17. Charge-Pump Operation at Heavy Loads
10
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Feature Description (continued)
7.3.3 Low-Power Mode
At light loads and high input voltages (VIN > approximately 8 V such that charge pump is off) the device operates
in the low-power mode and the quiescent current consumption decreases to 25 µA (typical) as shown in Table 1.
Table 1. Typical Quiescent Current Consumption
IOUT
CHARGE PUMP ON
CHARGE PUMP OFF
IOUT < approximately 2 mA
(light load)
250 µA
25 µA
(low-power mode)
IOUT > approximately 2 mA
(heavy load)
280 µA
70 µA
7.3.4 Undervoltage Shutdown
This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage
(VIN) falls below an internally fixed UVLO threshold level (VIN-UVLO) as shown in Figure 18. This ensures that the
regulator does not latch into an unknown state during low input-voltage conditions. The regulator normally
powers up when the input voltage exceeds the VIN(POWERUP) threshold.
7.3.5 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation, and the output voltage tracks input minus a voltage
based on the load current (IOUT) and switch resistance (RSW) as shown in Figure 18. This allows for a smaller
input capacitor and can possibly eliminate the need of using a boost convertor during cold-crank conditions.
VIN-UVLO
VIN
0
5V or 3.3V
VOUT
0
Tracking
Figure 18. Undervoltage Shutdown and Low-Voltage Tracking
7.3.6 Integrated Fault Protection
This device features integrated fault protection to make them ideal for use in automotive applications. To keep
the device in a safe area of operation during certain fault conditions, the device uses internal current limit
protection and current limit foldback to limit the maximum output current. This protects the device from excessive
power dissipation. For example, during a short-circuit condition on the output, limiting current through the pass
element to ICL protects the device from excessive power dissipation.
7.3.7 Thermal Shutdown
This device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the
output turns on again. Figure 19 shows this.
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Feature Description (continued)
Figure 19. Thermal Cycling Waveform for TPS7A6550-Q1 (VIN = 24 V, IOUT = 300 mA, VOUT = 5 V)
7.4 Device Functional Modes
7.4.1 Operation With VIN Lower Than 4 V
The TPS7A65-Q1 device operates with input voltage above 4 V. The typical UVLO voltage is 3.16 V, the device
can operate at input voltage lower than 4 V. But at input voltage below the actual UVLO, the device shuts down.
7.4.2 Operation With VIN Larger Than 4 V
When VIN is greater than 4 V, if the input voltage is higher than VOUT plus the dropout voltage, the output voltage
is equal to the set value. Otherwise, the output voltage is equal to VIN minus the dropout voltage.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A65-Q1 is a low-dropout linear voltage regulator designed for low power consumption and quiescent
current less than 25 µA in light-load applications. This device features integrated overcurrent protection and a
design to achieve stable operation even with low-ESR ceramic output capacitors. A low-voltage tracking feature
allows for a smaller input capacitor and can possibly eliminate the need of using a boost converter during cold
crank conditions. Because of these features, this device is well-suited in power supplies for various automotive
applications.
8.2 Typical Application
A typical application circuit for TPS7A65-Q1 is Figure 20. Depending on the end application, one may use
different values of external components. An application may require a larger output capacitor during fast load
steps to prevent the output from temporarily dropping down. TI recommends a low-ESR ceramic capacitor with
dielectric of type X5R or X7R. The user can additionally connect a bypass capacitor at the output to decouple
high-frequency noise as per the end application.
TPS7A65-Q1
VIN
VIN
VOUT
VOUT
1µF
to
10µF
10µF
to
22µF
0.1µF
0.1µF
GND
Figure 20. Typical Application Schematic
8.2.1 Design Requirements
Table 2 lists the parameters for this design example.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
11 V to 40 V
Output voltage
3.3 V, 5 V
Output current rating
300 mA maximum
Output capacitor range
1 µF to 10 µF
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8.2.2 Detailed Design Procedure
When using the TPS7A6533-Q1, TPS7A6550-Q1, TI recommends adding a 10-μF to 22-μF capacitor to the input
to keep the input voltage stable. TI also recommends adding a 1-μF to 10-μF low ESR ceramic capacitor to get a
stable output.
8.2.3 Application Curve
Figure 21. TPS7A6533-Q1 Load Transient Waveform
14
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9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range from 11 V to 40 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS7A65-Q1 device, TI
recommends adding an electrolytic capacitor with a value of 10 μF and a ceramic bypass capacitor at the input.
10 Layout
10.1 Layout Guidelines
For the LDO power supply, especially these high voltage and large current ones, layout is an important step. If
layout is not carefully designed, the regulator could not deliver enough output current because of the thermal
limitation. To improve the thermal performance of the device, and maximize the current output at high ambient
temperature, TI recommends spreading the thermal pad as large as possible and putting enough thermal vias on
the thermal pad.
10.1.1 Power Dissipation and Thermal Considerations
Calculate the power dissipated in the device using Equation 1.
PD = IOUT × (VIN - VOUT)) + IQUIESCENT × VIN
where
•
•
•
•
•
PD = continuous power dissipation
IOUT = output current
VIN = input voltage
VOUT = output voltage
IQUIESCENT = quiescent current.
(1)
IQUIESCENT << IOUT; therefore, ignore the term IQUIESCENT × VIN in Equation 1.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ)
using Equation 2.
TJ = TA + (θJA × PD)
where
•
θJA = junction-to-ambient air thermal impedance.
(2)
Calculate the rise in junction temperature due to power dissipation using Equation 3.
ΔT = TJ – TA = (θJA × PD)
(3)
For a given maximum junction temperature (TJ-Max), calculate the maximum ambient air temperature (TA-Max) at
which the device can operate using Equation 4.
TA-Max = TJ-Max – (θJA × PD)
(4)
Example
If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT = 250 µA and θJA= 30˚C/W, the continuous power dissipated
in the device is 0.9 W. The rise in junction temperature due to power dissipation is 27˚C. For a maximum junction
temperature of 150˚C, maximum ambient air temperature at which the device can operate is 123˚C.
For adequate heat dissipation, TI recommends soldering the power pad (exposed heat sink) to the thermal land
pad on the PCB. Doing this provides a heat conduction path from the die to the PCB and reduces overall
package thermal resistance. Figure 22 shows power derating curves for the TPS7A65-Q1 family of devices in the
KVU (DPAK) package.
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Layout Guidelines (continued)
4
3.5
Power Dissipated (W)
3
JESD 51-5 (KVU)
2.5
JESD 51-3 (KVU)
2
1.5
1
0.5
0
0
25
50
75
100
125
150
Ambient Air Temperature (°C)
Figure 22. Power Derating Curves
For optimum thermal performance, TI recommends using a high-K PCB with thermal vias between the ground
plane and solder pad or thermal land pad. Figure 23 (a) and (b) show this. Further, a design can improve the
heat-spreading capabilities of a PCB considerably by using a thicker ground plane and a thermal land pad with a
larger surface area.
16
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SLVSA98E – MAY 2010 – REVISED MAY 2018
Layout Guidelines (continued)
Exposed Tab
Thermal Via
Thermal Land Pad
PCB
Ground Plane
(a) Before soldering
(b) After soldering
Figure 23. Using a Multilayer PCB and Thermal Vias for Adequate Heat Dissipation
Keeping other factors constant, the surface area of the thermal land pad contributes to heat dissipation only to a
certain extent. Figure 24 shows the variation of θJA with surface area of the thermal land pad (soldered to the
exposed pad) for the KVU package.
55
q JA (°C/W)
50
45
KVU (DPAK) (JESD 51-3)
40
35
30
0
200
400
600
800
1000
Thermal Pad Area (sq. mm)
Figure 24. θJA vs Thermal Pad Area
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10.2 Layout Example
GND
VIN
VOUT
Figure 25. Layout Recommendation
18
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SLVSA98E – MAY 2010 – REVISED MAY 2018
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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19
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A6533QKVURQ1
ACTIVE
TO-252
KVU
3
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
7A6533Q1
TPS7A6550QKVURQ1
ACTIVE
TO-252
KVU
3
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
7A6550Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7A6533QKVURQ1
TO-252
KVU
3
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
TPS7A6550QKVURQ1
TO-252
KVU
3
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A6533QKVURQ1
TO-252
KVU
3
2500
340.0
340.0
38.0
TPS7A6550QKVURQ1
TO-252
KVU
3
2500
340.0
340.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
KVU0003A
TO-252 - 2.52 mm max height
SCALE 1.500
TO-252
10.41
9.40
B
1.27
0.89
6.22
5.97
A
1
2.29
2
4.58
5.460
4.953
6.70
6.35
3
0.890
0.635
C A B
1.02
0.61
3X
0.25
NOTE 3
OPTIONAL
0.61
0.46
2.52 MAX
C
0.61
0.46
SEE DETAIL A
5.21 MIN
3
2
4.32
MIN
4
1
EXPOSED
THERMAL PAD
NOTE 3
0.51
GAGE PLANE
0 -8
0.13
0.00
1.78
1.40
A 7.000
DETAIL A
TYPICAL
4218915/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Shape may vary per different assembly sites.
4. Reference JEDEC registration TO-252.
www.ti.com
EXAMPLE BOARD LAYOUT
KVU0003A
TO-252 - 2.52 mm max height
TO-252
2X (2.75)
2X (1)
(6.15)
1
4
(4.58)
SYMM
(5.55)
3
(R0.05) TYP
(4.2)
(2.5)
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218915/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers
SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).
6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
KVU0003A
TO-252 - 2.52 mm max height
TO-252
(1.18) TYP
2X (1)
2X (2.75)
(0.14)
1
(R0.05)
(1.33) TYP
SYMM
(4.58)
4
3
20X (0.98)
(4.2)
20X (1.13)
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
65% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4218915/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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