Texas Instruments | TPS65023x Power Management IC (PMIC) With 3 DC/DCs, 3 LDOs, I2C Interface and DVS (Rev. L) | Datasheet | Texas Instruments TPS65023x Power Management IC (PMIC) With 3 DC/DCs, 3 LDOs, I2C Interface and DVS (Rev. L) Datasheet

Texas Instruments TPS65023x Power Management IC (PMIC) With 3 DC/DCs, 3 LDOs, I2C Interface and DVS (Rev. L) Datasheet
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TPS65023, TPS65023B
SLVS670L – JUNE 2006 – REVISED MAY 2018
TPS65023x Power Management IC (PMIC) With 3 DC/DCs, 3 LDOs, I2C Interface and DVS
1 Features
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1.7-A, 90% Efficient Step-Down Converter for
Processor Core (VDCDC1)
1.2-A, Up to 95% Efficient Step-Down Converter
for System Voltage (VDCDC2)
1.0-A, 92% Efficient Step-Down Converter for
Memory Voltage (VDCDC3)
30-mA LDO and Switch for Real Time Clock
(VRTC)
2 × 200-mA General-Purpose LDO
Dynamic Voltage Management for Processor Core
Preselectable LDO Voltage Using Two Digital
Input Pins
Externally Adjustable Reset Delay Time
Battery Backup Functionality
Separate Enable Pins for Inductive Converters
I2C-Compatible Serial Interface
I2C™ Setup and Hold Timing:
– TPS65023: 300 ns
– TPS65023B: 100 ns
85-μA Quiescent Current
Low Ripple PFM Mode
Thermal Shutdown Protection
40-Pin, 5-mm × 5-mm WQFN Package
The TPS65023x also integrates two general-purpose
200-mA LDO voltage regulators, which are enabled
with an external input pin. Each LDO operates with
an input voltage range from 1.5 V to 6.5 V, thus
allowing them to be supplied from one of the stepdown converters or directly from the battery. The
default output voltage of the LDOs can be digitally set
to 4 different voltage combinations using the
DEFLDO1 and DEFLDO2 pins. The serial interface
can be used for dynamic voltage scaling, masking
interrupts, or for disabling or enabling and setting the
LDO output voltages. The interface is compatible with
both the fast and standard mode I2C specifications,
allowing transfers at up to 400 kHz. The TPS65023x
is available in a 40-pin WQFN package, and operates
over a free-air temperature of –40°C to 85°C.
Device Information(1)
PART NUMBER
Digital Media Players
Internet Audio Players
Digital Still Cameras
Smart Phones
Supply DaVinci™ DSP Family Solutions
3 Description
The TPS65023x device is an integrated power
management IC for applications powered by one
Li-Ion or Li-Polymer cell, which require multiple power
rails. The TPS65023x provides three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O, and memory rails in a
processor-based system. The core converter allows
for on-the-fly voltage changes through serial
interface, allowing the system to implement dynamic
power savings. All three step-down converters enter a
low-power mode at light load for maximum efficiency
across the widest possible range of load currents.
WQFN (40)
TPS65023B
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
TPS6502x
Example SoC
2.2 µH
Monitored
Voltage1
R1
2 Applications
•
•
•
•
•
PACKAGE
TPS65023
DCDC1
R2
PWRFAIL
+
±
R4
LOWBATT
+
±
Monitored
Voltage2
R3
CORE
22 µF
2.2 µH
1.8-V IO
Domain
DCDC2
22 µF
3.3-V IO
Domain
LDO1
2.2 µF
BACKUP
RTC AND
RESPWRON
VBACKUP
2.2 µF
System Reset
Memory
2.2 µH
DCDC3
DCDC1_EN
DCDC2_EN
DCDC3_EN
LDO_EN
DEFDCDC1
DEFDCDC2
DEFDCDC3
22 µF
Memory
Enables
and
Vout
Select
LDO1
Peripherals
2.2 µF
System Platform
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65023, TPS65023B
SLVS670L – JUNE 2006 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
7
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Electrical Characteristics: Supply Pins VCC,
VINDCDC1, VINDCDC2, VINDCDC3...................... 10
6.7 Electrical Characteristics: Supply Pins VBACKUP,
VSYSIN, VRTC, VINLDO......................................... 10
6.8 Electrical Characteristics: VDCDC1 Step-Down
Converter ................................................................. 11
6.9 Electrical Characteristics: VDCDC2 Step-Down
Converter ................................................................. 12
6.10 Electrical Characteristics: VDCDC3 Step-Down
Converter ................................................................. 12
6.11 I2C Timing Requirements for TPS65023B ............ 13
6.12 Typical Characteristics .......................................... 16
7
Detailed Description ............................................ 21
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
21
22
22
27
28
31
Application and Implementation ........................ 37
8.1 Application Information............................................ 37
8.2 Typical Application ................................................. 39
9
Power Supply Recommendations...................... 44
9.1 Requirements for Supply Voltages Below 3.0 V ..... 44
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
47
47
47
12 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (December 2015) to Revision L
Page
•
Changed the title of the data sheet ....................................................................................................................................... 1
•
Replaced references of TI PowerPAD IC package with thermal pad ................................................................................... 6
•
Added the Device Support and Documentation Support sections ....................................................................................... 46
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 46
Changes from Revision J (September 2011) to Revision K
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision I (July 2010) to Revision J
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Page
Added Thermal Information Table and deleted Dissipation Ratings Table ............................................................................ 8
Changes from Revision H (December 2009) to Revision I
Page
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Added I2C Compatible Serial Interface to Features list .......................................................................................................... 1
•
Added TPS65023B device specs ........................................................................................................................................... 1
•
Added ordering info for TPS65023B device. ......................................................................................................................... 1
•
Added specs for TPS65023B device...................................................................................................................................... 8
2
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Copyright © 2006–2018, Texas Instruments Incorporated
Product Folder Links: TPS65023 TPS65023B
TPS65023, TPS65023B
www.ti.com
SLVS670L – JUNE 2006 – REVISED MAY 2018
•
Changed "VBACKUP threshold" test condition typographical error from "VBACKUP falling" to "VBACKUP rising" ........... 11
•
Added specs for TPS65023B device.................................................................................................................................... 13
•
Added Differences table for TPS65023 and TPS65023B devices ....................................................................................... 39
Changes from Revision G (October 2008) to Revision H
Page
•
Changed IO(DCDC1) MAX from: 1500 mA to: 1700 mA ............................................................................................................. 7
•
Added High level input voltage for the SDAT pin ................................................................................................................... 8
•
Changed IO from:1500 mA MIN to 1700 mA ....................................................................................................................... 11
•
Changed IO maximum from:1.5 A to: 1.7 A for VDCDC1 fixed and adjustable output voltage test condition specs. .......... 11
•
Changed IO maximum from: 1500 mA to: 1700 mA for VDCDC1 Load Regulation test condition ...................................... 11
•
Changed VDCDC1 "soft-start ramp time" spec to: "tStart and tRamp" specifications with MIN TYP MAX values. .................. 11
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Changed VDCDC2 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values. ................. 12
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Changed VDCDC3 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values. ................. 13
•
Changed FBD graphic to show 1700 mA for DCDC1 Buck Converter ................................................................................ 22
•
Changed text string from: "1.2 V or 1.8 V" to: "1.2 V to 1.6 V" in the STEP-DOWN CONVERTERS.,VDCDC1....
description. ........................................................................................................................................................................... 24
•
Changed graphic entity to the one used in the Application Note SLVA273 ......................................................................... 39
Changes from Revision F (July 2007) to Revision G
•
Page
Changed the Interrupt Management and the INT Pin section.............................................................................................. 28
Changes from Revision E (January 2007) to Revision F
•
Page
Changed text string from: "If it is tied to VCC, the default is 2.5 V" To: "If it is tied to VCC, the default is 3.3 V" ............... 24
Changes from Revision D (December 2006) to Revision E
Page
•
Changed LDO1 output voltage range from: 3.3 to: 3.3 .......................................................................................................... 9
•
Changed text string from: "VDCDC2 converter defaults to 1.8 V or 2.5 V" to: "VDCDC2 converter defaults to 1.8 V
or 3.3 V"................................................................................................................................................................................ 24
Changes from Revision C (October 2006) to Revision D
•
Page
Changed Typical Configuration for Ti DaVinci Processors .................................................................................................. 39
Changes from Revision B (June 2006) to Revision C
Page
•
Changed from: AD Coupled to: AD Coupled - Figure 16 .................................................................................................... 17
•
Changed from: AD Coupled to: AD Coupled - Figure 17 .................................................................................................... 18
Changes from Revision A (June 2006) to Revision B
Page
•
Changed from: 1.5A and 97% Efficient Step-Down to: 1.7A and 90% Efficient Step-Down.................................................. 1
•
Changed from: 6 mm × 6 mm QFN Package to: 5 mm × 5 mm QFN Package .................................................................... 1
•
Changed from: RHA package to: RSB package .................................................................................................................... 1
•
Changed from:O(DCDC2) to: IO(DCDC1) ........................................................................................................................................ 7
•
Changed Forward current limit - removed TBD and added values ...................................................................................... 11
Copyright © 2006–2018, Texas Instruments Incorporated
Product Folder Links: TPS65023 TPS65023B
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TPS65023, TPS65023B
SLVS670L – JUNE 2006 – REVISED MAY 2018
www.ti.com
•
Changed Fixed output voltage - removed TBD and added values ...................................................................................... 11
•
Changed Fixed output voltage - removed TBD and added values ...................................................................................... 12
•
Added VINDCDC3 = 3.6 V to Maximum output current ....................................................................................................... 12
•
Changed Fixed output voltage - removed TBD and added values ...................................................................................... 13
•
Changed Figure 3 (DVS Timing) .......................................................................................................................................... 15
•
Changed Figure 11 (Graph - DCDC2: OUTPUT VOLTAGE)............................................................................................... 17
•
Added Figure 12 (Graph - DCDC3: OUTPUT VOLTAGE ).................................................................................................. 17
•
Changed Figure 20 (Graph - VDCDC2 OUTPUT VOLTAGE RIPPLE) ............................................................................... 18
•
Added Reset Condition of DCDC1 Information .................................................................................................................... 37
•
Changed Typical Configuration for Ti DaVinci Processors .................................................................................................. 39
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Changed from: TPS65023 typically use a 3.3 μH output inductor to: TPS65023 typically use a 2.2 μH output inductor.... 40
•
Changed from: VDCDC3 to: VDCDC1 ................................................................................................................................. 41
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Changed from: VDEFDCDC3 to: DEFDCDC1 ..................................................................................................................... 41
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Changed from: 2.5 V to 3.3 V (Table 20) ............................................................................................................................. 41
Changes from Original (May 2006) to Revision A
Page
•
Changed Electrical Characteristics: VDCDC1 Step-Down Converter .................................................................................. 11
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Changed Electrical Characteristics: VDCDC3 Step-Down Converter ................................................................................. 12
•
Changed CON_CTRL Register Address - Column B0 default value changed from 1 to 0.................................................. 33
•
Changed VDCDC# to VDCDC1 ........................................................................................................................................... 35
4
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Copyright © 2006–2018, Texas Instruments Incorporated
Product Folder Links: TPS65023 TPS65023B
TPS65023, TPS65023B
www.ti.com
SLVS670L – JUNE 2006 – REVISED MAY 2018
5 Pin Configuration and Functions
PWRFAIL
DEFDCDC2
PGND2
VDCDC2
L2
VINDCDC2
PWRFAIL_SNS
VCC
LOWBAT_SNS
AGND1
RSB Package
40-Pin WQFN
Top View
40 39 38 37 36 35 34 33 32 31
DEFDCDC3
1
30
SCLK
VDCDC3
2
29
SDAT
3
28
INT
L3
4
27
RESPWRON
VINDCDC3
5
26
TRESPWRON
VINDCDC1
6
25
DCDC1_EN
L1
7
24
DCDC2_EN
PGND1
8
23
DCDC3_EN
VDCDC1
9
22
LDO_EN
10
21
LOWBAT
PGND3
DEFDCDC1
VLDO1
VINLDO
VLDO2
VRTC
AGND2
VBACKUP
VSYSIN
DEFLDO1
DEFLDO2
HOT_RESET
11 12 13 14 15 16 17 18 19 20
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND1
40
—
Analog ground. All analog ground pins are connected internally on the chip.
AGND2
17
—
Analog ground. All analog ground pins are connected internally on the chip.
DCDC1_EN
25
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN
24
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN
23
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DEFDCDC1
10
I
Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V DEFDCDC1 can also be
connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1
converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2
32
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC2 can also be
connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2
converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3
1
I
Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC3 can also be
connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3
converter is set in a range from 0.6 V to VINDCDC3 V.
L1
7
—
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2
35
—
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3
4
—
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1
8
—
Power ground for VDCDC1 converter
Copyright © 2006–2018, Texas Instruments Incorporated
Product Folder Links: TPS65023 TPS65023B
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TPS65023, TPS65023B
SLVS670L – JUNE 2006 – REVISED MAY 2018
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
PGND2
34
—
Power ground for VDCDC2 converter
PGND3
3
—
Power ground for VDCDC3 converter
VCC
37
I
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters.
VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
VCC also supplies serial interface block.
VDCDC1
9
I
VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
VDCDC2
33
I
VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
VDCDC3
2
I
VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VINDCDC1
6
I
Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage
supply as VINDCDC2, VINDCDC3, and VCC.
VINDCDC2
36
I
Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage
supply as VINDCDC1, VINDCDC3, and VCC.
VINDCDC3
5
I
Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage
supply as VINDCDC1, VINDCDC2, and VCC.
Thermal Pad
—
—
Connect the power pad to analog ground
LDO REGULATOR SECTION
DEFLD01
12
I
Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02
13
I
Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
LDO_EN
22
I
Enable input for LDO1 and LDO2. A logic high enables the LDOs and a logic low disables the LDOs.
VBACKUP
15
I
Connect the backup battery to this input pin
VINLDO
19
I
Input voltage for LDO1 and LDO2
VLDO1
20
O
Output voltage of LDO1
VLDO2
18
O
Output voltage of LDO2
VRTC
16
O
Output voltage of the LDO and switch for the real time clock
VSYSIN
14
I
Input of system voltage for VRTC switch
CONTROL AND I2C SECTION
HOT_RESET
11
I
Push button input that reboots or wakes up the processor through the RESPWRON output pin.
INT
28
O
Open-drain output
LOW_BAT
21
O
Open-drain output of LOW_BAT comparator
LOWBAT_SNS
39
I
Input for the comparator driving the LOW_BAT output.
PWRFAIL
31
O
Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS
38
I
Input for the comparator driving the PWRFAIL output
RESPWRON
27
O
Open-drain system reset output
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
TRESPWRON
26
I
6
Serial interface data and address
Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms
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Product Folder Links: TPS65023 TPS65023B
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SLVS670L – JUNE 2006 – REVISED MAY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
MIN
MAX
UNIT
–0.3
7
V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3,
PGND3
2000
mA
Peak current at all other pins
1000
mA
Input voltage on all pins except AGND and PGND pins with respect to AGND
Continuous total power dissipation
TA
Operating free-air temperature
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
See Thermal Information
–40
–65
85
°C
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
VO
NOM
2.5
6
Output voltage for VDCDC1 step-down converter (1)
0.6
VINDCDC1
Output voltage for VDCDC2 step-down converter (1)
0.6
VINDCDC2
(1)
0.6
VINDCDC3
Output voltage for VDCDC3 step-down converter
VI
Input voltage for LDOs (VINLDO1, VINLDO2)
VO
Output voltage for LDOs (VLDO1, VLDO2)
IO(DCDC1)
Output current at L1
1.5
6.5
1
VINLDO1–2
1700
Inductor at L1 (2)
1.5
2.2
CI(DCDC1)
Input capacitor at VINDCDC1
(2)
10
CO(DCDC1)
Output capacitor at VDCDC1
(2)
10
22
IO(DCDC2)
Output current at L2
1.5
2.2
Inductor at L2
(2)
10
CO(DCDC2)
Output capacitor at VDCDC2
(2)
10
IO(DCDC3)
Output current at L3
CI(DCDC3)
1.5
Input capacitor at VINDCDC3 (2)
10
(2)
10
CO(DCDC3)
Output capacitor at VDCDC3
CI(VCC)
Input capacitor at VCC
Ci(VINLDO)
Input capacitor at VINLDO
CO(VLDO1-2)
(1)
(2)
(2)
(2)
Output capacitor at VLDO1, VLDO2
(2)
V
V
V
V
mA
μF
μF
mA
μH
μF
22
μF
1000
(2)
Inductor at L3
UNIT
μH
1200
(2)
Input capacitor at VINDCDC2
CI(DCDC2)
MAX
Input voltage step-down converters
(VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same
voltage rail
2.2
mA
μH
μF
22
μF
1
μF
1
μF
2.2
μF
When using an external resistor divider at DEFDCDC3, DEFDCDC2, and DEFDCDC1
See Application Information section for more information.
Copyright © 2006–2018, Texas Instruments Incorporated
Product Folder Links: TPS65023 TPS65023B
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SLVS670L – JUNE 2006 – REVISED MAY 2018
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
IO(VLDO1-2)
Output current at VLDO1, VLDO2
CO(VRTC)
Output capacitor at VRTC
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
(2)
NOM
UNIT
200
mA
4.7
μF
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (3)
(3)
MAX
1
85
°C
125
°C
10
Ω
Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted
accordingly.
6.4 Thermal Information
TPS65023x
THERMAL METRIC
(1)
RSB (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
32.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.3
°C/W
RθJB
Junction-to-board thermal resistance
13.6
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
5.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023
VIH
High level input voltage (except the
SDAT pin)
Resistor pullup at SCLK = 4.7 kΩ, pulled to
VRTC
1.3
VCC
V
VIH
High level input voltage for the SDAT pin
Resistor pullup at SDAT = 4.7 kΩ, pulled to
VRTC
1.45
VCC
V
VIL
Low level input voltage
Resistor pullup at SCLK and SDAT = 4.7 kΩ,
pulled to VRTC
0
0.4
V
IH
Input bias current
0.1
μA
0.01
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023B
VIH
High level input voltage for the SCLK pin
Rpullup at SCLK = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V
1.4
VCC
V
VIH
High level input voltage for the SDAT pin
Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V
1.69
VCC
V
VIH
High level input voltage for the SDAT pin
Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 4.5 V
1.55
VCC
V
VIL
Low level input voltage
Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to
VRTC
0
0.35
V
IH
Input bias current
0.1
μA
V
0.01
CONTROL SIGNALS: HOT_RESET, DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH
High-level input voltage
1.3
VCC
VIL
Low-level input voltage
0
0.4
V
IIB
Input bias current
0.01
0.1
μA
tdeglitch
Deglitch time at HOT_RESET
30
35
ms
(1)
8
25
Typical values are at TA = 25°C, unless otherwise noted.
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Electrical Characteristics (continued)
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT)
VOH
High-level output voltage
VOL
Low-level output voltage
IIL = 5 mA
6
Duration of low pulse at RESPWRON
External capacitor 1 nF
ICONST
Internal charge / discharge current on pin
Used for generating RESPWRON delay
TRESPWRON
TRESPWRON_LOWTH
Internal lower comparator threshold on
pin TRESPWRON
Used for generating RESPWRON delay
TRESPWRON_UPTH
Internal upper comparator threshold on
pin TRESPWRON
Used for generating RESPWRON delay
Resetpwron threshold
VRTC falling
Resetpwron threshold
VRTC rising
Leakage current
Output inactive high
ILK
0
0.3
100
V
V
ms
1.7
2
2.3
μA
0.225
0.25
0.275
V
0.97
1
1.103
V
–3%
2.4
3%
V
–3%
2.52
3%
V
0.1
μA
1.5
6.5
V
1
3.15
V
1
3.3
V
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
VI
Input voltage range for LDO1, 2
VO(LD01)
LDO1 output voltage range
VO(LDO2)
LDO2 output voltage range
IO
Maximum output current for LDO1,
LDO2
I(SC)
LDO1 and LDO2 short-circuit current
limit
VI = 1.8 V, VO = 1.3 V
200
VI = 1.5 V, VO = 1.3 V
V(LDO1) = GND, V(LDO2) = GND
400
IO = 50 mA, VINLDO = 1.8 V
Minimum voltage drop at LDO1, LDO2
mA
120
mA
120
IO = 50 mA, VINLDO = 1.5 V
65
IO = 200 mA, VINLDO = 1.8 V
150
mV
300
Output voltage accuracy for LDO1,
LDO2
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1, 2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2
IO = 0 mA to 50 mA
–1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
1%
10
μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High-level input voltage
1.3
VCC
VIL
Low-level input voltage
0
0.1
V
0.05
μA
Input bias current
0.001
V
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO
Internal UVLO
VCC falling
V(UVLO_HYST)
Internal UVLO comparator hysteresis
–2%
2.35
2%
120
V
mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)
Falling threshold
Hysteresis
Propagation delay
–1%
1
1%
V
40
50
60
mV
10
μs
25-mV overdrive
POWER-GOOD
V(PGOODF)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, decreasing
–12%
–10%
–8%
V(PGOODR)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, increasing
–7%
–5%
–3%
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6.6 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
I(q)
II
I(q)
Operating quiescent
current, PFM
Current into VCC; PWM
Quiescent current
TEST CONDITIONS
MIN
TYP (1)
MAX
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
85
100
All 3 DCDC converters enabled, zero
load, and no switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
78
90
DCDC1 and DCDC2 converters
enabled, zero load, and no switching,
LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
57
70
DCDC1 converter enabled, zero load,
and no switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
43
55
All 3 DCDC converters enabled and
running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
2
3
DCDC1 and DCDC2 converters
enabled and running in PWM, LDOs
off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
1.5
2.5
DCDC1 converter enabled and running VCC = 3.6 V, VBACKUP = 3 V;
in PWM, LDOs off
V(VSYSIN) = 0 V
0.85
2
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
23
33
μA
VCC = 2.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
3.5
5
μA
43
μA
All converters disabled, LDOs off
μA
VCC = 3.6 V, VBACKUP = 0 V;
V(VSYSIN) = 0 V
(1)
UNIT
All 3 DCDC converters enabled, zero
load, and no switching, LDOs enabled
mA
Typical values are at TA = 25°C, unless otherwise noted.
6.7 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
20
33
μA
3
μA
UNIT
VBACKUP, VSYSIN, VRTC
I(q)
Operating quiescent current
VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP
I(SD)
Operating quiescent current
VBACKUP < V_VBACKUP, current into
VBACKUP
2
VRTC LDO output voltage
VSYSIN = VBACKUP = 0 V, IO = 0 mA
3
Output current for VRTC
VSYSIN < 2.57 V and VBACKUP < 2.57 V
30
mA
VRTC short-circuit current limit
VRTC = GND; VSYSIN = VBACKUP = 0 V
100
mA
Maximum output current at VRTC for
RESPWRON = 1
VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V
Output voltage accuracy for VRTC
VSYSIN = VBACKUP = 0 V; IO = 0 mA
–1%
1%
Line regulation for VRTC
VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA
–1%
1%
Load regulation VRTC
IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V
–3%
1%
Regulation time for VRTC
Load change from 10% to 90%
Input leakage current at VSYSIN
VSYSIN < V_VSYSIN
IO
VO
Ilkg
30
mA
10
rDS(on) of VSYSIN switch
μA
12.5
Ω
12.5
Ω
2.73
3.75
V
Input voltage range at VSYSIN (2)
2.73
3.75
V
3%
V
VSYSIN threshold
10
μs
2
Input voltage range at VBACKUP (2)
rDS(on) of VBACKUP switch
(1)
(2)
V
VSYSIN falling
–3%
2.55
Typical values are at TA = 25°C, unless otherwise noted.
Based on the requirements for the Intel PXA270 processor.
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Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO (continued)
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
VSYSIN threshold
VSYSIN rising
–3%
2.65
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.55
3%
V
VBACKUP threshold
VBACKUP rising
–3%
2.65
3%
V
I(q)
Operating quiescent current
Current per LDO into VINLDO
for LDO_CTRL = 0x0
16
30
μA
I(SD)
Shutdown current
Total current for both LDOs into VINLDO,
VLDO = 0 V
0.1
1
μA
VINLDO
6.8 Electrical Characteristics: VDCDC1 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
IO
Maximum output current
I(SD)
Shutdown supply current in VINDCDC1
DCDC1_EN = GND
0.1
1
μA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
125
261
mΩ
Ilkg
P-channel leakage current
VINDCDC1 = 6 V
2
μA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
130
260
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
μA
Forward current limit (P-channel and
N-channel)
2.5 V < VI(MAIN) < 6 V
1.94
2.19
2.44
A
1.95
2.25
2.55
MHz
1700
Oscillator frequency
Fixed output voltage
FPWMDCDC1 = 0
6
UNIT
Input voltage range, VINDCDC1
fS
2.5
MAX
VI
VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.7 A
–2%
2%
VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.7 A
–1%
1%
Adjustable output voltage with resistor divider
at DEFDCDC1; FPWMDCDC1 = 0
VINDCDC1 = VDCDC1 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.7 A
–2%
2%
Adjustable output voltage with resistor divider
at DEFDCDC1; FPWMDCDC1 = 1
VINDCDC1 = VDCDC1 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.7 A
–1%
1%
Line Regulation
VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Fixed output voltage
FPWMDCDC1 = 1
All VDCDC1
0%
V
Load Regulation
IO = 10 mA to 1700 mA
tStart
Start-up time
Time from active EN to start switching
145
175
200
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
Internal resistance from L1 to GND
(1)
0.25%
A
1
VDCDC1 discharge resistance
DCDC1 discharge = 1
V
mA
300
μs
μs
MΩ
Ω
Typical values are at TA = 25°C, unless otherwise noted.
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6.9 Electrical Characteristics: VDCDC2 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
2.5
MAX
6
UNIT
VI
Input voltage range, VINDCDC2
DEFDCDC2 = GND
1200
IO
Maximum output current
VINDCDC2 = 3.6 V;
3.3 V - 1% ≤ VDCDC2 ≤ 3.3V + 1%
1000
I(SD)
Shutdown supply current in VINDCDC2
DCDC2_EN = GND
0.1
1
μA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
140
300
mΩ
Ilkg
P-channel leakage current
VINDCDC2 = 6 V
rDS(on)
N-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
Ilkg
N-channel leakage current
V(DS) = 6 V
ILIMF
Forward current limit (P-channel and Nchannel)
2.5 V < VINDCDC2 < 6 V
fS
Oscillator frequency
mA
2
μA
150
297
mΩ
7
10
μA
1.74
1.94
2.12
A
1.95
2.25
2.55
MHz
VDCDC2 = 1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–2%
2%
VDCDC2 = 3.3 V
VINDCDC2 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–1%
1%
VDCDC2 = 1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–2%
2%
VDCDC2 = 3.3 V
VINDCDC2 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC2 FPWMDCDC2=0
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6
V; 0 mA ≤ IO ≤ 1 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=1
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6
V; 0 mA ≤ IO ≤ 1 A
–1%
1%
Line Regulation
VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6
V; IO = 10 mA
Fixed output voltage
FPWMDCDC2=0
Fixed output voltage
FPWMDCDC2=1
V
0%
V
Load Regulation
IO = 10 mA to 1000 mA
tStart
Start-up time
Time from active EN to start switching
145
0.25%
175
200
µs
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
μs
Internal resistance from L2 to GND
1
VDCDC2 discharge resistance
(1)
A
DCDC2 discharge =1
MΩ
Ω
300
Typical values are at TA = 25°C, unless otherwise noted.
6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
VI
MIN TYP (1)
TEST CONDITIONS
Input voltage range, VINDCDC3
2.5
DEFDCDC3 = GND
MAX
6
UNIT
V
1000
IO
Maximum output current
VINDCDC3 = 3.6 V;
3.3V - 1% ≤ VDCDC3 ≤ 3.3V + 1%
I(SD)
Shutdown supply current in VINDCDC3
DCDC3_EN = GND
0.1
1
μA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
310
698
mΩ
Ilkg
P-channel leakage current
VINDCDC3 = 6 V
0.1
2
μA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
220
503
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
μA
Forward current limit (P-channel and Nchannel)
2.5 V < VINDCDC3 < 6 V
1.49
1.69
A
(1)
12
mA
525
1.28
Typical values are at TA = 25°C, unless otherwise noted.
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Electrical Characteristics: VDCDC3 Step-Down Converter (continued)
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER
fS
TEST CONDITIONS
Oscillator frequency
MIN TYP (1)
MAX
UNIT
1.95
2.55
MHz
2.25
VDCDC3 = 1.8 V
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
–2%
2%
VDCDC3 = 3.3 V
VINDCDC3 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1 A
–1%
1%
VDCDC3 = 1.8 V
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
–2%
2%
VDCDC3 = 3.3 V
VINDCDC3 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC3 FPWMDCDC3=0
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to
6 V; 0 mA ≤ IO ≤ 800 mA
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC3; FPWMDCDC3=1
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to
6 V; 0 mA ≤ IO ≤ 800 mA
–1%
1%
Line Regulation
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to
6 V; IO = 10 mA
Load Regulation
IO = 10 mA to 1000 mA
tStart
Start-up time
Time from active EN to start switching
145
175
200
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
Fixed output voltage
FPWMDCDC3=0
Fixed output voltage
FPWMDCDC3=1
0%
V
0.25%
A
Internal resistance from L3 to GND
1
VDCDC3 discharge resistance
DCDC3 discharge =1
µs
μs
MΩ
Ω
300
6.11 I2C Timing Requirements for TPS65023B
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5 V to 5.5 V, VBACKUP = 3.0 V, TA = –40 °C to 85 °C
MIN
MAX
UNIT
400
kHz
fMAX
Clock frequency
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
tF
DATA and CLK fall time
th(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated)
600
ns
tsu(DATA)
Setup time for repeated START condition
600
ns
th(DATA)
Data input hold time
100
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
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ns
ns
300
ns
300
ns
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Figure 1. HOT_RESET Timing
VCC
2.35V
1.9V
1.2V
2.47V
1.9V
0.8V
UVLO*
VRTC
2.52V
2.4V
3.0V
RESPWRON
tNRESPWRON
DCDCx_EN
Ramp within
800 μs
VO DCDCx
slope depending
on load
LDO_EN
VO LDOx
*... internal signal
VSYSIN=VBACKUP=GND;
VINLDO=VCC
Figure 2. Power-Up and Power-Down Timing
14
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SLVS670L – JUNE 2006 – REVISED MAY 2018
Figure 3. DVS Timing
DATA
t(BUF)
th(STA)
t(LOW)
tf
tr
CLK
t(HIGH)
th(STA)
th(DATA)
STO
STA
tsu(STA)
tsu(STO)
tsu(DATA)
STA
STO
Figure 4. Serial I/F Timing Diagram
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6.12 Typical Characteristics
Table 1. Table of Graphs
FIGURE
η
Figure 5, Figure 6, Figure 7,
Figure 8, Figure 9, Figure 10
Efficiency
vs Output current
Output voltage
vs Output current at 85°C
Line transient response
Figure 13, Figure 14, Figure 15
Load transient response
Figure 16, Figure 17, Figure 18
VDCDC2 PFM operation
Figure 19
VDCDC2 low ripple PFM operation
Figure 20
VDCDC2 PWM operation
Figure 21
Startup VDCDC1, VDCDC2 and VDCDC3
Figure 22
Startup LDO1 and LDO2
Figure 23
Line transient response
Figure 24, Figure 25, Figure 26
Load transient response
Figure 27, Figure 28, Figure 29
100
100
VI = 2.5 V
90
80
90
VI = 3.6 V
Efficiency - %
Efficiency - %
50
VI = 5 V
40
VI = 3.6 V
60
50
40
VI = 4.2 V
30
30
TA = 25°C
VO = 1.2 V
PWM/PFM Mode
20
10
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
20
0
0.01
10 k
90
80
80
Efficiency - %
60
VI = 5 V
40
30
0.1
1k
10 k
1
10
100
IO - Output Current - mA
1k
60
50
VI = 4.2 V
40
VI = 5 V
20
10
10 k
Figure 7. DCDC2: Efficiency vs Output Current
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VI = 2.5 V
VI = 3.6 V
30
TA = 25°C
VO = 1.8 V
PWM/PFM Mode
10
0
0.01
TA = 25°C
VO = 1.8 V
PWM Mode
70
VI = 4.2 V
20
1
10
100
IO - Output Current - mA
Figure 6. DCDC1: Efficiency vs Output Current
VI = 2.5 V
50
0.1
100
VI = 3.6 V
70
VI = 5 V
10
Figure 5. DCDC1: Efficiency vs Output Current
100
Efficiency - %
VI = 2.5 V
70
VI = 4.2 V
60
90
TA = 25°C
VO = 1.2 V
PWM Mode
80
70
16
Figure 11, Figure 12
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
10 k
Figure 8. DCDC2: Efficiency vs Output Current
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100
90 VI = 3.6 V
90
80
80
70
60
VI = 5 V
50
40
30
VI = 3.6 V
60
50
VI = 4.2 V
40
VI = 5 V
30
20
20
TA = 25°C
VO = 1.8 V
PWM/PFM Mode
10
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
10
0
0.01
10 k
Figure 9. DCDC3: Efficiency vs Output Current
3.354
TA = 85°C
DEFDCDC2 = VINDCDC2
1k
10 k
TA = 85°C
DEFDCDC3 = VINDCDC3
3.354
VO - Output Voltage - V
VI = 3.8 V
3.294
VI = 3.7 V
3.274
3.234
0.1
1
10
100
IO - Output Current - mA
3.334
3.314
3.254
0.1
Figure 10. DCDC3: Efficiency vs Output Current
3.334
VO - Output Voltage - V
VI = 2.5 V
TA = 25°C
VO = 1.8 V
PWM Mode
70
VI = 4.2 V
Efficiency - %
Efficiency - %
100
VI = 2.5 V
VI = 3.5 V
VI = 3.6 V
3.314
VI = 4 V
3.294
VI = 3.5 V
3.274
VI = 3.9 V
VI = 3.8 V
VI = 3.6 V
VI = 3.7 V
3.254
1
IO - Output Current - A
10
3.234
0.1
Figure 11. DCDC2: Output Voltage
vs Output Current at 85°C
1
IO - Output Current - A
Figure 12. DCDC3: Output Voltage
vs Output Current at 85°C
VINDCDC2
VINDCDC1
C1 High
4.01 V
C1 High
4.71 V
C1 Low
3.02 V
C1 Low
3.68 V
C2 Pk-Pk
28.5 mV
VDCDC1
C2 Mean
1.18925 V
IO = 100 mA
VINDCDC1 = 3.7 V - 4.7 V
DEFDCDC1 = VINDCDC1
PWW Mode
Figure 13. VDCDC1 Line Transient Response
10
C2 Pk-Pk
48.9 mV
VDCDC2
IO = 100 mA
VINDCDC2 = 3 V - 4 V
DEFDCDC2 = GND
PWW Mode
C2 Mean
1.81053 V
Figure 14. VDCDC2 Line Transient Response
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VINDCDC3
C1 High
4.20 V
C1 Low
3.59 V
C2 Pk-Pk
60.4 mV
VDCDC3
IO = 100 mA
VINDCDC3 = 3.6 V - 4.2 V
DEFDCDC3 = VINDCDC3
PWW Mode
C2 Mean
3.28264 V
Figure 15. VDCDC3 Line Transient Response
Figure 16. VDCDC1 Load Transient Response
VDCDC3 = 3.3 V @ 50 mV/Div
(AC Coupled)
ILOAD @ 500 mA/Div
800 mA
100 mA
VIN = 3.8 V
18
TIMESCALE = 50 ms/Div
Figure 17. VDCDC2 Load Transient Response
Figure 18. VDCDC3 Load Transient Response
Figure 19. VDCDC2 Output Voltage Ripple
Figure 20. VDCDC2 Output Voltage Ripple
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mV
Figure 21. VDCDC2 Output Voltage Ripple
ENABLE
Figure 22. Start-Up VDCDC1, VDCDC2, and VDCDC3
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 1.1 V
o
TA = 25 C
C1 High
3.83 V
C1 Low
3.29 V
LDO1
C2 PK-PK
6.2 mV
C2 Mean
1.09702 V
LDO2
Figure 23. Start-Up LDO1 and LDO2
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 3.3 V
TA = 25oC
C1 High
4.51 V
Figure 24. LDO1 Line Transient Response
Ch1 = VI
Ch2 = VO
IO = 10 mA
VO = 3 V
o
TA = 25 C
C1 High
3.82 V
C1 Low
3.99 V
C1 Low
3.28 V
C2 PK-PK
6.1 mV
C2 PK-PK
22.8 mV
C2 Mean
3.29828 V
C2 Mean
2.98454 V
Figure 25. LDO2 Line Transient Response
Figure 26. VRTC Line Transient Response
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C4 High
47.8 mA
C4 High
48.9 mA
C4 Low
-2.9 mA
C4 Low
2.1 mA
C2 PK-PK
40.4 mV
C2 PK-PK
42.5 mV
C2 Mean
3.29821 V
C2 Mean
1.09664 V
Ch2 = VO
Ch4 = IO
VI = 3.3 V
VO = 1.1 V
o
TA = 25 C
VI = 4 V
VO = 3.3 V
o
TA = 25 C
Ch2 = VO
Ch4 = IO
Figure 28. LDO2 Load Transient Response
Figure 27. LDO1 Load Transient Response
C4 High
21.4 mA
C4 Low
-1.4 mA
C2 PK-PK
76 mV
C2 Mean
2.9762 V
Ch2 = VO
Ch4 = IO
VI = 3.8 V
VO = 3 V
o
TA = 25 C
Figure 29. VRTC Load Transient Response
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7 Detailed Description
7.1 Overview
TPS65023x has 5 regulator channels, 3 DCDCs and 2 LDOs. DCDC3 has dynamic voltage scaling feature (DVS)
that allows for power reduction to CORE supplies during idle operation or overvoltage during heavy-duty
operation. With DVS and 2 more DCDCs plus 2 LDOs, the TPS65023x is ideal for CORE, Memory, IO, and
peripheral power for the entire system of a wide range of suitable applications.
The device incorporates enables for the DCDCs and LDOs, I2C for device control, push button, and a reset
interface that complete the system and allow the TPS65023x to be adapted for different kinds of processors or
FPGAs.
For noise-sensitive circuits, the DCDCs can be synchronized out of phase from one another, reducing the peak
noise at the switching frequency. Each converter can be forced to operate in PWM mode to ensure constant
switching frequency across the entire load range. However, for low load efficiency performance the DCDCs
automatically enter PSM mode which reduces the switching frequency when the load current is low, saving
power at idle operation.
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7.2 Functional Block Diagram
TPS65023, TPS65023B
VCC
VSYSIN
BBAT
SWITCH
VBACKUP
VRTC
Thermal
Shutdown
VINDCDC1
L1
DCDC1
Buck Converter
1700 mA
SCLK
SDAT
VDCDC1
DEFDCDC1
PGND1
Serial Interface
VINDCDC2
DCDC1_EN
L2
DCDC2_EN
DCDC2
Buck Converter
1200 mA
DCDC3_EN
LDO_EN
CONTROL
VDCDC2
DEFDCDC2
PGND2
HOT_RESET
Dynamic
Voltage
Management
RESPWRON
INT
VINDCDC3
L3
LOWBAT_SNS
PWRFAIL_SNS
LOW_BATT
PWRFAIL
DCDC3
Buck Converter
1000 mA
UVLO
VREF
OSC
VDCDC3
DEFDCDC3
PGND3
TRESPWRON
LDO1
200 mA
DEFLDO1
DEFLDO2
VLDO1
VINLDO
LDO2
200 mA
VLDO2
AGND1
AGND2
7.3 Feature Description
7.3.1 VRTC Output and Operation With or Without Backup Battery
The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (that is, for
a real time clock). The TPS65023x asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is selected
from a priority scheme based on the VSYSIN and VBACKUP inputs.
When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input through a PMOS
switch and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA,
which must be considered when using VRTC. VSYSIN can be connected to any voltage source with the
appropriate input voltage, including VCC or, if set to 3.3-V output, DCDC2 or DCDC3. When VSYSIN falls below
2.65 V or shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to
either VBACKUP or the output of a dedicated 3-V or 30-mA LDO.
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Feature Description (continued)
NOTE
Texas Instruments recommends connecting VSYSIN to VCC or ground – VCC if a nonreplaceable primary cell is connected to VBACKUP and ground if the VRTC output will
float.
If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to
VBACKUP through a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which must be
considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any
battery that provides a voltage between 2.65 V and 6 V (that is, a single Li-Ion cell or a single boosted NiMH
battery) is acceptable, to supply the VRTC output.
NOTE
In systems with no backup battery, the VBACKUP pin must be connected to GND.
If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V or 30-mA LDO, driven
from VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V.
Inside TPS65023x there is a switch (Vmax switch) which selects the higher voltage between VCC and VBACKUP.
This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax
switch are:
• INT output
• RESPWRON output
• HOT_RESET input
• LOW_BATT output
• PWRFAIL output
• Enable pins for DC-DC converters, LDO1 and LDO2
• Undervoltage lockout comparator (UVLO)
• Reference system with low frequency timing oscillators
• LOW_BATT and PWRFAIL comparators
The main 2.25-MHz oscillator, and the I2C interface are only powered from VCC.
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Feature Description (continued)
VSYSIN
Vref
V_VSYSIN
priority
#1
VCC
VBACKUP
Vref
V_VBACKUP
priority
#2
V_VSYSIN
V_VBACKUP
EN
VRTC
LDO
priority
#3
VRTC
RESPWRON
Vref
A.
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B.
RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
Figure 30. RTC and nRESPWRON
7.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
The TPS65023x incorporates three synchronous step-down converters operating typically at
2.25-MHz, fixed frequency pulse width modulation (PWM) at moderate to heavy-load currents. At light-load
currents, the converters automatically enter the power save mode (PSM), and operate with pulse frequency
modulation (PFM). The VDCDC1 converter is capable of delivering 1.5-A output current, the VDCDC2 converter
is capable of delivering 1.2 A and the VDCDC3 converter is capable of delivering up to 1 A.
The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins.
The pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND.
The VDCDC1 converter defaults to 1.2 V or 1.6 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1
is tied to ground, the default is 1.2 V. If it is tied to VCC, the default is 1.6 V. When the DEFDCDC1 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See
Application Information for more details. The core voltage can be reprogrammed through the serial interface in
the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst
any programmed voltage change is underway, whether the voltage is being increased or decreased. The
DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage
transitions.
The VDCDC2 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2
is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3
is tied to ground the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V.
The step-down converter outputs (when enabled) are monitored by power-good (PG) comparators, the outputs of
which are available through the serial interface. The outputs of the DC-DC converters can be optionally
discharged through on-chip 300-Ω resistors when the DC-DC converters are disabled.
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Feature Description (continued)
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead-time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three DC-DC converters operate synchronized to each other with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 1.2 V, the
VDCDC2 converter from 3.7 V to 1.8 V, and the VDCDC3 converter from 3.7 V to 3.3 V. The phase of the three
converters can be changed using the CON_CTRL register.
7.3.3 Power Save Mode Operation
As the load current decreases, the converters enter the power save mode operation. During PSM, the converters
operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal for one burst
cycle. However, the frequency between different burst cycles depends on the actual load current and is typically
far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
To optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the
inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is
calculated as shown in Equation 1, Equation 2 and Equation 3.
VINDCDC1
IPFMDCDC1 enter =
(1)
24 Ω
VINDCDC2
IPFMDCDC2 enter =
26 Ω
(2)
VINDCDC3
IPFMDCDC3 enter =
39 W
(3)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined in Equation 4, Equation 5 and Equation 6.
VINDCDC1
IPFMDCDC1 leave =
18 W
(4)
VINDCDC2
IPFMDCDC2 leave =
20 W
(5)
VINDCDC3
IPFMDCDC3 leave =
29 W
(6)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. the output voltage drops 2% below the nominal VO due to increasing load current
2. the PFM burst time exceeds 16 × 1/fs (7.11 μs typical).
These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to
a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light-load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM
mode.
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Feature Description (continued)
7.3.4 Low Ripple Mode
Setting bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the DC-DC converters if operated
in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
7.3.5 Soft-Start
Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The
soft-start is realized by using a low current to initially charge the internal compensation capacitor. The soft-start
time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 μs between the converter being enabled and switching activity actually
starting. This allows the converter to bias itself properly, to recognize if the output is precharged, and if so to
prevent discharging of the output while the internal soft-start ramp catches up with the output voltage.
7.3.6 100% Duty Cycle Low Dropout Operation
The TPS65023x converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load
current and output voltage. It is calculated in Equation 7.
Vinmin
Voutmin Ioutmax u rDS(on) max RL
where
•
•
•
•
Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
Voutmin = nominal output voltage minus 2% tolerance limit
(7)
7.3.7 Active Discharge When Disabled
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or
OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is
individually enabled through the CON_CTRL2 register in the serial interface. When this feature is enabled, the
VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300-Ω (typical) load which is active as long as
the converters are disabled.
7.3.8 Power-Good Monitoring
All three step-down converters and both the LDO1 and LDO2 linear regulators have power-good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register through the serial interface.
An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled
when the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
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Feature Description (continued)
7.3.9 Low-Dropout Voltage Regulators
The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
LDO_EN pin, both LDOs can be disabled or programmed through the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS65023x step-down and LDO voltage
regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction
temperature rises above 160°C.
7.3.10 Undervoltage Lockout
The undervoltage lockout circuit for the five regulators on the TPS65023x prevents the device from
malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and
LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV)
hysteresis. When any of the DC-DC converters are running, there is an input current at the VCC pin, which is up
to 3 mA when all three converters are running in PWM mode. Consider this current if an external RC filter is used
at the VCC pin to remove switching noise from the TPS65023x internal analog circuitry supply.
7.3.11 Power-Up Sequencing
The TPS65023x power-up sequencing is designed to be entirely flexible and customer driven. This is achieved
by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs.
The relevant control pins are described in Table 2.
Table 2. Control Pins and Status Outputs for DC–DC Converters
PIN NAME
I/O
FUNCTION
DEFDCDC3
I
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V,
DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.
DEFDCDC2
I
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V,
DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V,
DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
HOT_RESET
I
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65023x settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1
to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS65023x.
RESPWRON
O
RESPWRON is held low when power is initially applied to the TPS65023x. The VRTC voltage is monitored:
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the
TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).
7.4 Device Functional Modes
The TPS6502x devices are either in the ON or the OFF mode. The OFF mode is entered when the voltage on
VCC is below the UVLO threshold, 2.35 V (typically). Once the voltage at VCC has increased above UVLO, the
device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use.
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7.5 Programming
7.5.1 System Reset + Control Signals
The RESPWRON signal can be used as a global reset for the application. It is an open-drain output. The
RESPWRON signal is generated according to the power-good comparator of VRTC, and remains low for tnrespwron
seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an
external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the
HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1-V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, or RESPWRON active.
7.5.1.1 DEFLDO1 and DEFLDO2
These two pins are used to set the default output voltage of the two 200-mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3. LDO1 and LDO2 Default Voltage Options
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
0
1.3 V
3.3 V
0
1
2.8 V
3.3 V
1
0
1.3 V
1.8 V
1
1
1.8 V
3.3 V
7.5.1.2 Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each DC–DC converter and the LDOs. The
INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin
remains active (low state) during power up as long as all enabled power rails are below their regulation limit.
Once the last enabled power rail is within regulation, the INT pin transitions to a high state.
During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the
corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT
transitions back to a high state.
While INT is in an active-low state, reading the PGOODZ register through the I2C bus forces INT into a high-Z
state. Because this pin requires an external pullup resistor, the INT pin transitions to a logic high state even
though the supply in question is still out of regulation. The corresponding bit in the PGOODZ register still
indicates that the power rail is out of regulation.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts
because this provides the POWER_OK function. If none of the DCDC converters or LDos are enabled, /INT
defaults to a low state independently of the settings of the MASK register.
7.5.2 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65023x has a 7-bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
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For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65023x device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65023x device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65023x device must leave the data line high to enable the master to generate the stop
condition. See I2C Timing Requirements for TPS65023B for more information.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 31. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 32. START and STOP Conditions
SCLK
SDAT
A6
A5
A4
A0
R/W
ACK
R6
R5
R0
0
0
Start
R7
ACK
D7
D5
D0 ACK
0
0
Register Address
Slave Address
D6
Data
Stop
Note: SLAVE = TPS65023
Figure 33. Serial I/F WRITE to TPS65023x Device
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SCLK
SDAT
A6
Start
A0
R/W
ACK
0
0
R7
R0
A6
ACK
A0
R/W
ACK
1
0
0
Register
Address
Slave Address
D0
D7
ACK
Slave
Drives
the Data
Slave Address
Stop
Master
Drives
ACK and Stop
Repeated
Start
Note: SLAVE = TPS65023
Figure 34. Serial I/F READ from TPS65023x: Protocol A
SCLK
SDA
A6
A0
R/W
ACK
0
Start
R7
R0
0
Slave Address
0
Register
Address
A6
ACK
A0
R/W
1
Stop Start
ACK
D7
D0
ACK
0
Slave Address
Slave
Drives
the Data
Stop
Master
Drives
ACK and Stop
Note: SLAVE = TPS65023
Figure 35. Serial I/F READ from TPS65023x: Protocol B
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7.6 Register Maps
7.6.1 VERSION Register Address: 00h (Read Only)
Table 4. VERSION Register
VERSION
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
0
0
1
0
0
0
1
1
Read and write
R
R
R
R
R
R
R
R
7.6.2 PGOODZ Register Address: 01h (Read Only)
Table 5. PGOODZ Register
PGOODZ
B7
B6
B5
B4
B3
B2
B1
B0
PWRFAILZ
LOWBATTZ
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
–
Set by signal
PWRFAIL
LOWBATT
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
–
Default value
loaded
PWRFAILZ
LOWBATTZ
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
–
R
R
R
R
R
R
R
R
Bit name and
function
Read and write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PWRFAILZ:
0=
indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.
1=
indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.
LOWBATTZ:
0=
indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.
1=
indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.
PGOODZ VDCDC1:
0=
indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if
the VDCDC1 converter is disabled.
1=
indicates that the VDCDC1 converter output voltage is below its target regulation voltage
PGOODZ VDCDC2:
0=
indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if
the VDCDC2 converter is disabled.
1=
indicates that the VDCDC2 converter output voltage is below its target regulation voltage
PGOODZ VDCDC3: .
0=
indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if
the VDCDC3 converter is disabled and during a DVM controlled output voltage transition
1=
indicates that the VDCDC3 converter output voltage is below its target regulation voltage
PGOODZ LDO2:
0=
indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is
disabled.
1=
indicates that LDO2 output voltage is below its target regulation voltage
PGOODZ LDO1
0=
indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is
disabled.
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indicates that the LDO1 output voltage is below its target regulation voltage
7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
Table 6. MASK Register
MASK
Bit name and
function
Default
Default value
loaded
Read and write
B7
B6
B5
B4
B3
B2
B1
B0
MASK
PWRFAILZ
MASK
LOWBATTZ
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
–
1
1
0
0
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The
contents of the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO
condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The
REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.
Table 7. REG_CTRL Register
REG_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
–
–
VDCDC1
ENABLE
VDCDC2
ENABLE
VDCDC3
ENABLE
LDO2
ENABLE
LDO1
ENABLE
–
Default
1
1
1
1
1
Set by signal
–
–
Default value
loaded
–
–
UVLO
UVLO
Read and write
–
–
R/W
R/W
Bit 5
1
1
1
LDO_ENZ
LDO_ENZ
–
UVLO
UVLO
UVLO
–
R/W
R/W
R/W
–
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ
VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface.
The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when
DCDC1_EN returns high.
Bit 4
VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface.
The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when
DCDC2_EN returns high.
Bit 3
VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface.
The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when
DCDC3_EN returns high.
Bit 2
LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1
when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
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Bit 1
SLVS670L – JUNE 2006 – REVISED MAY 2018
LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1
when the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.
7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
Table 8. CON_CTRL Register
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
1
0
1
1
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Default value
loaded
Read and write
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters to minimize
the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as
the reference and consequently has a fixed zero phase shift.
Table 9. DCDC2 and DCDC3 Phase Delay
CON_CTRL<7:6>
DCDC2 CONVERTER
DELAYED BY
CON_CTRL<5:4>
DCDC3 CONVERTER
DELAYED BY
00
zero
00
zero
01
1/4 cycle
01
1/4 cycle
10
1/2 cycle
10
1/2 cycle
11
3/4 cycle
11
3/4 cycle
Bit 3
Bit 2
Bit 1
Bit 0
LOW RIPPLE:
0=
PFM mode operation optimized for high efficiency for all converters
1=
PFM mode operation optimized for low output voltage ripple for all converters
FPWM DCDC2:
0=
DCDC2 converter operates in PWM / PFM mode
1=
DCDC2 converter is forced into fixed frequency PWM mode
FPWM DCDC1:
0=
DCDC1 converter operates in PWM / PFM mode
1=
DCDC1 converter is forced into fixed frequency PWM mode
FPWM DCDC3:
0=
DCDC3 converter operates in PWM / PFM mode
1=
DCDC3 converter is forced into fixed frequency PWM mode
7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
Table 10. CON_CTRL2 Register
CON_CTRL2
Bit name and
function
Default
B7
B6
GO
Core adj
allowed
B5
–
0
1
0
B4
B3
B2
B1
B0
–
–
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
0
0
0
0
0
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Table 10. CON_CTRL2 Register (continued)
CON_CTRL2
B7
B6
B5
B4
B3
B2
B1
B0
Default value
loaded
UVLO +
DONE
RESET(1)
–
–
–
UVLO
UVLO
UVLO
R/W
R/W
–
–
–
R/W
R/W
R/W
Read and write
The CON_CTRL2 register can be used to take control the inductive converters.
•
•
•
•
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
undervoltage lockout (UVLO)
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
Bit 7
GO:
Bit 6
0=
no change in the output voltage for the DCDC1 converter
1=
the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC1 output voltage is actually in regulation at the
desired voltage.
CORE ADJ Allowed:
Bit 2– 0
0=
the output voltage is set with the I2C register
1=
DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up
0=
the output capacitor of the associated converter is not actively discharged when the converter is
disabled
1=
the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load
7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
Table 11. DEFCORE Register
DEFCORE
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
–
–
–
CORE4
CORE3
CORE2
CORE1
CORE0
Default
0
0
0
1
DEFDCDC1
DEFDCDC1
DEFDCDC1
DEFDCDC1
Default value
loaded
–
–
–
RESET(1)
RESET(1)
RESET(1)
RESET(1)
RESET(1)
Read and write
–
–
–
R/W
R/W
R/W
R/W
R/W
RESET(1): DEFCORE is reset to its default value by one of these events:
• undervoltage lockout (UVLO)
• HOT_RESET pulled low
• RESPWRON active
• VRTC below threshold
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Table 12. DCDC3 DVS Voltages
CORE4 CORE3
CORE2
CORE1
CORE0
VDCDC1
CORE4
CORE3
CORE2
CORE1
CORE0
VDCDC1
0
0
0
0
0
0.8 V
1
0
0
0
0
1.2 V
0
0
0
0
1
0.825 V
1
0
0
0
1
1.225 V
0
0
0
1
0
0.85 V
1
0
0
1
0
1.25 V
0
0
0
1
1
0.875 V
1
0
0
1
1
1.275 V
0
0
1
0
0
0.9 V
1
0
1
0
0
1.3 V
0
0
1
0
1
0.925 V
1
0
1
0
1
1.325 V
0
0
1
1
0
0.95 V
1
0
1
1
0
1.35 V
0
0
1
1
1
0.975 V
1
0
1
1
1
1.375 V
0
1
0
0
0
1V
1
1
0
0
0
1.4 V
0
1
0
0
1
1.025 V
1
1
0
0
1
1.425 V
0
1
0
1
0
1.05 V
1
1
0
1
0
1.45 V
0
1
0
1
1
1.075 V
1
1
0
1
1
1.475 V
0
1
1
0
0
1.1 V
1
1
1
0
0
1.5 V
0
1
1
0
1
1.125 V
1
1
1
0
1
1.525 V
0
1
1
1
0
1.15 V
1
1
1
1
0
1.55 V
0
1
1
1
1
1.175 V
1
1
1
1
1
1.6 V
7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
Table 13. DEFSLEW Register
DEFSLEW
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
–
–
–
–
–
SLEW2
SLEW1
SLEW0
Default
–
–
–
–
–
1
1
0
Default value
loaded
–
–
–
–
–
UVLO
UVLO
UVLO
Read and write
–
–
–
–
–
R/W
R/W
R/W
Table 14. DCDC3 DVS Slew Rate
SLEW2
SLEW1
SLEW0
VDCDC1 SLEW RATE
0
0
0
0.225 mV/μs
0
0
1
0.45 mV/μs
0
1
0
0.9 mV/μs
0
1
1
1.8 mV/μs
1
0
0
3.6 mV/μs
1
0
1
7.2 mV/μs
1
1
0
14.4 mV/μs
1
1
1
Immediate
7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and
DEFLDO2
Table 15. LDO_CTRL Register
LDO_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
RSVD
LDO2_2
LDO2_1
LDO2_0
RSVD
LDO1_2
LDO1_1
LDO1_0
Default
–
DEFLDOx
DEFLDOx
DEFLDOx
–
DEFLDOx
DEFLDOx
DEFLDOx
Default value
loaded
–
UVLO
UVLO
UVLO
–
UVLO
UVLO
UVLO
Read and write
–
R/W
R/W
R/W
–
R/W
R/W
R/W
Bit name and
function
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The LDO_CTRL registers are used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and
LDO_CTRL[3] are reserved and must always be written to 0.
The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 16.
Table 16. LDO2 and LDO3 I2C Voltage Options
36
LDO2_2
LDO2_1
LDO2_0
LDO2 OUTPUT
VOLTAGE
LDO1_2
LDO1_1
LDO1_0
0
0
0
1.05 V
0
0
0
1V
0
0
1
1.2 V
0
0
1
1.1 V
0
1
0
1.3 V
0
1
0
1.3 V
0
1
1
1.8 V
0
1
1
1.8 V
1
0
0
2.5 V
1
0
0
2.2 V
1
0
1
2.8 V
1
0
1
2.6 V
1
1
0
3.0 V
1
1
0
2.8 V
1
1
1
3.3 V
1
1
1
3.15 V
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LDO1 OUTPUT
VOLTAGE
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input Voltage Connection
The low power section of the control circuit for the step-down converters DCDC1, DCDC2, and DCDC3 is
supplied by the VCC pin while the circuitry with high power such as the power stage is powered from the
VINDCDC1, VINDCDC2, and VINDCDC3 pins. For proper operation of the step-down converters, VINDCDC1,
VINDCDC2, VNDCDC3, and VCC must be tied to the same voltage rail. Step-down converters that are planned
to be not used, still need to be powered from their input pin on the same rails than the other step-down
converters and VCC.
LDO1 and LDO2 share a supply voltage pin which can be powered from the VCC rails or from a voltage lower
than VCC, for example, the output of one of the step-down converters as long as it is operated within the input
voltage range of the LDOs. If both LDOs are not used, the VINLDO pin can be tied to GND.
8.1.2 Unused Regulators
In case a step-down converter is not used, its input supply voltage pin VINDCDCx still needs to be connected to
the VCC rail along with supply input of the other step-down converters. TI recommends closing the control loop
such that an inductor and output capacitor is added in the same way as it would be when operated normally. If
one of the LDOs is not used, its output capacitor must be added as well. If both LDOs are not used, the input
supply pin as well as the output pins of the LDOs (VINLDO, VLDO1, VLDO2) must be tied to GND.
8.1.3 Reset Condition of DCDC1
If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output
voltage of DCDC1 defaults to 1.225 V instead of 1.2 V (high by 2%). Figure 36 illustrates the problem.
VCC/VINDCDC1
DCDC1_EN
1.225 V
1.225 V
1.225 V
VDCDC1
Figure 36. Default DCDC1
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Application Information (continued)
One workaround is to tie DCDC1_EN to VINDCDC1 (Figure 37).
VCC/VINDCDC1
DCDC1_EN
1.20 V
1.20 V
1.20 V
VDCDC1
Figure 37. Workaround 1
Another workaround is to write the correct voltage to the DEF_CORE register through I2C. This can be done
before or after the converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The
voltage is 1.2 V, however, when the enable is pulled high (Figure 38).
VCC/VINDCDC1
DCDC1_EN
I2C Bus
DEF_CORE
??
0x1F
0x11
1.225 V
VDCDC1
0x10
??
0x1F
0x1E
0x10
1.20 V
1.20 V
Pull DCDC1_EN High
Write DEF_CORE to 0x10
Write CON_CTRL [7] to 1
Write DEF_CORE to 0x10
Pull DCDC1_EN High
Figure 38. Workaround 2
A third workaround is to generate a HOT_RESET after enabling DCDC1 (Figure 39)
VCC/VINDCDC1
DCDC1_EN
HOT_RESET
1.225 V
1.225 V
1.20 V
VDCDC1
1.20 V
Figure 39. Workaround 3
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Application Information (continued)
Table 17. Changes of TPS65023B vs TPS65023
ITEM
DESCRIPTION
Reference
VIH
High level input voltage for the SDAT pin
VIH
High level input voltage for the SCLK pin
VIL
Low level input voltage for SCLK and
SDAT pin
th(DATA)
Data input hold time
tsu(DATA)
Data input setup time
Electrical
Characteristics
2
I C Timing
Requirements for
TPS65023B
TPS65023
TPS65023B
Minimum 1.3 V
Minimum 1.69 V;
Vcc = 2.5 V to 5.25 V
Minimum 1.55 V;
Vcc = 2.5 V to 4.5 V
Minimum 1.3 V
Minimum 1.4 V;
Vcc = 2.5 V to 5.25 V
Maximum 0.4 V
Maximum 0.35 V
Minimum 300 ns
Minimum 100 ns
Minimum 300 ns
Minimum 100 ns
8.2 Typical Application
Figure 40. Typical Configuration for the Texas Instruments TMS320DM644x DaVinci™ Processors
8.2.1 Design Requirements
The TPS6502x devices have only a few design requirements. Use the following parameters for the design
examples:
• 1- μ F bypass capacitor on VCC, located as close as possible to the VCC pin to ground
• VCC and VINDCDCx must be connected to the same voltage supply with minimal voltage difference.
• Input capacitors must be present on the VINDCDCx and VIN_LDO supplies if used
• Output inductor and capacitors must be used on the outputs of the DC–DC converters if used
• Output capacitors must be used on the outputs of the LDOs if used
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection for the DC-DC Converters
Each of the converters in the TPS65023x typically use a 2.2-μH output inductor. Larger or smaller inductor
values are used to optimize the performance of the device for specific operation conditions. The selected
inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance
influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance must be
selected for highest efficiency.
For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended.
Equation 8 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current as calculated with Equation 8. This is needed
because during heavy load transient the inductor current rises above the calculated value.
1
'IL
Vout u
IL max
Iout max
Vout
Vin
/u¦
(8)
'IL
2
where
•
•
•
•
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILMAX = Maximum Inductor current
(9)
The highest inductor current occurs at maximum Vin.
Open-core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65023x (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core
material from inductor to inductor differs and has an impact on the efficiency especially at high switching
frequencies.
See Table 18 and the typical applications for possible inductors.
Table 18. Tested Inductors
DEVICE
INDUCTOR
VALUE
TYPE
COMPONENT SUPPLIER
2.2 μH
LPS4012-222LMB
Coilcraft
All converters
2.2 μH
VLCF4020T-2R2N1R7
TDK
For DCDC2 or
DCDC3
2.2 uH
LQH32PN2R2NN0
Murata
For DCDC1
1.5 uH
LQH32PN1R5NN0
Murata
All converters
2.2 uH
PST25201B-2R2MS
Cyntec
8.2.2.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the inductive converters implemented in the
TPS65023x allow the use of small ceramic capacitors with a typical value of 10 μF for each converter without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. See Table 19 for recommended
components.
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If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness, the RMS ripple current is calculated in Equation 10.
V
1 - out
Vin
1
x
IRMSCout = Vout x
L x ¦
2 x Ö3
(10)
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1 - out
Vin
1
DVout = Vout x
x
+ ESR
L x ¦
8 x Cout x ¦
(
)
where
•
The highest output voltage ripple occurs at the highest input voltage Vin
(11)
At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output
capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output voltage ripple is less than 1% of the nominal output voltage.
8.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the
input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC
pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow
through this resistor into the VCC pin when all converters are running in PWM mode.
Table 19. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 μF
1206
TDK C3216X5R0J226M
Ceramic
22 μF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 μF
0805
TDK C2012X5R0J226MT
Ceramic
22 μF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 μF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 μF
0805
TDK C2012X5R0J106M
Ceramic
8.2.2.4 Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 20 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 41.
The output voltage of VDCDC1 is set with the I2C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1
does not change the voltage set with the register.
Table 20. DCDC1, DCDC2, and DCDC3 Default Voltage Levels
PIN
DEFDCDC1
DEFDCDC2
LEVEL
DEFAULT OUTPUT VOLTAGE
VCC
1.6 V
GND
1.2 V
VCC
3.3 V
GND
1.8 V
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Table 20. DCDC1, DCDC2, and DCDC3 Default Voltage Levels (continued)
PIN
DEFDCDC3
LEVEL
DEFAULT OUTPUT VOLTAGE
VCC
3.3 V
GND
1.8 V
Using an external resistor divider at DEFDCDCx:
10 R
V(bat)
VCC
1 mF
VDCDC3
L3
VINDCDC3
VO
L
CI
CO
R1
DEFDCDC3
DCDC3_EN
R2
AGND
PGND
Figure 41. External Resistor Divider
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1 + R2) of the voltage divider must be kept in the 1-MR range to maintain a
high efficiency at light load.
V(DEFDCDCx) = 0.6 V
R1 + R2
R2
VOUT = VDEFDCDCx x
R1 = R2 x
(
VOUT
VDEFDCDCx
)
- R2
(12)
8.2.2.5 VRTC Output
It is required that a 4.7-μF (minimum) capacitor be added to the VRTC pin even if the output is not used.
8.2.2.6 LDO1 and LDO2
The LDOs in the TPS65023x are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2 μF. The LDOs output voltage can be changed to different voltages
between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in
applications powering processors different from DaVinci. The supply voltage for the LDOs needs to be connected
to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the
highest efficiency.
8.2.2.7 TRESPWRON
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends not
leaving signal pins open.
t(reset) = 2 x 128 x
(
(1 V - 0.25 V) x C(reset)
2 mA
)
where
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•
•
t(reset) is the reset delay time
C(reset) is the capacitor connected to the TRESPWRON pin
(13)
The minimum and maximum values for the timing parameters called ICONST (2 uA), TRESPWRON_UPTH (1
V), and TRESPWRON_LOWTH (0.25 V) can be found under Electrical Characteristics.
8.2.2.8 VCC Filter
An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other
analog circuitry. A typical value of 1 R and 1 μF is used to filter the switching spikes, generated by the DC-DC
converters. A larger resistor than 10 R must not be used because the current into VCC of up to 3 mA causes a
voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off
too early.
8.2.3 Application Curves
Graphs were taken using the EVM with the following inductor and output capacitor combinations:
CONVERTER
INDUCTOR
OUTPUT CAPACITOR
OUTPUT CAPACITOR VALUE
VDCDC1
VLCF4020-2R2
C2012X5R0J106M
2 × 10 μF
VDCDC2
VLCF4020-2R2
C2012X5R0J106M
2 × 10 μF
VDCDC3
VLF4012AT-2R2M1R5
C2012X5R0J106M
2 × 10 μF
100
100
VI = 2.5 V
90
80
90
VI = 3.6 V
80
70
Efficiency - %
Efficiency - %
70
VI = 4.2 V
60
50
VI = 5 V
40
VI = 4.2 V
60
50
VI = 5 V
40
30
30
TA = 25°C
VO = 1.2 V
PWM/PFM Mode
20
10
0
0.01
VI = 2.5 V
VI = 3.6 V
0.1
1
10
100
IO - Output Current - mA
1k
TA = 25°C
VO = 1.8 V
PWM/PFM Mode
20
10
10 k
0
0.01
0.1
Figure 42. DCDC1 Efficiency
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1
10
100
IO - Output Current - mA
1k
10 k
Figure 43. DCDC2 Efficiency
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100
VI = 2.5 V
90 VI = 3.6 V
80
Efficiency - %
70
VI = 4.2 V
60
VI = 5 V
50
40
30
20
TA = 25°C
VO = 1.8 V
PWM/PFM Mode
10
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
10 k
Figure 44. DCDC3 Efficiency
9 Power Supply Recommendations
9.1 Requirements for Supply Voltages Below 3.0 V
For a supply voltage on pins Vcc, VINDCDC1, VINDCDC2, and VINDCDC3 below 3.0 V, TI recommends
enabling the DCDC1, DCDC2, and DCDC3 converters in sequence. If all 3 step-down converters are enabled at
the same time while the supply voltage is close to the internal reset detection threshold, a reset may be
generated during power-up. Therefore TI recommends enabling the DC-DC converters in sequence. This can be
done by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltage
of one of the other step-down converters. If a voltage above 3.0 V is applied on pin VBACKUP while VCC and
VINDCDCx is below 3.0 V, there is no restriction in the power-up sequencing as VBACKUP will be used to power
the internal circuitry.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Take care in board layout to get the specified performance. If the
layout is not carefully done, the regulators may show poor line, load regulation, or both, along with stability issues
and EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for
the main current paths. The input capacitors must be placed as close as possible to the IC pins as well as the
inductor and output capacitor.
For TPS65023x, connect the PGND pins of the device to the thermal pad land of the PCB and connect the
analog ground connections (AGND) to the PGND at the thermal pad. It is essential to provide a good thermal
and electrical connection of all GND pins using multiple vias to the GND-plane. Keep the common path to the
AGND pins, which returns the small signal components, and the high current of the output capacitors as short as
possible to avoid ground noise. The VDCDCx line must be connected right to the output capacitor and routed
away from noisy components and traces (for example, the L1, L2, and L3 traces).
10.2 Layout Example
VIN
Cout
L3
Cout
CIN
VDCDC3
PGND3
Figure 45. Layout Example of a DC–DC Converter
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For development support, refer to:
• Altera Cyclone IV FPGA Power Reference Design with TPS65023
• Altera Cyclone III FPGA Power Reference Design with TPS65023
• Integrated Power Supply Reference Design for Xilinx Artix®-7, Spartan®-7, and Zynq®-7000 FPGAs
• Integrated Power Supply Reference Design for Xilinx Zynq® UltraScale+™ ZU2CG−ZU5EV MPSoCs
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, DaVinci™ Sequencing Using The TPS65023 application report
• Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor Applications
application report
• Texas Instruments, Optimizing Resistor Dividers at a Comparator Input application report
• Texas Instruments, Optimizing OMAP3630 BOOT Sequence Using the TPS65023-Q1 application report
• Texas Instruments, Power Supply Design for NXP i.MX 6 Using the TPS65023 application report
• Texas Instruments, Power Supply Design for NXP i.MX 7 Using the TPS65023 application report
• Texas Instruments, Power Supply Reference Design for Freescale™ i.MX35 Using TPS65021 reference
guide
• Texas Instruments, Powering OMAP™3 With TPS65023: Design-In Guide application report
• Texas Instruments, Push-Button Circuit application report
• Texas Instruments, TPS65023x Check List
• Texas Instruments, TPS65023EVM user's guide
• Texas Instruments, TPS65023B/TPS650231EVM user's guide
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 21. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65023
Click here
Click here
Click here
Click here
Click here
TPS65023B
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
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Community Resources (continued)
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
DaVinci, OMAP, E2E are trademarks of Texas Instruments.
Freescale is a trademark of Motorola, Inc.
I2C is a trademark of NXP Semiconductors.
UltraScale+ is a trademark of Xilinx Inc.
Artix, Spartan, Zynq are registered trademarks of Xilinx Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65023BRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023B
TPS65023BRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023B
TPS65023RSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023
TPS65023RSBRG4
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023
TPS65023RSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023
TPS65023RSBTG4
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65023
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS65023 :
• Automotive: TPS65023-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS65023BRSBR
WQFN
RSB
40
TPS65023BRSBT
WQFN
RSB
TPS65023RSBR
WQFN
RSB
TPS65023RSBT
WQFN
RSB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
40
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65023BRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
TPS65023BRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
TPS65023RSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
TPS65023RSBT
WQFN
RSB
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040B
WQFN - 0.8 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
B
A
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 3.6
(0.2) TYP
SYMM
EXPOSED
THERMAL PAD
11
20
10
21
SYMM
41
2X 3.6
3.5 0.1
30
1
36X 0.4
PIN 1 ID
31
40
40X
0.5
0.3
40X
0.25
0.15
0.1
0.05
C A B
4219094/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSB0040B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.5)
SYMM
40
31
40X (0.6)
40X (0.2)
SEE SOLDER MASK
DETAIL
30
1
36X (0.4)
(0.9) TYP
(R0.05) TYP
(0.6) TYP
41
SYMM
(4.8)
( 0.2) TYP
VIA
21
10
11
20
(0.6) TYP
(0.9) TYP
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4219094/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSB0040B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2) TYP
40
31
40X (0.6)
40X (0.2)
30
1
36X (0.4)
(1.2) TYP
(R0.05) TYP
41
(4.8)
SYMM
METAL
TYP
10
21
11
SYMM
20
9X (1)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 41
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219094/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2018, Texas Instruments Incorporated
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