Texas Instruments | TPS7B67xx-Q1 450-mA High-Voltage Ultra-Low IQ Low-Dropout Regulator (Rev. D) | Datasheet | Texas Instruments TPS7B67xx-Q1 450-mA High-Voltage Ultra-Low IQ Low-Dropout Regulator (Rev. D) Datasheet

Texas Instruments TPS7B67xx-Q1 450-mA High-Voltage Ultra-Low IQ Low-Dropout Regulator (Rev. D) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
TPS7B67xx-Q1 450-mA High-Voltage Ultra-Low IQ Low-Dropout Regulator
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
4-V to 40-V Wide-VIN Input-Voltage Range With
up to 45-V Transient
Maximum Output Current, 450 mA
Low Quiescent Current (IQ))
– < 4 µA When EN = Low (Shutdown Mode)
– 15 µA Typical at Light Loads
Low-ESR (0.001 to 20 Ω) Ceramic Output-Stability
Capacitor (10 µF to 500 µF When VO ≥ 2.5 V, 22
µF to 500 µF when VO = 1.5 V to 2.5 V)
Maximum Dropout Voltage 450 mV at 400 mA
Adjustable 1.5-V to 18-V Output Voltages
Low-Input Voltage Tracking to UVLO
Integrated Power-On Reset
– Programmable-Reset Pulse Delay
– Open-Drain Reset Output
Integrated Fault Protection
– Thermal Shutdown
– Short-Circuit Protection
20-Pin HTSSOP Package
Automotive
Infotainment Tuner Supply
Body Control Modules
Always-ON Battery Applications
– Gateway Applications
– Remote Keyless Entry Systems
– Immobilizers
3 Description
The
TPS7B6701-Q1,
TPS7B6733-Q1,
and
TPS7B6750-Q1 devices (TPS7B67xx-Q1) are lowdropout linear regulators designed for up to 40-V VIN
operations. With only 15-µA quiescent current at light
load that greatly increases the endurance time of the
automotive battery, the devices drive loads up to
450 mA.
The TPS7B67xx-Q1 family of devices features an
integrated short-circuit and overcurrent protection.
Reset delay and power-good signal are implemented
on power-up to indicate that the output voltage is
stable and is in regulation. An external capacitor
programs the delay. The enable function activates
and deactivates the device with an I/O port from the
MCU.
The device family operates at a temperature range of
–40°C to 125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm × 4.40 mm
TPS7B6701-Q1
TPS7B6733-Q1
TPS7B6750-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Adjustable Output Option
VI
TPS7B6701-Q1
VO
Vbat
EN
RESET
Fixed Output Option
Vreg
Vbat
VI
EN
TPS7B6733-Q1
TPS7B6750-Q1
VO
Vreg
RESET
ADJ
DELAY
GND
DELAY
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 17
10.1 Dropout Recovery ................................................. 17
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2014) to Revision D
•
Page
Added Dropout Recovery section explaining LDO behavior when exiting dropout ............................................................. 17
Changes from Revision B (March 2014) to Revision C
Page
•
Deleted the TPS7B6750A-Q1 and TPS7B6750B-Q1 devices and DDPAK package from the data sheet............................ 1
•
Changed the word terminal to pin throughout the data sheet ................................................................................................ 4
•
Changed the Handling Ratings table to ESD Ratings and moved the storage temperature into the Absolute
Maximum Ratings table. Added corner pin values for CDM ratings. .................................................................................... 5
Changes from Revision A (November 2013) to Revision B
Page
•
Updated the first page by making the following additions: the Device Information table, device family name to
document title, and added the navigation buttons.................................................................................................................. 1
•
Changed the IQ value from < 2 to < 4 when EN = Low in the Features list .......................................................................... 1
•
Added the Table of Contents and moved the Revision History to the second page ............................................................. 1
•
Replaced the ORDERING INFORMATION table with the Device Comparison Table and deleted the Device and
Package columns ................................................................................................................................................................... 4
•
Added Moved all electrical specifications tables and the Typical Characteristics section into the Specifications section..... 5
•
Changed the max value for DELAY from VI to 45 V in the Absolute Maximum Ratings table. Also added new table
note for DELAY....................................................................................................................................................................... 5
•
Changed the max value for ADJ, RESET from VO to 22 V in the Absolute Maximum Ratings table .................................... 5
•
Changed the value of IO from 1 mA to 450 mA for the Input voltage test conditions in the Electrical Characteristics table . 6
•
Added the value for VI in the test conditions of the Regulated output and the Line regulator parameters in the
Electrical Characteristics table .............................................................................................................................................. 6
•
Moved the timing parameters (TIMING FOR RESET) out of the Electrical Characteristics table and into the new
Timing Requirements table .................................................................................................................................................... 7
•
Added the Overview section title to the first paragraph of the Detailed Description section ............................................... 11
2
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
•
Updated the Power-On_Reset (RESET) section by making the following changes: changed the percentage that VO
exceeds for the reset output to change from 90% to 91.6% (also changed this value in the Reset Delay Timer
(DELAY) section), removed The on-chip oscillator presets the delay, and changed the percentage level to assert the
output from 90% to 89.6% .................................................................................................................................................... 12
•
Changed the junction temperature value that disables thermal protection from 170°C to 175°C in the Thermal
Protection section ................................................................................................................................................................. 14
•
Added the Device Functional Modes section ...................................................................................................................... 14
•
Added the Typical Application section in the new Applications and Implementation section ............................................. 15
•
Added the Power Supply Recommendations section ......................................................................................................... 17
•
Changed the LAYOUT INFORMATION section to the Layout section and added the Layout Example section................. 19
•
Added the Mechanical, Packaging, and Orderable Information section. Also added the Device and Documentation
Support section which now contains the trademark section and Electrostatic Discharge Caution. This section also
includes a new reference to the TI Glossary ........................................................................................................................ 22
Changes from Original (October 2013) to Revision A
Page
•
Changed max dropout voltage from 500 mV to 450 mV in FEATURES list .......................................................................... 1
•
Added body control modules to APPLICATIONS list ............................................................................................................. 1
•
Changed the low-voltage tracking feature text to enable function text in the DESCRIPTION ............................................... 1
•
Changed document status from Product Preview to Production Data ................................................................................... 1
•
Changed TYPICAL APPLICATION SCHEMATIC to show difference between adjustable output and fixed output option... 1
•
Changed the MIN value for RESET and ADJ in the RECOMMENDED OPERATING CONDITIONS table from 0 to
1.5 and removed low voltage parameter for those pins ......................................................................................................... 5
•
Added Added board dimensions to the high K profile THERMAL INFORMATION table note............................................... 5
•
Changed test condition for the input voltage to fixed 3.3-V output and added 5-V and two adjustable output conditions .... 6
•
Changed max value for the line regulation parameter from 2 to 10....................................................................................... 6
•
Changed TYP value for dropout voltage where IO = 400 mA from 240 to 260 ...................................................................... 6
•
Changed TYP value for dropout voltage where IO = 200 mA from 160 to 150 ...................................................................... 6
•
Changed Output current-limit typ value to max value for VOUT short to ground ..................................................................... 6
•
Deleted VIN condition from test condition for PSRR ............................................................................................................... 6
•
Added TYPICAL CHARACTERISTICS section...................................................................................................................... 8
•
Added the DETAILED DESCRIPTION section..................................................................................................................... 11
•
Added block diagram fro the TPS7B6733-Q1 and TPS7B6750-Q1..................................................................................... 11
•
Added the APPLICATION INFORMATION section.............................................................................................................. 15
•
Added the LAYOUT INFORMATION section ....................................................................................................................... 19
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
3
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
5 Device Comparison
ORDERABLE PART NUMBER
VOLTAGE OPTION (VOUT)
TPS7B6701QPWPRQ1
Adjustable 1.5 V to 18 V
TPS7B6733QPWPRQ1
Fixed 3.3 V
TPS7B6750QPWPRQ1
Fixed 5 V
6 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP With PowerPAD™
Top View
180
RESET
1
20
NC
NC
2
19
VIN
DELAY
3
18
NC
VOUT
4
17
NC
ADJ/NC
5
16
NC
NC
6
15
EN
NC
7
14
NC
GND
8
13
GND
NC
9
12
NC
NC
10
11
NC
Pin Functions
PIN
NAME
PWP
TYPE
DESCRIPTION
ADJ
5
I
Feedback pin. This pin is used with an external resistor divider or the NC pin when in a fixed version.
DELAY
3
O
Reset pulse delay adjustment. Connect this pin through a capacitor to GND.
EN
15
I
Enable pin. When the EN pin becomes lower than threshold, the device enters the stand-by state.
8, 13
G
Ground reference
2, 6, 7, 9,
10, 11, 12,
14, 16, 17,
18, 20
—
Not connected
RESET
1
O
Output ready. This open-drain pin must be connected to VOUT through an external resistor. RESET is
pulled down when the output voltage goes below threshold.
VIN
19
P
Input power-supply voltage
VOUT
4
P
Output voltage
—
Thermal pad
GND
NC
PowerPAD™
4
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Unregulated input range (2) (3) (4)
Output range
MIN
MAX
VIN, EN
–0.3
45
VOUT
–0.3
22
DELAY (2) (3) (5)
45
ADJ, RESET
22
UNIT
V
V
Operating junction temperature (TJ)
–40
150
°C
Storage temperature (Tstg)
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
All voltage values are with respect to GND.
Absolute negative voltage on these pins does not go below –0.3 V.
Absolute maximum voltage.
The voltage at the DELAY pin must be lower than the VIN voltage.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1) (2)
±2000
All pins
±500
Corner pins (1, 10, 11,
and 20)
±750
Charged-device model (CDM), per AEC
Q100-011
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The human body model is a 107-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Unregulated input range
Output range
TJ
MIN
MAX
VIN
4
40
EN, DELAY
0
40
1.5
18
–40
150
VOUT, RESET, ADJ
Operating junction temperature range
UNIT
V
V
°C
7.4 Thermal Information
TPS7B67xx-Q1
THERMAL METRIC (1) (2)
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.4
°C/W
RθJB
Junction-to-board thermal resistance
23.6
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
23.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
°C/W
(1)
(2)
The thermal data is based on JEDEC standard high K profile — JESD 51-7. Two signal, two plane, four-layer board with 2-oz copper.
The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
5
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
7.5 Electrical Characteristics
VI = 14 V, 1 mΩ < ESR < 20 Ω, TJ = –40°C to 150°C unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
Fixed 3.3-V output, IO = 0 mA to 450 mA
VI
Input voltage
IQ
4
40
5.5
40
Adjustable output, VO ≤ 3.5 V, IO = 0 mA to 450 mA
4
40
Adjustable output, VO ≥ 3.5 V, IO = 0 mA to 450 mA
VO + 0.5
40
Fixed 5-V output, IO = 0 mA to 450 mA
Quiescent current
VI = 5.5 V to 40 V (fixed 5 V), 4 V to 40 V (fixed 3.3 V),
EN = ON, IO = 0.2 mA
15
25
VI = 4 V to 40 V (adjustable version, VO = 1.5 V),
EN = ON, IO = 0.2 mA
15
25
VI = 18.5 V to 40 V (adjustable version, VO = 18 V),
EN = ON, IO = 0.2 mA
25
35
V
µA
ISleep
Input sleep current
NO load current and EN = OFF
4
µA
IEN
EN pin current
EN = 40 V
1
µA
Vbg
Band gap
Reference voltage for ADJ
2%
V
VINUVLO
Undervoltage detection
Ramp VI down until output is turned OFF
2.6
V
UVLOHys
Undervoltage detection
hysteresis
–2%
1.233
1
V
ENABLE INPUT (EN)
VIL
Logic input low level
VIH
Logic input high level
0
0.4
1.7
V
V
REGULATED OUTPUT (VOUT)
VO
Regulated output (1)
VI = VO + 0.5 V to 40 V and VI ≥ 4 V, IO = 0 mA to 450 mA
ΔVO(ΔVI)
Line regulation
VI = VO + 1 V to 40 V and VI ≥ 4 V, IO = 100 mA, ∆VO
10
mV
ΔVO(ΔIL)
Load regulation
IO = 1 mA to 450 mA, ∆VO
10
mV
Vdropout
Dropout voltage
IO
Output current
–2%
2%
VI – VO, IO = 400 mA
240
450
VI – VO, IO = 200 mA
160
300
VO in regulation
0
450
VO short to ground
140
360
VO = VO typical × 0.9
470
850
Ilreg-CL
Output current-limit
PSRR
Power-supply ripple rejection (2) IL = 100 mA, CO = 22 µF
Freq = 100 Hz
60
Freq = 100 kHz
40
mV
mA
mA
dB
RESET
VOL
Reset pulled low
IOL = 0.5 mA
IOH
Reset pulled VOUT through
10-kΩ resistor
Leakage current
VTH-(POR)
Power-on-reset threshold
VO power-up set tolerance
Vhys
Hysteresis
VO power-down set tolerance
89.6
0.4
V
1
µA
91.6
93.6 % of VOUT
2
% of VOUT
RESET DELAY
IChg
Delay capacitor charging
current
Vth
Threshold to release RESET
high
Rdelay = 0 V
6
9.5
14
1
µA
V
OPERATING TEMPERATURE RANGE
TJ
Junction temperature
Tsd
Junction shutdown
temperature
Thys
Hysteresis of thermal
shutdown
(1)
(2)
6
–40
150
°C
175
°C
24
°C
External resistor divider variation is not considered.
Design information — not tested, ensured by characterization.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
TIMING FOR RESET
tPOR
Power-on reset delay
Where C = delay-capacitor value
capacitance, C = 100 nF (1)
tPOR-fixed
Power-on reset delay
No capacitor on pin
tDeglitch
Reset deglitch time
(1)
10.5
ms
100
325
550
µs
55
180
420
µs
This information only will NOT be tested in production. The equation is based on:
(C × 1) / (9.5 × 10–6) = tDelay (delay time)
Where
tab● C = delay capacitor value capacitance
tab● C range = 100 pf to 500 nF
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
7
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
7.7 Typical Characteristics
1.60
160
1.58
140
120
1.54
1.52
IGND (µA)
VO Nominal (%)
1.56
1.50
1.48
1.46
VO
VO (±40ƒC)
(t40ƒC)
1.44
VO (25ƒC)
(25°C)
VO
1.42
100
80
60
40
IGND
(±40ƒC)
IGND (t40°C)
20
IGND (25°C)
IGND
(25ƒC)
VO (125ƒC)
(125°C)
VO
IGND (125°C)
IGND
(125ƒC)
0
1.40
0
5
10
15
20
25
30
35
VI (V)
0
40
50
100
150
200
250
300
350
400
450
IO (mA)
C001
Figure 1. Line Regulation
(VO = 1.5 V, IL = 100 mA)
C002
Figure 2. Ground Current vs Output Current
(VI = 14 V, VO = 1.5 V)
160
25
140
120
15
IGND (µA)
IQ (µA)
20
10
5
100
80
60
IO (t40°C)
IO
(±40ƒC)
40
IO (25°C)
IO
(25ƒC)
20
IGND
(±40ƒC)
IGND (t40°C)
IGND (25°C)
IGND
(25ƒC)
IGND (125°C)
IGND
(125ƒC)
IO (125°C)
IO
(125ƒC)
0
0
0
10
20
30
0
40
VI (V)
30
350
Dropout Voltage (mV)
400
IQ (µA)
25
20
15
10
IGND
(±40ƒC)
IO (t40°C)
5
IO (25°C)
IGND
(25ƒC)
IO (125°C)
IGND
(125ƒC)
30
35
40
VI (V)
Figure 5. Quiescent Current vs Input Voltage
(VO = 18 V)
8
Submit Documentation Feedback
200
250
300
350
400
450
C004
300
250
200
150
100
Vdrop
(±40ƒC)
Vdrop (t40°C)
50
Vdrop (25°C)
Vdrop
(25ƒC)
Vdrop (125°C)
Vdrop
(125ƒC)
0
0
25
150
Figure 4. Ground Current vs Output Current
(VI = 24 V, VO = 18 V)
35
20
100
IO (mA)
Figure 3. Quiescent Current vs Input Voltage
(VO = 1.5 V)
15
50
C003
45
0
50
100
150
200
250
300
350
400
IO (mA)
C005
450
C006
Figure 6. Dropout Voltage vs Output Current
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
Typical Characteristics (continued)
1.60
100
500
1.58
1.56
80
400
1.52
CL (µF)
VO (V)
1.54
1.50
1.48
1.46
VO
VO (±40ƒC)
(t40ƒC)
1.44
VO (125ƒC)
(125°C)
VO
1.40
0
50
100
150
200
250
300
350
400
IO (mA)
Stable Region
40
200
20
100
VO
VO (25ƒC)
(25°C)
1.42
60
300
220
0.001
0.0
450
5
0.5
10
1.0
15
1.5
20
ESR of CO (
C007
Figure 7. Load Regulation
(VI = 14 V, VO = 1.5 V)
C008
Figure 8. ESR Stability vs Load Capacitance
(VO ≤ 2.5 V)
100
500
6
5
80
400
VO (V)
CL (µF)
4
60
300
Stable Region
40
200
3
2
20
100
1
100
0
0.001
0.0
5
0.5
10
1.0
15
1.5
20
ESR of CO (
0
10
15
20
25
30
35
VS (V)
Figure 9. ESR Stability vs Load Capacitance
(VO ≥ 2.5 V)
40
C010
Figure 10. Output Voltage vs Supply Voltage
(Fixed 5-V Version, IL = 0)
3.5
120
3.0
100
2.5
80
PSRR (dB)
VO (V)
5
C009
2.0
1.5
60
40
1.0
20
0.5
0.0
0
0
5
10
15
20
25
30
35
VS (V)
Figure 11. Output Voltage vs Supply Voltage
(Fixed 3.3-V Version, IL = 0)
Copyright © 2013–2018, Texas Instruments Incorporated
40
C011
1010
100
100000010000000
10000000
100 1000
1000 10000
10000100000
100000 1000000
100000000
Frequency (Hz)
C012
Figure 12. Power-Supply Rejection Ratio vs Frequency
(VI = 14 V, CO = 47 µF, IL = 25 mA)
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
9
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
Typical Characteristics (continued)
220
630
620
610
Current Limit (mA)
Current Limit (mA)
215
210
205
200
600
590
580
570
560
550
540
195
530
190
520
±40 ±25 ±10
5
20
35
50
65
Temperature (ƒC)
80
95
110 125
±40 ±25 ±10
Figure 13. Short to GND Current-Limit vs Temperature
5
20
35
50
65
80
95
110 125
Temperature (ƒC)
C013
C014
Figure 14. Current-Limit vs Temperature
Figure 15. Load Transient
10-µF Ceramic Output Capacitor
10
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
8 Detailed Description
8.1 Overview
The TPS7B67xx-Q1 family of devices is an low-dropout linear regulator combined with an enable and reset
function. The power-on-reset initializes when the output voltage, VO, exceeds 91.6% of the target value. The
power-on reset delay is a function of the value set by an external capacitor on the DELAY pin before releasing
the RST pin high.
8.2 Functional Block Diagrams
UVLO
±
Comp
Band Gap
Vref
+
VIN
Vbat
47 µF
Vref
EN
Logic
Control
0.1 µF
Overcurrent
Detection
Thermal
Shutdown
Regulator
Control
VOUT
Vreg
GND
+
±
22 µF
Vref
ADJ
10 k
DELAY
RESET
Reset Control
Figure 16. TPS7B6701-Q1 Functional Block Diagram
UVLO
±
Comp
+
Vref
VIN
Vbat
Band Gap
47 µF
Vref
EN
Logic
Control
0.1 µF
Overcurrent
Detection
Thermal
Shutdown
Regulator
Control
VOUT
Vreg
GND
+
±
DELAY
Reset Control
22 µF
Vref
RESET
10k
Figure 17. TPS7B6733-Q1 and TPS7B6750-Q1 Functional Block Diagram
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
11
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
8.3 Feature Description
8.3.1 Enable (EN)
The enable pin is a high-voltage-tolerant pin. A high input on EN actives the device and turns on the regulator.
For self-bias applications, connect this input to the VIN pin.
8.3.2 Regulated Output (VOUT)
The VOUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has a soft start incorporated to control the initial current through the pass element.
In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
8.3.3 Power-On-Reset (RESET)
The power-on-reset is an output with an external pullup resistor to the regulated supply. The reset output remains
low until the regulated VO exceeds approximately 91.6% of the set value and the power-on-reset delay has
expired. The regulated output falling below the 89.6% level asserts this output low after a short de-glitch time of
approximately 180 µs (typical).
8.3.4 Reset Delay Timer (DELAY)
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 325 µs (typical).
The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY (see Equation 1).
´1V
C
t d = DELAY
9.5 µA
(1)
The power-on-reset initializes when VO exceeds 91.6% of the programmed value. The power-on-reset delay is a
function of the value set by an external capacitor on the DELAY pin before the RESET pin is released high.
V IN
t <t RST_ DEGLITCH
VTH( POR)
UVThres
VOUT
Internally Set
VTH( RST_ DLY)
VTH(RST_DLY)
DELAY
tRST_ DELAY
tRST_ DELAY
tRST_ DEGLITCH
RESET
tRST_ DEGLITCH
Figure 18. Conditions to Activate RESET
12
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
Feature Description (continued)
VIN
0.9 × VO
VOUT
VTH
DELAY
tPOR
RESET
Figure 19. External Programmable-Reset Delay
8.3.5 Adjustable Output Voltage (ADJ for TPS7B6701)
An output voltage between 1.5 V and 18 V can be selected by using the external resistor dividers. Use
Equation 2 to calculate the output voltage, where VADJ = 1.233 V. In order to avoid a large leakage current and to
prevent a divider error, the value of (R1 + R2) must between 10 k and 100 kΩ.
æ R2 ö
VO = VADJ ´ ç 1 +
R1 ÷ø
è
(2)
VI
Vbat
47 µF
TPS7B6701-Q1
VO
Vreg
22 µF
10k
EN
R2
RESET
ADJ
GND
DELAY
R1
Figure 20. External Feedback Resistor Divider
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
13
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
Feature Description (continued)
8.3.6 Undervoltage Shutdown
The TPS7B67xx-Q1 family of devices has an internally-fixed undervoltage shutdown threshold. Undervoltage
shutdown activates when the input voltage on VIN drops below VINUVLO. This activation ensures the regulator is
not latched into an unknown state during low-input supply voltage. If the input voltage has a negative transient
that drops below the UVLO threshold and recovers, the regulator shuts down and powers up similar to a typical
power-up sequence when the input voltage is above the required levels.
8.3.7 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
standard operation, the junction temperature must not exceed the TSD trip-point. If the junction temperature
exceeds the TSD trip-point, the output turns off. When the junction temperature falls below the TSD trip-point
minus TSD hysteresis, the output turns on again.
8.3.8 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 175°C which allows
the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator and protects it from damage as a result of
overheating.
The internal protection circuitry of the TPS7B67xx-Q1 device has been designed to protect against overload
conditions. The circuitry was not intended to replace proper heat-sinking. Continuously running the TPS7B67xxQ1 device into thermal shutdown degrades device reliability.
8.4 Device Functional Modes
8.4.1 Operation With VIN < 4 V
The devices operate with input voltages above 4 V. The maximum UVLO voltage is 2.6 V and operates at input
voltage above 4 V. The devices can also operate at lower input voltages; no minimum UVLO voltage is specified.
At input voltages below the actual UVLO voltage, the devices do not operate.
8.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.7 V (maximum), with the EN pin is held above that voltage and the
input voltage is above the 4 V, the device becomes active. The enable falling edge is 0.4 V (minimum), with the
EN pin is held below that voltage the device is disabled, the IC quiescent current is reduced in this state.
14
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 21 and Figure 22 show typical application circuits for the TPS7B6701-Q1 device and the TPS7B6733-Q1
and TPS7B6750-Q1 device respectively. Based on the end-application, different values of external components
can be used. An application can require a larger output capacitor during fast load steps in order to prevent a
reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better
load transient response.
9.2 Typical Application
VI
Vbat
TPS7B6733-Q1
TPS7B6750-Q1
TPS7B6701-Q1
VO
47 µF
Vreg
VI
Vbat
22 µF
47 µF
10k
EN
VO
Vreg
22 µF
R2
10k
RESET
EN
RESET
ADJ
GND
GND
R1
DELAY
Figure 21. Typical Application Schematic for
TPS7B6701-Q1
DELAY
Figure 22. Typical Application Schematic for
TPS7B6733-Q1 and TPS7B6750-Q1
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4 V to 40 V
Output voltage
1.5 V to 18 V
Output current rating
450 mA
Output capacitor range
10 µF to 500 µF
Output capacitor ESR range
1 mΩ to 20 Ω
DELAY capacitor range
100 pF to 500 nF
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
15
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
9.2.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process, determine the following:
Input voltage range
Output voltage
Output current rating
Output capacitor
Power-up reset delay time
9.2.2.1 Power Dissipation and Thermal Considerations
Device power dissipation is calculated with Equation 3.
PD = IO × (VI – VO) + IQ × VI
where
•
•
•
•
PD = continuous power dissipation
IO = output current
VI = input voltage
VO = output voltage
(3)
As IQ « IO, the term IQ × VI in Equation 3 can be ignored.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with
Equation 4.
TJ = TA + (RθJA × PD)
where
•
RθJA = junction-to-ambient air thermal impedance
(4)
A rise in junction temperature because of power dissipation can be calculated with Equation 5.
ΔT = TJ – TA = (RθJA × PD)
(5)
For a given maximum junction temperature (TJM), the maximum ambient air temperature (TAM) at which the
device can operate is calculated with Equation 6.
TAM = TJM – (RθJA × PD)
(6)
9.2.3 Application Curves
Load = 200 mA
CIN = COUT = 47 µF
Figure 23. TPS7B6750-Q1 Power-Up Waveform
16
Submit Documentation Feedback
Load = 200 mA
CIN = COUT = 47 µF
Figure 24. TPS7B6750-Q1 Power-Down Waveform
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 40 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS7B67xx-Q1 device, an
electrolytic capacitor with a value of 47 µF and a ceramic bypass capacitor are recommended to add at the input.
10.1 Dropout Recovery
All LDOs have some overshoot when recovering from dropout, how much is primarily dependent on the transient
response (bandwidth) of the error amplifier. Because of design and system level tradeoffs made when creating
the TPS7B67xx-Q1, the error amplifier has a slower transient response than many other LDOs, which is evident
in the load transient plot in Figure 15. This slower transient response can cause the output to overshoot
significantly when the device is recovering from a dropout condition. A well-regulated power supply eliminates
this behavior by keeping the TPS7B67xx-Q1 out of dropout. If the device is placed into dropout and the rising VIN
ramp rate is less than 200 mV/ms, the overshoot is limited to 0.5 V; however, faster ramp rates result in more
overshoot and may require a zener diode on the output to limit the VOUT overshoot.
10.1.1 LDO Dropout Recovery Explained
When an LDO is in dropout the output voltage is below the accuracy specification. This condition causes the
error amplifier to force the gate of the pass transistor such that the pass transistor is fully on and provides the
least resistance possible, meaning VOUT tracks VIN as closely as possible. When the input voltage recovers, the
error amplifier must force the gate of the pass device to the opposite rail making the pass transistor more
resistive. The change in gate voltage takes a finite amount of time, as dictated by the bandwidth of the error
amplifier. If VIN rises quickly during that time then VOUT tracks VIN and overshoots above the nominal output
voltage. Figure 25 depicts a graphical representation of an LDO recovering from dropout.
The amplitude of the overshoot is determined by both the speed of the VIN ramp and the transient response of
the LDO, which determines how long is required for the error amplifier to respond to changes on VOUT. The
amount of time required for the overshoot to be discharged is determined by the load current that must drain the
excess charge that has accumulated on COUT.
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
17
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
Dropout Recovery (continued)
Transient r esp onse
time of the LDO
Input V olta ge
Loa d curre nt
discharges
output
voltage
Dropou t
VOUT = VIN - VDO
Output Voltage
VDO
Voltage
Output Voltage in
normal reg ulation
VGS voltage
duri ng
overshoot
(pass de vice
fully off)
Input V olta ge
VGS voltage for
normal op eration
VGS voltage for
normal op eration
Gate Voltage
VGS in dro pout (pass
device full y on)
Time
Figure 25. LDO Response Entering and Exiting Dropout
10.1.2 TPS7B67xx-Q1 Dropout During Startup
The TPS7B67xx-Q1 does not overshoot significantly if the LDO is enabled after the input voltage is already
above VOUT(NOM) plus VDO. Furthermore, startup performance is not affected as long as the input voltage
transitions from VUVLO+(IN) to VOUT(NOM) plus VDO in less than 1 millisecond. Approximately 1 millisecond is
required for the TPS7B67xx-Q1 reference voltage to reach its steady state value, so input voltage startup
transitions that are less than 1 millisecond do not force the device into dropout. One example that does not
overshoot is a 5-V output voltage with full load (full load has the highest dropout), where the input voltage ramps
steadily from 0 V to 5.45 V in less than 3 milliseconds. Overshoot does not occur in this case because the input
reaches VOUT plus VDO before the reference has come up all the way to its final value, keeping the LDO out of
dropout. Figure 26 depicts an example of a startup ramp rate that is just fast enough to keep a device with a 5-V
output voltage from going into dropout.
18
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
Dropout Recovery (continued)
Figure 26. Startup Ramp Speed to Avoid Dropout
11 Layout
11.1 Layout Guidelines
11.1.1
Enhanced Thermal Pad
For the PWP package, TI recommends to layout an enhanced thermal pad on the board in order to realize better
thermal impedance; see Figure 27. No extra board size is required and the standard operation is not influenced
by this layout.
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
19
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
Layout Guidelines (continued)
180
RESET
1
20
NC
NC
2
19
VIN
DELAY
3
18
NC
VOUT
4
17
NC
ADJ/NC
5
16
NC
NC
6
15
EN
NC
7
14
NC
GND
8
13
GND
NC
9
12
NC
NC
10
11
NC
Large Pad on EVM
Enhance Thermal
dissipating
Figure 27. Thermally Enhanced Layout for the PWP Package (TPS7B6701-Q1)
11.1.2 Package Mounting
Solder-pad footprint recommendations for the TPS7B67xx-Q1 devices are available at the end of this data sheet
and at www.ti.com.
11.1.3 Board Layout Recommendations to Improve PSRR and Noise Performance
•
•
•
•
20
To improve AC performance such as PSRR, output noise, and transient response, TI recommends to design
the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND
pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND
pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and
ensure stability. Every capacitor must be placed as close to the device as possible and on the same side of
the PCB as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The
use of vias and long traces is strongly discouraged because of the negative impact on system performance.
Vias and long traces can also cause instability.
If possible, and to ensure the maximum performance listed in this data sheet, use the same layout pattern
used for TPS7B67xx-Q1 evaluation board, available at www.ti.com.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
Layout Guidelines (continued)
11.1.4 Additional Layout Considerations
Because of the high impedance of the ADJ pin, the regulator is sensitive to parasitic capacitances that can
couple undesirable signals from nearby components (especially from logic and digital ICs, such as
microcontrollers and microprocessors). These capacitive-coupled signals can produce undesirable output-voltage
transients. If undesirable output-voltage transients occur, TI recommends to use a fixed-voltage version of the
TPS7B67xx-Q1 devices, or to isolate the ADJ node by flooding the local PCB area with ground-to-plane copper
in order to minimize any undesirable signal coupling.
11.2 Layout Example
180
RESET
NC
NC
VIN
DELAY
NC
VOUT
NC
ADJ
NC
NC
EN
Connect through
bottom layer
VI
Power Ground
Output filter
capacitor, place
close to chip VOUT
Input bypass
capacitor
TPS7B6701-Q1 (PWP)
NC
GND
NC
GND
Power Ground
NC
NC
NC
NC
Figure 28. TPS7B6701-Q1 Layout Example
Copyright © 2013–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
21
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
SLVSCB2D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS7B6701-Q1
Click here
Click here
Click here
Click here
Click here
TPS7B6733-Q1
Click here
Click here
Click here
Click here
Click here
TPS7B6750-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7B6701QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B6701
TPS7B6733QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B6733
TPS7B6750QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B6750
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS7B6701QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
TPS7B6733QPWPRQ1
HTSSOP
PWP
20
2000
330.0
TPS7B6750QPWPRQ1
HTSSOP
PWP
20
2000
330.0
6.95
7.1
1.6
8.0
16.0
Q1
16.4
6.95
7.1
1.6
8.0
16.0
Q1
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7B6701QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS7B6733QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS7B6750QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising