Texas Instruments | CSD17483F4 30-V N-Channel FemtoFET MOSFET (Rev. E) | Datasheet | Texas Instruments CSD17483F4 30-V N-Channel FemtoFET MOSFET (Rev. E) Datasheet

Texas Instruments CSD17483F4 30-V N-Channel FemtoFET MOSFET (Rev. E) Datasheet
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CSD17483F4
SLPS447E – JULY 2013 – REVISED APRIL 2018
CSD17483F4 30-V N-Channel FemtoFET™ MOSFET
1 Features
•
•
•
•
1
•
•
•
•
Product Summary
Low On-Resistance
Low Qg and Qgd
Low-Threshold Voltage
Ultra-Small Footprint (0402 Case Size)
– 1.0 mm × 0.6 mm
Ultra-Low Profile
– 0.35-mm Height
Integrated ESD Protection Diode
– Rated > 4-kV HBM
– Rated > 2-kV CDM
Lead and Halogen Free
RoHS Compliant
TA = 25°C
•
•
Drain-to-Source Voltage
Qg
Gate Charge Total (4.5 V)
Qgd
Gate Charge Gate-to-Drain
RDS(on)
VGS(th)
Drain-to-Source
On-Resistance
UNIT
30
V
1010
pC
130
pC
VGS = 1.8 V
370
VGS = 2.5 V
240
VGS = 4.5 V
200
Threshold Voltage
0.85
mΩ
V
Device Information(1)
DEVICE
QTY
CSD17483F4
3000
CSD17483F4T
250
MEDIA
PACKAGE
SHIP
7-Inch Reel
Femto(0402)
1.00 mm × 0.60 mm
SMD Lead Less
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
TYPICAL VALUE
VDS
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Single-Cell Battery Applications
Handheld and Mobile Applications
Absolute Maximum Ratings
TA = 25°C unless otherwise stated
3 Description
This 200-mΩ, 30-V N-Channel FemtoFET™
MOSFET technology is designed and optimized to
minimize the footprint in many handheld and mobile
applications. This technology is capable of replacing
standard small signal MOSFETs while providing at
least a 60% reduction in footprint size.
Typical Part Dimensions
5m
0.3
m
VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
VGS
Gate-to-Source Voltage
12
V
ID
Continuous Drain Current, TA = 25°C(1)
1.5
A
IDM
Pulsed Drain Current, TA = 25°C(2)
5
A
Continuous Gate Clamp Current
35
Pulsed Gate Clamp Current(2)
350
Power Dissipation(1)
500
IG
PD
V(ESD)
Human-Body Model (HBM)
4
Charged-Device Model (CDM)
2
TJ,
Tstg
Operating Junction,
Storage Temperature
EAS
Avalanche Energy, Single Pulse ID = 7.4 A,
L = 0.1 mH, RG = 25 Ω
mA
mW
kV
–55 to 150
°C
2.7
mJ
(1) Typical RθJA = 90°C/W on 1-in2 (6.45-cm2), 2-oz
(0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4
PCB.
(2) Pulse duration ≤ 300 μs, duty cycle ≤ 2%.
Top View
60
1.
0.
00
m
m
D
m
m
G
S
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17483F4
SLPS447E – JULY 2013 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
6.5
7
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 Mechanical Dimensions ............................................ 8
7.2 Recommended Minimum PCB Layout...................... 9
7.3 Recommended Stencil Pattern ................................. 9
4 Revision History
Changes from Revision D (Decermber 2016) to Revision E
Page
•
Raised IDSS Test Condition Voltage ........................................................................................................................................ 3
•
Raised IGSS Test Condition Voltage........................................................................................................................................ 3
Changes from Revision C (September 2014) to Revision D
Page
•
Added Receiving Notification of Documentation Updates in the Device and Documentation Support section ..................... 7
•
Added Community Resources in the Device and Documentation Support section ............................................................... 7
•
Updated all mechanical drawings, increased the size of the pads in the Recommended Stencil Pattern section. .............. 8
Changes from Revision B (January 2014) to Revision C
•
Page
Corrected timing VDS to read 15 V ......................................................................................................................................... 3
Changes from Revision A (November 2013) to Revision B
Page
•
Added IG parameter ................................................................................................................................................................ 1
•
Lowered IDSS limit.................................................................................................................................................................... 3
•
Lowered IGSS limit ................................................................................................................................................................... 3
Changes from Original (July 2013) to Revision A
•
2
Page
Removed jumbo reel info and included small reel info........................................................................................................... 1
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 24 V
100
nA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 10 V
50
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 μA
V
RDS(on)
Drain-to-source on-resistance
gfs
Transconductance
30
0.65
V
0.85
1.10
VGS = 1.8 V, IDS =0.5 A
370
550
VGS = 2.5 V, IDS =0.5 A
240
310
VGS = 4.5 V, IDS = 0.5 A
200
260
VGS = 8 V, IDS = 0.5 A
185
240
VDS = 15 V, IDS = 0.5 A
2.4
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (4.5 V)
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tf
Fall time
145
190
pF
42
55
pF
2
3
pF
1300
pC
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Ω
23
1010
VDS = 15 V, IDS = 0.5 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 0.5 A,RG = 2 Ω
130
pC
220
pC
145
pC
1095
pC
3.3
ns
1.3
ns
10.6
ns
3.4
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 0.5 A, VGS = 0 V
VDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs
0.73
0.9
V
1475
pC
5.5
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
TYPICAL VALUES
Junction-to-ambient thermal resistance (1)
90
Junction-to-ambient thermal resistance (2)
250
UNIT
°C/W
Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
3.6
2.2
3.2
2
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
Figure 1. Transient Thermal Impedance
2.8
2.4
2
1.6
1.2
0.8
VGS =8V
VGS =4.5V
0.4
0
0
0.1
VGS =2.5V
VGS =1.8V
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
1
VDS = 5V
1.8
1.6
1.4
1.2
1
0.8
0.6
TC = 125°C
TC = 25°C
TC = −55°C
0.4
0.2
0
0
G001
Figure 2. Saturation Characteristics
4
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0.4
0.8
1.2
1.6
VGS - Gate-to-Source Voltage (V)
2
2.4
G001
Figure 3. Transfer Characteristics
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
1000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 0.5A
VDS =15V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
100
10
2
1
0
0
0.2
0.4
0.6
0.8 1 1.2 1.4 1.6
Qg - Gate Charge (nC)
1.8
2
1
2.2
0
3
6
G001
Figure 4. Gate Charge
30
G001
400
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
27
Figure 5. Capacitance
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
−75
−25
25
75
125
TC - Case Temperature (ºC)
280
240
200
160
120
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
Figure 7. On-State Resistance vs Gate-to-Source Voltage
10
VGS = 1.8V
VGS = 8V
ISD − Source-to-Drain Current (A)
ID =0.5A
1.3
1.2
1.1
1
0.9
0.8
0.7
−75
320
G001
Figure 6. Threshold Voltage vs Temperature
1.4
TC = 25°C Id = 0.5A
TC = 125ºC Id = 0.5A
360
80
175
1.5
Normalized On-State Resistance
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs Temperature
1
G001
Figure 9. Typical Diode Forward Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
1ms
10ms
100ms
1s
DC
10
1
0.1
Single Pulse
Typical RthetaJA =250ºC/W(min Cu)
0.01
0.01
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
100
0.1
1
10
VDS - Drain-to-Source Voltage (V)
10
1
0.1
0.001
50
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Typical RthetaJA =90ºC/W(max Cu)
0.0
−50
−25
0
25
50
75
100 125
TA - AmbientTemperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs Temperature
6
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
FemtoFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
1.04
0.96
A
B
PIN 1 INDEX AREA
0.64
0.56
0.35 MAX
C
SEATING PLANE
0.65
0.325
0.175
2
3
0.35
0.51
0.49
1
0.015
8
0.16
2X
0.14
C B
A
2X
0.26
0.24
0.26
0.24
0.015
C A
B
(1)
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and
tolerancing per ASME Y14.5M.
(2)
This drawing is subject to change without notice.
(3)
This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device data
sheet or contact a local TI representative.
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7.2 Recommended Minimum PCB Layout
(0.25)
2X (0.25)
PKG
0.05 MIN
ALL AROUND
2X (0.15)
1
3
SYMM
(0.35)
(0.5)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
LAND PATTERN EXAMPLE
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
SCALE:50X
(1)
All dimensions are in millimeters.
(2)
For more information, see QFN/SON PCB Attachment (SLUA271).
7.3 Recommended Stencil Pattern
2X (0.25)
2X (0.2)
PKG
(0.25)
1
SYMM
(0.4)
(0.5)
3
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
SOLDER PASTE EXAMPLE
(1)
(2)
BASED ON 0.075 - 0.1 mm THICK STENCIL
All dimensions are in millimeters.
SCALE:50X
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may
have alternate design recommendations.
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PACKAGE OPTION ADDENDUM
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20-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD17483F4
ACTIVE
PICOSTAR
YJC
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
DP
CSD17483F4T
ACTIVE
PICOSTAR
YJC
3
250
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
DP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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20-Apr-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
CSD17483F4
PICOST
AR
YJC
3
3000
178.0
8.4
CSD17483F4
PICOST
AR
YJC
3
3000
180.0
CSD17483F4T
PICOST
AR
YJC
3
250
CSD17483F4T
PICOST
AR
YJC
3
250
0.7
1.1
0.46
4.0
8.0
Q2
8.4
0.7
1.1
0.46
4.0
8.0
Q2
178.0
8.4
0.7
1.1
0.46
4.0
8.0
Q2
180.0
8.4
0.7
1.1
0.46
4.0
8.0
Q2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17483F4
PICOSTAR
YJC
3
3000
220.0
220.0
35.0
CSD17483F4
PICOSTAR
YJC
3
3000
182.0
182.0
20.0
CSD17483F4T
PICOSTAR
YJC
3
250
220.0
220.0
35.0
CSD17483F4T
PICOSTAR
YJC
3
250
182.0
182.0
20.0
Pack Materials-Page 2
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