Texas Instruments | CSD86360Q5D Synchronous Buck NexFET™ Power Block (Rev. B) | Datasheet | Texas Instruments CSD86360Q5D Synchronous Buck NexFET™ Power Block (Rev. B) Datasheet

Texas Instruments CSD86360Q5D Synchronous Buck NexFET™ Power Block (Rev. B) Datasheet
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CSD86360Q5D
SLPS327B – SEPTEMBER 2012 – REVISED APRIL 2018
CSD86360Q5D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The CSD86360Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 5-mm × 6-mm outline.
Optimized for 5-V gate drive applications, this product
offers a flexible solution capable of offering a highdensity power supply when paired with any 5-V gate
drive from an external controller/driver.
1
Half-Bridge Power Block
91% System Efficiency at 25 A
Up to 50-A Operation
High-Frequency Operation (Up to 1.5 MHz)
High-Density SON 5-mm × 6-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Figure 1. Top View
2 Applications
•
•
•
•
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
BG
P0116-01
Device Information(1)
DEVICE
CSD86360Q5D
MEDIA
13-Inch Reel
QTY
PACKAGE
SHIP
2500
SON
5.00-mm × 6.00-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency (%)
100
7
90
6
80
5
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = .29µH
fSW = 500kHz
TA = 25ºC
70
60
50
4
3
2
1
40
30
Power Loss (W)
Typical Power Block Efficiency
and Power Loss
Typical Circuit
0
5
10
15
Output Current (A)
20
25
0
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD86360Q5D
SLPS327B – SEPTEMBER 2012 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
6
8
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Power Block Performance ........................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 11
6.1 Application Information............................................ 11
6.2 Typical Application .................................................. 14
7
Layout ................................................................... 16
7.1 Layout Guidelines ................................................... 16
7.2 Layout Example ...................................................... 17
8
Device and Documentation Support.................. 18
8.1
8.2
8.3
8.4
8.5
8.6
9
Documentation Support .......................................... 18
Receiving Notification of Documentation Updates.. 18
Community Resources............................................ 18
Trademarks ............................................................. 18
Electrostatic Discharge Caution .............................. 18
Glossary .................................................................. 18
Mechanical, Packaging, and Orderable
Information ........................................................... 19
9.1
9.2
9.3
9.4
Q5D Package Dimensions......................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
Q5D Tape and Reel Information .............................
19
20
21
21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2013) to Revision B
Page
•
Changed Recommended PCB Design Overview section to Layout section ........................................................................ 16
•
Added Device and Documentation Support section............................................................................................................. 18
•
Changed Mechanical Data section to Mechanical, Packaging, and Orderable Information section.................................... 19
•
Updated Q5D Package Dimensions section ........................................................................................................................ 19
•
Updated Land Pattern Recommendation drawing................................................................................................................ 20
•
Updated Stencil Recommendation drawing ......................................................................................................................... 21
Changes from Original (September 2012) to Revision A
Page
•
Changed the footnote notations in the THERMAL INFORMATION table .............................................................................. 3
•
Updated Figure 7.................................................................................................................................................................... 6
•
Updated Figure 8.................................................................................................................................................................... 6
•
Updated Figure 9.................................................................................................................................................................... 6
•
Updated Figure 10.................................................................................................................................................................. 6
2
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SLPS327B – SEPTEMBER 2012 – REVISED APRIL 2018
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)
(1)
PARAMETER
CONDITIONS
Voltage
MIN
MAX
VIN to PGND
25
VSW to PGND
25
VSW to PGND (10 ns)
UNIT
27
TG to TGR
–8
BG to PGND
–8
V
10
10
Pulsed current rating, IDM (2)
120
A
Power dissipation, PD (3)
13
W
Avalanche energy, EAS
Sync FET, ID = 110 A, L = 0.1 mH
605
Control FET, ID = 61 A, L = 0.1 mH
186
mJ
Operating junction, TJ
–55
150
°C
Storage temperature, TSTG
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µs. Duty cycle ≤ 0.01%.
TPCB ≤ 95°C.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
PARAMETER
VGS
Gate drive voltage
VIN
Input supply voltage
ƒSW
Switching frequency
CONDITIONS
MIN
4.5
UNIT
8
V
22
CBST = 0.1 μF (min)
200
Operating current
TJ
MAX
Operating temperature
1500
V
kHz
50
A
125
°C
MAX
UNIT
5.3 Power Block Performance
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
PLOSS
Power loss (1)
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 25 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25°C
2.6
W
IQVIN
VIN quiescent current
TG to TGR = 0 V
BG to PGND = 0 V
10
µA
(1)
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5-V driver IC.
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
Junction-to-ambient thermal resistance (min Cu) (1)
Junction-to-ambient thermal resistance (max Cu) (1) (2)
MIN
TYP
MAX
102
50
UNIT
°C/W
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
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Thermal Information (continued)
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJC
Junction-to-case thermal resistance (top of package)
MIN
TYP
(1)
MAX
20
Junction-to-case thermal resistance (PGND pin) (1)
2
UNIT
°C/W
5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
Q1 Control FET
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
25
25
IDSS
Drain-to-source leakage
current
VGS = 0 V, VDS = 20 V
IGSS
Gate-to-source leakage
current
VDS = 0 V, VGS = +10 / –8
V
VGS(th)
Gate-to-source threshold
voltage
VDS = VGS, IDS = 250 μA
ZDS(on)
Drain-to-source onimpedance
VIN = 12 V, VDD = 5 V,
VOUT = 1.3 V IOUT = 25 A,
ƒSW = 500 kHz,
LOUT = 0.3 μH
3.7
0.7
mΩ
gfs
Transconductance
VDS = 10 V, IDS = 20 A
113
169
S
1
V
1
1
μA
100
100
nA
1.15
V
2.1
0.75
DYNAMIC CHARACTERISTICS
CISS
Input capacitance (1)
COSS
Output capacitance (1)
CRSS
Reverse transfer
capacitance (1)
VGS = 0 V, VDS = 12.5 V,
ƒ = 1 MHz
(1)
1590
2060
3910
5080
pF
840
1090
1970
2560
pF
42
54
53
69
pF
RG
Series gate resistance
1.2
2.5
1.1
2.2
Ω
Qg
Gate charge total (4.5 V) (1)
9.7
12.6
23
30
nC
Qgd
Gate charge gate-to-drain
VDS = 12.5 V,
Gate charge gate-to-source IDS = 20 A
2.3
3.6
nC
Qgs
3.5
6.0
nC
Qg(th)
Gate charge at Vth
1.9
3.5
nC
QOSS
Output charge
15.1
33
nC
td(on)
Turnon delay time
8.4
9.5
ns
tr
Rise time
20.4
14.8
ns
td(off)
Turnoff delay time
14.5
29.3
ns
tf
Fall time
4.3
6.6
ns
VDS = 12.5 V, VGS = 0 V
VDS = 12.5 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
IDS = 20 A, VGS = 0 V
0.85
Qrr
Reverse recovery charge
50
nC
Reverse recovery time
Vdd = 12 V, IF = 20 A,
di/dt = 300 A/μs
27
trr
22
34
ns
(1)
4
1
0.75
0.82
V
Specified by design.
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SLPS327B – SEPTEMBER 2012 – REVISED APRIL 2018
HD
LD
HD
LG
HG
HS
LS
86350 5x6 QFN TTA MIN Rev1
86350 5x6 QFN TTA MIN Rev1
Max RθJA = 50°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
LD
Max RθJA = 102°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
LG
HG
M0189-01
HS
LS
M0190-01
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5.6 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise.
14
1.4
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
Power Loss (W)
10
8
6
4
2
0
1.1
1
0.9
0.8
0.7
0.6
0.5
0
5
10
15
20
25
30
35
Output Current (A)
40
45
0.4
−50
50
50
45
45
40
40
Output Current (A)
50
35
30
25
15
400LFM
200LFM
100LFM
Nat Conv
10
5
0
10
20
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
80
90
20
Output Current (A)
150
G001
25
20
15
0
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
400LFM
200LFM
100LFM
Nat Conv
0
10
20
G001
Figure 4. Safe Operating Area – PCB Vertical Mount (1)
0
125
30
5
30
40
50
60
70
Ambient Temperature (ºC)
25
50
75
100
Junction Temperature (ºC)
35
10
60
55
50
45
40
35
30
25
20
15
10
5
0
0
Figure 3. Normalized Power Loss vs Temperature
55
20
−25
G001
Figure 2. Power Loss vs Output Current
Output Current (A)
1.2
55
0
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
1.3
Power Loss, Normalized
12
30
40
50
60
70
Ambient Temperature (ºC)
80
90
G001
Figure 5. Safe Operating Area – PCB Horizontal Mount (1)
40
60
80
100
Board Temperature (ºC)
120
140
G001
Figure 6. Typical Safe Operating Area(1)
(1)
6
The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and
Implementation section for detailed explanation.
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Typical Power Block Device Characteristics (continued)
TJ = 125°C, unless stated otherwise.
1.5
16.1
12.1
1.2
8.0
1.1
4.0
1
0.0
0.8
0
200
400
600
800 1000 1200
Switching Frequency (kHz)
1.4
1.3
4.0
1
0.0
−8.0
1400 1550
0.8
−4.0
2
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 0.3µH
IOUT = 50A
1.2
7.6
0
1
2
2.5
3
3.5
4
Output Voltage (V)
4.5
5
−15.2
5.5
18
20
22
24
−8.0
G001
20.1
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
IOUT = 50A
1.4
1.3
16.1
12.1
1.2
8
1.1
4
1
0
−4
0.8
0
0.1
0.2
G001
Figure 9. Normalized Power Loss vs Output Voltage
10 12 14 16
Input Voltage (V)
0.9
−7.6
0.8
1.5
8
Figure 8. Normalized Power Loss vs Input Voltage
Power Loss, Normalized
22.9
SOA Temperature Adj (ºC)
Power Loss, Normalized
30.5
15.2
1
6
1.5
38.1
1.4
0.6
0.5
4
G001
45.7
1.6
12.1
8.0
Figure 7. Normalized Power Loss vs Switching Frequency
1.8
16.1
1.1
0.9
2.2
2
20.1
1.2
−4.0
0.9
24.1
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
IOUT = 50A
SOA Temperature Adj (ºC)
1.3
1.6
20.1
SOA Temperature Adj (ºC)
Power Loss, Normalized
1.4
24.1
Power Loss, Normalized
VIN = 12V
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
IOUT = 50A
1.5
SOA Temperature Adj (ºC)
1.6
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
−8
1.1
G001
Figure 10. Normalized Power Loss vs Output Inductance
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5.7 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
200
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
80
60
40
20
0
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage (V)
180
160
140
120
100
80
60
20
0
0.5
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
40
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage (V)
G001
Figure 11. Control MOSFET Saturation
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
100
VDS = 5V
10
1
0.1
TC = 125°C
TC = 25°C
TC = −55°C
0.01
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
VDS = 5V
10
1
0.1
TC = 125°C
TC = 25°C
TC = −55°C
0.01
0.001
0
0.5
G001
Figure 13. Control MOSFET Transfer
ID = 20A
VDD = 12.5V
9
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
3
G001
10
8
7
6
5
4
3
2
1
0
4
8
12
16
Qg - Gate Charge (nC)
20
24
ID = 20A
VDD = 12.5V
9
8
7
6
5
4
3
2
1
0
0
5
G001
Figure 15. Control MOSFET Gate Charge
8
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
Figure 14. Sync MOSFET Transfer
10
0
G001
Figure 12. Sync MOSFET Saturation
100
0.001
0.5
10
15
20 25 30 35 40
Qg - Gate Charge (nC)
45
50
55
G001
Figure 16. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
10
10
1
1
C − Capacitance (nF)
C − Capacitance (nF)
TA = 25°C, unless stated otherwise.
0.1
0.01
0.001
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
5
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
10
15
20
VDS - Drain-to-Source Voltage (V)
25
0.001
0
5
G001
Figure 17. Control MOSFET Capacitance
f = 1MHz
VGS = 0V
10
15
20
VDS - Drain-to-Source Voltage (V)
1.4
ID = 250µA
VGS(th) - Threshold Voltage (V)
VGS(th) - Threshold Voltage (V)
ID = 250µA
1.6
1.4
1.2
1
0.8
0.6
−75
−25
25
75
125
TC - Case Temperature (ºC)
1.2
1
0.8
0.6
0.4
0.2
−75
175
−25
G001
Figure 19. Control MOSFET VGS(th)
25
75
125
TC - Case Temperature (ºC)
175
G001
Figure 20. Sync MOSFET VGS(th)
15
15
ID = 20A
TC = 25°C
TC = 125ºC
RDS(on) - On-State Resistance (mΩ)
RDS(on) - On-State Resistance (mΩ)
G001
Figure 18. Sync MOSFET Capacitance
1.8
12
9
6
3
0
25
0
1
2
3
4
5
6
7
8
VGS - Gate-to- Source Voltage (V)
9
Figure 21. Control MOSFET RDS(on) vs VGS
10
ID = 20A
TC = 25°C
TC = 125ºC
12
9
6
3
0
0
1
G001
2
3
4
5
6
7
8
VGS - Gate-to- Source Voltage (V)
9
10
G001
Figure 22. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
1.6
1.4
1.2
1
0.8
0.6
−75
−25
ID = 20A
VGS = 8V
Normalized On-State Resistance
Normalized On-State Resistance
ID = 20A
VGS = 8V
25
75
125
TC - Case Temperature - ºC
1.4
1.2
1
0.8
0.6
−75
175
Figure 23. Control MOSFET Normalized RDS(on)
ISD − Source-to-Drain Current (A)
ISD − Source-to-Drain Current (A)
10
1
0.1
0.01
0.001
G001
TC = 25°C
TC = 125°C
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
1
10
1
0.1
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
0
1
G001
Figure 26. Sync MOSFET Body Diode
I(AV) - Peak Avalanche Current (A)
200
100
TC = 25°C
TC = 125°C
10
0.01
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 25. Control MOSFET Body Diode
I(AV) - Peak Avalanche Current (A)
175
100
200
0.1
1
t(AV) - Time in Avalanche (ms)
10
100
TC = 25°C
TC = 125°C
10
0.01
G001
Figure 27. Control MOSFET Unclamped Inductive Switching
10
25
75
125
TC - Case Temperature - ºC
Figure 24. Sync MOSFET Normalized RDS(on)
100
0.0001
−25
G001
0.1
1
t(AV) - Time in Avalanche (ms)
10
G001
Figure 28. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following Application section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI customers are
responsible for determining suitability of components selection for their designs.
Customers should validate and test their design implementation to confirm system
functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 29). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Figure 29. Equivalent System Schematic
The CSD86360Q5D is part of TI’s power block product family, which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon, which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 30). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET, which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With CSI Consideration for
Synchronous Buck Converters (SLPA009).
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Application Information (continued)
Figure 30. Elimination of Parasitic Inductances
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 31 and Figure 32 compare the efficiency and power loss performance of the
CSD86360Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86360Q5D clearly highlights the importance of considering the effective AC on-impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
100
14
PowerBlock HS/LS RDS(ON) = 3.7mΩ/1.5mΩ
Discrete HS/LS RDS(ON) = 3.7mΩ/1.5mΩ
Discrete HS/LS RDS(ON) = 3.7mΩ/0.7mΩ
98
96
Power Loss (W)
Efficiency (%)
94
92
90
88
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
86
84
82
80
78
0
5
10
15
10
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
8
6
4
2
20 25 30 35 40
Output Current (A)
45
50
55
60
0
0
5
G001
Figure 31. Efficiency Comparison for Discrete Parts vs
Power Block
12
PowerBlock HS/LS RDS(ON) = 3.7mΩ/1.5mΩ
Discrete HS/LS RDS(ON) = 3.7mΩ/1.5mΩ
Discrete HS/LS RDS(ON) = 3.7mΩ/0.7mΩ
12
10
15
20 25 30 35 40
Output Current (A)
45
50
55
60
G001
Figure 32. Power Loss Comparison for Discrete Parts vs
Power Block
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Application Information (continued)
Table 1 below compares the traditional DC measured RDS(ON) of CSD86360Q5D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD86360Q5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
HS
PARAMETER
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
3.7
—
0.7
—
DC measured RDS(ON) (VGS = 4.5 V)
3.7
4.5
1.5
1.9
The CSD86360Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed, which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 2 plots the power loss of the CSD86360Q5D as a function of load current. This curve
is measured by configuring and running the CSD86360Q5D as it would be in the final application (see
Figure 33).The measured power loss is the CSD86360Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power loss
(1)
The power loss curve in Figure 2 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
The SOA curves in the CSD86360Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 4 to Figure 6 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.1.4 Normalized Curves
The normalized curves in the CSD86360Q5D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
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6.2 Typical Application
Figure 33. Typical Application
14
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Typical Application (continued)
6.2.1 Design Example: Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions
section). Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions,
the following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.2.1.1 Operating Conditions
•
•
•
•
•
Output current = 25 A
Input voltage = 7 V
Output voltage = 1 V
Switching frequency = 800 kHz
Inductor = 0.2 µH
6.2.1.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 25 A = 3.5 W (Figure 2)
Normalized power loss for input voltage ≈ 1.03 (Figure 8)
Normalized power loss for output voltage ≈ 0.90 (Figure 9)
Normalized power loss for switching frequency ≈ 1.15 (Figure 7)
Normalized power loss for output inductor ≈ 1.03 (Figure 10)
Final calculated power loss = 3.5 W × 1.03 × 0.90 × 1.15 × 1.03 ≈ 3.84 W
6.2.1.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 1.3°C (Figure 8)
SOA adjustment for output voltage ≈ –2.5°C (Figure 9)
SOA adjustment for switching frequency ≈ 6.0°C (Figure 7)
SOA adjustment for output inductor ≈ 1.3°C (Figure 10)
Final calculated SOA adjustment = 1.3 + (–2.5) + 6.0 + 1.3 ≈ 6.1°C
In the design example above, the estimated power loss of the CSD86360Q5D would increase to 3.84 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 6.1°C. Figure 34
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 6.1°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 34. Power Block SOA
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7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 35).
The example in Figure 35 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8
should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to TI App Note Snubber
Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber
values. The RC snubber should be placed as close as possible to the VSW node and PGND see Figure 35 (1)
7.1.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 35 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
16
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.2 Layout Example
Input Capacitors
Input Capacitors
TGR
TG
VIN
PGND
Output Capacitors
Driver IC
Power Block
BG
V SW
VSW
V SW
RC Snubber
Power Block
Location on Top
Layer
Top Layer
Output Inductor
Bottom Layer
Figure 35. Recommended PCB Layout (Top Down View)
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation see the following:
• Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters
(SLPA009)
• Snubber Circuits: Theory, Design and Application (SLUP100)
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.4 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
18
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q5D Package Dimensions
6.1
5.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
1.6 MAX
SEATING PLANE
0.08 C
3.156±0.1
(0.2) TYP
(1) TYP
EXPOSED
THERMAL PAD
0.05
0.00
4X (0.25)
4
5
2X
3.81
9
4.319±0.1
8
1
6X 1.27
PIN 1 ID
(OPTIONAL)
6X
(0.45)
0.71
0.51
0.71
0.51
8X
0.46
0.36
0.1
0.05
C A
C
B
4222206/A 01/2016
NOTES:
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
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Q5D Package Dimensions (continued)
MILLIMETERS
DIM
INCHES
MIN
MAX
MIN
MAX
a
1.40
1.5
0.055
0.059
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
1.630
1.730
0.064
0.068
d1
0.280
0.380
0.011
0.015
d2
0.200
0.300
0.008
0.012
d3
0.291
0.391
0.012
0.015
D1
4.900
5.100
0.193
0.201
D2
4.269
4.369
0.168
0.172
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.106
3.206
0.122
0.126
e
1.27 TYP
0.050
f
0.396
0.496
0.016
0.020
L
0.510
0.710
0.020
0.028
θ
0.00
—
—
—
K
0.812
0.032
9.2 Land Pattern Recommendation
(0.81)
( 0.2) VIA
TYP
(3.156)
PKG
(0.45)
6X (0.81)
8
1
(0.05) TYP
2X (0.41)
(4.319)
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
PKG
9
6X (0.41)
(0.705) TYP
(1.205)
6X (1.27)
4
5
(R0.05) TYP
(1.328)
TYP
(5.59)
LAND PATTERN EXAMPLE
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
NON SOLDER MASK DEFINED
(PREFERRED FOR PADS 3 - 8)
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK DEFINED
(PADS 1 - 2, OPTIONAL FOR OTHER PADS)
MASK DETAILS
1. This package is designed to be soldered toSOLDER
a thermal
pad on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
20
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9.3 Stencil Recommendation
(1.57) TYP
8X (0.81)
(0.785) TYP
METAL
TYP
PKG
(0.45)
6X (0.81)
8X (0.41)
8
1
SOLDER
MASK
EDGE
(0.56)
(1.41)
(0.15)
9
PKG
6X (1.27)
6X
(1.21)
4
5
(R0.05) TYP
6X (1.37)
(5.59)
SOLDER PASTE EXAMPLE
1. Laser cutting apertures with trapezoidal walls and
rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
9.4 Q5D Tape and Reel Information
4.00 ±0.10 (See Note 1)
K0
0.30 ±0.05
+0.10
2.00 ±0.05
Ø 1.50 –0.00
1.75 ±0.10
5.50 ±0.05
12.00 ±0.30
B0
R 0.20 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 5.30 ±0.10
B0 = 6.50 ±0.10
K0 = 1.90 ±0.10
M0191-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF reflow compatible.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD86360Q5D
ACTIVE
Package Type Package Pins Package
Drawing
Qty
LSON-CLIP
DQY
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
86360D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CSD86360Q5D
LSONCLIP
DQY
8
2500
330.0
15.4
5.3
6.3
1.2
8.0
12.0
Q2
CSD86360Q5D
LSONCLIP
DQY
8
2500
330.0
12.4
5.3
6.3
1.8
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD86360Q5D
LSON-CLIP
DQY
8
2500
335.0
335.0
32.0
CSD86360Q5D
LSON-CLIP
DQY
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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