Texas Instruments | TPS84250 7-V to 50-V Input, 2.5-A Step-Down Integrated Power Solution (Rev. C) | Datasheet | Texas Instruments TPS84250 7-V to 50-V Input, 2.5-A Step-Down Integrated Power Solution (Rev. C) Datasheet

Texas Instruments TPS84250 7-V to 50-V Input, 2.5-A Step-Down Integrated Power Solution (Rev. C) Datasheet
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TPS84250
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
TPS84250 7-V to 50-V Input, 2.5-A Step-Down, Integrated Power Solution
1 FEATURES
3 DESCRIPTION
•
The TPS84250 is an easy-to-use integrated power
solution that combines a 2.5-A DC/DC converter with
an inductor and passives into a low profile, QFN
package. This total power solution allows as few as
five external components and eliminates the loop
compensation and magnetics part selection process.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
Wide Input-Voltage Range from 7 V to 50 V
Output Adjustable from 2.5 V to 15 V
65-V Surge Capability
Efficiencies Up to 96%
Adjustable Switching Frequency
(300 kHz to 1 MHz)
Synchronizes to an External Clock
Adjustable Slow Start
Output Voltage Sequencing and Tracking
Power-Good Output
Programmable Undervoltage Lockout (UVLO)
Output Overcurrent Protection
Overyemperature Protection
Prebias Output Start-Up
Operating Temperature Range: –40°C to +85°C
Enhanced Thermal Performance: 14°C/W
Meets EN55022 Class B Emissions
For Design Help Visit http://www.ti.com/TPS84250
The small 9 mm × 11 mm × 2.8 mm, QFN package is
easy to solder onto a printed circuit board and allows
a compact point-of-load design with greater than 90%
efficiency and excellent power dissipation capability.
The TPS84250 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for
powering a wide range of ICs and systems.
Advanced packaging technology affords a robust and
reliable power solution compatible with standard QFN
mounting and testing techniques.
SIMPLIFIED APPLICATION
TPS84250
VIN
VOUT
VIN
VOUT
CIN
COUT
VADJ
2 APPLICATIONS
•
•
•
•
RSET
INH/UVLO
PWRGD
Industrial and Motor Controls
Automated Test Equipment
Medical and Imaging Equipment
High Density Power Systems
RT/CLK
SS/TR
STSEL
100
AGND
PGND
Efficiency (%)
95
90
85
80
75
70
VIN = 24 V, VOUT = 15 V, fSW = 1 MHz
VIN = 24 V, VOUT = 12 V, fSW = 800 kHz
0
0.5
1
1.5
Output Current (A)
2
2.5
G000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS84250
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
www.ti.com
Table 1. ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
4 Specifications
ABSOLUTE MAXIMUM RATINGS (1)
4.1
over operating temperature range (unless otherwise noted)
Input Voltage
Output Voltage
MIN
MAX
UNIT
VIN
–0.3
65
V
INH/UVLO
–0.3
5
V
VADJ
–0.3
3
V
PWRGD
–0.3
6
V
SS/TR
–0.3
3
V
STSEL
–0.3
3
V
RT/CLK
–0.3
3.6
V
PH
–0.6
65
V
–2
65
V
–0.6
VIN
V
±200
mV
RT/CLK
100
µA
INH/UVLO
100
µA
SS/TRK
200
µA
PWRGD
10
mA
PH 10ns Transient
VOUT
VDIFF (GND to exposed thermal
pad)
Source Current
Sink Current
Operating Junction Temperature
–40
105 (2)
°C
Storage Temperature
–65
150
°C
250
°C
Peak Reflow Case Temperature (3) (4)
Maximum Number of Reflows Allowed (3) (4)
Mechanical Shock
3
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mechanical Vibration
(1)
1500
Mil-STD-883D, Method 2007.2, 20-2000Hz
G
20
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the temperature derating curves in the Typical Characteristics section for thermal information.
For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.
Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.
(2)
(3)
(4)
4.2 RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
7
50
V
Output Voltage
2.5
15
V
fSW
Switching Frequency
400
1000
kHz
TA
Operating Ambient Temperature
-40
85
°C
VIN
Input Voltage
VOUT
UNIT
4.3 PACKAGE SPECIFICATIONS
TPS84250
UNIT
Weight
Flammability
MTBF Calculated reliability
2
0.9 grams
Meets UL 94 V-O
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
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31.7 MHrs
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4.4
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
ELECTRICAL CHARACTERISTICS
-40°C ≤ TA ≤ +85°C, VIN = 24 V, VOUT = 5.0 V, IOUT = 2.5 A, RT = Open
CIN = 2 x 2.2 µF ceramic, COUT = 2 x 47 µF ceramic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
IOUT
Output current
Over input voltage and output voltage range
VIN
Input voltage range
Over output current range
UVLO
VIN Undervoltage lockout
No hysteresis, Rising and Falling
VOUT(adj)
Output voltage adjust range
Over output current range
Set-point voltage tolerance
TA = 25°C; IOUT = 100 mA
Temperature variation
-40°C ≤ TA ≤ +85°C
±0.5%
Line regulation
Over input voltage range
±0.1%
Load regulation
Over output current range
±0.4%
Total output voltage variation
Includes set-point, line, load, and temperature variation
VOUT
VIN = 24 V
IOUT = 1.5 A
Efficiency
η
Output voltage ripple
ILIM
VIN = 48 V
IOUT = 1.5 A
VINH
Inhibit threshold voltage
IINH
INH Input current
II(stby)
Input standby current
Power Good
±2.0%
VOUT = 12 V, fSW = 800 kHz
93 %
VOUT = 5.0 V, fSW = 500 kHz
84 %
VOUT = 3.3 V, fSW = 400 kHz
79 %
VOUT = 12 V, fSW = 800 kHz
87 %
VOUT = 5.0 V, fSW = 500 kHz
79 %
VOUT = 3.3 V, fSW = 400 kHz
74 %
A
Recovery time
400
µs
VOUT
over/undershoot
90
PWRGD Thresholds
VOUT falling
Synchronization frequency
VCLK-H
CLK High-Level Threshold
VCLK-L
CLK Low-Level Threshold
DCLK
CLK Duty cycle
Thermal Shutdown
CIN
External input capacitance
COUT
External output capacitance
1.25
-3.8
INH pin to AGND
fCLK
VOUT
5.1
VINH > 1.36 V
RT/CLK pin OPEN
(4)
(3)
-0.9
I(PWRGD) = 3.5 mA
(7)
1%
V
(4)
±1.0%
±3.0%
1.15
Switching frequency
V
15
VINH < 1.15 V
PWRGD Low Voltage
(5)
(6)
V
2.5 (3)
No hysteresis
fSW
(2)
(3)
(4)
50 (2)
2.5
VOUT rising
(1)
A
7.0 (1)
20 MHz bandwith, 0.25 A ≤ IOUT ≤ 2.5 A, VOUT ≥ 3.3V
1.0 A/µs load step from 50 to 100%
IOUT(max)
UNIT
2.5
Current limit threshold
Transient response
MAX
0
1.3
Good
94%
Fault
109%
Fault
91%
Good
106%
mV
1.36
(5)
μA
4
µA
500
kHz
1000
kHz
0.2
300
400
300
1.9
CLK Control
0.5
0.7
25%
50%
Thermal shutdown
Thermal shutdown hysteresis
Ceramic
4.4
(6)
Non-ceramic
V
2.2
(7)
V
V
75%
180
°C
15
°C
10
µF
22
100
V
μA
430
µF
For output voltages ≤ 12 V, the minimum input voltage is 7 V or (VOUT+ 3 V), whichever is greater. For output voltages > 12 V, the
minimum input voltage is (1.33 x VOUT). See Figure 27 for more details.
The maximum input voltage is 50 V or (15 x VOUT), whichever is less.
Output voltages < 3.3 V are subject to reduced VIN(max) specifications and higher ripple magnitudes.
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor.
Value when no voltage divider is present at the INH/UVLO pin.
A minimum of 4.4µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation.
Locate the capacitor close to the device. See Table 3 for more details.
The required capacitance must include at least 2 x 47µF ceramic capacitors (or 4 x 22µF). Locate the capacitance close to the device.
Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 for more details.
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4.5 THERMAL INFORMATION
TPS84250
THERMAL METRIC (1)
RKG
UNIT
41 PINS
θJA
Junction-to-ambient thermal resistance (2)
14
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (4)
(1)
(2)
(3)
(4)
4
3.3
°C/W
6.8
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB
with 1 oz. copper and natural convection cooling. Additional airflow reduces θJA.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
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5 DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
TPS84250
Thermal Shutdown
PWRGD
PWRGD
Logic
Shutdown
Logic
VADJ
OCP
INH/UVLO
VIN
UVLO
VIN
PH
+
+
SS/TR
VREF
STSEL
RT/CLK
Comp
Power
Stage
and
Control
Logic
VOUT
OSC w/PLL
PGND
AGND
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Table 2. PIN DESCRIPTIONS
TERMINAL
NAME
DESCRIPTION
NO.
1
4
5
30
AGND
32
33
These pins are connected to the internal analog ground (AGND) of the device. This node should be treated
as the zero volt ground reference for the analog control circuitry. Pad 37 should be connected to PCB
ground planes using multiple vias for good thermal performance. Not all pins are connected together
internally. All pins must be connected together externally with a copper plane or pour directly under the
module. Connect AGND to PGND at a single point (GND_PT; pins 8 & 9). See Layout Recommendations.
34
37
2
DNC
3
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
25
6
7
21
22
PH
23
Phase switch node. Do not place any external component on these pins or tie them to a pin of another
function.
24
38
41
GND_PT
8
9
Ground Point. Connect AGND to PGND at these pins as shown in the Layout Considerations. These pins
are not connected to internal circuitry, and are not connected to one another.
10
11
12
VOUT
13
14
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
load and connect external bypass capacitors between these pins and PGND. Connect a resistor from these
pins to VADJ to set the output voltage.
15
39
16
17
18
PGND
19
This is the return current path for the power stage of the device. Connect these pins to the load and to the
bypass capacitors associated with VIN and VOUT. Pad 40 should be connected to PCB ground planes using
multiple vias for good thermal performance.
20
40
VIN
26
Input voltage. This pin supplies all power to the converter. Connect this pin to the input supply and connect
bypass capacitors between this pin and PGND.
INH/UVLO
27
Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control
the INH function. A resistor divider between this pin, AGND, and VIN sets the UVLO voltage.
SS/TR
28
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
A voltage applied to this pin allows for tracking and sequencing control.
STSEL
29
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this
pin open to enable the TR feature.
RT/CLK
31
This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An
external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be
used to synchronize to an external clock.
PWRGD
35
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
±6% out of regulation. A pull-up resistor is required.
VADJ
36
Connecting a resistor between this pin and VOUT sets the output voltage.
6
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DNC
AGND
AGND
AGND
RT/CLK
AGND
1
PWRGD
AGND
VADJ
RKG PACKAGE
(TOP VIEW)
36
35
34
33
32
31
30
2
29
STSEL
28
SS/TR
27
INH/UVLO
26
VIN
25
DNC
24
PH
23
PH
22
PH
21
PH
20
PGND
37
DNC
3
AGND
4
AGND
5
AGND
PH
PH
PH
6
PH
7
38
41
GND_PT
8
VOUT
GND_PT
9
PGND
VOUT
39
10
12
13
14
15
16
17
18
VOUT
VOUT
PGND
PGND
PGND
11
VOUT
VOUT
VOUT
40
19
PGND
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6 TYPICAL CHARACTERISTICS (VIN = 12 V)
(1) (2)
100
40
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
Output Voltage Ripple (mV)
95
Efficiency (%)
90
85
80
75
70
65
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
60
55
50
0
0.5
1
1.5
Output Current (A)
2
30
20
10
0
2.5
0
0.5
Figure 1. Efficiency vs. Output Current
2
2.5
G000
Figure 2. Voltage Ripple vs. Output Current
90
2.5
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
2
80
Ambient Temperature (°C)
Power Dissipation (W)
1
1.5
Output Current (A)
G000
1.5
1
70
60
50
40
30
All Output Voltages
20
0.5
0
0.5
1
1.5
Output Current (A)
Natural Convection
2
2.5
G000
Figure 4. Safe Operating Area
0
0
0.5
1
1.5
Output Current (A)
2
2.5
G000
40
120
30
90
30
90
20
60
20
60
10
30
10
30
0
0
0
0
−10
−30
−10
−30
−20
−60
−20
−60
−90
−30
−30
−40
1000
Gain
Phase
10000
Frequency (Hz)
100000
−120
300000
−40
1000
G000
Figure 5. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2=
56 µF electrolytic, fSW= 500 kHz
(1)
(2)
8
Gain
Phase
Phase (°)
120
Gain (dB)
40
Phase (°)
Gain (dB)
Figure 3. Power Dissipation vs. Output Current
−90
10000
Frequency (Hz)
100000
−120
300000
G000
Figure 6. VOUT= 3.3 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 400 kHz
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 4.
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7 TYPICAL CHARACTERISTICS (VIN = 24 V)
(1) (2) (3)
60
100
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
95
80
75
70
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
60
55
50
0
0.5
1
1.5
Output Current (A)
2
40
30
20
10
0
2.5
0
Figure 7. Efficiency vs. Output Current
1
1.5
Output Current (A)
Ambient Temperature (°C)
2
1.5
1
70
60
50
40
30
All Output Voltages
0
0.5
1
1.5
Output Current (A)
2
20
2.5
0
1
1.5
Output Current (A)
2
2.5
G000
Figure 10. Safe Operating Area
40
120
30
90
30
90
20
60
20
60
10
30
10
30
0
0
0
0
Gain (dB)
120
Phase (°)
Gain (dB)
Natural Convection
40
−10
−30
−10
−30
−20
−60
−20
−60
−90
−30
−30
−40
1000
Gain
Phase
10000
Frequency (Hz)
100000
−120
300000
−40
1000
G000
Figure 11. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 500 kHz
(3)
0.5
G000
Figure 9. Power Dissipation vs. Output Current
(2)
G000
80
0.5
(1)
2.5
90
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
2.5
0
2
Figure 8. Voltage Ripple vs. Output Current
3
Power Dissipation (W)
0.5
G000
Gain
Phase
Phase (°)
Efficiency (%)
85
65
50
Output Voltage Ripple (mV)
90
−90
10000
Frequency (Hz)
100000
−120
300000
G000
Figure 12. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 800 kHz
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 7, Figure 8, and Figure 9.
At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to
Figure 8.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 10.
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8 TYPICAL CHARACTERISTICS (VIN = 36 V)
(1) (2) (3)
60
100
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
95
80
75
70
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
60
55
50
0
0.5
1
1.5
Output Current (A)
2
40
30
20
10
0
2.5
Figure 13. Efficiency vs. Output Current
0.5
1
1.5
Output Current (A)
2
G000
90
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
VOUT = 2.5 V, fSW = 400 kHz
3
2.5
80
Ambient Temperature (°C)
3.5
2
1.5
1
70
60
50
40
0.5
30
0
20
VO = 5 V
VO = 12 V
VO = 15 V
Natural Convection
0
0.5
1
1.5
Output Current (A)
2
2.5
0
G000
120
30
90
30
90
20
60
20
60
10
30
10
30
0
0
0
0
Gain (dB)
40
Phase (°)
Gain (dB)
2.5
Figure 16. Safe Operating Area
−10
−30
−10
−30
−20
−60
−20
−60
−90
−30
Gain
Phase
10000
Frequency (Hz)
100000
−120
300000
−40
1000
G000
Figure 17. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 500 kHz
10
2
120
−40
1000
(3)
1
1.5
Output Current (A)
40
−30
(2)
0.5
G000
Figure 15. Power Dissipation vs. Output Current
(1)
2.5
Figure 14. Voltage Ripple vs. Output Current
4
Power Dissipation (W)
0
G000
Gain
Phase
Phase (°)
Efficiency (%)
85
65
50
Output Voltage Ripple (mV)
90
−90
10000
Frequency (Hz)
100000
−120
300000
G000
Figure 18. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 800 kHz
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 13, Figure 14, and Figure 15.
At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to
Figure 14.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 16.
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9 TYPICAL CHARACTERISTICS (VIN = 48 V)
(1) (2) (3)
70
100
95
Output Voltage Ripple (mV)
90
80
75
70
65
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
60
55
50
0
0.5
1
1.5
Output Current (A)
2
50
40
30
20
10
0
2.5
Figure 19. Efficiency vs. Output Current
0.5
1
1.5
Output Current (A)
2
G000
90
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
80
Ambient Temperature (°C)
5
4
3
2
1
70
60
50
40
VO = 5 V
VO = 12 V
VO = 15 V
30
Natural Convection
0
0
0.5
1
1.5
Output Current (A)
2
20
2.5
0
2.5
G000
Figure 22. Safe Operating Area
120
30
90
30
90
20
60
20
60
10
30
10
30
0
0
0
0
Gain (dB)
40
Phase (°)
Gain (dB)
2
120
−10
−30
−10
−30
−20
−60
−20
−60
−90
−30
−40
1000
Gain
Phase
10000
Frequency (Hz)
100000
−120
300000
−40
1000
G000
Figure 23. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 500 kHz
(3)
1
1.5
Output Current (A)
40
−30
(2)
0.5
G000
Figure 21. Power Dissipation vs. Output Current
(1)
2.5
Figure 20. Voltage Ripple vs. Output Current
6
Power Dissipation (W)
0
G000
Gain
Phase
Phase (°)
Efficiency (%)
85
VOUT = 15 V, fSW = 1 MHz
VOUT = 12 V, fSW = 800 kHz
VOUT = 5.0 V, fSW = 500 kHz
VOUT = 3.3 V, fSW = 400 kHz
60
−90
10000
Frequency (Hz)
100000
−120
300000
G000
Figure 24. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic,
COUT2= 56 µF electrolytic, fSW= 800 kHz
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 19, Figure 20, and Figure 21.
At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to
Figure 20.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 22.
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10 CAPACITOR RECOMMENDATIONS FOR THE TPS84250 POWER SUPPLY
10.1 Capacitor Technologies
10.1.1 Electrolytic, Polymer-Electrolytic Capacitors
When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature
is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide
adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures
are above 0°C.
10.1.2 Ceramic Capacitors
The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the
regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient
response of the output.
10.1.3 Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many
other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and
small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended
for power applications.
10.2 Input Capacitor
The TPS84250 requires a minimum input capacitance of 4.4 μF of ceramic type. The voltage rating of input
capacitors must be greater than the maximum input voltage. The ripple current rating of the capacitor must be at
least 450 mArms. Table 3 includes a preferred list of capacitors by vendor.
10.3 Output Capacitor
The output capacitance of the TPS84250 can be comprised of either all ceramic capacitors, or a combination of
ceramic and bulk capacitors. The required output capacitance must include at least 100 µF of ceramic type (or 2
x 47 µF). When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in
Table 3 are required. Additional capacitance above the minimum is determined by actual transient deviation
requirements. Table 3 includes a preferred list of capacitors by vendor.
Table 3. Recommended Input/Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE
(V)
CAPACITANCE
(µF)
ESR (2)
(mΩ)
Murata
X5R
GRM31CR61H225KA88L
50
4.7
2
TDK
X5R
C3216X5R1H475K
50
4.7
2
Murata
X5R
GRM32ER61E226K
16
22
2
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X5R
GRM32ER60J476M
6.3
47
2
Sanyo
POSCAP
16TQC68M
16
68
50
Sanyo
POSCAP
6TPE100MI
6.3
100
25
Kemet
T530
T530D227M006ATE006
6.3
220
6
(1)
(2)
12
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Maximum ESR @ 100 kHz, 25°C.
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11 APPLICATION INFORMATION
11.1 TPS84250 OPERATION
The TPS84250 can operate over a wide input voltage range of 7V to 50V and produce output voltages from 2.5V
to 15V. The performance of the device varies over this wide operating range, and there are some important
considerations when operated near the boundary limits. This section offers guidance in selecting the optimum
components depending on the application and operating conditions.
The user must select three primary parameters when designing with the TPS84250.
• Output Voltage
• UVLO Threshold
• Switching Frequency
The adjustment of each of these parameters can be made using just one or two resistors. Figure 25 below shows
a typical TPS84250 schematic with the key parameter-setting resistors labeled.
TPS84250
VIN
VIN
PWRGD
VOUT
CIN2
CIN1
RUVLO1
VOUT
INH/UVLO
COUT1
COUT2
RSET
RUVLO2
VADJ
COMP
RT/CLK
RRT
SS/TR
STSEL AGND PGND
Figure 25. TPS84250 Typical Schematic
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11.2 ADJUSTING THE OUTPUT VOLTAGE
The TPS84250 is designed to provide output voltages from 2.5V to 15V. The output voltage is determined by the
value of RSET, which must be connected between the VOUT node and the VADJ pin (Pin 36). For output voltages
greater than 5.0V, improved operating performance can be obtained by increasing the operating frequency. This
adjustment requires the addition of RRT between RT/CLK (Pin 31) and AGND (Pin 30). See the Switching
Frequency section for more details. Table 4 gives the standard external RSET resistor for a number of common
bus voltages and also includes the recommended RRT resistor for output voltages above 5.0V.
Table 4. Standard RSET Resistor Values for Common Output Voltages
OUTPUT VOLTAGE VOUT (V)
RESISTORS
2.5
3.3
5.0
8.0
12.0
15.0
RSET (kΩ)
21.5
31.6
52.3
90.9
140
178
RRT (kΩ)
open
open
1100
549
267
178
For other output voltages the value of RSET can be calculated using the following formula, or simply selected from
the range of values given in Table 5.
æV
ö
RSET = 10 ´ ç OUT - 1÷ (kW )
è 0.798
ø
(1)
Table 5. Standard RSET and RRT Resistor Values
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
2.5
21.5
open
400
9.0
102
365
700
3.0
27.4
open
400
9.5
110
365
700
3.3
31.6
open
400
10.0
115
365
700
3.5
34.0
open
400
10.5
121
267
800
4.0
40.2
open
400
11.0
127
267
800
4.5
46.4
open
400
11.5
133
267
800
5.0
52.3
1100
500
12.0
140
267
800
5.5
48.7
1100
500
12.5
147
215
900
6.0
64.9
1100
500
13.0
154
215
900
6.5
71.5
1100
500
13.5
158
215
900
7.0
78.7
549
600
14.0
165
178
1000
7.5
84.5
549
600
14.5
174
178
1000
8.0
90.9
549
600
15.0
178
178
1000
8.5
97.6
365
700
11.3 Input Voltage
The TPS84250 operates over the input voltage range of 7 V to 50 V. For reliable start-up and operation at light
loads, the minimum input voltage depends on the output voltage. For output voltages ≤ 12V, the minimum input
voltage is 7V or (VOUT + 3V), whichever is greater. For output voltages > 12V, the minimum input voltage is
(1.33 x VOUT).
The maximum input voltage is (15 x VOUT) or 50 V, whichever is less.
While the device can safely handle input surge voltages up to 65 V, sustained operation at input voltages above
50 V is not recommended.
See the Undervoltage Lockout (UVLO) Threshold section of this datasheet for more information.
14
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11.4 Undervoltage Lockout (UVLO) Threshold
At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power
conversion. During the power-down sequence, the VOFF UVLO threshold determines the input voltage where
power conversion ceases. The turn-on and turn-off thresholds are set by two resistors, RUVLO1 and RUVLO2 as
shown in Figure 26.
The VON UVLO threshold must be set to at least (VOUT + 3 V) or 7 V whichever is greater to insure proper startup and reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set
the UVLO threshold to appproximantely 80 to 85% of the minimum expected input voltage.
Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during
power-up when the input voltage is rising. VOFF is the voltage threshold during power-down when the input
voltage is decreasing. VOFF should be selected to be at least 500mV less than VON. Table 6 lists standard resistor
values for RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages.
RUVLO1 =
RUVLO2 =
(VON - VOFF )
2.9 ´ 10-3
(kW )
(2)
1.25
æ (VON - 1.25 ) ö
-3
çç
÷÷ + 0.9 ´ 10
R
UVLO1
è
ø
(kW )
(3)
VIN
VIN
RUVLO1
INH/UVLO
RUVLO2
AGND
Figure 26. Adjustable VIN UVLO
Table 6. Standard Resistor Values to set VON UVLO Threshold
VON THRESHOLD (V)
6.5
10.0
15.0
20.0
25.0
30.0
35.0
40.0
RUVLO1 (kΩ)
174
174
174
174
174
174
174
174
45.0
174
RUVLO2 (kΩ)
40.2
24.3
15.8
11.5
9.09
7.50
6.34
5.62
4.99
11.5 Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the output voltage is between 94% and 106% of the set voltage,
the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10
kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once VIN is
greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking
capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the output voltage is lower than
91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or
thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
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11.6 Switching Frequency
Nominal switching frequency of the TPS84250 is set from the factory at 400 kHz. This switching frequency is
optimum for output voltages below 5.0 V. For output voltages 5.0V and above, better operating performance can
be obtained raising the operating frequency. This is easily done by adding a resistor, RRT in , from the RT/CLK
pin (Pin 31) to the AGND pin (Pin 30). Raising the operating frequency reduces output voltage ripple, lowers the
load current threshold where pulse skipping begins, and improves transient response.
The recommended switching frequency for all output voltages is listed in Table 5.
For the maximum recommended output voltage value of 15 V, the switching frequency computes to 1000 kHz or
1 MHz. Operation above 1 MHz is not recommended. Use Table 7 below to select the value of the timing resistor
for the given values of switching frequencies.
Table 7. Standard Resistor Values to set the Switching Frequency
fSW (kHz)
400
500
600
700
800
900
1000
RRT(kΩ)
OPEN
1100
549
365
267
215
178
It is also possible to synchronize the switching frequency to an external clock signal. See the Synchronization
(CLK) section for further details.
While it is possible to set the operating frequency higher than 400 kHz when using the device at output voltages
of 5 V or less, minimum duty cycle and pulse skipping issues restrict the maximum recommended input voltage
under these conditions. The recommended operating conditions for the TPS84250 can be summarized by
Figure 27. The graph shows the maximum input voltage vs. output voltage restriction for several operating
frequencies. The lower boundary of the graph shows the minimum input voltage as a function of the output
voltage.
Figure 27. Optimum Operating Range with Switching Frequency
16
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11.7 Application Schematics
VIN
7-36 V
TPS84250
VIN
4.7 F
50 V
PWRGD
174kΩ
VOUT
3.3V @ 2.5A
VOUT
INH/UVLO
31.6kΩ
40.2kΩ
47 F
6.3 V
47 F
6.3 V
VADJ
RT/CLK
SS/TR
STSEL AGND PGND
Figure 28. Typical Schematic
VIN = 7 V to 36 V, VOUT = 3.3 V
VIN
15-50 V
TPS84250
VIN
2.2 F
100 V
2.2 F
100 V
PWRGD
VOUT
12 V @ 2.5 A
VOUT
174kΩ
INH/UVLO
140kΩ
15.4kΩ
47 F
16 V
47 F
16 V
VADJ
RT/CLK
SS/TR
22 nF
267kΩ
STSEL AGND PGND
Figure 29. Typical Schematic
VIN = 15 V to 50 V, VOUT = 12 V
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Application Schematics (continued)
VIN
8-50 V
TPS84250
VIN
2.2 F
100 V
2.2 F
100 V
174kΩ
PWRGD
VOUT
5 V @ 2.5 A
VOUT
INH/UVLO
52.3kΩ
31.6kΩ
47 F
6.3 V
47 F
6.3 V
VADJ
RT/CLK
SS/TR
1100kΩ
STSEL AGND PGND
Figure 30. Typical Schematic
VIN = 8 V to 50 V, VOUT = 5 V
11.8 Power-Up Characteristics
When configured as shown in the front page schematic, the TPS84250 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is
recognized. Figure 31 shows the start-up waveforms for a TPS84250, operating from a 24-V input and the output
voltage adjusted to 5 V. The waveform were measured with a 2-A constant current load.
Figure 31. Start-Up Sequence
18
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11.9 Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin.
Figure 32 shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to
VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown
in Figure 33. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 34. A
regulated output voltage is produced within 5 ms. The waveforms were measured with a 2-A constant current
load.
VIN
VIN
RUVLO1
INH/UVLO
Q1
INH
Control
RUVLO2
AGND
Figure 32. Typical Inhibit Control
Figure 34. Inhibit Turn-On
Figure 33. Inhibit Turn-Off
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11.10 Slow Start (SS/TR)
For outputs voltages of 5V or less, the slow start capacitance built into the TPS84250 is sufficient to provide for a
turn-on ramp rate that does not induce large surge currents while charging the output capacitors. Connecting the
STSEL pin (Pin 29) to AGND while leaving SS pin (Pin 28) open enables the internal SS capacitor with a slow
start interval of approximately 5 ms. For output voltages greater than 5V, additional slow start capacitance is
recommended. For 12V to 15V output voltages, a 22nF capacitor should be connected between the SS/TR pin
(Pin 28) and AGND, while connecting the STSEL pin (Pin 29) to AGND as well. Figure 35 shows an additional
SS capacitor connected to the SS pin and the STSEL pin connected to AGND. See Table 8 below for SS
capacitor values and timing interval.
SS/TR
CSS
(Optional)
AGND
STSEL
Figure 35. Slow Start Capacitor (CSS) and STSEL Connection
Table 8. Slow Start Capacitor Values and Slow Start Time
20
CSS (nF)
open
4.7
10
15
22
SS Time (msec)
5
7
10
13
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11.11 Overcurrent Protection
For protection against load faults, the TPS84250 incorporates cycle-by-cycle current limiting. During an
overcurrent condition the output current is limited and the output voltage is reduced, as shown in Figure 36. As
the output voltage drops more than 8% below the set point, the PWRGD signal is pulled low. If the output voltage
drops more than 25%, the switching frequency is reduced to reduce power dissipation within the device. When
the overcurrent condition is removed, the output voltage returns to the established voltage.
The TPS84250 is not designed to endure a sustained short circuit condition. The use of an output fuse, voltage
supervisor circuit, or other overcurrent protection circuit is recommended. A recommended overcurrent protection
circuit is shown in Figure 37. This circuit uses the PWRGD signal as an indication of an overcurrent condition. As
PWRGD remains low, the 555 timer operates as a low frequency oscillator, driving the INH/UVLO pin low for
approximately 400ms, halting the power conversion of the device. After the inhibit interval, the INH/UVLO pin is
released and the TPS84250 restarts. If the overcurrent condition is removed, the PWRGD signal goes high,
resetting the oscillator and power conversion resumes, otherwise the inhibit cycle repeats.
3.3V/5V
475kΩ
VDD
DIS
CONT
47.5kΩ
To INH/UVLO
Pin 27
TLC555
THRS
BSS138
TRIG
OUT
3.3V/5V
1 F
100kΩ
100kΩ
RST
GND
From PWRGD
Pin 35
BSS138
Figure 37. Over-Current Protection Circuit
Figure 36. Overcurrent Limiting
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11.12 Light-Load Behavior
The TPS84250 is a non-synchronous converter. One of the characteristics of a non-synchronous converter is
that as the load current on the output is decreased, a point is reached where the energy delivered by a single
switching pulse is more than the load can absorb. This causes the output voltage to rise slightly. This rise in
output voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles
until the output voltages falls back to the set point. At very light loads or no load, many switching cycles are
skipped. The observed effect during this pulse skipping mode of operation is an increase in the peak to peak
ripple voltage, and a decrease in the ripple frequency. The load current where pulse skipping begins is a function
of the input voltage, the output voltage, and the switching frequency. A plot of the pulse skipping threshold
current as a function of input voltage is given in Figure 38 for a number of popular output voltage and switching
frequency combinations.
900
2.5 V, 400 kHz
3.3 V, 400 kHz
5.0 V, 400 kHz
9 V, 600 kHz
12 V, 800 kHz
15 V, 1 MHz
Output Current (mA)
800
700
600
500
400
300
200
100
0
10
15
20
25
30
35
Input Voltage (V)
40
45
50
G000
Figure 38. Pulse Skipping Threshold
11.13 Synchronization (CLK)
An internal phase locked loop (PLL) allows synchronization between 400 kHz and 1 MHz, and to easily switch
from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to
the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8
V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In
applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 39.
Before the external clock is present, the device works in RT mode where the switching frequency is set by the
RRT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK
pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100
kHz first before returning to the switching frequency set by the RRT resistor .
470 pF
1 kΩ
RT/CLK
External Clock
300 kHz to 1 MHz
RRT
AGND
Figure 39. CLK/RT Configuration
22
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11.14 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
180°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C
typically.
11.15 Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 40 and
Figure 41 show two layers of a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place a dedicated AGND copper area beneath the TPS84250.
• Isolate the PH copper area from the VOUT copper area using the PGND copper area.
• Connect the AGND and PGND copper area at one point; at pins 8 & 9.
• Place RSET, RRT, and CSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
• Use a dedicated sense line to connect RSET to VOUT near the load for best regulation.
PGND
VIN
LOAD
VOUT sense
Via
VOUT
PGND
Plane
COUT2
CIN1
Thermal
Vias
COUT1
PH
RSET
VOUT sense
Via
AGND to PGND
Connection
AGND
Figure 40. Typical Top-Layer Recommended Layout
Figure 41. Typical PGND-Layer Recommended Layout
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Product Folder Links: TPS84250
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TPS84250
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
www.ti.com
11.16 EMI
The TPS84250 is compliant with EN55022 Class B radiated emissions. Figure 42 and Figure 43 show typical
examples of radiated emissions plots for the TPS84250 operating from 24 V and 12 V respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 42. Radiated Emissions 24-V Input, 5-V Output, 2-A
Load (EN55022 Class B)
24
Figure 43. Radiated Emissions 12-V Input, 5-V Output, 2-A
Load (EN55022 Class B)
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Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: TPS84250
TPS84250
www.ti.com
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2017) to Revision C
Page
•
Added top navigator icon for TI reference design ................................................................................................................. 1
•
Increased the peak reflow temperature and maximum number of reflows to JEDEC specification for improved
manufacturability. ................................................................................................................................................................... 2
Changes from Revision A (June 2013) to Revision B
Page
•
Added peak reflow and maximum number of reflows information ........................................................................................ 2
•
Added Mechanical, Packaging, and Orderable Information section..................................................................................... 26
Changes from Original (August 2012) to Revision A
•
Page
Changed describing pins 8 & 9 not connected together internally. ........................................................................................ 6
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Product Folder Links: TPS84250
25
TPS84250
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
www.ti.com
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: TPS84250
TPS84250
www.ti.com
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
14.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS84250RKGR
B1QFN
RKG
41
500
330.0
24.4
9.35
11.35
3.1
16.0
24.0
Q1
TPS84250RKGT
B1QFN
RKG
41
250
330.0
24.4
9.35
11.35
3.1
16.0
24.0
Q1
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TPS84250
SLVSAR6C – AUGUST 2012 – REVISED APRIL 2018
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
28
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS84250RKGR
B1QFN
RKG
41
500
383.0
353.0
58.0
TPS84250RKGT
B1QFN
RKG
41
250
383.0
353.0
58.0
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: TPS84250
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS84250RKGR
ACTIVE
B1QFN
RKG
41
500
RoHS Exempt
& Green
CU NIPDAU
Level-3-250C-168 HR
-40 to 85
(54260, TPS84250)
TPS84250RKGT
ACTIVE
B1QFN
RKG
41
250
RoHS Exempt
& Green
CU NIPDAU
Level-3-250C-168 HR
-40 to 85
(54260, TPS84250)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS84250RKGR
B1QFN
RKG
41
500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPS84250RKGT
B1QFN
RKG
41
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS84250RKGR
B1QFN
RKG
41
500
346.0
346.0
35.0
TPS84250RKGT
B1QFN
RKG
41
250
203.0
203.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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