Texas Instruments | TPS54418 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter (Rev. E) | Datasheet | Texas Instruments TPS54418 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter (Rev. E) Datasheet

Texas Instruments TPS54418 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter (Rev. E) Datasheet
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TPS54418
SLVS946E – SEPTEMBER 2009 – REVISED APRIL 2018
TPS54418 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down
SWIFT™ Converter
1 Features
3 Description
•
TheTPS54418 device is a full-featured, 6-V, 4-A,
synchronous, step-down current-mode converter with
two integrated MOSFETs.
1
•
•
•
•
•
•
•
•
•
•
•
Two, 30-mΩ (typical) MOSFETs for HighEfficiency at 4-A loads
Switching Frequency: 200 kHz to 2 MHz
Voltage Reference Over Temperature: 0.8 V ± 1%
Synchronizes to External Clock
Adjustable Soft Start/Sequencing
UV and OV Power-Good Output
Low Operating and Shutdown Quiescent Current
Safe Start-Up into Prebiased Output
Cycle-by-Cycle Current Limit, Thermal and
Frequency Foldback Protection
Operating Junction Temperature Range: –40°C to
150°C
Thermally Enhanced 3 mm × 3 mm 16-pin WQFN
Package
Create a Custom Design Using the TPS54418
With the WEBENCH® Power Designer
2 Applications
•
•
•
Low-Voltage, High-Density Power Systems
Point-of-Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
The TPS54418 device enables small designs by
integrating the MOSFETs, implementing current
mode control to reduce external component count,
reducing inductor size by enabling up to 2-MHz
switching frequency, and minimizing the device
footprint with a small, 3 mm x 3 mm, thermally
enhanced, QFN package.
The TPS54418 device provides accurate regulation
for a variety of loads with an accurate ±1% voltage
reference (VREF) over temperature.
Efficiency is maximized through the integrated 30-mΩ
MOSFETs and a 350-μA typical supply current. Using
the EN pin, shutdown supply current is reduced to 2
μA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the soft-start pin.
An open-drain power-good signal indicates the output
is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protects
the device during an overcurrent condition.
For more SWIFT™ documentation, see the TI
website at www.ti.com/swift.
Device Information(1)
PART NUMBER
TPS54418
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VIN
Efficiency vs Output Current
TPS54418
100
BOOT
EN
PH
PWRGD
SS
RT/CLK
COMP
VSENSE
PowerPad
95
90
VOUT
85
Efficiency (%)
VIN
80
75
70
65
GND
AGND
60
VIN = 5 V
55
VOUT = 1.8 V
fSW = 500 kHz
50
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54418
SLVS946E – SEPTEMBER 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2014) to Revision E
•
update title ............................................................................................................................................................................. 1
Changes from Revision C (July 2013) to Revision D
•
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision B (August 2012) to Revision C
Page
•
Added Figure 22 to Typical Characteristics section ............................................................................................................... 9
•
Added clarity to Fixed Frequency PWM Control section ...................................................................................................... 12
•
Added clarity to Soft-Start Pin section.................................................................................................................................. 14
•
Added clarity to Synchronize Using the RT/CLK Pin section ............................................................................................... 16
•
Added Step Five: Minimum Load DC COMP Voltage section ............................................................................................. 23
•
Added clarity to the Step Six: Choose the Soft-Start Capacitor section .............................................................................. 23
2
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SLVS946E – SEPTEMBER 2009 – REVISED APRIL 2018
5 Pin Configuration and Functions
VIN
EN
PWRGD
BOOT
RTE Package
16 Pin WQFN
(TOP VIEW)
16
15
14
13
VIN 1
12 PH
VIN 2
11 PH
Thermal
Pad
GND 3
10 PH
GND 4
5
6
7
8
AGND
VSENSE
COMP
RT/CLK
9
SS
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AGND
5
G
Analog ground should be electrically connected to GND close to the device.
BOOT
13
I
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP
7
O
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
EN
15
I
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to
set the on/off threshold (adjust UVLO) with two additional resistors.
G
Power ground. This pin should be electrically connected directly to the power pad under the device.
O
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
GND
3
4
10
PH
11
12
PWRGD
14
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
over/under-voltage or EN shut down.
RT/CLK
8
I/O
Resistor Timing or External Clock input pin.
SS
9
I/O
Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft
1
VIN
2
I
Input supply voltage, 2.95 V to 6 V.
I
Inverting node of the transconductance (gm) error amplifier.
G
GND pin should be connected to the exposed power pad for proper operation. This power pad should
be connected to any internal PCB ground plane using multiple vias for good thermal performance.
16
VSENSE
Thermal Pad
(1)
6
I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
EN, PWRGD, VIN
–0.3
7
RT/CLK
–0.3
6
COMP, SS, VSENSE
–0.3
3
BOOT
8
PH
PH (10 ns transient)
Source current
Sink current
V
VPH+ 8 V
BOOT-PH
Output voltage
UNIT
–0.6
7
–2
7
V
EN, RT/CLK
100
COMP, SS
100
µA
µA
PWRGD
10
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
VALUE
UNIT
±2000
V
±500
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VVIN
Input voltage
TJ
Operating junction temperature
MAX
UNIT
3
6
V
–40
150
°C
6.4 Thermal Information (1)
TPS54418
THERMAL METRIC (2)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
59.1
RθJB
Junction-to-board thermal resistance
23.1
ψJT
Junction-to-top characterization parameter
1.4
ψJB
Junction-to-board characterization parameter
23.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.9
(1)
(2)
(3)
4
50
(3)
37
°C/W
Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Test Board Conditions:
(a) 2 inches × 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes located on the two internal layers and bottom layer
(d) 4 thermal vias (10 mil) located under the device package
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SLVS946E – SEPTEMBER 2009 – REVISED APRIL 2018
6.5 Electrical Characteristics
–40°C ≤ TJ ≤ 150°C, 2.95 ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN)
VVIN
Operating input voltage
VUVLO
Internal under voltage lockout
threshold
No voltage hysteresis, rising and falling
IQ(vin)
Shutdown supply current
VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V
Quiescent current
VVSENSE = 0.9 V, VVIN = 5 V, 25°C,
RT = 400 kΩ
Iq
2.95
6
V
2.6
2.8
V
2
5
μA
350
500
μA
1.25
1.37
ENABLE AND UVLO (EN)
VTH(en)
Enable threshold
IEN
Input current
Rising
1.16
Falling
1.18
Enable rising threshold + 50 mV
–3.2
Enable falling threshold – 50 mV
–0.65
V
μA
VOLTAGE REFERENCE (VSENSE)
VREF
Voltage reference
2.95 V ≤ VVIN ≤ 6 V, –40°C <TJ < 150°C
0.795
0.803
0.811
(VBOOT – VPH) = 5 V
30
60
(VBOOT – VPH) = 2.95 V
44
70
VVIN = 5 V
30
60
VVIN = 2.95 V
44
70
V
MOSFET
RDS(HFET)
High-side switch resistance
RDS(LFET)
Low-side switch resistance
mΩ
mΩ
ERROR AMPLIFIER
IIN
Input current
7
nA
gM(ea)
Error amplifier transconductance –2 μA < ICOMP < 2 μA, VCOMP = 1 V
225
μS
gm(EA,ss)
Error amplifier transconductance –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
during soft-start
VVSENSE = 0.4 V
70
μS
ICOMP
Error amplifier source/sink
±20
μA
gM
COMP to ISWITCH
transconductance
13
A/V
6.4
A
175
°C
15
°C
VCOMP = 1 V, 100 mV overdrive
CURRENT LIMIT
ILIM
Current limit threshold
Instantaneous peak current
5.0
THERMAL SHUTDOWN
TSD
Thermal Shutdown
TSD(hyst)
Hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)
fSW
Switching frequency range using
RT mode
fSW
Switching frequency
fSW
Switching frequency range using
CLK mode
tMIN(CLK)
Minimum CLK pulse width
VRT/CLK
RT/CLK voltage
VIH(CLK)
RT/CLK high threshold
VIL(CLK)
RT/CLK low threshold
0.6
V
tDLY
RT/CLK falling edge to PH rising
fSW = 500 kHz with RRT resistor in series
edge delay
90
ns
tLOCK(PLL)
PLL lock-in time
14
μs
200
RRT = 400 kΩ
400
500
300
2000
kHz
600
kHz
2000
kHz
75
RRT/CLK = 400 kΩ
ns
0.5
1.6
0.4
fSW = 500 kHz
V
2.2
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 150°C, 2.95 ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-SIDE POWER MOSFET (PH)
Measured at 50% points on PH, IOUT = 4
60
tON(min)
Minimum on time
tOFF(min)
Minimum off time
Prior to skipping off pulses,
(VBOOT – VPH) = 2.95 V, IOUT = 4
60
ns
tRISE
Rise time
VVIN = 5 V
1.5
V/ns
tFALL
Fall time
VVIN = 5 V
1.5
V/ns
Measured at 50% points on PH, VVIN = 5 V,
IOUT = 0 A
ns
110
BOOT (BOOT)
RBOOT
BOOT charge resistance
VVIN = 5 V
16
Ω
VUVLO(Boot)
BOOT-PH UVLO
VVIN = 2.95 V
2.1
V
SOFT-START (SS )
ICHG
Charge current
VSS = 0.4 V
1.8
μA
VSSxREF
SS to reference crossover
98% nominal
0.9
V
VDSCHG(SS)
SS discharge voltage (overload) VVSENSE = 0 V
20
μA
IDSCHG(SS)
SS discharge current (UVLO,
EN, thermal fault)
VVIN = 5 V, VSS = 0.5 V
1.25
mA
VVSENSE falling (fault)
91%
POWER GOOD (PWRGD)
VVSENSE rising (good)
93%
VVSENSE rising (fault)
107%
VVSENSE falling (Good)
105%
VTH(PG)
VSENSE threshold
VHYST(PG)
Hysteresis
VVSENSE falling
IPH(lkg)
Output high leakage
VVSENSE = VREF, VPWRGD = 5.5 V
RPG
Power Good on-resistance
VOL
Low-level output voltage
IPWRGD = 3.5 mA
VMIN(PG)
Minimum input voltage for valid
output
VPWRGD < 0.5 V , IOUT = 100 μA
1.2
6
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VREF
2%
2
nA
100
Ω
0.3
V
1.6
V
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SLVS946E – SEPTEMBER 2009 – REVISED APRIL 2018
550
0.055
High Side Rdson
VI = 3.3 V
Low Side Rdson
VI = 3.3 V
0.05
0.045
540
fs - Switching Frequency - kHz
RDSON - Static Drain-Source On-State Resistance - W
6.6 Typical Characteristics
High Side Rdson
VI = 5 V
0.04
0.035
Low Side Rdson
VI = 5 V
0.03
RT = 400 kW,
VI = 3.3 V
530
520
510
500
490
480
470
0.025
460
0.02
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
450
-50
150
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Frequency vs Junction Temperature
Figure 1. High-Side and Low-Side On-Resistance vs
Junction Temperature
7
6.9
-25
0.808
VIN = 3 .3 V
VIN = 3 V
0.806
Vref - Voltage Reference - V
High Side Switch Current - A
6.8
6.7
6.6
6.5
6.4
6.3
0.802
0.8
0.798
0.796
6.2
0.794
6.1
6
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0.792
-50
150
Figure 3. High-Side Current Limit vs Junction Temperature
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
2000
1900
fs - Switching Frequency - KHz
900
800
700
600
500
400
300
200
100
-25
Figure 4. Voltage Reference vs Junction Temperature
1000
fs - Switching Frequncy - KHz
0.804
1800
1700
1600
1500
1400
1300
1200
1100
200
300
400
500
600
700
RT - Resistance - kW
800
900
1000
Figure 5. Switching Frequency vs RT Resistance Low
Frequency Range
1000
80
100
120
140
160
RT - Resistance kW
180
200
Figure 6. Switching Frequency vs RT Resistance High
Frequency Range
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Typical Characteristics (continued)
100
280
VIN = 3 .3 V
260
EA - Transconductance - mA/V
Normal Switching Frequency - %
Vsense Falling
75
Vsense Rising
50
25
240
220
200
180
160
0
0
0.1
0.2
0.3
0.4
0.5
Vsense - V
0.6
0.7
140
-50
0.8
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 8. Transconductance vs Junction Temperature
Figure 7. Switching Frequency vs Vsense
1.3
90
VIN = 3 .3 V
85
1.29
1.28
75
EN - Threshold - V
EA - Transconductance - mA/V
1.26
70
65
60
55
1.24
1.23
1.22
1.21
1.2
VIN = 3.3 V, falling
1.18
50
1.17
40
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
1.16
1.15
-50
150
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 10. Enable Pin Voltage vs Junction Temperature
Figure 9. Transconductance (Soft-Start) vs Junction
Temperature
-0.25
-2.75
VIN = 5 V,
Ien = Threshold +50 mV
-2.85
-2.95
-0.45
-3.05
-0.55
-3.15
-3.25
-3.35
-3.45
-0.65
-0.75
-0.85
-0.95
-3.55
-1.05
-3.65
-1.15
-3.75
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
VIN = 5 V,
Ien = Threshold -50 mV
-0.35
EN - Pin Current - mA
EN - Pin Current - mA
1.25
1.19
45
125
150
Figure 11. Pin Current vs Junction Temperature
8
VIN = 3.3 V, rising
1.27
80
-1.25
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12. Pin Current vs Junction Temperature
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Typical Characteristics (continued)
-1
105
-1.2
103
SS/TR - Discharge Current - mA
SS/TR - Charge Current - mA
-1.4
VIN = 5 V
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
101
VIN = 5 V
99
97
95
93
91
89
87
-3
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
85
-50
150
Figure 13. Charge Current vs Junction Temperature
-25
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 14. Discharge Current vs Junction Temperature
3
3
VIN = 3.3 V
2.9
2.5
2.7
Shutdown Supply Current - mA
2.8
VIN - Input Voltage - V
0
UVLO Start Switching
2.6
2.5
UVLO Stop Switching
2.4
2.3
2.2
2
1.5
1
0.5
2.1
2
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0
-50
150
Figure 15. Input Voltage vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 16. Shutdown Supply Current vs Junction
Temperature
3
400
TJ = 25°C
390
VIN = 3.3 V
380
ICC - Supply Current - mA
Shutdown Supply Current mA
2.5
2
1.5
1
370
360
350
340
330
320
0.5
310
0
3
3.5
4
4.5
5
VIN - Input Voltage - V
5.5
6
Figure 17. Shutdown Supply Current vs Input Voltage
300
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 18. Supply Current vs Junction Temperature
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Typical Characteristics (continued)
110
400
390
108
380
106
PWRGD - Threshold - % Vref
ICC - Supply Current - mA
TJ = 25°C
370
360
350
340
330
320
102
100
98
96
94
310
90
300
88
-50
3.5
4
4.5
5
VIN - Input Voltage - V
5.5
6
Figure 19. Supply Current vs Input Voltage
Vsense Rising
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
1
200
180
Vsense Falling
Figure 20. PWRGD Threshold vs Junction Temperature
±3 Sigma
0.9
VIN = 3.3 V
Typical
0.8
160
COMP Voltage (V)
RDSON - Static Drain-Sourec On State Resistance - W
Vsense Falling
104
92
3
140
120
100
80
60
+3 Sigma
0.7
0.6
0.5
0.4
0.3
0.2
40
0.1
20
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 21. PWRGD On Resistance vs Junction Temperature
10
Vsense Rising, VIN = 3.3 V
0
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Figure 22. Comp Voltage Clamp vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS54418 device is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients the device implements a constant frequency,
peak current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide supported switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size
optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to
ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to
synchronize the power switch turn on to a falling edge of an external system clock.
The TPS54418 device has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In
addition, the pull up current provides a default condition when the EN pin is floating for the device to operate.
The total operating current for the TPS54418 device is 350 μA when not switching and under no load. When the
device is disabled, the supply current is less than 5 μA.
The integrated, 30-mΩ MOSFETs allow for high-efficiency power supply designs with continuous output currents
up to 4 amperes.
The TPS54418 device reduces the external component count by integrating the boot recharge diode. The bias
voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54418 device to operate approaching 100%. The
output voltage can be stepped down to as low as the 0.8 V reference.
The TPS54418 device has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54418 device minimizes excessive output overvoltage transients by taking advantage of the overvoltage
power good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the
overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until
the output voltage is lower than 105%.
The SS (soft-start) pin is used to minimize inrush currents or provide power supply sequencing during power up.
A small value capacitor should be coupled to the pin for soft-start. The SS pin is discharged before the output
power up to ensure a repeatable re-start after an over-temperature fault, UVLO fault or disabled condition.
The use of a frequency-foldback circuit reduces the switching frequency during startup and over current fault
conditions to help limit the inductor current.
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7.2 Functional Block Diagram
PWRGD EN
VIN
i1
93%
iHYS
Logic
Thermal
Shutdown
Enable
Comparator
107%
Shutdown
Logic
Voltage
Reference
VSENSE
UVLO
Enable
Threshold
Boot
Charge
Boot
UVLO
+
+
BOOT
SS
Shutdown
Minimum
COMP Clamp
Logic
PWM
Comparator
COMP
Logic and
PWM Latch
PH
Slope
Compensation
Frequency
Shift
Overload
Recovery
Maximum
Clamp
GND
OSC with
PLL
AGND
PowerPad
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54418 device uses an adjustable fixed-frequency peak-current-mode control. The output voltage is
compared through external resistors on the VSENSE to pin an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error
amplifier output is compared to the high-side power-switch current. When the power switch reaches the COMP
voltage, the high-side power switch is turned off and the low-side power switch is turned on.
The COMP pin voltage increases and decreases as the peak switch current increases and decreases. The
device implements a current-limit function by clamping the COMP pin voltage to a maximum value, which limits
the maximum peak current the device supplies. The device also implements a minimum COMP pin voltage
clamp for improved transient response. When the COMP pin voltage is pushed low to the minimum clamp, such
as during a load release event, turn-on of the high-side power switch is inhibited.
7.3.2 Slope Compensation and Output Current
The TPS54418 device adds a compensating ramp to the switch current signal. This slope compensation
prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant
over the full duty cycle range.
7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
The TPS54418 device has an integrated boot regulator and requires a small ceramic capacitor between the
BOOT and PH pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic
capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V
or higher is recommended because of the stable characteristics overtemperature and voltage.
12
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Feature Description (continued)
To improve drop out, the TPS54418 device is designed to operate at 100% duty cycle as long as the BOOT to
PH pin voltage is greater than 2.5 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the
low-side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Because the supply current
sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high.
7.3.4 Error Amplifier
The TPS54418 device has a transconductance amplifier. The error amplifier compares the VSENSE voltage to
the lower of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error
amplifier is 225 μA/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is
regulating using the SS voltage, the transconductance is 70 μA/V. The frequency compensation components are
placed between the COMP pin and ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output
of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting
input of the error amplifier.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a value of 100 kΩ for the R1 resistor and use
Equation 1 to calculate R2. To improve efficiency at very light loads, consider using larger resistor values. If the
values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current
are noticeable.
æ
ö
0.8 V
R2 = R1 ´ ç
÷
è VO - 0.8 V ø
(1)
VOUT
R1
VSENSE
+
R2
0.8 V
Figure 23. Voltage Divider Circuit
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54418 device is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher
under-voltage lockout (UVLO), use the EN pin as shown in Figure 24 to adjust the input voltage UVLO by using
two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (VSTOP)
above 2.7 V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input
supply variations. The EN pin has an internal pull-up current source that provides the default condition of the
TPS54418 device operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.55
μA of hysteresis is added. When the EN pin is pulled below 1.18 V, the 2.55 μA is removed. This additional
current facilitates input voltage hysteresis.
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Feature Description (continued)
VIN
I1
0.6 µA
IHYS
2.55 µA
R1
EN
+
R2
Figure 24. Adjustable Undervoltage Lockout
R1 =
0.944 × VSTART - VSTOP
2.59 ´ 10-6
(2)
1.18 × R1
R2 =
VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6
(3)
7.3.8 Soft-Start Pin
The TPS54418 device regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the
SS pin to ground implements a soft-start time. The TPS54418 device has an internal pull-up current source of
1.8 μA which charges the external soft-start capacitor. Equation 4 calculates the required soft-start capacitor
value where tSS is the desired soft-start time in ms, ISS is the internal soft-start charging current of 1.8 μA, and
VREF is the internal voltage reference of 0.8 V. it is recommended to maintain the soft-start time in the range
between 1 ms and 10 ms.
I ´t
CSS = SS SS
VREF
where
•
•
•
•
CSS is in nF
tSS is in ms
ISS is in µA
VREF is in V
(4)
If during normal operation, the input voltage goes below the UVLO, EN pin pulled below 1.2 V, or a thermal
shutdown event occurs, the TPS54418 device stops switching and the SS is discharged to 0 volts before
reinitiating a powering up sequence.
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD
pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin
of another device. Figure 25 shows the sequential method. The power good is coupled to the EN pin on
theTPS54418 device which enables the second power supply once the primary supply reaches regulation.
Ratiometric start up can be accomplished by connecting the SS pins together. The regulator outputs ramp up
and reach regulation at the same time. When calculating the soft-start time the pull up current source must be
doubled in Equation 4. The ratiometric method is shown in Figure 27.
14
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Feature Description (continued)
TPS54218
TPS54218
EN1 = 2 V / div
PWRGD
EN
EN
SS
PWRGD
PWRGD1 = 2 V / div
SS/TR
CSS
CSS
Vout1 = 1 / div
Vout2 = 1 V / div
Time = 5 msec / div
Figure 25. Sequencial Start-Up Schematic
Figure 26. Sequential Startup using EN and
PWRGD
EN1 = 2 V / div
TPS54418
EN
TPS54418
EN
SS
SS
PWRGD
PWRGD
Vout1 = 1 V / div
CSS
Vout2 = 1 V / div
Time = 5 msec / div
Figure 27. Ratiometric Start-Up Schematic
Figure 28. Ratiometric Start-Up Using Coupled SS
Pins
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54418 device is adjustable over a wide range from 200 kHz to 2000 kHz by
placing a maximum of 1000 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier
holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The
RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in
Figure 5 or Figure 6 or Equation 5.
311890
RRT =
(fSW )1.0793
where
•
•
fSW =
RRT is in kΩ
fSW is in kHz
(5)
133870
(RRT )0.9393
where
•
•
RRT is in kΩ
fSW is in kHz
(6)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered.
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Feature Description (continued)
The minimum controllable on time is typically 60 ns at full current load and 110 ns at no load, and limits the
maximum operating input voltage or output voltage.
7.3.11 Overcurrent Protection
The TPS54418 device implements a cycle-by-cycle current limit. During each switching cycle the high-side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
7.3.12 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54418
device implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the
low-side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%,
then 75%, then 50%, then 25% as the voltage decreases from 0.8 to 0 volts on VSENSE pin to allow the lowside MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching
frequency increases as the voltage on VSENSE increases from 0 to 0.8 volts. See Figure 7 for details.
7.3.13 Reverse Overcurrent Protection
The TPS54418 device implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is more than 1.3 A. By implementing this additional protection scheme, the
converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
7.3.14 Synchronize Using the RT/CLK Pin
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement
the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least
75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set
by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The recommended synchronization frequency range is 300 kHz to 2000 kHz. If the external system
clock is to be removed, TI recommends that it be removed on the falling edge of the clock.
.
.
SYNC Clock = 2 V / div
RT/CLK
PLL
RRT
PH = 2 V / div
Time = 500 nsec / div
Figure 29. Synchronizing to a System Clock
16
Figure 30. Plot of Synchronizing to System Clock
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Feature Description (continued)
7.3.15 Power Good (PWRGD Pin)
The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is
recommended to use a pull-up resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or
less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.
7.3.16 Overvoltage Transient Protection
The TPS54418 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which
is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the
high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.
When the VSENSE voltage drops lower than the OVTP threshold the high-side MOSFET is allowed to turn on
the next clock cycle.
7.3.17 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 160°C, the device reinitiates the power up sequence
by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C.
7.4 Device Functional Modes
7.4.1 Small Signal Model for Loop Response
Figure 31 shows an equivalent model for the TPS54418 device control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gM of 225 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor ROUT(ea) and capacitor COUT(ea) model the open loop gain and frequency
response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control
loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency
compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can
be checked by replacing the RLOAD with a current source with the appropriate load step amplitude and step rate
in a time domain analysis.
PH
Power Stage
13 A/V
VOUT
a
RESR
b
R1
VSENSE
COMP
RLOAD
COUT
c
+
C2
R3
COUT(ea)
ROUT(ea)
0.8 V
gM
225 µA/V
R2
C1
Figure 31. Small Signal Model for Loop Response
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Device Functional Modes (continued)
7.4.2 Simple Small Signal Model for Peak Current Mode Control
Figure 32 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54418 device power stage can be approximated to a voltage controlled current source
(duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 7 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage
transconductance. The gM for the TPS54418 device is 13 A/V. The low frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 8. As
the load current increases and decreases, the low frequency gain decreases and increases, respectively. This
variation with load may seem problematic at first glance, but the dominant pole moves with load current [see
Equation 9]. The combined effect is highlighted by the dashed line in the right half of Figure 33. As the load
current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the
same for the varying load conditions which makes it easier to design the frequency compensation.
VC
RESR
RLOAD
Adc
COUT
Gain
gM(PS)
fZ
fP
Frequency
Figure 32. Simple Small Signal Model
VOUT
VC
æ s
1+ ç
è 2p ´ fZ
= Adc ´
æ s
1+ ç
è 2p ´ fP
Figure 33. Frequency Response
ö
÷
ø
ö
÷
ø
(7)
Adc = gM(PS ) ´ RLOAD
(8)
1
fP =
COUT ´ RLOAD ´ 2p
(9)
1
fZ =
COUT ´ RESR ´ 2p
(10)
7.4.3 Small Signal Model for Frequency Compensation
The TPS54418 device uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 34. The Type-II
circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type-IIA, one additional high frequency pole is added to attenuate high-frequency noise.
18
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Device Functional Modes (continued)
VOUT
VSENSE
COMP
+
R3
C2
C1
Type IIB
VREF
R3
COUT(ea)
5 pF
C1
R1
gM(ea)
R2
ROUT(ea)
Type IIA
Figure 34. Types of Frequency Compensation
The design guidelines for TPS54418 device loop compensation are as follows:
1. Calculate the modulator pole (fP(MOD)) and the esr zero, (fZ1) using Equation 11 and Equation 12. If the output
voltage is a high percentage of the capacitor rating it may be necessary to derate the output capacitor
(COUT). Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and
Equation 14 to estimate a starting point for the crossover frequency, fC. Equation 13 shows the geometric
mean of the modulator pole and the ESR zero and Equation 14 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover
frequency.
IOUT(max )
fP(mod) =
2p ´ VOUT ´ COUT
(11)
fZ1 =
COUT
1
× RESR × tN
(12)
fC = §fP:mod ; + fZ1
(13)
f
fC = fP(mod) ´ SW
2
2. Calculate resistor R3. Equation 15 shows the calculation for resistor R3.
2p ´ fC ´ VOUT ´ COUT
R3 =
gM(ea ) ´ VREF ´ gM(ps )
(14)
where
•
•
gM(ea) is the amplifier gain (225 μA/V)
gM(ps) is the power stage gain (13 A/V)
(15)
3. Place a compensation zero at the dominant pole. fP. Equation 16 shows the calculation for capacitor C1.
1
fP =
COUT ´ RLOAD ´ 2p
(16)
RL ´ COUT
C1 =
R3
(17)
4. Capacitor C2 is optional. It can be used to cancel the zero from the output capacitor (COUT) ESR.
´ COUT
R
C2 = ESR
R3
(18)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This design example describes a high-frequency switching regulator design using ceramic output capacitors. This
design is available as the HPA375 (SLVU280) evaluation module (EVM).
8.2 Typical Application
This section details a high-frequency, 1.8-V output power supply design application with adjusted UVLO.
VIN = 3 V to 6 V
16
VIN
1
C1
10 PF
L1
1.0 H
U1
TPS54418RTE
C2
0.1 PF
R1
48.7 NŸ
2
15
6
R2
VSNS
32.4 NŸ
R3
7.5 NŸ
7
8
R4
182 NŸ
C3
2700 pF
VIN
PH
VIN
PH
VIN
PH
EN
BOOT
VSNS
PWRGD
COMP
GND
RT/CLK
GND
AGND
9
VOUT = 1.8 V
IOUT = 4 A
VOUT
10
11
12
13
14
C5
0.1 PF
R6
100 NŸ
C6
C7
22 PF 22 PF
R5
100 NŸ
VSNS
VIN
3
4
R7
80.6 NŸ
PWRGD
5
SS
PowerPAD
C4
0.01 PF
Figure 35. Typical Application Schematic, TPS54418
8.2.1 Design Requirements
Table 1. Design Parameters
PARAMETER
NOTES AND CONDITIONS
MIN
TYP
MAX
3
3.3
6
VIN
Input voltage
Operating
VSTART
Start input voltage
Rising
3.1
VSTOP
Stop input voltage
Falling
2.8
VOUT
Output voltage
ΔVOUT
Transient response
1-A to 2-A load step
3%
IOUT(max)
Maximum output current
VOUT(ripple)
Output voltage ripple
fSW
Switching frequency
20
V
1.8
1
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UNIT
V
4
A
30
mVP-P
MHz
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8.2.2 Detailed Design Procedure
8.2.2.1
Step One: Select the Switching Frequency
Choose the highest switching frequency possible in order to produce the smallest solution size. The high
switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. However, the highest switching frequency causes extra switching losses,
which in turn decrease the device performance. The device is capable of operating between 200 kHz and 2 MHz.
Select a moderate switching frequency of 1 MHz in order to achieve both a small solution size and a highefficiency operation. Using Equation 5, R4 is calculates to 180 kΩ. A standard 1%, 182-kΩ resistor is used in the
design.
8.2.2.2 Step Two: Select the Output Inductor
The inductor selected must operate across the entire TPS54418 device input voltage range. To calculate the
value of the output inductor, use Equation 19. KIND is a coefficient that represents the amount of inductor ripple
current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output
capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the
inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority
of applications.
For this design example, use a KIND of 0.3 and the inductor value is calculated to be 0.96 μH. For this design,
use an inductor with the nearest standard value of 1.0 μH. For the output filter inductor, it is important that the
RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be
calculated in Equation 21 and Equation 22.
For this design, the RMS inductor current is 4.014 A and the peak inductor current is 4.58 A. The chosen
inductor is a TOKO FDV0630-1R0M. It has a RMS current rating of 9.1 A and a saturation current rating of 20.2
A. The current ratings for this exceed the requirement, but the inductor was chosen for small physical size and
low series resistance for high efficiency.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
L1 =
(V
IN(max ) - VOUT
IOUT ´ KIND
IRIPPLE =
IL(rms ) =
)´
VOUT
VIN(max ) ´ fSW
(V
IN(max ) - VOUT
L1
(IOUT )
2
)´
(19)
VOUT
VIN(max ) ´ fSW
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
+
´
12 çç
VIN(max ) ´ L1´ fSW
è
(20)
)ö÷
2
÷
÷
ø
(21)
æI
ö
IL(peak ) = IOUT + ç RIPPLE ÷
2
è
ø
(22)
8.2.2.3 Step Three: Choose the Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
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The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for two clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 25 shows the necessary minimum output
capacitance.
For this example, the transient load response is specified as a 3% change in VOUT for a load step from 1 A (50%
load) to 2 A (100%).
ΔIOUT = 2 –1 = 1 A
ΔVOUT = 0.03 × 1.8 = 0.054 V
(23)
(24)
Using these numbers gives a minimum capacitance of 37 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 26 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Equation 26 yields 5.2 µF.
2 × IIOUT
fSW × VOUT
IRipple
COUT (ripple ) >
8 × fSW × VOUT (ripple )
COUT (transient ) >
(25)
(26)
where
•
•
•
•
•
ΔIOUT is the load step size
ΔVOUT is the acceptable output deviation
fSW is the switching frequency
IRipple is the inductor ripple current
VOUT(Ripple) is the acceptable DC output voltage ripple
Equation 27 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 27 indicates the ESR should be less than 57 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 57 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22-μF, 10-V, X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (root mean square) value of the maximum ripple current. Equation 28 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 28 yields
333 mA.
R ESR <
VOUT (ripple )
IRipple
ICO(rms ) =
22
(
VOUT ´ VIN(max ) - VOUT
(27)
)
12 ´ VIN(max ) ´ L1´ fSW
(28)
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8.2.2.4 Step Four: Select the Input Capacitor
The TPS54418 device requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least
4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes
any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the device.
The input ripple current can be calculated using Equation 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 30.
ICIN(rms ) = IOUT ´
DVIN =
(
VIN(min ) - VOUT
VOUT
´
VIN(min )
VIN(min )
)
(29)
IOUT(max ) ´ 0.25
CIN ´ fSW
(30)
Using the design example values, IOUT(max) = 4 A, CIN = 10 μF, fSW = 1 MHz, yields an input voltage ripple of 99
mV and a rms input ripple current of 1.96 A.
8.2.2.5 Step Five: Minimum Load DC COMP Voltage
The TPS54418 implements a minimum COMP voltage clamp for improved load-transient response. The COMP
voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreases as the
peak inductor current decreases. During a severe load-dump event, for instance, the COMP voltage decreases
suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop
compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turnon of
the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage
overshoot more quickly.
Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3
sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steadystate DC level of COMP must be measured at the minimum designed load and at the maximum designed input
voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions give the
minimum COMP voltage for a given design. Generally, the COMP voltage and minimum clamp voltage move by
about the same amount with temperature. Increasing the minimum load COMP voltage is accomplished by
decreasing the output inductor value or the switching frequency used in a given design.
8.2.2.6 Step Six: Choose the Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
device reach the current limit or excessive current draw from the input power supply may cause the input voltage
rail to sag. Limiting the output voltage slew rate solves both of these problems.
The soft-start capacitor value can be calculated using Equation 31. For the example circuit, the soft-start time is
not too critical since the output capacitor value is 44 µF which does not require much current to charge to 1.8 V.
The example circuit has the soft-start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In
the device, ISS is 2 μA and VREF is 0.8 V. For this application, maintain the soft-start time in the range between
1 ms and 10 ms.
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I ´t
CSS = SS SS
VREF
where
•
•
•
•
CSS is in nF
ISS is in µA
tSS is in ms
VREF is in V
(31)
8.2.2.7 Step Seven: Select the Bootstrap Capacitor
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
8.2.2.8 Step Eight: Undervoltage Lockout Threshold
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54418. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 3.1 V (VSTART). Switching continues until the input voltage falls
below 2.8 V (VSTOP).
The programmable UVLO and enable voltages are set using a resistor divider between the VIN pin and GND to
the EN pin. Equation 32 and Equation 33 can be used to calculate the resistance values necessary. From
Equation 32 and Equation 33, a 48.7 kΩ between the VIN pin and the EN pin and a 32.4-kΩ resistor between the
EN pin and GND are required to produce the 3.1-V start voltage and the 2.8-V stop voltage.
0.944 × VSTART - VSTOP
R1 =
2.59 ´ 10-6
(32)
R2 =
1.18 × R1
VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6
(33)
8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
For the example design, 100 kΩ was selected for R6. Using Equation 34, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.6 kΩ.
Vref
R7 =
R6
VOUT - Vref
(34)
8.2.2.9.1 Output Voltage Limitations
Due to the internal design of the TPS54418, there are limitations to the minimum and maximum achievable
output voltages. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by Equation 35. There is also a maximum achievable output voltage which is limited by the minimum off
time. The maximum output voltage is given by Equation 36. These equations represent the results when the
power MOSFETs are matched. Refer to SLYT293 for more information.
VOUT :min ; = t ON (min ) × fSW (max ) × VIN:max ; F IOUT (min )kRLS (min ) + RDCR o
where
•
•
•
•
•
•
•
24
VOUT(min) is the minimum achievable output voltage
tON(min) is the minimum controllable on-time (110 nsec typical)
fSW(max) is the maximum switching frequency including tolerance
VIN(max) is the maximum input voltage
IOUT(min) is the minimum load current
RLS(min) is the minimum low-side MOSFET on-resistance. (30 mΩ typical)
RDCR is the series resistance of output inductor
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VOUT :max ; = k1 F tOFF :max ;fSW (max )oVIN:min ; F IOUT :max ;kRLS(max ) + RDCR o
where
•
•
•
•
•
•
•
VOUT(max) is the maximum achievable output voltage
tOFF(max) is the maximum, minimum controllable off time (60 ns typical)
fSW(max) is the maximum switching frequency including tolerance
VIN(min) is the minimum input voltage
IOUT(max) is the maximum load current
RHS(max) is the maximum high-side MOSFET on-resistance. (70 mΩ max)
RDCR is the series resistance of output inductor
(36)
8.2.2.10 Step 10: Select Loop Compensation Components
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54418. Because the slope compensation is ignored, the actual crossover frequency is usually lower than
the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fP(mod), and the esr zero, fZ1 must be calculated using Equation 37 and
Equation 38. For COUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 39 and Equation 40 to estimate a starting point for the
crossover frequency, fC. For the example design, fP(mod) is 8.04 kHz and fZ1 is 2412 kHz. Equation 39 is the
geometric mean of the modulator pole and the esr zero and Equation 40 is the mean of modulator pole and the
switching frequency. Equation 39 yields 139 kHz and Equation 40 gives 63 kHz. Use the lower value of
Equation 39 or Equation 40 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
IOUT(max )
fP(mod) =
2p ´ VOUT ´ COUT
(37)
fZ1 =
COUT
1
× RESR × tN
(38)
fC = §fP:mod ; + fZ1
(39)
f
fC = fP(mod) ´ SW
2
(40)
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 41 to calculate the compensation network’s
resistor value. In this example, the anticipated cross-over frequency fC is 35 kHz. The power stage gain
(gM(ps)) is 13 A/V and the error amplifier gain (gM(ea)) is 225uA/V.
2p ´ fC ´ VOUT ´ COUT
R3 =
gM(ea ) ´ VREF ´ gM(ps )
(41)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network’s capacitor can be calculated from Equation 42.
´ COUT
R
C3 = OUT
R3
(42)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
From the procedures above, start with a 11.2 kΩ resistor and a 2650pF capacitor. After prototyping and bode
plot measurement, the optimized compensation network selected for this design includes a 7.5 kΩ resistor and a
2700 pF capacitor.
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8.2.2.11 Power Dissipation Estimate
Use Equation 43 through Equation 52 to help estimate the device power dissipation under continuous conduction
mode (CCM) operation. The power dissipation of the device (PTOT) includes conduction loss (PCOND), dead time
loss (PD), switching loss (PSW), gate drive loss (PGD) and supply current loss (PQ).
PCOND= (IOUT)2 × RDS(on)
PD = ƒSW × IOUT × 0.7 × 60 × (10)–9
PD = ƒSW × IOUT × 0.7 × 60 × (10)–9
PSW = 2 × (VIN)2 × ƒSW × IOUT × 0.25 × (10)–9
PSW = 2 × (VIN)2 × ƒSW × IOUT × 0.25 × (10)–9
PGD = 2 × VIN × 3 × (10)–9 × ƒSW
PQ = 350 × (10)–6 × VIN
(43)
(44)
(45)
(46)
(47)
(48)
where
• IOUT is the output current (A)
• RDS(on) is the on-resistance of the high-side MOSFET (Ω)
• VOUT is the output voltage (V)
• VIN is the input voltage (V)
• ƒSW is the switching frequency (Hz)
PTOT = PCOND + PD + PSW + PGD + PQ
(49)
(50)
For a given ambient temperature,
TJ = TA + RTH × PTOT
(51)
For maximum junction temperature (TJ(max) = 150°C)
TA(max) = TJ(max) – RTH × PTOT
where
•
•
•
•
•
•
PTOT is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
(52)
3.5
3.5
3
3
Power Dissipation (W)
Power Dissipation (W)
Additional power can be lost in the regulator circuit due to the inductor ac and dc losses and trace resistance that
impact the overall regulator efficiency. Figure 36 and Figure 37 show power dissipation for the EVM.
2.5
2
1.5
1
0.5
2.5
2
1.5
1
0.5
0
0
20 30 40 50 60 70 80 90 100 110 120 130 140 150
20 30 40 50 60 70 80 90 100 110 120 130 140 150
Junction Temperature (°C)
TA = 25°C
Maximum Ambient Temperature (°C)
No air flow
Figure 36. Power Dissipation vs Junction Temperature
26
TJ(max) = 150°C
No air flow
Figure 37. Power Dissipation vs Ambient Temperature
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8.2.3 Application Curves
100
100
3.3 Vin,1.8 Vout
95
90
3.3 Vin,1.8 Vout
90
80
5 Vin, 1.8 Vout
Efficiency - %
Efficiency - %
85
80
75
70
65
70
60
5 Vin, 1.8 Vout
50
40
30
60
20
55
10
50
0
1
2
3
4
0
0.001
0.01
0.1
Output Current - A
Output Current - A
Figure 38. Efficiency vs Load Current
Vout = 50 mV / div (ac coupled)
1
10
Figure 39. Efficiency vs Load Current
Vout = 50 mV / div (ac coupled)
Iout = 1 A / div (1 A to 3 A load step)
Iout = 2 A / div (0 A to 4 A load step)
Time = 500 μsec / div
Time = 600 μsec / div
4-A Current Step
2-A Current Step
Figure 40. Transient Response
Figure 41. Transient Response
Vin = 5 V / div
Vin = 5 V / div
EN = 2 V / div
EN = 2 V / div
SS = 2 V / div
SS = 2 V / div
Vout = 2 V / div
Vout = 2 V / div
Time = 5 msec / div
Time = 5 msec / div
Figure 42. Power Up VOUT, VIN
Figure 43. Power Down Vout, Vin
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Vin = 5 V / div
Vin = 5 V / div
EN = 2 V / div
EN = 2 V / div
SS = 2 V / div
SS = 2 V / div
Vout = 2 V / div
Vout = 2 V / div
Time = 5 msec / div
Time = 5 msec / div
Figure 45. Power Down VOUT, EN
Figure 44. Power Up VOUT, EN
Vout = 10 mV / div (ac coupled)
Vout = 10 mV / div (ac coupled)
PH = 2 V / div
PH = 2 V / div
Time = 500 nsec / div
Time = 500 msec / div
IOUT = 0 A
IOUT = 4 A
Figure 46. Output Ripple
Figure 47. Output Ripple
Vin = 100 mV / div (ac coupled)
Vin = 100 mV / div (ac coupled)
PH = 2 V / div
PH = 2 V / div
Time = 500 nsec / div
Time = 500 nsec / div
IOUT = 0 A
IOUT = 4 A
Figure 48. Input Ripple
Figure 49. Input Ripple
28
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60
180
50
150
40
120
90
20
60
10
30
0
Gain
0.1
0
-10
-30
-20
-60
-30
-90
-40
-120
-50
-150
-60
-180
0.05
0
-0.05
-0.1
-0.15
-0.2
1000000
VIN = 3.3 V
100000
10000
1000
100
Frequency - Hz
Vin = 3.3
0.15
Percent Deviation - %
Phase
30
0.2
Phase - Deg
Gain
www.ti.com
0
1
2
3
4
Output Current - A
IOUT = 4 A
Figure 51. Load Regulation vs Load Current
Figure 50. Closed Loop Response
0.2
0.1
Vin = 5.0 V
0.08
0.15
Iout = 2 A
0.1
Percent Deviation - %
Percent Deviation - %
0.06
0.05
0
-0.05
-0.1
0.04
0.02
0
-0.02
-0.04
-0.06
-0.15
-0.08
-0.2
-0.1
0
1
2
3
4
3
Output Current - A
4
5
6
Input Voltage-V
Figure 52. Load Regulation vs Load Current
Figure 53. Regulation vs Input Voltage
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 2.95 V and 6 V. This supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme. See the recommendations in the Layout Guidelines
section.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance.
• Minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 54 for a
PCB layout example.
• The GND pins and AGND pin should be tied directly to the power pad under the TPS54418 device. The
power pad should be connected to any internal PCB ground planes using multiple vias directly under the
device. Additional vias can be used to connect the top-side ground area to the internal planes near the input
and output capacitors. For operation at full rated load, the top-side ground area along with any additional
internal ground planes must provide adequate heat dissipating area.
• Place the input bypass capacitor as close to the device as possible.
• Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output
inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive
coupling.
• The boot capacitor must also be located close to the device.
• The sensitive analog ground connections for the feedback voltage divider, compensation components, softstart capacitor and frequency set resistor should be connected to a separate analog ground trace as shown in
Figure 54.
• The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to
the device and routed with minimal trace lengths.
• The additional external components can be placed approximately as shown. It is possible to obtain
acceptable performance with alternate PCB layouts, however, this layout has been shown to produce good
results and can be used as a guide.
30
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTRORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
VOUT
OUTPUT
FILTER
CAPACITOR
PH
SLOW START
CAPACITOR
RT/CLK
COMP
VSENSE
AGND
SS
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 54. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54418 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Development Support
For more SWIFTTM documentation, see the TI website at www.ti.com/swift.
11.2 Trademarks
SWIFT is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
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6-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA00835RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54418
TPS54418RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54418
TPS54418RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54418
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54418RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS54418RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54418RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS54418RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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