Texas Instruments | CSD87335Q3D Synchronous Buck NexFET™ Power Block (Rev. B) | Datasheet | Texas Instruments CSD87335Q3D Synchronous Buck NexFET™ Power Block (Rev. B) Datasheet

Texas Instruments CSD87335Q3D Synchronous Buck NexFET™ Power Block (Rev. B) Datasheet
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CSD87335Q3D
SLPS574B – FEBRUARY 2016 – REVISED APRIL 2018
CSD87335Q3D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The CSD87335Q3D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5-V gate drive applications, this
product offers a flexible solution capable of offering a
high-density power supply when paired with any 5-V
gate drive from an external controller or driver.
1
Half-Bridge Power Block
Up to 27-V VIN
93.5% System Efficiency at 15 A
Up to 25-A Operation
High-Frequency Operation (Up to 1.5 MHz)
High-Density SON 3.3-mm × 3.3-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Top View
2 Applications
•
•
•
•
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
8
VSW
7
VSW
3
6
VSW
4
5
BG
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
P0116-01
Device Information(1)
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD87335Q3D
13-Inch Reel
2500
CSD87335Q3DT
7-Inch Reel
250
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Circuit
Typical Power Block Efficiency and Power Loss
100
VIN
VDD
6
BOOT
VDD
VIN
TGR
BG
ENABLE
PWM
ENABLE
VSW
LL
90
VOUT
Sync
FET
PWM
DRVL
PGND
Driver IC
CSD87335Q3D
Efficiency (%)
GND
Control
FET
4.5
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 950 nH
fSW = 500 kHz
TA = 25qC
80
70
3
Power Loss (W)
TG
DRVH
1.5
Copyright © 2017, Texas Instruments Incorporated
60
0
5
10
15
Output Current (A)
20
0
25
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87335Q3D
SLPS574B – FEBRUARY 2016 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Block Performance ........................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Applications and Implementation ...................... 10
6.1
6.2
6.3
6.4
Application Information............................................
Power Loss Curves ................................................
Safe Operating Curves (SOA) ................................
Normalized Curves..................................................
10
12
12
12
6.5 Calculating Power Loss and SOA .......................... 13
7
Recommended PCB Design Overview .............. 15
7.1 Electrical Performance ............................................ 15
7.2 Thermal Performance ............................................. 16
8
Device and Documentation Support.................. 17
8.1
8.2
8.3
8.4
8.5
9
Receiving Notification of Documentation Updates.. 17
Community Resources............................................ 17
Trademarks ............................................................. 17
Electrostatic Discharge Caution .............................. 17
Glossary .................................................................. 17
Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1
9.2
9.3
9.4
9.5
Q3D Package Dimensions......................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
Q3D Tape and Reel Information .............................
Pin Configuration.....................................................
18
19
19
20
20
4 Revision History
Changes from Revision A (October 2017) to Revision B
•
Page
Updated Figure 33 top layer showing pins 1 and 2 connected. .......................................................................................... 16
Changes from Original (February 2016) to Revision A
Page
•
Corrected X & Y axis labels on Figure 29 ............................................................................................................................ 11
•
Corrected X & Y axis labels on Figure 30 ............................................................................................................................ 11
2
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SLPS574B – FEBRUARY 2016 – REVISED APRIL 2018
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
Voltage
MAX
VIN to PGND
30
VSW to PGND
30
VSW to PGND (10 ns)
UNIT
32
TG to TGR
–8
10
BG to PGND
–8
10
V
Pulsed current rating, IDM (2)
70
A
Power dissipation, PD
6
W
Avalanche energy, EAS
Sync FET, ID = 51 A, L = 0.1 mH
130
Control FET, ID = 33 A, L = 0.1 mH
54
Operating junction and storage temperature, TJ, TSTG
(1)
(2)
–55
mJ
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µs, duty cycle ≤ 1%.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
VGS
Gate drive voltage
VIN
Input supply voltage
ƒSW
Switching frequency
MIN
MAX
4.5
8
V
27
V
CBST = 0.1 µF (min)
1500
Operating current
TJ
Operating temperature
UNIT
kHz
25
A
125
°C
5.3 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
MIN
TYP
Junction-to-ambient thermal resistance (min Cu) (1)
MAX
135
Junction-to-ambient thermal resistance (max Cu) (1) (2)
73
Junction-to-case thermal resistance (top of package) (1)
29
Junction-to-case thermal resistance (PGND pin) (1)
2.5
UNIT
°C/W
°C/W
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
5.4 Power Block Performance (1)
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PLOSS
Power loss (1)
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 15 A, ƒSW = 500 kHz,
LOUT = 950 nH, TJ = 25°C
IQVIN
VIN quiescent current
TG to TGR = 0 V, BG to PGND = 0 V
(1)
MIN
TYP
MAX
UNIT
1.5
W
10
µA
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high-current 5-V driver IC.
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5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
Q1 Control FET
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
IDSS
Drain-to-source leakage
current
30
30
VGS = 0 V, VDS = 24 V
IGSS
Gate-to-source leakage
current
VDS = 0 V,
VGS = +10 V / –8 V
VGS(th)
Gate-to-source threshold
voltage
VDS = VGS, IDS = 250 µA
ZDS(on)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 15 A,
ƒSW = 500 kHz,
LOUT = 950 nH
6.7
1.9
mΩ
gfs
Transconductance
VDS = 3 V, IDS = 15 A
59
107
S
1.0
V
1
1
µA
100
100
nA
1.20
V
1.9
0.75
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
805
1050
1620
2100
pF
412
536
783
1020
CRSS
pF
Reverse transfer capacitance
15
20
28
36
pF
RG
Series gate resistance
1.2
2.4
0.6
1.2
Ω
Qg
Gate charge total (4.5 V)
5.7
7.4
10.7
14.0
nC
Qgd
Gate charge – gate-to-drain
Qgs
Gate charge – gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tf
Fall time
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
VDS = 15 V,
IDS = 15 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 15 A, RG = 2 Ω
1.1
1.7
nC
2.1
2.8
nC
1.1
1.4
nC
11
19
nC
8
8
ns
29
27
ns
13
17
ns
4
5
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IDS = 15 A, VGS = 0 V
0.8
VDS = 15 V, IF = 15 A,
di/dt = 300 A/µs
24
40
nC
17
22
ns
Max RθJA = 73°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
4
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1.0
0.8
1.0
V
Max RθJA = 135°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm) thick
Cu.
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SLPS574B – FEBRUARY 2016 – REVISED APRIL 2018
5.6 Typical Power Block Device Characteristics
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 950 nH, IOUT = 25 A, TJ = 125°C, unless stated
otherwise.
5
1.05
1
Power Loss, Normalized
Power Loss (W)
4
3
2
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0
0
5
10
15
Output Current (A)
20
25
0.55
-50
-25
0
D001
Figure 1. Power Loss vs Output Current
25
50
75
100
Junction Temperature (qC)
125
150
D002
Figure 2. Power Loss vs Temperature
30
Output Current (A)
25
20
15
10
400 LFM
200 LFM
100 LFM
Nat. conv.
5
0
0
10
20
30
40
50
60
Ambient Temperature (qC)
70
80
90
D004
Figure 3. Safe Operating Area – PCB Horizontal Mount(1)
(1)
The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Applications and
Implementation section for detailed explanation.
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Typical Power Block Device Characteristics (continued)
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 950 nH, IOUT = 25 A, TJ = 125°C, unless stated
otherwise.
30
Output Current (A)
25
20
15
10
5
0
0
15
30
45
60
75
90
Board Temperature (qC)
105
120
135
D005
1.25
4.3
1.5
8.5
1.2
3.4
1.4
6.8
1.15
2.6
1.3
5.1
1.1
1.7
1.2
3.4
1.05
0.9
1.1
1.7
1
0.0
1
0.0
-1.7
0.95
-3.4
500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
D006
0.9
0.8
50
200
350
-0.9
0
5.8
1.3
5.0
1.25
4.2
1.2
3.3
1.15
2.5
1.1
1.7
1.05
0.8
1
0.0
0.95
12
16
Input Voltage (V)
20
-1.7
24
D007
1.3
5.1
1.2
3.4
1.1
1.7
1
0.0
0.9
-1.7
-0.8
0.9
0.7
1
1.3
1.6
1.9 2.2 2.5 2.8
Output Voltage (V)
3.1
3.4
-1.7
3.7
0.8
50
200
D008
Figure 7. Normalized Power Loss vs Output Voltage
6
8
Figure 6. Normalized Power Loss vs Input Voltage
Power Loss, Normalized
1.35
SOA Temperature Adj. (qC)
Power Loss, Normalized
Figure 5. Normalized Power Loss vs Switching Frequency
4
SOA Temperature Adj. (qC)
0.9
SOA Temperature Adj. (qC)
10.2
Power Loss, Normalized
1.6
SOA Temperature Adj. (qC)
Power Loss, Normalized
Figure 4. Typical Safe Operating Area(1)
350
500
650
800
Output Inductance (nH)
950
-3.4
1100
D009
Figure 8. Normalized Power Loss vs Output Inductance
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5.7 Typical Power Block MOSFET Characteristics
100
100
90
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C, unless stated otherwise.
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6 V
VGS = 8.0 V
10
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6 V
VGS = 8.0 V
10
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VDS - Drain-to-Source Voltage (V)
0.8
0.9
0
0.1
D010
Figure 9. Control MOSFET Saturation
D010
Figure 10. Sync MOSFET Saturation
IDS - Drain-to-Source Current (A)
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
0.001
0.001
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
0
3.5
0.5
D011
1
1.5
2
VGS - Gate-to-Source Voltage (V)
2.5
D011
VDS = 5 V
VDS = 5 V
Figure 12. Sync MOSFET Transfer
Figure 11. Control MOSFET Transfer
8
8
7
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.6
100
100
IDS - Drain-to-Source Current (A)
0.2
0.3
0.4
0.5
VDS - Drain-to-Source Voltage (V)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0
2
4
6
Qg - Gate Charge (nC)
ID = 15 A
8
10
0
2
4
D012
VDD = 15 V
6
8
10
12
14
Qg - Gate Charge (nC)
ID = 15 A
Figure 13. Control MOSFET Gate Charge
16
18
20
D012
VDD = 15 V
Figure 14. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
5000
10000
C - Capacitance (pF)
C - Capacitance (pF)
1000
100
10
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
3
6
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
27
30
0
3
6
D013
Figure 15. Control MOSFET Capacitance
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
27
30
D013
Figure 16. Sync MOSFET Capacitance
1.8
1.3
VGS(th) - Threshold Voltage (V)
VGS(th) - Threshold Voltage (V)
1.2
1.6
1.4
1.2
1
0.8
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
0.3
-75
175
-50
-25
D014
ID = 250 µA
Figure 17. Control MOSFET VGS(th)
150
175
D014
Figure 18. Sync MOSFET VGS(th)
12
TC = 25° C, I D = 15 A
TC = 125° C, I D = 15 A
16
RDS(on) - On-State Resistance (m:)
RDS(on) - On-State Resistance (m:)
125
ID = 250 µA
18
14
12
10
8
6
4
2
0
TC = 25° C, I D = 15 A
TC = 125° C, I D = 15 A
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
Figure 19. Control MOSFET RDS(on) vs VGS
8
0
25
50
75 100
TC - Case Temperature (° C)
10
0
1
2
D014
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D014
Figure 20. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
VGS = 4.5 V
VGS = 8.0 V
Normalized On-State Resistance
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
ID = 15 A
125
150
VGS = 4.5 V
VGS = 8.0 V
1.4
1.2
1
0.8
0.6
-75
175
0
25
50
75 100
TC - Case Temperature (° C)
ID = 15 A
125
150
175
D016
VGS = 4.5 V
Figure 22. Sync MOSFET Normalized RDS(on)
100
100
TC = 25° C
TC = 125° C
10
ISD - Source-to-Drain Current (A)
ISD - Source-to-Drain Current (A)
-25
VGS = 4.5 V
Figure 21. Control MOSFET Normalized RDS(on)
1
0.1
0.01
0.001
0.0001
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
0
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D017
Figure 24. Sync MOSFET Body Diode
100
100
IAV - Peak Avalanche Current (A)
TC = 25q C
TC = 125q C
10
1
0.01
0.2
D017
Figure 23. Control MOSFET Body Diode
IAV - Peak Avalanche Current (A)
-50
D016
0.1
TAV - Time in Avalanche (ms)
1
10
TC = 25q C
TC = 125q C
1
0.01
D018
Figure 25. Control MOSFET Unclamped Inductive Switching
0.1
TAV - Time in Avalanche (ms)
1
D018
Figure 26. Sync MOSFET Unclamped Inductive Switching
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6 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 27). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Power Stage
Components
Input
Supply
+
-
Power Block
Components
Ci
Control
FET
Driver
PWM
Driver
Switch
Node
Lo
Sync
FET
Co
IL
Load
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Figure 27. Equivalent System Schematic
The CSD87335Q3D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 28). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
10
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Application Information (continued)
Input
Supply
RPCB
CESR
LDRAIN
CINPUT
Control
FET
Driver
PWM
CESL
LSOURCE
Switch
Node
Lo
Co
IL
Load
LDRAIN
Sync
FET
Driver
CTOTAL
LSOURCE
Figure 28. Elimination of Parasitic Inductances
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 29 and Figure 30 compare the efficiency and power loss performance of the
CSD87335Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87335Q3D clearly highlights the importance of considering the effective AC on-impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
96
6.0
5.0
92
4.5
90
Power Loss (W)
Efficiency (%)
PowerBlock HS/LS RDS(ON) = 6.7 m:/3.1 m:
PowerBlock HS/LS RDS(ON) = 6.7 m:/3.1 m:
PowerBlock HS/LS RDS(ON) = 6.7 m:/1.9 m:
5.5
94
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 950 nH
fSW = 500 kHz
TA = 25qC
88
86
84
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 950 nH
fSW = 500 kHz
TA = 25qC
4.0
3.5
3.0
2.5
2.0
1.5
PowerBlock HS/LS RDS(ON) = 6.7 m:/3.1 m:
PowerBlock HS/LS RDS(ON) = 6.7 m:/3.1 m:
PowerBlock HS/LS RDS(ON) = 6.7 m:/1.9 m:
82
1.0
0.5
80
0.0
0
5
10
15
20
Output Current (A)
25
30
0
D030
Figure 29. Efficiency
5
10
15
20
Output Current (A)
25
30
D031
Figure 30. Power Loss
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Application Information (continued)
Table 1 compares the traditional DC measured RDS(ON) of CSD87335Q3D versus its ZDS(ON). This comparison
takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87335Q3D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs. ZDS(ON)
HS
PARAMETER
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
6.7
—
1.9
—
DC measured RDS(ON) (VGS = 4.5 V)
6.7
8.1
3.1
3.9
The CSD87335Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87335Q3D as a function of load current. This curve
is measured by configuring and running the CSD87335Q3D as it would be in the final application (see
Figure 31).The measured power loss is the CSD87335Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.3 Safe Operating Curves (SOA)
The SOA curves in the CSD87335Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. to Figure 4 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.4 Normalized Curves
The normalized curves in the CSD87335Q3D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change in system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
12
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Normalized Curves (continued)
Input Current (IIN)
Gate Drive
Current (IDD)
VDD
A
A
VDD
V
Input Voltage (VIN)
VIN
Gate Drive V
Voltage (VDD)
VIN
BOOT
DRVH
ENABLE
TG
Control
FET
Output Current (IOUT)
VSW
LL
PWM
PWM
DRVL
GND
A
TGR
BG
Sync
FET
PGND
Averaging
Circuit
CSD87335Q3D
Driver IC
VOUT
Averaged Switch
V Node Voltage
(VSW_AVG)
Copyright © 2017, Texas Instruments Incorporated
Figure 31. Typical Application
6.5 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example section).
Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.5.1 Design Example
Operating conditions:
• Output current = 15 A
• Input voltage = 14 V
• Output voltage = 1.4 V
• Switching frequency = 750 kHz
• Inductor = 600 nH
6.5.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 15 A = 1.92 W (Figure 1)
Normalized power loss for input voltage ≈ 1.01 (Figure 6)
Normalized power loss for output voltage ≈ 1.01 (Figure 7)
Normalized power loss for switching frequency ≈ 1.08 (Figure 5)
Normalized power loss for output inductor ≈ 1.01 (Figure 8)
Final calculated power loss = 1.92 W × 1.01 × 1.01 × 1.08 × 1.01 ≈ 2.14 W
6.5.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 0.14°C (Figure 6)
SOA adjustment for output voltage ≈ 0.17°C (Figure 7)
SOA adjustment for switching frequency ≈ 1.32°C (Figure 5)
SOA adjustment for output inductor ≈ 0.18°C (Figure 8)
Final calculated SOA adjustment = 0.14 + 0.17 + 1.32 + 0.18 ≈ 1.81°C
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Calculating Power Loss and SOA (continued)
In the design example above, the estimated power loss of the CSD87335Q3D would increase to 2.14 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.81°C.
Figure 32 graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 1.81°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 32. Power Block SOA
14
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7 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33).
The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8
should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:
Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.
The RC snubber should be placed as close as possible to the Vsw node and PGND (see Figure 33). (1)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 33 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 33. Recommended PCB Layout (Top Down)
16
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q3D Package Dimensions
DIM
INCHES
MIN
MAX
MIN
MAX
A
1.400
1.500
0.055
0.059
b
0.280
0.400
0.011
0.016
b1
0.310 NOM
0.012 NOM
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
0.940
1.040
0.037
0.041
d1
0.160
0.260
0.006
0.010
d2
0.150
0.250
0.006
0.010
d3
0.250
0.350
0.010
0.014
d4
0.175
0.275
0.007
0.011
D1
3.200
3.400
0.126
0.134
D2
2.650
2.750
0.104
0.108
E
3.200
3.400
0.126
0.134
E1
3.200
3.400
0.126
0.134
E2
1.750
1.850
0.069
0.073
e
18
MILLIMETERS
0.650 TYP
0.026 TYP
L
0.400
0.500
0.016
0.020
θ
0.00
—
—
—
K
0.300 TYP
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9.2 Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
4
0.350 (0.014)
5
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
8
0.210
(0.008)
1
1.090
(0.043)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (inches).
9.3 Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
5
4
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
8
1
0.990
(0.039)
0.100
(0.004)
0.300 (0.012)
0.350 (0.014)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (inches).
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
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1.75 ±0.10
9.4 Q3D Tape and Reel Information
2.00 ±0.05
4.00 ±0.10 (See Note 1)
8.00 ±0.10
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
Ø 1.50
3.60
M0144-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF reflow compatible.
9.5 Pin Configuration
20
POSITION
DESIGNATION
Pin 1
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
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PACKAGE OPTION ADDENDUM
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22-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD87335Q3D
ACTIVE
LSON-CLIP
DQZ
8
2500
Pb-Free (RoHS
Exempt)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 150
87335D
CSD87335Q3DT
ACTIVE
LSON-CLIP
DQZ
8
250
Pb-Free (RoHS
Exempt)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 150
87335D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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22-Mar-2018
Addendum-Page 2
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life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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