Texas Instruments | LMZM33602 4-V to 36-V Input, 2-A Step-Down DC/DC Power Module in QFN Package (Rev. C) | Datasheet | Texas Instruments LMZM33602 4-V to 36-V Input, 2-A Step-Down DC/DC Power Module in QFN Package (Rev. C) Datasheet

Texas Instruments LMZM33602 4-V to 36-V Input, 2-A Step-Down DC/DC Power Module in QFN Package (Rev. C) Datasheet
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LMZM33602
SNVSAO4C – DECEMBER 2017 – REVISED MARCH 2018
LMZM33602 4-V to 36-V Input, 2-A Step-Down DC/DC Power Module in QFN Package
1 Features
3 Description
•
The LMZM33602 power module is an easy-to-use
integrated power solution that combines a 2-A, stepdown, DC/DC converter with power MOSFETs, a
shielded inductor, and passives into a low-profile
package. This power solution requires as few as four
external components and eliminates the loop
compensation and magnetics part selection from the
design process.
Complete Integrated Power Solution
– As Few as 4 External Components
– Minimum Solution Size < 100 mm2
9 mm × 7 mm × 4 mm QFN Package
– All Pins Accessible from Package Perimeter
– Pin Compatible with 3-A LMZM33603
Input Voltage Range: 4 V to 36 V
Output Voltage Range: 1 V to 18 V
Efficiencies Up To 95%
Adjustable Switching Frequency
(200 kHz to 1.2 MHz)
Allows Synchronization to an External Clock
Power-Good Output
Meets EN55011 Class B Radiated EMI Standards
Operating IC Junction Range: –40°C to +125°C
Operating Ambient Range: –40°C to +105°C
Create a Custom Design Using the LMZM33602
With the WEBENCH® Power Designer
1
•
•
•
•
•
•
•
•
•
•
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Device Information
DEVICE NUMBER
LMZM33602
PACKAGE
QFN (18)
BODY SIZE (NOM)
9.00 mm × 7.00 mm
space
space
2 Applications
•
•
•
•
•
•
The 9 mm × 7 mm × 4 mm, 18-pin QFN package is
easy to solder onto a printed circuit board and allows
a compact, low-profile, point-of-load design. The full
feature set, including power good, programmable
UVLO,
prebias
start-up,
overcurrent
and
overtemperature protections, make the LMZM33602
an excellent device for powering a wide range of
applications.
space
Factory and Building Automation
Smart Grid and Energy
Industrial
Medical
Defense
Inverted Output Applications
space
Safe Operating Area
Simplified Schematic
115
105
PGOOD
VIN
95
VOUT
EN/SYNC
VOUT
CIN
RFBT
LMZM33602
RT
COUT
FB
PGND
RRT
Ambient Temperature (°C)
VIN
85
75
65
55
45
RFBB
35
25
0.0
Copyright © 2017, Texas Instruments Incorporated
VIN = 24V
VOUT = 3.3V, fsw = 300kHz
VOUT = 5.0V, fsw = 450kHz
VOUT = 12V, fsw = 900kHz
0.5
1.0
Output Current (A)
1.5
2.0
SOA2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZM33602
SNVSAO4C – DECEMBER 2017 – REVISED MARCH 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
7
8
9
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics (VIN = 5 V)............................
Typical Characteristics (VIN = 12 V)..........................
Typical Characteristics (VIN = 24 V)..........................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Examples...................................................
Theta JA vs PCB Area ..........................................
EMI........................................................................
Package Specifications .........................................
23
23
24
24
26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Custom Design With WEBENCH® Tools .............
Related Documentation .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
12.1 Tape and Reel Information ................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2018) to Revision C
•
Added EMIsub-section ........................................................................................................................................................ 24
Changes from Revision A (February 2018) to Revision B
•
Page
Page
First release of production-data data sheet............................................................................................................................ 1
Changes from Original (December 2017) to Revision A
Page
•
Added new Application with link to SNVA800 app report; minor editorial updates ................................................................ 1
•
Added sentence re: inverting buck-boost topology to Application Information..................................................................... 20
2
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5 Pin Configuration and Functions
1
18
17 16
FB
PGOOD
AGND
PGND
RLR Package
18-Pin QFN
Top View
15
PGND
EN/SYNC
2
14
PGND
RT
3
13
DNC
VIN
4
12
DNC
PGND
5
11
SW
VOUT
8
9
SW
7
VOUT
VOUT
6
10
SW
Pin Functions
PIN
NO.
1
TYPE
NAME
AGND
DESCRIPTION
G
Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to
PGND; the connection is made internal to the device. See the Layout section of the datasheet for a
recommended layout.
2
EN/SYNC
I
EN - Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. This
pin can be used to set the input under voltage lockout with two resistors. See the Programmable
Undervoltage Lockout (UVLO) section.
SYNC - The internal oscillator can be synchronized to an external clock via AC-coupling. See the
Synchronization (SYNC) section for details.
3
RT
I
An external timing resistor connected between this pin and AGND adjusts the switching frequency of
the device. If left open, the default switching frequency is 400 kHz.
4
VIN
I
Input supply voltage. Connect external input capacitors between this pin and PGND.
5, 14, 15, 18
PGND
G
Power ground. This is the return current path for the power stage of the device. Connect pin 5 to the
input source, the load, and to the bypass capacitors associated with VIN and VOUT using power
ground planes on the PCB. Pins 14 and 15 are not connected to PGND internal to the device
and must be connected to PGND at pad 18. Connect pad 18 to the power ground planes using
multiple vias for good thermal performance. See the Layout section of the datasheet for a
recommended layout.
6, 7, 8
VOUT
O
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external bypass capacitors between these pins and PGND.
9, 10, 11
SW
O
Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not
place any external component on these pins or tie them to a pin of another function.
12, 13
DNC
—
Do not connect. Each pin must be soldered to an isolated pad. These pins connect to internal
circuitry. Do not connect these pins to one another, AGND, PGND, or any other voltage.
16
FB
I
Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the
upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the
lower resistor (RFBB) of the feedback divider to AGND.
17
PGOOD
O
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other
DC voltage no higher than 12 V.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
42
V
EN/SYNC
–5.5
VIN + 0.3
V
PGOOD
–0.3
15
V
FB, RT
–0.3
4.5
V
SW
–1
VIN + 0.3
V
SW (< 10-ns transients)
–5
42
V
–0.3
VIN
V
VOUT
Sink current
PGOOD
3
mA
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
500
G
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
20
G
–40
125
°C
–40
105
°C
–40
150
°C
Operating IC junction temperature, TJ
Operating ambient temperature, TA
(2)
(2)
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
Input voltage, VIN
Output voltage, VOUT
EN/SYNC voltage
PGOOD pullup voltage, VPGOOD
MIN
MAX
4 (1)
36
V
1
18
V
–5
VIN
V
–0.3
12
V
1
mA
0
2
A
–40
105
°C
PGOOD sink current, IPGOOD
Output current, IOUT
Operating ambient temperature, TA
(1)
4
UNIT
For output voltages ≤ 5 V, the recommended minimum VIN is 4 V or (VOUT + 1.5 V), whichever is greater. For output voltages > 5 V, the
recommended minimum VIN is (1.3 × VOUT). See Voltage Dropout for information on voltage dropout.
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6.4 Thermal Information
LMZM33602
THERMAL METRIC (1)
RLR (QFN)
UNIT
18 PINS
RθJA
Junction-to-ambient thermal resistance (2)
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (4)
(1)
(2)
(3)
(4)
18.9
°C/W
2.0
°C/W
6.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 63 mm × 63 mm, 4-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA.
The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Over –40°C to +105°C ambient temperature, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2 × 4.7-µF, 50-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4 × 22-µF, 25-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN)
VIN
Input voltage
UVLO
VIN undervoltage lockout
ISHDN
Shutdown supply current
Over IOUT range
4 (1)
36
V
VIN increasing
3.3
3.6
3.9
V
3
3.3
3.5
V
2
4
µA
18
V
VIN decreasing
VEN = 0 V, VIN = 12 V
OUTPUT VOLTAGE (VOUT)
VOUT(ADJ)
Output voltage adjust
Over IOUT range
1
VOUT(Ripple)
Output voltage ripple
20-MHz bandwidth
10
mV
FEEDBACK
Feedback voltage (2)
VFB
IFB
TA = 25°C, IOUT = 0 A
Over VIN range, –40°C ≤ TJ ≤ 125°C, IOUT = 0 A
Load regulation
Over IOUT range, TA = 25°C
Feedback leakage current
VFB = 1 V
Output current
Natural convection, TA = 25°C
0.985
0.98
1
1.015
V
1
1.02
V
0.04%
10
nA
CURRENT
IOUT
Overcurrent threshold
0
2
3.6
A
A
PERFORMANCE
VIN = 24 V,
IOUT = 1 A
ƞ
Efficiency
VIN = 12 V,
IOUT = 1 A
Transient response
(1)
(2)
25% to 75%
load step
1 A/µs slew rate
VOUT = 12 V, fSW = 900 kHz
94%
VOUT = 5 V, fSW = 450 kHz
90%
VOUT = 3.3 V, fSW = 300 kHz
88%
VOUT = 5 V, fSW = 450 kHz
93%
VOUT = 3.3 V, fSW = 300 kHz
91%
VOUT = 2.5 V, fSW = 250 kHz
89%
Over/undershoot
90
mV
Recovery time
55
µs
See Voltage Dropout for information on voltage dropout.
The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
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Electrical Characteristics (continued)
Over –40°C to +105°C ambient temperature, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2 × 4.7-µF, 50-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4 × 22-µF, 25-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
TSS
Internal soft start time
6
ms
170
°C
15
°C
THERMAL
TSHDN
Thermal shutdown
Shutdown temperature
Hysteresis
ENABLE (EN)
VEN-H
EN rising threshold
VEN-HYS
EN hysteresis voltage
IEN
EN Input leakage current
1.4
1.55
1.7
V
100
nA
1
µA
0.4
VIN = 4 V to 36 V, VEN = 2 V
10
V
VIN = 4 V to 36 V, VEN = 36 V
POWER GOOD (PGOOD)
VPGOOD
PGOOD thresholds
VOUT rising (good)
92%
94%
96.5%
VOUT rising (fault)
104%
107%
110%
VOUT falling hysteresis
1.5%
Minimum VIN for valid
PGOOD
50-μA pullup, VEN = 0 V, TA = 25°C
1.5
V
PGOOD low voltage
0.5-mA pullup, VEN = 0 V
0.4
V
CAPACITANCE
CIN
External input capacitance
COUT
External output
capacitance
(3)
(4)
(5)
9.4 (3)
Ceramic type
Non-ceramic type
µF
47
min
(3)
(4)
µF
max
(5)
µF
A minimum of 9.4 µF (2 × 4.7 µF) ceramic input capacitance is required for proper operation. An additional 47 µF of bulk capacitance is
recommended for applications with transient load requirements. See the Input Capacitors section of the datasheet for further guidance.
The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ). A
minimum amount of ceramic output capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or
non-ceramic capacitance close to the load improves the response of the regulator to load transients.
The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection ).
6.6 Switching Characteristics
Over operating ambient temperature range (unless otherwise noted)
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm, and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
340
400
MAX
UNIT
FREQUENCY (RT) and SYNCHRONIZATION (EN/SYNC)
460
kHz
Switching frequency range
200
1200
kHz
VSYNC
Peak-to-peak amplitude of SYNC clock AC
signal (measured at SYNC pin)
2.8
5.5
TS-MIN
Minimum SYNC ON/OFF time
fSW
6
Default switching frequency
RT pin = open
100
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V
ns
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6.7 Typical Characteristics (VIN = 5 V)
1.4
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
VOUT, fSW
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
1.2
Power Dissipation (W)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
VOUT, fSW
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
0.5
1.0
Output Current (A)
1.5
1.0
0.8
0.6
0.4
0.2
0.0
0.0
2.0
VIN = 5 V
1.0
Output Current (A)
1.5
2.0
D005
VIN = 5 V
Figure 1. Efficiency vs Output Current
Figure 2. Power Dissipation vs Output Current
10.0
115
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
1.0 V, 250 kHz
9.0
105
Ambient Temperature (°C)
9.5
Output Ripple Voltage (mV)
0.5
D001
8.5
8.0
7.5
7.0
6.5
6.0
95
85
75
65
55
45
Airflow
Nat Conv
35
5.5
5.0
0.0
0.5
VIN = 5 V
1.0
Output Current (A)
1.5
2.0
25
0.0
D009
COUT = 4 × 22 µF, 25 V, 1210 ceramic
VIN = 5 V
Figure 3. Voltage Ripple vs Output Current
0.5
1.0
Output Current (A)
1.5
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D004
All VOUT
Figure 4. Safe Operating Area
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6.8 Typical Characteristics (VIN = 12 V)
1.4
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
VOUT, fSW
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
1.2
Power Dissipation (W)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
VOUT, fSW
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
0.5
1.0
Output Current (A)
1.5
1.0
0.8
0.6
0.4
0.2
0.0
0.0
2.0
VIN = 12 V
Figure 5. Efficiency vs Output Current
1.5
2.0
D006
Figure 6. Power Dissipation vs Output Current
115
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
5.0 V, 450 kHz
1.0 V, 250 kHz
14
13
12
105
Ambient Temperature (°C)
15
11
10
9
8
7
95
85
75
65
55
45
6
Airflow
Nat Conv
35
5
4
0.0
0.5
VIN = 12 V
1.0
Output Current (A)
1.5
2.0
25
0.0
0.5
D010
COUT = 4 × 22 µF, 25 V, 1210 ceramic
VIN = 12 V
Figure 7. Voltage Ripple vs Output Current
8
1.0
Output Current (A)
VIN = 12 V
16
Output Ripple Voltage (mV)
0.5
D002
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1.0
Output Current (A)
1.5
VOUT = 5 V
2.0
D004
fSW = 450 kHz
Figure 8. Safe Operating Area
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6.9 Typical Characteristics (VIN = 24 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
2.2
95
2.0
90
1.8
Power Dissipation (W)
100
Efficiency (%)
85
80
75
70
65
VOUT, fSW
12 V, 900 kHz
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
60
55
50
0.0
0.5
1.0
Output Current (A)
1.5
VOUT, fSW
12 V, 900 kHz
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
2.0
VIN = 24 V
1.0
Output Current (A)
1.5
2.0
D007
VIN = 24 V
Figure 9. Efficiency vs Output Current
Figure 10. Power Dissipation vs Output Current
16.0
115
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
12 V, 900 kHz
5.0 V, 450 kHz
14.0
13.0
105
Ambient Temperature (°C)
15.0
Output Ripple Voltage (mV)
0.5
D003
12.0
11.0
10.0
9.0
8.0
95
85
75
65
55
45
Airflow
100LFM
Nat Conv
35
7.0
6.0
0.0
0.5
VIN = 24 V
1.0
Output Current (A)
1.5
2.0
25
0.0
0.5
D011
COUT = 4 × 22 µF, 25 V, 1210 ceramic
1.0
Output Current (A)
VIN = 24 V
Figure 11. Voltage Ripple vs Output Current
1.5
VOUT = 5 V
2.0
D008
fSW = 450 kHz
Figure 12. Safe Operating Area
115
Ambient Temperature (°C)
105
95
85
75
65
55
45
35
25
0.0
VIN = 24 V
Airflow
200LFM
100LFM
Nat Conv
0.5
1.0
Output Current (A)
1.5
VOUT = 12 V
2.0
D012
fSW = 900 kHz
Figure 13. Safe Operating Area
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7 Detailed Description
7.1 Overview
The LMZM33602 is a full-featured, 36-V input, 2-A, synchronous step-down converter with PWM, MOSFETs,
shielded inductor, and control circuitry integrated into a low-profile, overmolded package. The device integration
enables small designs, while providing the ability to adjust key parameters to meet specific design requirements.
The LMZM33602 provides an output voltage range of 1 V to 18 V. An external resistor divider is used to adjust
the output voltage to the desired value. The switching frequency can also be adjusted, by either an external
resistor or a sync signal, which allows the LMZM33602 to accommodate a variety of input and output voltage
conditions as well as optimize efficiency. The device provides accurate voltage regulation over a wide load range
by using a precision internal voltage reference. Input undervoltage lockout is internally set at 3.6 V (typical), but
can be adjusted upward using a resistor divider on the EN/SYNC pin of the device. The EN/SYNC pin can also
be pulled low to put the device into standby mode to reduce input quiescent current. A power-good signal is
provided to indicate when the output is within its nominal voltage range. Thermal shutdown and current limit
features protect the device during an overload condition. An 18-pin, QFN package that includes exposed bottom
pads provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Precision
Enable
EN/SYNC
Sync
Detect
Shutdown
Logic
OCP
Oscillator
RT
Thermal
Shutdown
VIN
UVLO
VIN
PGOOD
SW
PGOOD
Logic
FB
Soft
Start
Power
Stage
and
Control
Logic
+
+
VREF
6.8µH
VOUT
Comp
AGND
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 16) programs the output voltage of the LMZM33602. The output
voltage adjustment range is from 1 V to 18 V. Figure 14 shows the feedback resistor connections for setting the
output voltage. The recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using
Equation 1. Depending on the output voltage, a feed-forward capacitor, CFF, may be required for optimum
transient performance. Table 1 lists the standard external RFBT and CFF values for several output voltages
between 2.5 V and 18 V. Table 2 lists the values for output voltages below 2.5 V. Additionally, Table 1 and
Table 2 include the recommended switching frequency (FSW), the frequency setting resistor (RRT), and the
minimum and maximum output capacitance for each of the output voltages listed.
For designs with RFBB other than 10 kΩ, adjust CFF and RFBT such that (CFF × RFBT) is unchanged and adjust
RFBT such that (RFBT / RFBB) is unchanged.
space
RFBT
10 u VOUT 1 k:
(1)
VOUT
RFBT
CFF
FB
RFBB
10 k
AGND
Figure 14. Setting the Output Voltage
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Feature Description (continued)
Table 1. Required Component Values (VOUT ≥ 2.5 V)
VOUT (V)
(1)
(2)
(3)
RFBT (kΩ)
(1)
CFF (pF)
fSW (kHz)
RRT (kΩ)
COUT(min) (µF) (2)
COUT(max) (µF) (3)
2.5
15.0
220
250
162
150
400
3.3
23.2
150
300
133
88
300
5
40.2
100
450
88.7
66
200
6
49.9
68
550
71.5
54
160
7.5
64.9
47
650
60.4
40
130
9
80.6
47
700
56.2
36
110
12
110
open
900
44.2
22
80
13.5
124
open
1000
39.2
22
75
15
140
open
1100
35.7
20
65
18
169
open
1200
33.2
16
55
RFBB = 10.0 kΩ.
For output voltages ≥ 2.5 V, the minimum required output capactiance must be comprised of ceramic type and account for DC bias and
temperature derating.
The maximum output capactiance must include the required ceramic COUT(min). Additional capacitance, may be ceramic type, low-ESR
polymer type, or a combination of the two.
Table 2. Required Component Values (VOUT < 2.5 V)
VOUT (V)
1 to 2.5
(1)
RFBT (kΩ) (1)
see Equation 1
CFF (pF)
open
FSW (kHz)
250
RRT (kΩ)
COUT
162
150-µF ceramic +
470-µF polymer
RFBB = 10 kΩ. For VOUT = 1 V, RFBB= open and RFBT = 0 Ω.
7.3.2 Feed-Forward Capacitor, CFF
The LMZM33602 is internally compensated to be stable over the operating frequency and output voltage range.
However, depending on the output voltage, an additional feed-forward capacitor may be required. TI
recommends an external feed-forward capacitor, CFF, be placed in parallel with the top resistor divider, RFBT for
optimum transient performance. The value for CFF can be calculated using Equation 2.
CFF
1000
pF
§
·
8.32
4S ¨
¸ u RFBT
© VOUT u COUT ¹
where
•
•
COUT is the value after derating in µF
RFBT is in kΩ
(2)
Refer to the Table 1 for the recommended CFF value for several output voltages.
7.3.3 Voltage Dropout
Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output
voltage regulation while providing the rated output current.
To ensure the LMZM33602 maintains output voltage regulation at the recommended switching frequency, over
the operating temperature range, the following requirements apply:
For output voltages ≤ 5 V, the minimum VIN is 4 V or (VOUT + 1.5 V), whichever is greater.
For output voltages > 5 V, the minimum VIN is (1.3 × VOUT).
space
However, if fixed switching frequency operation is not required, the LMZM33602 operates in a frequency
foldback mode when the dropout voltage is less than the recommendations above. Frequency foldback reduces
the switching frequency to allow the output voltage to maintain regulation as input voltage decreases. Figure 15
through Figure 20 show typical dropout voltage and frequency foldback curves for 3.3 V, 5 V, and 12 V outputs
at TA = 25°C. (Note: As ambient temperature increases, dropout voltage and frequency foldback occur at higher
input voltage.)
12
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3.4
350
325
3.3
300
3.2
275
250
Frequency (kHz)
Output Voltage (V)
3.1
3.0
2.9
2.8
225
200
175
150
125
2.7
100
Iout
0.5 A
1.0 A
2.0 A
2.6
2.5
3.3
3.4
3.5
3.6
VOUT = 3.3 V
3.7
3.8
Input Voltage (V)
3.9
4.0
4.1
Iout
0.5 A
1.0 A
2.0 A
75
50
3.3
4.2
3.4
3.5
3.6
3.7
D017
fSW = 300 kHz
VOUT = 3.3 V
Figure 15. Voltage Dropout
3.8
3.9
4.0
Input Voltage (V)
4.1
4.2
4.3
4.4
4.5
D018
fSW = 300 kHz
Figure 16. Frequency Foldback
5.4
500
5.2
450
5.0
4.8
400
350
Frequency (kHz)
Output Voltage (V)
4.6
4.4
4.2
4.0
300
250
3.8
3.6
200
3.4
Iout
0.5 A
1.0 A
2.0 A
3.2
3.0
4.0
4.2
4.4
4.6
4.8
VOUT = 5 V
5.0
5.2
5.4
Input Voltage (V)
5.6
5.8
6.0
6.2
Iout
0.5 A
1.0 A
2.0 A
150
100
4.0
6.4
4.3
4.6
4.9
5.2
5.5
5.8
Input Voltage (V)
D019
fSW = 450 kHz
VOUT = 5 V
Figure 17. Voltage Dropout
6.1
6.4
6.7
7.0
D020
fSW = 450 kHz
Figure 18. Frequency Foldback
12.4
1000
12.2
900
12.0
800
11.8
700
11.4
Frequency (kHz)
Output Voltage (V)
11.6
11.2
11.0
10.8
10.6
600
500
400
300
10.4
200
Iout
0.5 A
1.0 A
2.0 A
10.2
10.0
9.8
11.0
11.2
11.4
VOUT = 12 V
11.6
11.8
12.0 12.2 12.4
Input Voltage (V)
12.6
12.8
13.0
fSW = 900 kHz
13.2
Iout
0.5 A
1.0 A
2.0 A
100
13.4
0
11.0
11.5
12.0
D021
VOUT = 12 V
Figure 19. Voltage Dropout
12.5
13.0
13.5
14.0
Input Voltage (V)
14.5
15.0
15.5
16.0
D022
fSW = 900 kHz
Figure 20. Frequency Foldback
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7.3.4 Switching Frequency (RT)
The switching frequency range of the LMZM33602 is 200 kHz to 1.2 MHz. The switching frequency can easily be
set by connecting a resistor (RRT) between the RT pin and AGND. Additionally, the RT pin can be left floating
and the LMZM33602 will operate at 400 kHz default switching frequency. Use Equation 3 to calculate the RRT
value for a desired frequency or simply select from Table 3.
The switching frequency must be selected based on the output voltage setting of the device and the operating
input voltage. See Table 3 for RRT resistor values and the allowable output voltage range for a given switching
frequency for three common input voltages.
RRT
§ 40200
¨¨
© fSW kHz
·
¸¸ 0.6 k:
¹
(3)
Table 3. Switching Frequency vs Output Voltage
14
VIN = 5 V (±5%)
VIN = 12 V (±5%)
VIN = 24 V (±5%)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
MIN
MAX
MIN
MAX
MIN
200
1
3.4
1
5.5
1
6.2
250
158
1
3.5
1
6.2
1
10.6
300
133
1
3.5
1
6.8
1
10.6
350
113
1
3.5
1
7.4
1
10.7
400
100 or
(RT pin open)
1
3.5
1
7.9
1
11.4
450
88.7
1
3.5
1
8.4
1.2
12.1
500
78.7
1
3.5
1
8.9
1.3
12.8
550
71.5
1
3.4
1
9.3
1.4
13.4
600
66.5
1
3.4
1
9.5
1.6
14.1
650
60.4
1
3.4
1
9.4
1.7
14.6
700
56.2
1
3.3
1
9.3
1.8
15.2
750
52.3
1
3.3
1
9.2
2.0
15.8
800
49.9
1
3.3
1
9.1
2.1
16.3
850
46.4
1
3.2
1.1
9.0
2.2
16.8
900
44.2
1
3.2
1.2
9.0
2.3
17.3
950
41.2
1
3.2
1.2
8.9
2.5
17.8
1000
39.2
1
3.1
1.3
8.8
2.6
18
1050
37.4
1
3.1
1.4
8.7
2.7
18
1100
35.7
1
3.1
1.4
8.6
2.9
18
1150
34.0
1
3
1.5
8.5
3
18
1200
33.2
1
3
1.6
8.5
3.1
18
SWITCHING
FREQUENCY
(kHz)
RRT
RESISTOR
(kΩ)
200
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7.3.5 Synchronization (SYNC)
The LMZM33602 switching frequency can also be synchronized to an external clock from 200 kHz to 1.2 MHz.
To implement the synchronization feature, couple an AC signal to the EN/SYNC pin (pin 2) with a peak-to-peak
amplitude of at least 2.8 V, not to exceed 5.5 V. The minimum SYNC clock ON and OFF time must be longer
than 100ns. The AC signal must be coupled through a small capacitor (1 nF) as shown in Figure 21. RENT is
required for this synchronization circuit, but RENB is not required if an external UVLO adjustment is not needed.
Before the external clock is present, or when a valid clock signal is removed, the device works in RT mode and
the switching frequency is set by RRT resistor. Select RRT so that it sets the frequency close to the external
synchronization frequency. When the external clock is present, the SYNC mode overrides the RT mode.
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. Table 3 shows the allowable frequencies for a given range of output voltages. For the most
efficient solution, always select the lowest allowable frequency.
VIN
CSYNC
VIN
RENT
EN/SYNC
1 nF
Clock
Source
RENB
PGND
Figure 21. AC Coupled SYNC Signal
7.3.6 Input Capacitors
The LMZM33602 requires a minimum input capacitance of 9.4 μF (2 × 4.7 μF) of ceramic type. High-quality,
ceramic-type X5R or X7R capacitors with sufficient voltage rating are recommended. TI recommends an
additional 100 µF of non-ceramic capacitance for applications with transient load requirements. The voltage
rating of input capacitors must be greater than the maximum input voltage.
Table 4. Recommended Input Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE
(V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
Murata
X7R
GRM32ER71H475KA88L
50
4.7
2
TDK
X5R
C3225X5R1H106K250AB
50
10
3
Murata
X7R
GRM32ER71H106KA12
50
10
2
TDK
X7R
C3225X7R1H106M250AB
50
10
3
EEHZA1H101P
50
100
28
Panasonic
(1)
(2)
(3)
ZA
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Standard capacitance values
Maximum ESR @ 100 kHz, 25°C.
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7.3.7 Output Capacitors
The LMZM33602 minimum and maximum output capacitance listed in Table 1 and Table 2 represents the
amount of effective capacitance. The effects of DC bias and temperature variation must be considered when
using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material will
contribute to differences between the standard rated value and the actual effective value of the capacitance.
When adding additional capacitance, above COUT(min), the capacitance may be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 5 for a preferred list of output capacitors by vendor.
Table 5. Recommended Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE
(V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
Murata
X7R
GRM32ER71E226KE15L
25
22
2
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X5R
GRM32ER61C476K
16
47
3
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
Murata
X5R
GRM32ER61A107M
10
100
2
Kemet
X5R
C1210C107M4PAC7800
16
100
2
Panasonic
POSCAP
6TPE100MI
6.3
100
18
Panasonic
POSCAP
6TPE150MF
6.3
150
15
Panasonic
POSCAP
10TPF150ML
10
150
15
Panasonic
POSCAP
6TPF220M9L
6.3
220
9
Panasonic
POSCAP
6TPE220ML
6.3
220
12
Panasonic
POSCAP
4TPF330ML
4
330
12
Panasonic
POSCAP
6TPF330M9L
6.3
330
9
Panasonic
POSCAP
6TPE470MAZU
6.3
470
35
(1)
(2)
(3)
16
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Standard capacitance values.
Maximum ESR @ 100 kHz, 25°C.
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7.3.8 Output On/Off Enable (EN)
The voltage on the EN/SYNC pin provides electrical ON/OFF control of the device. Once the EN pin voltage
exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold
voltage, the regulator stops switching and enters low quiescent current state.
The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZM33602 is to
connect the EN pin to VIN directly as shown in Figure 22. This allows self-start-up of the LMZM33602 when VIN
is within the operation range.
If an application requires controlling the EN pin, an external logic signal can be used to drive EN/SYNC pin as
shown in Figure 23. Applications using an open drain/collector device to interface with this pin require a pull-up
resistor to a voltage above the enable threshold.
Figure 24 and Figure 25 show typical turn-ON and turn-OFF waveforms using the enable control.
VIN
VIN
EN/SYNC
EN/SYNC
PGND
PGND
Figure 22. Enabling the Device
Figure 23. Typical Enable Control
Figure 24. Enable Turn-ON
Figure 25. Enable Turn-OFF
7.3.9 Programmable Undervoltage Lockout (UVLO)
The LMZM33602 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.9 V (maximum)
with a typical hysteresis of 300 mV.
If an application requires a higher UVLO threshold, a resistor divider can be placed on the EN/SYNC pin as
shown in Figure 26. Table 6 lists recommended resistor values for RENT and RENB to adjust the ULVO voltage.
To insure proper start-up and reduce input current surges, the UVLO threshold must be set to at least
(VOUT + 1.5 V) for output voltages ≤ 5 V and at least (1.3 × VOUT) for output voltages > 5 V. TI recommends to set
the UVLO threshold to approximately 80% to 85% of the minimum expected input voltage.
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VIN
VIN
RENT
EN/SYNC
RENB
PGND
Figure 26. Adjustable UVLO
Table 6. Resistor Values for Adjusting UVLO
VIN UVLO (V)
6.5
10
15
20
25
30
RENT (kΩ)
100
100
100
100
100
100
RENB (kΩ)
35.7
20.5
12.7
9.31
7.32
6.04
7.3.10 Power Good (PGOOD)
The LMZM33602 has a built in power-good signal (PGOOD) which indicates whether the output voltage is within
its regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage
source of 12 V or less. The maximum recommended PGOOD sink current is 1 mA. A typical pullup resistor value
is between 10 kΩ and 100 kΩ.
Once the output voltage rises above 94% of the set voltage, the PGOOD pin rises to the pullup voltage level.
The PGOOD pin is pulled low when the output voltage drops lower than 92.5% or rises higher than 107% of the
nominal set voltage. See Figure 27 for typical power-good thresholds.
VFB
107%
105.5%
94%
92.5%
PGOOD
High
Low
Figure 27. Power Good Flag
18
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7.3.11 Overcurrent Protection (OCP)
The LMZM33602 is protected from overcurrent conditions. Hiccup mode is activated if a fault condition persists to
prevent overheating. In hiccup mode, the regulator is shut down and kept off for 10 ms typical before the
LMZM33602 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the
fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, and
prevents overheating and potential damage to the device. Once the fault is removed, the module automatically
recovers and returns to normal operation as shown in Figure 29.
Figure 28. Overcurrent Limiting
Figure 29. Removal of Overcurrent
7.3.12 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
170°C typically. The device reinitiates the power up sequence when the junction temperature drops below 155°C
typically.
7.4 Device Functional Modes
7.4.1 Active Mode
The LMZM33602 is in active mode when VIN is above the UVLO threshold and the EN/SYNC pin voltage is
above the EN high threshold. The simplest way to enable the LMZM33602 is to connect the EN/SYNC pin to
VIN. This allows self start-up of the LMZM33602 when the input voltage is in the operation range: 4 V to 36 V. In
active mode, the LMZM33602 is in continuous conduction mode (CCM) with fixed switching frequency.
7.4.2 Shutdown Mode
The EN/SYNC pin provides electrical ON and OFF control for the LMZM33602. When the EN/SYNC pin voltage
is below the EN low threshold, the device is in shutdown mode. In shutdown mode the standby current is 2 μA
typical. The LMZM33602 also employs input UVLO protection. If VIN is below the UVLO level, the output of the
regulator is turned off.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZM33602 is a synchronous, step-down, DC-DC power module. It is used to convert a higher DC voltage
to a lower DC voltage with a maximum output current of 2 A. The LMZM33602 can be configured in an inverting
buck-boost (IBB) topology with the output voltage inverted or negative with respect to ground. For more details,
see TI Application Report Inverting Application for the LMZM33602/03. The following design procedure can be
used to select components for the LMZM33602. Alternately, the WEBENCH® software may be used to generate
complete designs. When generating a design, the WEBENCH® software utilizes an iterative design procedure
and accesses comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Application
The LMZM33602 only requires a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. Figure 30 shows a basic LMZM33602 schematic with only the minimum required
components.
VIN
PGOOD
VIN
VOUT
EN/SYNC
VOUT
CIN
LMZM33602
RFBT
CFF
COUT
FB
RT
PGND
RRT
RFBB
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Figure 30. LMZM33602 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 7 as the input parameters and follow the design
procedures in Detailed Design Procedure.
Table 7. Design Example Parameters
20
DESIGN PARAMETER
VALUE
Input voltage VIN
24 V typical
Output voltage VOUT
5V
Output current rating
2A
Operating frequency
450 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZM33602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LMZM33602 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10.0 kΩ. The value for RFBT can be selected from Table 6 or calculated using Equation 4:
RFBT
10 u VOUT 1 k:
(4)
For the desired output voltage of 5.0 V, the formula yields a value of 40 kΩ. Choose the closest available value
of 40.2 kΩ for RFBT.
8.2.2.3 Feed-Forward Capacitor (CFF)
TI recommends placing an external feed-forward capacitor, CFF in parallel with the top resistor divider, RFBT for
optimum transient performance. The value for CFF can be calculated using Equation 2 or selected from Table 1.
The recommended CFF value for 5-V application is 100 pF.
8.2.2.4 Setting the Switching Frequency
The recommended switching frequency for a 5-V application is 450 kHz. To set the swtiching frequency to
450 kHz, a 88.7-kΩ RRT resistor is required.
8.2.2.5 Input Capacitors
The LMZM33602 requires a minimum input capacitance of 10 µF (or 2 × 4.7 μF) ceramic type. High-quality
ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 100 µF of
non-ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of
input capacitors must be greater than the maximum input voltage.
For this design, a 10-µF, 50-V, ceramic capacitor was selected.
8.2.2.6 Output Capacitor Selection
The LMZM33602 requires a minimum amount of output capacitance for proper operation. The minimum amount
of required output varies depending on the output voltage. See Table 1 for the required output capacitance.
For this design example, four 22 µF, 25 V ceramic capacitors are used.
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8.2.2.7 Application Curves
VIN = 24 V
VOUT = 5 V
COUT = 4 × 22 µF
IOUT = 0.5 A to 1 A
Slew rate: 1 A/µs
VIN = 24 V
Figure 31. Transient Response
VOUT = 5 V
COUT = 4 × 22 µF
Figure 32. Enable Turn-on
9 Power Supply Recommendations
The LMZM33602 is designed to operate from an input voltage supply range between 4 V and 36 V. This input
supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMZM33602 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMZM33602 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 100-µF
electrolytic capacitor.
22
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SNVSAO4C – DECEMBER 2017 – REVISED MARCH 2018
10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
optimal thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 33 thru
Figure 36, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Connect PGND pins 14 and 15 directly to pin 18 using thick copper traces.
• Connect the SW pins together using a small copper island under the device for thermal relief.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Examples
Figure 33. Typical Top-Layer Layout
Figure 34. Typical Layer-2 Layout
Figure 35. Typical Layer 3 Layout
Figure 36. Typical Bottom-Layer Layout
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10.3 Theta JA vs PCB Area
The amount of PCB copper effects the thermal performance of the device. Figure 37 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the LMZM33602. The junction-to-ambient thermal
resistance is plotted for a 2-layer PCB and a 4-layer PCB with PCB area from 16 cm2 to 49 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in the Typical Characteristics section.
2. Calculate the maximum θJA using Equation 5 and the maximum ambient temperature of the application.
(125ÛC ± TA(max))
(ÛC/W)
JA =
PD(max)
(5)
3. Reference Figure 37 to determine the minimum required PCB area for the application conditions.
32
2-layer PCB
4-layer PCB
30
28
Theta JA (°C/W)
26
24
22
20
18
16
15
20
25
30
35
PCB Area (cm²)
40
45
50
ThJA
Figure 37. θJA vs PCB Area
10.4 EMI
The LMZM33602 is compliant with EN55011 Class B radiated emissions. Figure 38, Figure 39, and Figure 40
show typical examples of radiated emissions plots for the LMZM33602. The graphs include the plots of the
antenna in the horizontal and vertical positions.
10.4.1 EMI Plots
EMI plots were measured using the standard LMZM33602EVM with no input filter.
24
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EMI (continued)
Figure 38. Radiated Emissions 24-V Input, 5-V Output, 2-A Load (EN55011 Class B)
Figure 39. Radiated Emissions 24-V Input, 12-V Output, 2-A Load (EN55011 Class B)
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EMI (continued)
Figure 40. Radiated Emissions 12-V Input, 5-V Output, 2-A Load (EN55011 Class B)
10.5 Package Specifications
LMZM33602
Weight
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
26
Submit Documentation Feedback
VALUE
UNIT
0.74
grams
98.0
MHrs
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: LMZM33602
LMZM33602
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SNVSAO4C – DECEMBER 2017 – REVISED MARCH 2018
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZM33602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.3 Related Documentation
For related documentation see the following:
TI Application Report Inverting Application for the LMZM33602/03
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
28
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMZM33602RLRR
B2QFN
RLR
18
500
330.0
24.4
7.35
9.35
4.35
12.0
24.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZM33602RLRR
B2QFN
RLR
18
500
383.0
353.0
58.0
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29
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
LMZM33602RLRR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
B2QFN
RLR
18
500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
RoHS & Green
Call TI
Level-3-250C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
LMZM33602
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
RLR0018A
B3QFN - 4.1 mm max height
SCALE 1.300
PLASTIC QUAD FLATPACK - NO LEAD
A
7.15
6.85
B
PIN 1 INDEX AREA
9.15
8.85
4.1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.551
(0.255) TYP
2X
EXPOSED
THERMAL PAD
PKG
10
8
36X 0.5
(0.2) TYP
7
11
2X 3.48 0.05
6
2X
7.5
PKG
2X 0.77 0.05
5
2X 1.6
0.05
12
46X
15
1
18
PIN 1 ID
(OPTIONAL)
0.3
0.2
0.1
0.05
C A B
0.6
TYP
0.4
2X 1.33
2X 0.105
2X 1
4223378/C 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RLR0018A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X
(0.45)
12X (0.7)
PKG
(0.75)
2X (1.6)
4X (0.595)
METAL UNDER
SOLDER MASK
TYP
(0.5) TYP
SOLDER MASK
OPENING
TYP
18
(4.35)
(4.33) TYP
15
4X (0.62)
1
(3.8)
(3.42) TYP
2X (3.48)
46X (0.25)
( 0.2) VIA
TYP
(2.51) TYP
12
0.05 MIN
TYP
(1.6) TYP
(0.69) TYP
PKG
5
0.000
(0.175) TYP
(0.825) TYP
(0.15) TYP
11
(R0.05) TYP
(1.6) TYP
6
(2.51) TYP
7X (0.25)
10
7
(3.42) TYP
(3.8)
4X (3.935)
(4.33) TYP
(4.35)
(3.35)
4X (2.947)
(2.45)
(1.405) TYP
(0.505) TYP
(0.76)
0.000
(0.395) TYP
(1.295) TYP
(2.195) TYP
(3.35)
8
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 12X
4223378/C 05/2018
NOTES: (continued)
4. This package designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RLR0018A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
16X (0.71)
(0.04)
(0.83)
16X (0.67)
6X (0.29)
5X (0.7)
8X (0.265)
18
(4.568)
(4.35)
(3.875)
15
1
46X (0.25)
2X (3.75)
(2.965)
(2.055)
EXPOSED METAL
TYP
12
(1.145)
5
(R0.05) TYP
0.000 PKG
(1.145)
11
(0.25) TYP
6
(2.055)
4X (0.585)
(2.965)
7
10
8
(3.35)
2X (3.568)
2X (2.775)
4X (2.943)
2X (0.395)
7X (0.7)
2X (0.895)
2X (2.775)
4X (0.61)
2X (3.568)
(3.35)
EXPOSED
METAL
TYP
2X (3.75)
4X (3.93)
(4.35)
2X (4.568)
SOLDER MASK EDGE
TYP
0.000 PKG
2X (0.105)
METAL UNDER
SOLDER MASK
TYP (3.875)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 8 & 18:
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4223378/C 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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