Texas Instruments | LMR14010A 4-V to 40-V, 1-A Step-Down Converter With High Efficiency Eco-mode | Datasheet | Texas Instruments LMR14010A 4-V to 40-V, 1-A Step-Down Converter With High Efficiency Eco-mode Datasheet

Texas Instruments LMR14010A 4-V to 40-V, 1-A Step-Down Converter With High Efficiency Eco-mode Datasheet
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LMR14010A
SLUSD87 – MARCH 2018
LMR14010A 4-V to 40-V, 1-A Step-Down Converter With High Efficiency Eco-mode™
1 Features
3 Description
•
The LMR14010A is a PWM DC-to-DC buck (stepdown) regulator. With a wide input range from 4 V to
40 V, it is suitable for a wide range of applications
from industrial to automotive. An ultra-low 1-µA
shutdown current prolongs battery life. Operating
frequency is fixed at 0.7 MHz, allowing the use of
small external components while minimizing output
ripple voltage. Soft-start and compensation circuits
are implemented internally, limiting the number of
external components.
Input Voltage Range: 4 V to 40 V with Transient
Protection to 45 V
0.7-MHz Switching Frequency
Ultra-High Efficiency at Light Load with Ecomode™
Low Dropout Operation
Output Current up to 1 A
Precision Enable Input
Overcurrent Protection
Internal Compensation
Internal Soft-Start
Small Overall Solution Size (TSOT-6L Package)
Create a Custom Design Using the LMR14010A
With the WEBENCH® Power Designer
1
•
•
•
•
•
•
•
•
•
•
The LMR14010A is optimized for up to 1-A load
current. It has a 0.765-V nominal feedback voltage.
The device has built-in protection features such as
pulse-by-pulse current limit, thermal sensing and
shutdown due to excessive power dissipation. The
LMR14010A is available in a low profile TSOT-6L
package (2.9 mm × 1.6 mm × 0.85 mm).
2 Applications
•
•
•
•
Device Information(1)
Smart Meters
Appliances
Elevators and Escalators
Cameras
Simplified Schematic
VIN
VIN
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMR14010A
TSOT-6L
2.9 mm x 1.6 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Efficiency vs. Current
(ƒSW= 0.7 MHz, VIN = 12 V, VOUT = 3.3 V)
CB
Cboot
L1
Cin
100
SW
SHDN
Cout
LMR14010A
90
D1
R1
80
FB
R2
Copyright © 2018, Texas Instruments Incorporated
Efficiency (%)
GND
70
60
50
40
30
20
0.1
1
10
Output Current (mA)
100
1000
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR14010A
SLUSD87 – MARCH 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration...................................................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2018
*
Initial release.
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5 Pin Configuration
DDC Package
(TOP VIEW)
CB
1
GND
2
FB
3
PIN 1 ID
6
SW
5
VIN
4
SHDN
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CB
1
I
SW FET gate bias voltage. Connect Cboot capacitor between CB and SW.
FB
3
I
Feedback Pin. Set feedback voltage divider ratio with VOUT = VFB
(1+(R1/R2)).
GND
2
G
Ground connection.
SHDN
4
I
Enable and disable input pin(high voltage tolerant). Internal pull-up current
source. Pull below 1.25 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
SW
6
O
Switch node. Connect to inductor, diode and Cboot capacitor.
VIN
5
I
Power input voltage pin. Input for internal supply and drain node input for
internal high-side MOSFET.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VIN to GND
–0.3
45
V
SHDN to GND
–0.3
45
V
FB to GND
–0.3
7
V
CB to SW
–0.3
7
V
SW to GND
–1
45
V
SW to GND less than 30ns transients
–2
45
V
Storage temperature range, Tstg
–55
165
°C
Operating junction temperature, TJ
–0
150
°C
Input Voltages
Output Voltages
(1)
Stresses at or beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
Vin
MIN
MAX
4
40
CB
Buck regulator
UNIT
46
CB to SW
SW
6
–0.7
40
FB
0
5
Control
SHDN
0
40
Temperature
Operating junction temperature, TJ
–40
125
V
°C
6.4 Thermal Information
LMR14010A
THERMAL METRIC (1)
SOT (DDC)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
102
RθJC(top)
Junction-to-case (top) thermal resistance
36.9
ψJB
Junction-to-board characterization parameter
28.4
(1)
4
°C/W
All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to
JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution, number
of thermal vias, board size, ambient temperature, and air flow.
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6.5 Electrical Characteristics
VIN = 12V, SHDN = VIN, TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT POWER SUPPLY
VIN
Operating input voltage
Shutdown supply current
Undervoltage lockout thresholds
IQ
4
EN = 0 V
1
Rising
Falling
40
V
3
µA
4
V
3
V
ECO mode, no load, VIN = 12 V, not
switching
30
µA
SHDN AND UVLO
Rising SHDN Threshold Voltage
SHDN PIN current
1.05
1.25
1.38
V
SHDN = 2.3 V
–4.2
µA
SHDN = 0.9 V
–1
µA
–3
µA
500
mΩ
Hysteresis current
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, CB to SW = 5.8 V
(1)
tON-MIN
95
DMAX
: Maximum duty cycle (1)
VFB
: Feedback voltage
ns
96%
0.74
0.765
0.79
V
850
kHz
CURRENT LIMIT
Current limit threshold
ƒSW
VIN = 12 V
Switching frequency
1500
550
700
mA
THERMAL PERFORMANCE
TSHUTDOW
Thermal shutdown trip point (1)
170
°C
10
°C
N
THYS
(1)
(1)
Hysteresis
Specified by design.
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6.6 Typical Characteristics
Unless otherwise noted, VIN = 12 V, L = 22 µH, COUT = 22 µF, TA = 25°C
100
100
Vin=15V
90
Vin=12V
90
Vin=18V
80
Efficiency (%)
Efficiency (%)
80
70
60
60
50
50
40
40
30
Vin=15V
70
30
1
10
100
1000
Output Current (mA)
ƒSW = 0.7 MHz
1
10
VOUT = 12 V
ƒSW = 0.7 MHz
Figure 1. Efficiency vs Load Current
1000
C002
VOUT = 5 V
Figure 2. Efficiency vs Load Current
1.5%
100
ECO
Input Current (uA)
1.0%
Output Voltage Change
100
Output Current (mA)
C001
0.5%
0.0%
-0.5%
10
Shutdown
1
-1.0%
-1.5%
0.1
0
200
400
600
Load Current (mA)
VIN = 18 V
VOUT = 12 V
Figure 3. Load Regulation
6
800
1000
4
14
24
Input Voltage (V)
C004
34
44
C005
VOUT = 5 V
Figure 4. Supply Current vs Input Voltage (No Load)
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7 Detailed Description
7.1 Overview
The LMR14010A device is a 40-V, 1-A step-down (buck) regulator. The buck regulator has a very low-quiescent
current during the light load to prolong the battery life.
The LMR14010A improves performance during line and load transients by implementing a constant frequency,
current mode control which reduces output capacitance and simplifies frequency compensation design. The
LMR14010A reduces the external component count by integrating the boot recharge diode. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The boot capacitor voltage is
monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset
threshold. The LMR14010A can operate at high duty cycles because of the boot UVLO and small refresh FET.
The output voltage can be stepped down to as low as the 0.765-V reference. Internal soft start is featured to
minimize inrush currents.
7.2 Functional Block Diagram
VIN
Leading Edge
Blanking
Bootstrap
Regulator
CB
Logic &
PWM Latch
HS
Driver
Frequency
Shift
PWM
Comparator
SW
±
+
COMP
+
EA +
±
Main OSC
SHDN
Bandgap
Ref
0.765V
SS
FB
™
Slope
Compensation
GND
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7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The LMR14010A operates at a fixed frequency, and it implements peak current mode control. The output voltage
is compared through external resistors on the FB pin to an internal voltage reference by an error amplifier which
drives the internal COMP node. An internal oscillator initiates the turn on of the high side power switch. The error
amplifier output is compared to the high side power switch current. When the power switch current reaches the
level set by the internal COMP voltage, the power switch is turned off. The internal COMP node voltage will
increase and decrease as the output current increases and decreases. The device implements a current limit by
clamping the COMP node voltage to a maximum level.
7.3.2 Bootstrap Voltage (CB)
The LMR14010A has an integrated boot regulator, and requires a small ceramic capacitor between the CB and
SW pins to provide the gate drive voltage for the high side MOSFET. The CB capacitor is refreshed when the
high side MOSFET is off and the low side diode conducts.
To improve drop out, the LMR14010A is designed to operate at 96% duty cycle as long as the CB to SW pin
voltage is greater than 3.2 V. When the voltage from CB to SW drops below 3.2 V, the high-side MOSFET is
turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the CB
capacitor. Since the supply current sourced from the CB capacitor is low, the high-side MOSFET can remain on
for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching
regulator is high.
Attention must be taken in maximum duty cycle applications with light load. To ensure SW can be pulled to
ground to refresh the CB capacitor, an internal circuit will charge the CB capacitor when the load is light or the
device is working in dropout condition.
7.3.3 Setting the Output Voltage
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the
front page schematic. The feedback pin voltage 0.765 V, so the ratio of the feedback resistors sets the output
voltage according to the following equation: VOUT = 0.765 V (1+(R1/R2)). Typically R2 will be given as 1 kΩ to
100 kΩ for a starting value. To solve for R1 given R2 and VOUT uses R1 = R2 ((VOUT/0.765 V) – 1).
7.3.4 Enable (SHDN ) and VIN Undervoltage Lockout
The LMR14010A SHDN pin is a high-voltage tolerant input with an internal pull-up circuit. The device can be
enabled even if the SHDN pin is floating. The regulator can also be turned on using 1.25-V or higher logic
signals. If the use of a higher voltage is desired due to system or other constraints it may be used. A 100-kΩ or
larger resistor is recommended between the applied voltage and the SHDN pin to protect the device. When
SHDN is pulled down to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown
mode the supply current will be decreased to approximately 1 µA. If the shutdown function is not to be used, the
SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin should not exceed 40 V.
The LMR14010A has an internal UVLO circuit to shutdown the output if the input voltage falls below an internally
fixed UVLO threshold level. This ensures that the regulator is not latched into an unknown state during low input
voltage conditions. The regulator will power up when the input voltage exceeds the UVLO voltage level. If there
is a requirement for a higher UVLO voltage, the SHDN can be used to adjust the input voltage UVLO by using
external resistors.
7.3.5 Current Limit
The LMR14010A implements current mode control which uses the internal COMP voltage to turn off the high
side MOSFET on a cycle by cycle basis. Each cycle the switch current and internal COMP voltage are
compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP node
high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch
current limit.
8
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Feature Description (continued)
7.3.6 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C
typical. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the
thermal trip threshold. Once the junction temperature decreases below 160°C typical, the device reinitiates the
power-up sequence.
7.4 Device Functional Modes
7.4.1 Continuous Conduction Mode
The LMR14010A steps the input voltage down to a lower output voltage. In continuous conduction mode (when
the inductor current never reaches zero at steady state), the buck regulator operates in two cycles. The power
switch is connected between VIN and SW. In the first cycle of operation the transistor is closed and the diode is
reverse biased. Energy is collected in the inductor, the load current is supplied by COUT and the current through
the inductor is rising. During the second cycle the transistor is open and the diode is forward biased due to the
fact that the inductor current cannot instantaneously change direction. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined approximately as: D = VOUT/VIN and D' = (1-D) where D is the duty cycle of the switch,
D and D' will be required for design calculations.
7.4.2 Eco-mode™
The LMR14010A operates in Eco-mode™ at light-load currents to improve efficiency by reducing switching and
gate drive losses. For Eco-mode™ operation, the LMR14010A senses peak current, not average or load current,
so the load current where the device enters Eco-mode™ is dependent on VIN, VOUT and the output inductor
value. When the load current is low and the output voltage is within regulation, the device enters Eco-mode™
(see Figure 12) and draws only 28-µA input quiescent current.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMR14010A is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 1 A. The following design procedure can be used to select
components for the LMR14010A. This section presents a simplified discussion of the design process.
8.2 Typical Application
VIN
VIN
CB
Cin
2.2µF/50V
Cboot
100nF
SW
SHDN
L1
22µH
5V, 1A
LMR14010A
D1
GND
R1
54.9k
Cout
22µF
C1out (optional)
100µF
FB
R2
10k
Copyright © 2018, Texas Instruments Incorporated
Figure 5. LMR14010A Application Circuit, 5-V Output
8.2.1 Design Requirements
8.2.1.1 Step-By-Step Design Procedure
This example details the design of a high-frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level:
PARAMETER
VALUE
Input voltage, VIN
9 V to 16 V, typical 12 V
Output voltage, VOUT
5.0 V ± 3%
Maximum output current example IO_max
1A
Minimum output current example IO_min
0.1 A
Transient response 0.03 A to 0.6 A
5%
Output voltage ripple
1%
Switching frequency fSW
Target during load transient
10
700 kHz
Overvoltage peak value
106% of output voltage
Undervoltage value
91% of output voltage
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR14010A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Inductor Selection
The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The
inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages. Since the
ripple current increases with the input voltage, the maximum input voltage is always used to determine the
inductance. Equation 1 is used to calculate the minimum value of the output inductor, where KIND is ripple current
percentage. A reasonable value is setting the ripple current to be 30% (KIND) of the DC output current. For this
design example, the minimum inductor value is calculated to be 16.4 µH, and a nearest standard value was
chosen: 22 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings
not be exceeded. The RMS and peak inductor current can be found from Equation 3 and Equation 4. The
inductor ripple current is 0.22 A, and the RMS current is 1 A. As the equation set demonstrates, lower ripple
currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. A good
starting point for most applications is 22 μH with a 1.6-A current rating. Using a rating near 1.6 A will enable the
LMR14010A to current limit without saturating the inductor. This is preferable to the LMR14010A going into
thermal shutdown mode and the possibility of damaging the inductor if the output is shorted to ground or other
long-term overload.
Vin max Vout
Vout
Lo min
u
I o u K IND
Vin max u f sw
(1)
I ripple
I L-RMS
IL
peak
Vout u (Vin max
Vout )
Vin max u Lo u f sw
(2)
1
I ripple2
12
(3)
I o2
Io
I ripple
2
(4)
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8.2.2.3 Output Capacitor Selection
The selection of COUT is mainly driven by three primary considerations. The output capacitor will determine the
modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The
output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The regulator usually needs two or
more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty
cycle to react to the change. The output capacitance must be large enough to supply the difference in current for
2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 5 shows the
minimum output capacitance necessary to accomplish this. For this example, the transient load response is
specified as a 3% change in Vout for a load step from 0.1 A to 1 A (full load). For this example, ΔIOUT = 1 - 0.1 =
0.9 A and ΔVOUT = 0.03 × 5 = 0.15 V. Using these numbers gives a minimum capacitance of 17.1 µF. For
ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and
tantalum capacitors have higher ESR that should be taken into account.
The stored energy in the inductor will produce an output voltage overshoot when the load current rapidly
decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning
from a high load current to a lower load current. Equation 6 is used to calculate the minimum capacitance to
keep the output voltage overshoot to a desired value. Where L is the value of the inductor, IOH is the output
current under heavy load, IOL is the output under light load, Vf is the final peak output voltage, and Vi is the initial
capacitor voltage. For this example, the worst case load step will be from 1 A to 0.1 A. The output voltage will
increase during this load transition and the stated maximum in our specification is 3 % of the output voltage. This
will make Vo_overshoot = 1.03 × 5 = 5.15 V. Vi is the initial capacitor voltage which is the nominal output voltage
of 5 V. Using these numbers in Equation 6 yields a minimum capacitance of 14.3 µF.
Equation 7 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vo_ripple is the maximum allowable output voltage ripple, and IL_ripple is
the inductor ripple current. Equation 7 yields 0.26 µF.
Equation 8 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 8 indicates the ESR should be less than 680 mΩ. Additional capacitance de-ratings for
aging, temperature and dc bias should be factored in which will increase this minimum value. For this example,
22 µF ceramic capacitors will be used. Capacitors in the range of 4.7 µF to 100 µF are a good starting point with
an ESR of 0.7 Ω or less.
2 u 'I out
Cout !
fsw u 'Vout
(5)
Cout ! Lo u
Cout
RESR
( Ioh2
(Vf
2
Iol 2 )
Vi 2 )
1
(6)
1
!
u
8 u fsw Vo _ ripple
I L _ ripple
(7)
Vo _ ripple
I L _ ripple
(8)
8.2.2.4 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the
target application, the current rating for the diode should be equal to the maximum output current for best
reliability in most applications. In cases where the input voltage is not much greater than the output voltage the
average diode current is lower. In this case it is possible to use a diode with a lower average current rating,
approximately (1-D) × IOUT, however the peak current rating should be higher than the maximum load current. A
1-A to 2-A rated diode is a good starting point.
12
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8.2.2.5 Input Capacitor Selection
A low ESR ceramic capacitor is needed between the VIN pin and ground pin. This capacitor prevents large
voltage transients from appearing at the input. Use a 1-µF to 10-µF value with X5R or X7R dielectric. Depending
on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is
applied. Consult with the capacitor manufactures data sheet for information on capacitor derating over voltage
and temperature. The capacitor must also have a ripple current rating greater than the maximum input current
ripple of the LMR14010A. The input ripple current can be calculated using below Equations.
For this example design, one 2.2-µF, 50-V capacitor is selected. The input capacitance value determines the
input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the
design example values, IOUTMAX = 1 A, CIN = 2.2 µF, ƒSW = 700 kHz, yields an input voltage ripple of 162 mV and
an rms input ripple current of 0.5 A.
I cirms
'Vin
I out u
(Vin min Vout )
Vout
u
Vin min
Vin min
(9)
I out max u 0.25
Cin u fsw
(10)
8.2.2.6 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor or larger is recommended for the bootstrap capacitor (Cboot). For applications where
the input voltage is close to output voltage a larger capacitor is recommended, generally 0.1 µF to 1 µF to ensure
plenty of gate drive for the internal switches and a consistently low RDSON. A ceramic capacitor with an X7R or
X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics
over temperature and voltage.
Below are the recommended typical output voltage inductor/capacitor combinations for optimized total solution
size.
P/N
VOUT (V)
R1 (kΩ)
R2 (kΩ)
L (µH)
COUT (µF)
LMR14010A
5
54.9 (1%)
10 (1%)
22
22
LMR14010A
5.7
64.9 (1%)
10 (1%)
22
22
LMR14010A
12
147 (1%)
10 (1%)
22
10
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8.2.3 Application Performance Curves
Unless otherwise noted, VIN = 12 V, L = 22 µH, COUT = 22 µF, TA = 25°C
VOUT (50 mV/DIV, AC coupled)
VOUT (10 mV/DIV, AC coupled)
VSW (5 V/DIV)
IINDUCTOR (500 mA/DIV)
Time (1 µs/DIV)
Time (800 µs/DIV)
Figure 6. Switching Node and Output Voltage
Waveform (VIN = 12 V, VOUT = 5 V, ILoad = 1 A)
Figure 7. Load Transient Between 0.1 A and 1 A
(VIN= 12 V, VOUT = 5 V)
VSHND (5 V/DIV)
VSHND (5 V/DIV)
VOUT (10 V/DIV)
VOUT (10 V/DIV)
VSW (10 V/DIV)
VSW (10 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (1 A/DIV)
Time (400 µs/DIV)
Time (400 µs/DIV)
Figure 8. Start-up Waveform
(VIN = 18 V, VOUT= 12 V, ILoad= 800 mA)
Figure 9. Shutdown Waveform
(VIN = 18 V, VOUT = 12 V, ILoad= 800 mA)
VSHND (5 V/DIV)
VSHND (5 V/DIV)
VOUT (5 V/DIV)
VOUT (5 V/DIV)
VSW (10 V/DIV)
VSW (10 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (1 A/DIV)
Time (200 µs/DIV)
Time (100 µs/DIV)
Figure 10. Start-Up Waveform
(VIN = 12 V, VOUT = 5 V, ILoad = 800 mA)
14
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Figure 11. Shutdown Waveform
(VIN = 12 V, VOUT = 5 V, ILoad= 800 mA)
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Unless otherwise noted, VIN = 12 V, L = 22 µH, COUT = 22 µF, TA = 25°C
VOUT (20 mV/DIV, AC coupled)
IINDUCTOR (100 mA/DIV)
VSW (5 V/DIV)
Time (200 µs/DIV)
Figure 12. Eco-mode™ Operation (VIN = 12 V, VOUT = 5 V, No Load)
9 Power Supply Recommendations
The LMR14010A is designed to operate from an input voltage supply range between 4 V and 40 V. This input
supply should be able to withstand the maximum input current and maintain a voltage above 4 V. The resistance
of the input supply rail should be low enough that an input current transient does not cause a high enough drop
at the LMR14010A supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the LMR14010A, additional bulk capacitance may be required in
addition to the ceramic input capacitors.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistors R1 and R2, should be kept close to the FB pin, and away from the inductor
to minimize coupling noise into the feedback pin.
2. The input capacitor CIN must be placed close to the VIN pin. This will reduce copper trace inductance which
effects input voltage ripple of the device.
3. The inductor L1 should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor COUT should be placed close to the junction of L1 and the diode D1. The L1, D1 and
COUT trace should be as short as possible to reduce conducted and radiated noise.
5. The ground connection for the diode, CIN and COUT should be tied to the system ground plane in only one
spot (preferably at the COUT ground point) to minimize conducted noise in the system ground plane.
10.2 Layout Example
Figure 13. LMR14010A Layout Example
16
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR14010A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMR14010ADDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1N72
LMR14010ADDCT
ACTIVE
SOT-23-THIN
DDC
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1N72
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2018
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
SCALE 4.000
SOT
3.05
2.55
1.75
1.45
PIN 1
INDEX AREA
1.1 MAX
B
1
0.1 C
A
6
4X 0.95
3.05
2.75
1.9
4
3
0.5
0.3
0.2
0.1
TYP
0.0
6X
0 -8 TYP
0.20
TYP
0.12
C A B
C
SEATING PLANE
0.6
TYP
0.3
0.25
GAGE PLANE
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
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EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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