Texas Instruments | LM5113-Q1 Automotive 90-V, 1.2-A, 5-A, Half Bridge GaN Driver (Rev. B) | Datasheet | Texas Instruments LM5113-Q1 Automotive 90-V, 1.2-A, 5-A, Half Bridge GaN Driver (Rev. B) Datasheet

Texas Instruments LM5113-Q1 Automotive 90-V, 1.2-A, 5-A, Half Bridge GaN Driver (Rev. B) Datasheet
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LM5113-Q1
SNVSAR1B – MARCH 2017 – REVISED MARCH 2018
LM5113-Q1 Automotive 90-V, 1.2-A, 5-A, Half Bridge GaN Driver
1 Features
3 Description
•
•
The LM5113-Q1 is designed to drive both the highside and the low-side enhancement mode Gallium
Nitride (GaN) FETs or silicon MOSFETs in a
synchronous buck, boost, or half bridge configuration
for automotive applications. The device has an
integrated 100-V bootstrap diode and independent
inputs for the high-side and low-side outputs for
maximum control flexibility. The high-side bias
voltage is internally clamped at 5.2 V, which prevents
the gate voltage from exceeding the maximum gatesource voltage rating of enhancement mode GaN
FETs. The inputs of the device are TTL-logic
compatible, which can withstand input voltages up to
14 V regardless of the VDD voltage. The LM5113-Q1
has split-gate outputs, providing flexibility to adjust
the turnon and turnoff strength independently.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C6
Independent High-Side and Low-Side
TTL Logic Inputs
1.2-A Peak Source, 5-A Peak Sink Output Current
High-Side Floating Bias Voltage Rail
Operates up to 100-VDC
Internal Bootstrap Supply Voltage Clamping
Split Outputs for Adjustable
Turnon and Turnoff Strength
0.6-Ω Pulldown, 2.1-Ω Pullup Resistance
Fast Propagation Times (28 ns Typical)
Excellent Propagation Delay Matching
(1.5 ns Typical)
Supply Rail Undervoltage Lockout
Low Power Consumption
In addition, the strong sink capability of the LM5113Q1 maintains the gate in the low state, preventing
unintended turnon during switching. The LM5113-Q1
can operate up to several MHz. The LM5113-Q1 is
available in a standard 10-pin WSON package with
an exposed pad to aid power dissipation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
LM5113-Q1
•
•
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Mobile Wireless Chargers
Audio Power Amplifiers
Audio Power Supplies
Current-Fed Push-Pull Converters
Half- and Full-Bridge Converters
Synchronous Buck Converters
WSON (10)
4.00 mm × 4.00 mm
Simplified Application Diagram
0.1 F
VIN
HB
HOH
VDD
HOL
1 F
Input
Filter 1
HI LM5113-Q1 HS
Input
Filter 2
LI
Load
LOH
LOL
EP
VSS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5113-Q1
SNVSAR1B – MARCH 2017 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2017) to Revision B
Page
•
Changed data sheet title from: LM5113-Q1 Automotive 90V, 1.2A/5A, Half Bridge GaN Driver to: LM5113-Q1
Automotive 90-V, 1.2-A, 5-A, Half Bridge GaN Driver............................................................................................................ 1
•
Added input filter references to Simplified Application Diagram............................................................................................. 1
•
Added EXT HI and EXT LO references to the Functional Block Diagram ........................................................................... 11
•
Changed the last paragraph and add new images to the Input and Output section ........................................................... 11
Changes from Original (March 2017) to Revision A
Page
•
Changed data sheet title from: LM5113-Q1 Automotive 80V, 1.2A/5A, Half Bridge GaN Driver to: LM5113-Q1
Automotive 90V, 1.2A/5A, Half Bridge GaN Driver ................................................................................................................ 1
•
Changed the Simplified Application Diagram ......................................................................................................................... 1
•
Changed the Functional Block Diagram ............................................................................................................................... 11
•
Added content to the Input and Output section.................................................................................................................... 11
•
Added content to the Start-up and UVLO section ................................................................................................................ 12
2
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5 Pin Configuration and Functions
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
VDD
1
10 LOH
HB
2
9
LOL
HOH
3
8
VSS
HOL
4
7
LI
HS
5
6
HI
Thermal Pad
Pin Functions
PIN
NO.
NAME
TYPE
(1)
DESCRIPTION
1
VDD
P
5-V positive gate drive supply: locally decouple to VSS using low-ESR/ESL capacitor
located as close as possible to the IC.
2
HB
P
High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor
to HB and the negative terminal to HS. The bootstrap capacitor must be placed as close to
the IC as possible.
3
HOH
O
High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnon speed.
4
HOL
O
High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnoff speed.
5
HS
P
High-side GaN FET source connection: connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN FET.
6
HI
I
High-side driver control input. The LM5113-Q1 inputs have TTL type thresholds. Unused
inputs must be tied to ground and not left open.
7
LI
I
Low-side driver control input. The LM5113-Q1 inputs have TTL type thresholds. Unused
inputs must be tied to ground and not left open.
8
VSS
G
Ground return: all signals are referenced to this ground.
9
LOL
O
Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
10
LOH
O
Low-side gate driver source-current output: connect to the gate of high-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
EP
—
—
Exposed pad: TI recommends that the exposed pad on the bottom of the package be
soldered to ground plane on the printed-circuit board to aid thermal dissipation.
(1)
I = Input, O = Output, G = Ground, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD to VSS
–0.3
7
V
HB to HS
–0.3
7
V
LI or HI input
–0.3
15
V
LOH, LOL output
–0.3
VDD + 0.3
V
HOH, HOL output
VHS – 0.3
VHB + 0.3
V
HS to VSS
–5
93
V
HB to VSS
0
100
V
150
°C
150
°C
Operating junction temperature
Storage temperature, Tstg
(1)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±1000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
LI or HI input
NOM
MAX
UNIT
4.5
5.5
V
0
14
V
HS
–5
90
V
HB
VHS + 4
VHS + 5.5
HS slew rate
Operating junction temperature
–40
V
50
V/ns
125
°C
6.4 Thermal Information
LM5113-Q1
THERMAL METRIC (1)
DPR (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
37.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.8
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
14.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
LI = HI = 0 V
IDDO
VDD operating current
f = 500 kHz
IHB
Total HB quiescent current
LI = HI = 0 V
IHBO
Total HB operating current
f = 500 kHz
IHBS
HB to VSS quiescent current
HS = HB = 90 V
IHBSO
HB to VSS operating current
f = 500 kHz
TJ = 25°C
0.07
TJ = –40°C to 125°C
0.1
TJ = 25°C
2
TJ = –40°C to 125°C
3
TJ = 25°C
0.08
TJ = –40°C to 125°C
0.1
TJ = 25°C
1.5
TJ = –40°C to 125°C
2.5
TJ = 25°C
0.1
TJ = –40°C to 125°C
10
TJ = 25°C
0.4
TJ = –40°C to 125°C
1
mA
mA
mA
mA
µA
mA
INPUT PINS
VIR
Input voltage threshold
Rising edge
VIF
Input voltage threshold
Falling edge
VIHYS
Input voltage hysteresis
RI
Input pulldown resistance
TJ = 25°C
TJ = –40°C to 125°C
2.06
1.89
TJ = 25°C
TJ = –40°C to 125°C
2.18
1.66
1.48
1.76
400
TJ = 25°C
100
V
mV
200
TJ = –40°C to 125°C
V
300
kΩ
UNDERVOLTAGE PROTECTION
VDDR
VDD rising threshold
VDDH
VDD threshold hysteresis
VHBR
HB rising threshold
VHBH
HB threshold hysteresis
TJ = 25°C
3.8
TJ = –40°C to 125°C
3.2
4.5
0.2
TJ = 25°C
V
3.2
TJ = –40°C to 125°C
2.5
V
3.9
0.2
V
V
BOOTSTRAP DIODE
VDL
Low-current forward voltage
IVDD-HB = 100 µA
VDH
High-current forward voltage
IVDD-HB = 100 mA
RD
Dynamic resistance
IVDD-HB = 100 mA
HB-HS clamp regulation voltage
(1)
TJ = 25°C
0.45
TJ = –40°C to 125°C
0.65
TJ = 25°C
0.90
TJ = –40°C to 125°C
1
TJ = 25°C
1.85
TJ = –40°C to 125°C
3.60
TJ = 25°C
TJ = –40°C to 125°C
5.2
4.7
5.45
V
V
Ω
V
Parameters that show only a typical value are ensured by design and may not be tested in production.
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Electrical Characteristics (continued)
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW- AND HIGH-SIDE GATE DRIVER
TJ = 25°C
0.06
VOL
Low-level output voltage
IHOL = ILOL = 100 mA
VOH
High-level output voltage
VOH = VDD – LOH
or VOH = HB – HOH
IHOH = ILOH = 100 mA
IOHL
Peak source current
HOH, LOH = 0 V
IOLL
Peak sink current
HOL, LOL = 5 V
IOHLK
High-level output leakage current
HOH, LOH = 0 V
TJ = –40°C to 125°C
1.5
µA
IOLLK
Low-level output leakage current
HOL, LOL = 5 V
TJ = –40°C to 125°C
1.5
µA
MAX
UNIT
TJ = –40°C to 125°C
V
0.10
TJ = 25°C
0.21
TJ = –40°C to 125°C
V
0.31
1.2
A
5
A
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tLPHL
LO turnoff propagation delay
LI falling to LOL falling
tLPLH
LO turnon propagation delay
LI rising to LOH rising
tHPHL
HO turnoff propagation delay
HI falling to HOL falling
tHPLH
HO turnon propagation delay
HI rising to HOH rising
tMON
Delay matching
LO on and HO off
TJ = 25°C
tMOFF
Delay matching
LO off and HO on
TJ = 25°C
tHRC
HO rise time (0.5 V – 4.5 V)
CL = 1000 pF
tLRC
LO rise time (0.5 V – 4.5 V)
tHFC
HO fall time (0.5 V – 4.5 V)
tLFC
LO fall time (0.5 V – 4.5 V)
tPW
Minimum input pulse width
that changes the output
tBS
Bootstrap diode
reverse recovery time
6
MIN
TJ = 25°C
TYP
26.5
TJ = –40°C to 125°C
TJ = 25°C
45
28.0
TJ = –40°C to 125°C
TJ = 25°C
45
26.5
TJ = –40°C to 125°C
TJ = 25°C
45
28
TJ = –40°C to 125°C
45.0
1.5
TJ = –40°C to 125°C
8
1.5
TJ = –40°C to 125°C
8
ns
ns
ns
ns
ns
ns
7
ns
CL = 1000 pF
7
ns
CL = 1000 pF
3.5
ns
CL = 1000 pF
3.5
ns
10
ns
40
ns
IF = 100 mA, IR = 100 mA
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LI
LI
HI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 1. Timing Diagram
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6.7 Typical Characteristics
8
Figure 2. Peak Source Current vs Output Voltage
Figure 3. Peak Sink Current vs Output Voltage
Figure 4. IDDO vs Frequency
Figure 5. IHBO vs Frequency
Figure 6. IDD vs Temperature
Figure 7. IHB vs Temperature
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Typical Characteristics (continued)
Figure 8. UVLO Rising Thresholds vs Temperature
Figure 9. UVLO Falling Thresholds vs Temperature
Figure 10. Input Thresholds vs Temperature
Figure 11. Input Threshold Hysteresis vs Temperature
Figure 12. Bootstrap Diode Forward Voltage
Figure 13. Propagation Delay vs Temperature
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Typical Characteristics (continued)
Note: Unless otherwise specified, VDD = VHB = 5 V,
VSS = VHS = 0 V.
Figure 14. LO and HO Gate Drive – High/Low Level
Output Voltage vs Temperature
10
Figure 15. HB Regulation Voltage vs Temperature
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7 Detailed Description
7.1 Overview
The LM5113-Q1 is a high-frequency, high- and low- side gate driver for enhancement mode Gallium Nitride
(GaN) FETs in a synchronous buck, boost, or half bridge configuration. The high-side bias voltage is generated
using a bootstrap technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding
the maximum gate-source voltage rating of enhancement mode GaN FETs. The LM5113-Q1 has split-gate
outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
The LM5113-Q1 can operate up to several MHz, and is available in a standard 10-pin WSON package that
contains an exposed pad to aid power dissipation.
7.2 Functional Block Diagram
HB
UVLO
& CLAMP
HOH
HOL
LEVEL
SHIFT
EXT HI
HS
HI
VDD
UVLO
EXT LI
LOH
LOL
LI
VSS
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7.3 Feature Description
7.3.1 Input and Output
The input pins of the LM5113-Q1 are independently controlled with TTL input thresholds and can withstand
voltages up to 12 V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs
of an analog PWM controller with up to 12-V power supply, eliminating the need for a buffer stage
The output pulldown and pullup resistance of LM5113-Q1 is optimized for enhancement mode GaN FETs to
achieve high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance
turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup
resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113Q1 offer flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either
the turnon path, the turnoff path, or both.
If the input signal for either of the two channels, HI or LI, is not used, the control pin must be tied to either VDD
or VSS. These inputs must not be left floating.
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Feature Description (continued)
Additionally, the input signals avoid pulses shorter than 3 ns by using the input filter to the HI and LI input pins.
The values and part numbers of the circuit components are shown in the Figure 16.
EXT HI
1k
HI
22 pF
Figure 16. Input Filter 1 (High-Side Input Filter)
If short pulses or short delays are required, the circuit in Figure 17 is recommended.
SN74LVC2G32YZP
HI
EXT HI
100 k
50 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Input Filter 1 for Short Pulses (High-Side Input Filter)
7.3.2 Start-Up and UVLO
The LM5113-Q1 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored to prevent the GaN FETs
from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and HOL
low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the UVLO
threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid
chattering.
The startup voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present
thereafter.
The LM5113-Q1 requires an external bootstrap diode with a 100 Ω series resistor from VDD to HB to charge the
high side supply on a cycle by cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or
LL4148.
Table 1. VDD UVLO Feature Logic Operation
12
CONDITION (VHB-HS > VHBR for all cases below)
HI
LI
HO
LO
VDD – VSS < VDDR during device start-up
H
L
L
L
VDD – VSS < VDDR during device start-up
L
H
L
L
VDD – VSS < VDDR during device start-up
H
H
L
L
VDD – VSS < VDDR during device start-up
L
L
L
L
VDD – VSS < VDDR – VDDH after device start-up
H
L
L
L
VDD – VSS < VDDR – VDDH after device start-up
L
H
L
L
VDD – VSS < VDDR – VDDH after device start-up
H
H
L
L
VDD – VSS < VDDR – VDDH after device start-up
L
L
L
L
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Table 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VDD > VDDR for all cases below)
HI
LI
HO
LO
VHB-HS < VHBR during device start-up
H
L
L
L
VHB-HS < VHBR during device start-up
L
H
L
H
VHB-HS < VHBR during device start-up
H
H
L
H
VHB-HS < VHBR during device start-up
L
L
L
L
VHB-HS < VHBR – VHBH after device start-up
H
L
L
L
VHB-HS < VHBR – VHBH after device start-up
L
H
L
H
VHB-HS < VHBR – VHBH after device start-up
H
H
L
H
VHB-HS < VHBR – VHBH after device start-up
L
L
L
L
7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is
usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on
HS pin. Moreover, this negative voltage transient may become even more pronounces due to the effects of board
layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap
configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side
GaN FET. The LM5113-Q1 solves this problem with an internal clamping circuit that prevents the bootstrap
voltage from exceeding 5.2 V typical.
7.3.4 Level Shift
The level-shift circuit is the interface from the high-side input to the high-side driver stage, which is referenced to
the switch node (HS). The level shift allows control of the HO output, which is referenced to the HS pin and
provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around
1.5 ns.
7.4 Device Functional Modes
Table 3 shows the device truth table.
Table 3. Truth Table
HI
LI
HOH
HOL
LOH
L
L
Open
L
Open
LOL
L
L
H
Open
L
H
Open
H
L
H
Open
Open
L
H
H
H
Open
H
Open
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current
levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation
is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which
cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive
voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer-drive
circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also address other needs such as minimizing the effect of high-frequency switching noise
(by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate-charge power losses from the controller into the driver.
The LM5113-Q1 is a MHz high- and low-side gate driver for enhancement mode GaN FETs in a synchronous
buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique
and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the maximum gate-source
voltage rating of enhancement mode GaN FETs. The LM5113-Q1 has split gate outputs with strong sink
capability, providing flexibility to adjust the turnon and turnoff strength independently.
14
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J3
VIN
C30
0.01 F
GND
GND
C16
220 pF
R2
100k
±1%
C3
2.2 F
2.2 F
C17
NU
2.2 F
R17
7.50k
GND
C31
0.1 F
R7
33.2k
R3
150k
2.2 F
2.2 F
C32
1 F
C18
0.1 F
R4
±1%
49.9
CS1
4
3
3
LM5025
15
¬ SYNC COMP
14
¬ RT
TIME
6 REF
AGND
7
VCC PGND
5
13
11
10
GND
ON/OFF
GND
GND
GND
4
R15
4.02k
BYP
U1 LP2982AIM5-5.0
5
1
OUT
IN
8
2
¬ RAMP OUTA ¬
12
¬ SS
OUTB ¬9
CS2
C19
1 F
VIN
U4
D1
TP1
EX VCC
MBR130T1G
16
¬ UVLO
1
GND
TP4
2.2 F
C7
GND
C6
C5
2
0R
NU
R14
D4
0R
R11
NU
D3
C20
100 pF
GND
C8
0.1 uF
C27
NU
C28
NU
C24
1 F
6.3V
GND
C21
2.2 F
5V
C9
0.01 uF
LI
HS
10
4
3
5
LM5113
LOL 9
LOH
HOL
GND
8 VSS
7
6 HI
HOH
0.1 F
HB
U3
1 VDD
2
C25
11
9
7
5
3
1
0
R18
R9
2R
R10
0R
Q1
EPC2001
10
8
6
4
2
D5
21.0k
R19
L1
GND
C26
1 F
MBR130T1G
D2
SER1360-272KL
2.7 H
MBR130T1G
1N4148W-7-F
D6
Q2
EPC2001
1
3
5
7
9
11
2
4
6
8
10
C4
TP3
C13
NU
1
1500 pF
C23
C14
1 uF
GND
3
4
R8
C12
22 F
GND
R16
21.0k
U2
LM8261M5
16.9k
330 pF
C22
GND
+ C1
330 F
5
2
C2
¬
Product Folder Links: LM5113-Q1
¬
Copyright © 2017–2018, Texas Instruments Incorporated
EP
¬
¬
VIN
+
-
J1
C29
1 F
C15
1.5 nF
R5
374
R13
6.98k
R6
21.0k
GND
TP2
R1
10.0
GND
C11
1 F
TP5
C10
22 F
VOUT
J4
VOUT
10V
J2
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SNVSAR1B – MARCH 2017 – REVISED MARCH 2018
LM5113-Q1
8.2 Typical Application
The circuit in Figure 18 shows a synchronous buck converter to evaluate the LM5113-Q1 device. Detailed
synchronous buck converter specifications are listed in Design Requirements. The active clamping voltage mode
controller LM5025 is used for close-loop control and generates the PWM signals of the buck switch and the
synchronous switch. For more information, see Figure 18.
Input 15 V to 60 V, output 10 V, 800 kHz
Figure 18. LP5113-Q1 Application Circuit
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Typical Application (continued)
8.2.1 Design Requirements
Table 4 lists the design requirements for the typical application.
Table 4. Design Parameters
PARAMETER
SPECIFICATION
Input operating range
15 – 60 V
Output voltage
10 V
Output current, 48-V input
10 A
Output current, 60-V input
7A
Efficiency at 48 V, 10 A
>90%
Frequency
800 kHz
8.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LM5113-Q1 in a synchronous buck converter with
enhancement mode GaN FET. Refer to Figure 18 for component names and network locations. For additional
design help, see Figure 18.
8.2.2.1 VDD Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
QgH QgL Qrr
CVDD !
'V
where
•
•
•
QgH and QgL are gate charge of the high-side and low-side transistors, respectively.
Qrr is the reverse recovery charge of the bootstrap diode, which is typically around 4 nC.
ΔV is the maximum allowable voltage drop across the bypass capacitor.
(1)
TI recommends a 0.1-µF or larger value, good quality, ceramic capacitor. The bypass capacitor must be placed
as close as possible to the pins of the ICto minimize the parasitic inductance.
8.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB UVLO circuit,
and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 2.
QgH IHB u tON Qrr
CBST !
'V
where
•
•
IHB is the quiescent current of the high-side driver.
ton is the maximum on-time period of the high-side transistor.
(2)
A good-quality, ceramic capacitor must be used for the bootstrap capacitor. TI recommends placement of the
bootstrap capacitor as close as possible to the HB and HS pin.
16
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8.2.2.3 Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It must be kept below the maximum power-dissipation limit of the package at
the operating temperature. The total power dissipation of the LM5113-Q1 is the sum of the gate driver losses and
the bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as:
P
CLoadH
2
CLoadL u VDD
u fSW
where
•
CLoadH and CLoadL are the high-side and the low-side capacitive loads, respectively.
(3)
It can also be calculated with the total input gate charge of the high-side and the low-side transistors as:
P
QgH
QgL u VDD u fSW
(4)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. Figure 19 shows the measured gate-driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. This plot can be used to
approximate the power losses due to the gate drivers.
Gate-driver power dissipation (LO+HO), VDD = +5 V
Figure 19. Neglecting Bootstrap Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger
capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
Figure 20 and Figure 21 show the forward bias power loss and the reverse bias power loss of the bootstrap
diode, respectively. The plots are generated based on calculations and lab measurements of the diode reverse
time and current under several operating conditions. The plots can be used to predict the bootstrap diode power
loss under different operating conditions.
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The load of high-side driver is a GaN FET with total gate charge of
10 nC.
Figure 20. Forward Bias Power Loss of
Bootstrap Diode VIN = 50 V
The load of high-side driver is a GaN FET with total gate charge of
10 nC.
Figure 21. Reverse Recovery Power Loss of
Bootstrap Diode VIN = 50 V
The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as Equation 5.
(TJ - TA)
P=
TJA
(5)
8.2.3 Application Curves
Conditions:
Input Voltage = 48 V DC, Load Current = 5 A
Traces:
Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V
Bottom Trace: LI of LM5113-Q1, Volt/div = 5 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 0.2 µs/div
Figure 22. Low-Side Driver Input and Output
18
Conditions:
Input Voltage = 48 V DC,
Load Current = 10 A
Traces:
Trace: Switch-Node Voltage, Volts/div = 20 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 50 ns/div
Figure 23. Switch-Node Voltage
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9 Power Supply Recommendations
The recommended bias supply voltage range for LM5113-Q1 is from 4.5 V to 5.5 V. The lower end of this range
is governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit. TI
recommends keeping proper margin to allow for transient voltage spikes while not violating the LM5113-Q1
absolute maximum VDD voltage rating and the GaN transistor gate breakdown voltage limit.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the VDD
power supply output must be smaller than the hysteresis specification of LM5113-Q1 UVLO to avoid triggering
device shutdown.
A local bypass capacitor must be placed between the VDD and VSS pins. This capacitor must be located as
close as possible to the device. A low-ESR, ceramic surface-mount capacitor is recommended. TI recommends
using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high frequency filtering
placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-μF, for IC bias
requirements.
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10 Layout
10.1 Layout Guidelines
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast
switching speed. The induced high dv/dt and di/dt, coupled with a low gate-threshold voltage and limited
headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum
performance. Following are some recommendations.
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the GaN FETs gate into a minimal physical area. This decreases the loop inductance and
minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs must be placed close to the
driver.
2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass
capacitor, and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through
the bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop length and area on the circuit board is important to
ensure reliable operation.
3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to
the respective source of the high-side and low-side transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form an
LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to
damp the ringing.
5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping
guideline number 1 above (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to
place the VDD decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the PC board
as the driver. The inductance of vias can impose excessive ringing on the IC pins.
6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing lowESR ceramic capacitors adjacent to the GaN FETs.
Figure 24 and Figure 25 show recommended layout patterns for the 10-pin WSON package. Two cases are
considered: (1) Without any gate resistors, and (2) with an optional turnon gate resistor. Note that 0402 surface
mount package is assumed for the passive components in Figure 24 and Figure 25.
Bootstrap
Capacitor
HO
To Hi-Side FET
To Hi-Side FET
HS
2
3
4
5
VDD 1
HB
HS
2
3
4
5
VDD 1
HB
HS
HO
HS
HOL
Bootstrap
Capacitor
HOH
10.2 Layout Example
Bypass
Capacitor
Bypass
Capacitor
9
10
LOL
LOH
LI
To Low-Side FET
8 VSS
7
HI
LOH
6
10
LOL
LI
9
7
HI
8 VSS
6
LO
GND
LO
To Low-Side FET
GND
Figure 24. 10-Pin WSON Without Gate Resistors
20
Figure 25. 10-Pin WSON With HOH and LOH Gate
Resistors
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SNVSAR1B – MARCH 2017 – REVISED MARCH 2018
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see:
AN-2149 LM5113 Evaluation Board (SNVA484)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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21
PACKAGE OPTION ADDENDUM
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17-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM5113QDPRRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
DPR
10
4500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
L5113Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5113-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jan-2018
• Catalog: LM5113
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM5113QDPRRQ1
Package Package Pins
Type Drawing
WSON
DPR
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
4500
330.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.3
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5113QDPRRQ1
WSON
DPR
10
4500
367.0
367.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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