Texas Instruments | LMR23630-Q1 SIMPLE SWITCHER® 36-V, 3-A Synchronous Step-Down Converter (Rev. B) | Datasheet | Texas Instruments LMR23630-Q1 SIMPLE SWITCHER® 36-V, 3-A Synchronous Step-Down Converter (Rev. B) Datasheet

Texas Instruments LMR23630-Q1 SIMPLE SWITCHER® 36-V, 3-A Synchronous Step-Down Converter (Rev. B) Datasheet
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LMR23630-Q1
SNVSAR6B – DECEMBER 2016 – REVISED MARCH 2018
LMR23630-Q1 SIMPLE SWITCHER® 36-V, 3-A Synchronous Step-Down Converter
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification:
– SOIC and WSON With RT — Level C4B
– WSON With PGOOD — Level C5
4-V to 36-V Input Range
3-A Continuous Output Current
Minimum Switch-On Time: 60 ns
Internal Compensation for Ease of Use
400 kHz Switching Frequency and Adjustable
Switching Frequency Options
PFM and Forced PWM Mode Options at Light
Load
Frequency Synchronization to External Clock
75-µA Quiescent Current at No Load for PFM
Option
Power-Good Option
Soft Start into a Prebiased Load
High Duty-Cycle Operation Supported
Output Short-Circuit Protection With Hiccup Mode
8-Pin HSOIC and 12-Pin WSON Wettable Flank
with PowerPAD™ Package Options
Create a Custom Design Using the LMR23630-Q1
With the WEBENCH® Power Designer
•
•
Automotive Infotainment: Clusters, Head Unit,
Heads-Up Display
USB Charging
General Off-Battery Power Applications
space
3 Description
The LMR23630-Q1 SIMPLE SWITCHER® is an easyto-use 36-V, 3-A synchronous step-down regulator.
With a wide input range from 4 V to 36 V, the device
is suitable for various applications from industrial to
automotive for power conditioning from unregulated
sources. Peak-current-mode control is employed to
achieve simple control-loop compensation and cycleby-cycle current limiting. A quiescent current of 75 μA
makes it suitable for battery powered systems.
Internal loop compensation means that the user is
free from the tedious task of loop compensation
design. This also minimizes the external components.
The device has option for constant frequency FPWM
mode to achieve small output voltage ripple at light
load. An extended family is available in 1-A
(LMR23610-Q1), 1.5-A (LMR23615-Q1), and 2.5-A
(LMR23625-Q1) load current options in pin-to-pin
compatible package which allows simple, optimum
PCB layout. A precision enable input allows
simplification of regulator control and system power
sequencing. Protection features include cycle-bycycle current limit, hiccup-mode short-circuit
protection, and thermal shutdown due to excessive
power dissipation.
Device Information(1)
PART NUMBER
LMR23630-Q1
PACKAGE
BODY SIZE (NOM)
HSOIC (8)
4.90 mm × 3.90 mm
WSON (12)
3.00 mm × 3.00 mm
(1) For detail part numbers for all available different options, see
the orderable addendum at the end of the data sheet.
Simplified Schematic
Efficiency vs Load, VIN = 12 V, PFM Option
VIN up to 36 V
100
CIN
VIN
90
BOOT
CBOOT
AGND
L
VOUT
SW
RFBT
COUT
VCC
FB
Efficiency (%)
EN/SYNC
80
70
60
RFBB
50
CVCC
VOUT = 5 V
VOUT = 3.3 V
PGND
40
0.0001
0.001
0.01
0.1
IOUT (A)
1
10
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR23630-Q1
SNVSAR6B – DECEMBER 2016 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Product Portfolio....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 19
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Examples................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Custom Design With WEBENCH® Tools .............
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2017) to Revision B
Page
•
Added the word "Wettable" in 12-Pin WSON ......................................................................................................................... 1
•
Removing Automotive Battery Regulation, Industrial Power Supply, Telecom and Datacom Systems and reworded
Applications ........................................................................................................................................................................... 1
•
Deleted "preview" from WSON content for release to market; editorial updates to format.................................................... 1
•
Updating the the drawing title for Pin Configurations and Functions for WSON with RT and WSON with PGOOD ............ 3
•
Corrected the column title for WSON with RT and WSON with PGOOD ............................................................................. 3
•
Updating the ESD Ratings to include both SOIC and WSON packages ............................................................................... 4
•
Changing from EN Pin to EN/SYNC Pin ............................................................................................................................... 5
•
Added WSON only on the Electrical Characteristic table for PGOOD ................................................................................... 5
•
Changing the minimum value for VPG_OV from 105% to 104% .............................................................................................. 5
•
Adding a row for WSON Peak and Valley inductor current limit ............................................................................................ 6
•
Changed the min and max for minimum adjustable frequency from 180kHz and 220kHz to 150kHz and 250kHz .............. 7
•
Changed the min,typ, and max values for maximum adjustable frequency from 1980kHz,2200kHz, and 2420kHz to
1750kHz,2150kHz and 2425kHz ............................................................................................................................................ 7
Changes from Original (December 2016) to Revision A
•
2
Page
Changed the ESD HBM rating to ±2000 from ±2500 ............................................................................................................. 4
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SNVSAR6B – DECEMBER 2016 – REVISED MARCH 2018
5 Product Portfolio
PACKAGE
SOIC (8)
WSON (12) (Pin 6 is RT)
WSON (12) (Pin 6 is PGOOD)
PART NUMBER
FIXED 400 kHz
ADJUSTABLE FREQUENCY
POWER GOOD
FPWM
LMR23630AQDDARQ1
Yes
No
No
No
LMR23630AFQDDARQ1
Yes
No
No
Yes
LMR23630QDRRRQ1
No
Yes
No
No
LMR23630FQDRRRQ1
No
Yes
No
Yes
LMR23630APQDRRRQ1
Yes
No
Yes
No
6 Pin Configuration and Functions
DDA Package
8-Pin SOIC With PowerPAD
Top View
SW
1
BOOT
2
VCC
FB
Thermal
Pad
9
3
4
DRR Package
12-Pin WSON With RT and Thermal Pad
Top View
8
PGND
7
VIN
6
AGND
5
DRR Package
12-Pin WSON With PGOOD and Thermal
Pad
Top View
SW
1
12
PGND
SW
1
12
PGND
SW
2
11
NC
SW
2
11
NC
BOOT
3
10
VIN
BOOT
3
10
VIN
VCC
4
9
VIN
FB
5
8
EN/SYNC
6
7
AGND
PAD
13
PAD
13
VCC
4
9
VIN
FB
5
8
EN/SYNC
RT
6
7
AGND
EN/SYNC
PGOOD
Pin Functions
PIN
SOIC
WSON
With
PGOOD
WSON
With RT
I/O (1)
SW
1
1, 2
1, 2
P
Switching output of the regulator. Internally connected to both power MOSFETs.
Connect to power inductor.
BOOT
2
3
3
P
Boot-strap capacitor connection for high-side driver. Connect a high-quality, 100-nF
capacitor from BOOT to SW.
VCC
3
4
4
P
Internal bias supply output for bypassing. Connect a 2.2-μF, 16-V or higher
capacitance bypass capacitor from this pin to AGND. Do not connect external
loading to this pin. Never short this pin to ground during operation.
FB
4
5
5
A
Feedback input to regulator, connect the midpoint of feedback resistor divider to this
pin.
RT
N/A
N/A
6
A
Connect a resistor RT from this pin to AGND to program switching frequency. Leave
floating for 400-kHz default switching frequency.
PGOOD
N/A
6
N/A
A
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to
logic rail or other DC voltage no higher than 12 V.
EN/SYNC
5
8
8
A
Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not
float. Adjust the input undervoltage lockout with two resistors. The internal oscillator
can be synchronized to an external clock by coupling a positive pulse into this pin
through a small coupling capacitor. See Enable/Synchronization for details.
AGND
6
7
7
G
Analog ground pin. Ground reference for internal references and logic. Connect to
system ground.
VIN
7
9, 10
9, 10
P
Input supply voltage.
PGND
8
12
12
G
Power ground pin, connected internally to the low side power FET. Connect to
system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as
short as possible.
PAD
9
13
13
G
Low impedance connection to AGND. Connect to PGND on PCB. Major heat
dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
N/A
11
11
N/A
NAME
NC
(1)
DESCRIPTION
Not for use. Leave this pin floating.
A = Analog, P = Power, G = Ground.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) (1)
PARAMETER
Input voltages
MIN
MAX
VIN to PGND
–0.3
42
EN/SYNC to AGND
–5.5
VIN + 0.3
FB to AGND
–0.3
4.5
RT to AGND
–0.3
4.5
PGOOD to AGND
–0.3
15
AGND to PGND
–0.3
0.3
–1
VIN + 0.3
SW to PGND
SW to PGND less than 10-ns transients
UNIT
V
-5
42
BOOT to SW
–0.3
5.5
VCC to AGND
–0.3
4.5 (2)
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Output voltages
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In shutdown mode, the VCC to AGND maximum value is 5.25 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM) for SOIC (1)
±2000
Human-body model (HBM) for WSON with RT or
PGOOD
±2500
Charged-device model (CDM) for SOIC
±1000
Charged-device model (CDM) for WSON with RT
±1000
Charged-device model (CDM) for WSON with PGOOD
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)
VIN
Input voltage
Input current
EN/SYNC
(1)
MIN
MAX
4
36
–5
36
FB
–0.3
1.2
PGOOD
–0.3
12
PGOOD pin current
UNIT
V
0
1
mA
Output voltage, VOUT
1
28
V
Output current, IOUT
0
3
A
–40
125
°C
Operating junction temperature, TJ
(1)
4
Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For specified specifications, see Electrical Characteristics.
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7.4 Thermal Information
LMR23630-Q1
THERMAL METRIC (1) (2)
DDA (SOIC)
DRR (WSON)
8 PINS
12 PINS
UNIT
42.0
41.5
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
5.9
0.3
°C/W
RθJB
Junction-to-board thermal resistance
23.4
16.5
°C/W
ψJT
Junction-to-top characterization parameter
45.8
39.1
°C/W
ψJB
Junction-to-board characterization parameter
3.6
3.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
23.4
16.3
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Determine power rating at a specific ambient temperature TA with a maximum junction temperature (TJ) of 125°C, which is illustrated in
Recommended Operating Conditions section.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY (VIN PIN)
VIN
Operation input voltage
4
36
Rising threshold
3.3
3.7
3.9
Falling threshold
2.9
3.3
3.5
2
4
VIN_UVLO
Undervoltage lockout thresholds
ISHDN
Shutdown supply current
VEN = 0 V, VIN = 12 V, TJ = –40°C to
125°C
IQ
Operating quiescent current (nonswitching)
VIN = 12 V, VFB = 1.1 V, TJ = –40°C to
125°C, PFM mode
75
V
V
μA
μA
ENABLE (EN/SYNC PIN)
VEN_H
Enable rising threshold voltage
VEN_HYS
Enable hysteresis voltage
VWAKE
Wake-up threshold
IEN
1.4
1.55
1.7
0.4
V
0.4
VIN = 4 V to 36 V, VEN= 2 V
Input leakage current at EN pin
V
V
10
VIN = 4 V to 36 V, VEN= 36 V
100
nA
1
μA
VOLTAGE REFERENCE (FB PIN)
VREF
Reference voltage
ILKG_FB
Input leakage current at FB pin
VIN = 4 V to 36 V, TJ = 25°C
VIN = 4 V to 36 V, TJ = –40°C to 125°C
0.985
1
1.015
0.98
1
1.02
VFB= 1 V
10
V
nA
POWER GOOD (PGOOD PIN) WSON Only
VPG_OV
Power-good flag overvoltage tripping
threshold
% of reference voltage
VPG_UV
Power-good flag undervoltage tripping
threshold
% of reference voltage
VPG_HYS
Power-good flag recovery hysteresis
% of reference voltage
Minimum VIN for valid PGOOD output
50 μA pullup to PGOOD pin, VEN = 0 V, TJ
= 25°C
1.5
50 μA pullup to PGOOD pin, VIN = 1.5 V,
VEN = 0 INV
0.4
0.5 mA pullup to PGOOD pin, V =13.5 V,
VEN = 0 V
0.4
VIN_PG_MIN
VPG_LOW
PGOOD low level output voltage
104%
107%
110%
92%
94%
96.5%
1.5%
V
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL LDO (VCC PIN)
VCC
Internal LDO output voltage
4.1
VCC_UVLO
VCC undervoltage lockout thresholds
V
Rising threshold
2.8
3.2
3.6
Falling threshold
2.4
2.8
3.2
HSOIC package
3.8
5
6.2
WSON package
4
5.5
6.6
HSOIC package
2.9
3.6
4.6
WSON package
2.9
3.6
4.2
V
CURRENT LIMIT
IHS_LIMIT
Peak inductor current limit
ILS_LIMIT
Valley inductor current limit
IL_ZC
Zero cross current limit
IL_NEG
Negative current limit (FPWM option)
–0.04
–2.7
–2
A
A
A
–1.3
A
INTEGRATED MOSFETS
RDS_ON_HS
High-side MOSFET ON-resistance
RDS_ON_LS
Low-side MOSFET ON-resistance
HSOIC package, VIN = 12 V, IOUT = 1 A
185
WSON package, VIN = 12 V, IOUT = 1 A
160
HSOIC package, VIN = 12 V, IOUT = 1 A
105
WSON package, VIN = 12 V, IOUT = 1 A
95
mΩ
mΩ
THERMAL SHUTDOWN
TSHDN
Thermal shutdown threshold
THYS
Hysteresis
162
170
178
15
°C
°C
7.6 Timing Characteristics
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
HICCUP MODE
NOC (1)
Number of cycles that LS current limit is tripped
to enter Hiccup mode
TOC
Hiccup retry delay time
Cycle
s
64
SOIC package
5
WSON package
ms
10
SOFT START
Internal soft-start time. The time of internal
reference to increase from 0 V to 1 V
TSS
SOIC package
WSON package
1
2
6
3
ms
POWER GOOD
TPGOOD_RISE
Power-good flag rising transition deglitch delay
150
μs
TPGOOD_FALL
Power-good flag falling transition deglitch delay
18
μs
(1)
6
Specified by design.
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7.7 Switching Characteristics
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
90
UNIT
SW (SW PIN)
TON_MIN
Minimum turnon time
60
TOFF_MIN (1)
Minimum turnoff time
100
ns
ns
OSCILLATOR (RT and EN/SYNC PIN)
fSW_DEFAULT
Oscillator default frequency
Fixed frequency option or RT pin open
circuit
340
400
460
kHz
fADJ
Minimum adjustable frequency
RT = 198 kΩ with 1% accuracy
150
200
250
kHz
Maximum adjustable frequency
RT = 17.8 kΩ with 1% accuracy
1750
2150
2425
kHz
fSYNC
SYNC frequency range
200
2200
kHz
VSYNC
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
2.8
5.5
TSYNC_MIN
Minimum sync clock ON- and OFF-time
(1)
100
V
ns
Specified by design.
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7.8 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25°C.
60
50
40
PFM, VIN = 12 V
PFM, VIN = 24 V
PFM, VIN = 36 V
FPWM, VIN = 12 V
FPWM, VIN = 24 V
FPWM, VIN = 36 V
30
20
10
0
1E-5
0.0001
0.001
fSW = 400 kHz
0.01
IOUT (A)
0.1
1
60
50
40
PFM, VIN = 12 V
PFM, VIN = 24 V
PFM, VIN = 36 V
FPWM, VIN = 12 V
FPWM, VIN = 24 V
FPWM, VIN = 36 V
30
20
10
0
1E-5
10
0.0001
VOUT = 5 V
fSW = 400 kHz
90
90
80
80
70
70
60
50
40
PFM, VIN = 12 V
PFM, VIN = 24 V
PFM, VIN = 36 V
FPWM, VIN = 12 V
FPWM, VIN = 24 V
FPWM, VIN = 36 V
30
20
10
0.0001
0.001
fSW = 200 kHz
(Sync)
0.01
IOUT (A)
0.1
1
0.1
1
10
D002
VOUT = 3.3 V
60
50
40
PFM, VIN = 12 V
PFM, VIN = 24 V
PFM, VIN = 36 V
FPWM, VIN = 12 V
FPWM, VIN = 24 V
FPWM, VIN = 36 V
30
20
10
0
1E-5
10
0.0001
0.001
D003
VOUT = 5 V
fSW = 200 kHz
(Sync)
Figure 3. Efficiency vs Load Current
0.01
IOUT (A)
0.1
1
10
D004
VOUT = 3.3 V
Figure 4. Efficiency vs Load Current
5.015
5.09
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
5.08
5.07
5.06
5.01
5.05
VOUT (V)
VOUT (V)
0.01
IOUT (A)
Figure 2. Efficiency vs Load Current
100
Efficiency (%)
Efficiency (%)
Figure 1. Efficiency vs Load Current
100
0
1E-5
0.001
D001
5.04
5.03
5.005
5.02
5.01
5
5
4.99
0
0.5
PFM Option
1
1.5
IOUT (A)
2
VOUT = 5 V
2.5
3
0
FPWM Option
Figure 5. Load Regulation
8
0.5
D004
1
1.5
IOUT (A)
2
2.5
3
D005
VOUT = 5 V
Figure 6. Load Regulation
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25°C.
5.5
3.6
5
4.5
VOUT (V)
VOUT (V)
3.3
4
2.7
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
3.5
3
4
4.5
5
VIN (V)
5.5
3
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
2.4
3.3
6
3.5
3.7
D006
VOUT = 5 V
4.1
4.3
4.5
D007
VOUT = 3.3 V
Figure 7. Dropout Curve
Figure 8. Dropout Curve
3.67
VIN UVLO Rising Threshold (V)
80
75
IQ (µA)
3.9
VIN (V)
70
65
60
-50
0
50
Temperature (°C)
VIN = 12 V
100
3.66
3.65
3.64
3.63
3.62
3.61
-50
150
0
D008
50
Temperature (°C)
100
150
D009
VFB = 1.1 V
Figure 9. IQ vs Junction Temperature
Figure 10. VIN UVLO Rising Threshold vs Junction
Temperature
5.5
0.425
5
Current Limit (A)
VIN UVLO Hysteresis (V)
LS Limit
HS Limit
0.42
0.415
4.5
4
3.5
0.41
-50
0
50
Temperature (°C)
100
150
3
-50
0
D010
50
Temperature (°C)
100
150
D011
VIN = 12 V
Figure 11. VIN UVLO Hysteresis vs Junction Temperature
Figure 12. HS and LS Current Limit vs Junction
Temperature
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8 Detailed Description
8.1 Overview
The LMR23630-Q1 SIMPLE SWITCHER® regulator is an easy-to-use synchronous step-down DC/DC converter
operating from 4-V to 36-V supply voltage. The device is capable of delivering up to 3-A DC load current with
good thermal performance in a small solution size. For both SOIC and WSON packages, an extended family is
available in multiple current options from 1-A to 3-A in pin-to-pin compatible packages.
The LMR23630-Q1 employs constant-frequency peak-current-mode control. The device enters PFM mode at
light load to achieve high efficiency. A user-selectable FPWM option is provided to achieve low output voltage
ripple, tight output voltage regulation, and constant switching frequency. The device is internally compensated,
which reduces design time and requires few external components. The switching frequency is fixed 400 kHz. For
the option which has an RT pin, the switching frequency is adjustable from 200 kHz to 2.2 MHz. Also, the
LMR23630-Q1 is capable of synchronization to an external clock within the range of 200 kHz to 2.2 MHz.
Additional features such as precision enable, power-good flag, and internal soft start provide a flexible and easyto-use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC
undervoltage lockout, cycle-by-cycle current limit, and hiccup-mode short-circuit protection.
The family requires very few external components and has a pinout designed for simple, optimum PCB layout.
8.2 Functional Block Diagram
VCC
EN/SYNC
SYNC Signal
SYNC
Detector
VCC
Enable
LDO
VIN
Precision
Enable
Internal
SS
CBOOT
HS I Sense
EA
REF
Rc
TSD
UVLO
Cc
(PGOOD)
PWM CONTROL LOGIC
PFM
Detector
OV/UV
Detector
SW
FB
Slope
Comp
Freq
Foldback
AGND
Zero
Cross
HICCUP
Detector
SYNC Signal
(RT)
Oscillator
LS I Sense
FB
PGND
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8.3 Feature Description
8.3.1 Fixed-Frequency Peak-Current-Mode Control
The following operating description of the LMR23630-Q1 refers to the Functional Block Diagram and to the
waveforms in Figure 13. LMR23630-Q1 is a step-down synchronous buck regulator with integrated high-side
(HS) and low-side (LS) switches (synchronous rectifier). The LMR23630-Q1 supplies a regulated output voltage
by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON-time, the
SW pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT)
/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of
a buck converter is defined as duty cycle D = tON / TSW, where tON is the high-side switch ON-time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
SW Voltage
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
Inductor Current
iL
TSW
ILPK
IOUT
'iL
t
0
Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The LMR23630-Q1 employs fixed-frequency peak-current-mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load
condition, the LMR23630-Q1 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode
for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM option).
8.3.2 Adjustable Frequency
For adjustable switching frequency option of LMR23630-Q1. The switching frequency can be programmed by the
impedance RT from the RT pin to ground. The frequency is inversely proportional to the RT resistance. The RT
pin can be left floating, and the LMR23630-Q1 will operate at 400-kHz default switching frequency. The RT pin is
not designed to be shorted to ground. For a desired requency, typical RT resistance can be found by Equation 1.
Table 1 gives typical RT values for a given fSW.
RT(kΩ) = 40200 / fSW(kHz) – 0.6
(1)
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Feature Description (continued)
250
RT Resistance (kŸ)
200
150
100
50
0
0
500
1000
1500
2000
Switching Frequency (kHz)
2500
C008
Figure 14. RT vs Frequency Curve
Table 1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
200
200
350
115
500
78.7
750
53.6
1000
39.2
1500
26.1
2000
19.6
2200
17.8
8.3.3 Adjustable Output Voltage
A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating
temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI
recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the lowside resistor RFBB for the desired divider current and use Equation 2 to calculate high-side RFBT. RFBT in the
range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static
loading is desired to reduce VOUT offset in PFM operation. Lower RFBT reduces efficiency at very light load. Less
static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. But
RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise.
Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature
variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
Figure 15. Output Voltage Setting
RFBT
12
VOUT VREF
u RFBB
VREF
(2)
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8.3.4 Enable/Synchronization
The voltage on the EN pin controls the ON or OFF operation of LMR23630-Q1. A voltage less than 1 V (typical)
shuts the device down while a voltage higher than 1.6 V (typical) is required to start the regulator. The EN/SYNC
pin is an input and cannot be left open or floating. The simplest way to enable the operation of the LMR23630Q1 is to connect the EN to VIN. This allows self-start-up of the LMR23630-Q1 when VIN is within the operation
range.
Many applications benefit from the employment of an enable divider RENT and RENB (Figure 16) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection.
VIN
RENT
EN/SYNC
RENB
Figure 16. System UVLO by Enable Divider
The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can
be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at the EN
pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse
detector, and the minimum SYNC clock ON and OFF time must be longer than 100ns (typ). A 3.3 V or a higher
amplitude pulse signal coupled through a 1 nF capacitor CSYNC is a good starting point. Keeping RENT // RENB
(RENT parallel with RENB) in the 100-kΩ range is a good choice. RENT is required for this synchronization circuit,
but RENB can be left unmounted if system UVLO is not needed. LMR23630-Q1 switching action can be
synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 18 and Figure 19 show the device
synchronized to an external system clock.
VIN
CSYNC
RENT
EN/SYNC
RENB
Clock
Source
Figure 17. Synchronize to External Clock
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Figure 18. Synchronizing in PWM Mode
Figure 19. Synchronizing in PFM Mode
8.3.5 VCC, UVLO
The LMR23630-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a
high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible
to VCC and grounded to the exposed PAD and ground pins. Do not load the VCC output pin or short to ground
during operation. Shorting VCC to ground during operation may cause damage to the LMR23630-Q1.
VCC undervoltage lockout (UVLO) prevents the LMR23630-Q1 from operating until the VCC voltage exceeds 3.2
V (typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to
temporary VIN drops.
8.3.6 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 60
ns in the LMR23630-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off.
TOFF_MIN is typically 100 ns in the LMR23630-Q1. In CCM operation, TON_MIN and TOFF_MIN limit the voltage
conversion range given a selected switching frequency.
The minimum duty cycle allowed is:
DMIN = TON_MIN × fSW
(3)
And the maximum duty cycle allowed is:
DMAX = 1 – TOFF_MIN × fSW
(4)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LMR23630-Q1, a frequency foldback scheme is employed to extend the maximum duty cycle when
TOFF_MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN
conditions. Wide range of frequency foldback allows the LMR23630-Q1 output voltage stay in regulation with a
much lower supply voltage VIN. This leads to a lower effective dropout voltage.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operation supply voltage can be found by:
VOUT
VIN _ MAX
fSW u TON _ MIN
(5)
At lower supply voltage, the switching frequency will decrease once TOFF_MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VOUT
VIN _ MIN
1 fSW u TOFF _ MIN
(6)
Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in Equation 5. With frequency foldback, VIN_MIN is lowered by decreased fSW.
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450
400
Frequency (kHz)
350
300
250
200
150
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
100
50
0
4.6
4.8
5
5.2
5.4
5.6
VIN (V)
5.8
6
6.2
6.4
D013
Figure 20. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 400 kHz)
8.3.7 Power Good (PGOOD)
The power-good version of LMR23630-Q1 has a built-in power-good flag shown on PGOOD pin to indicate
whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing
of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an
appropriate DC voltage. Voltage detected by the PGOOD pin must never exceed 15 V, and the maximum current
into this pin must be limited to 1 mA. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +6% above and –6% below the internal reference voltage
VREF typically, the PGOOD switch is turned off, and the PGOOD voltage is as high as the pulled-up voltage.
When the FB voltage is outside of the tolerance band, +7% above or –7% below VREF typically, the PGOOD
switch is turned on, and the PGOOD pin voltage is pulled low to indicate power bad. A glitch filter prevents falseflag operation for short excursions in the output voltage, such as during line and load transients. The values for
the various filter and delay times can be found in the Timing Characteristics table. Power-good operation can
best be understood by reference to Figure 21.
VREF
107%
106%
94%
93%
PGOOD
High
Low
Figure 21. Power-Good Flag
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8.3.8 Internal Compensation and CFF
The LMR23630-Q1 is internally compensated as shown in Functional Block Diagram. The internal compensation
is designed such that the loop response is stable over the entire operating frequency and output voltage range.
Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors.
An external feed-forward capacitor CFF is recommended to be placed in parallel with the top resistor divider RFBT
for optimum transient performance.
VOUT
RFBT
CFF
FB
RFBB
Figure 22. Feedforward Capacitor for Loop Compensation
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of
the control loop to boost phase margin. The zero frequency can be found by
1
fZ _ CFF
2S u CFF u RFBT
(7)
An additional pole is also introduced with CFF at the frequency of
1
fP _ CFF
2S u CFF u RFBT //RFBB
(8)
The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF
helps maintaining proper gain margin at frequency beyond the crossover. Table 2 lists the combination of COUT,
CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value, adjust
CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.
Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost the
phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not
need any CFF.
1
fZ _ESR
2S u COUT u ESR
(9)
The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore, calculate
CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might change based
on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB
node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced.
8.3.9 Bootstrap Voltage (BOOT)
The LMR23630-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is
0.1 μF or higher. TI recommends ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of
16 V or higher for stable performance over temperature and voltage.
8.3.10 Overcurrent and Short-Circuit Protection
The LMR23630-Q1 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.
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High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See
Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak
current threshold IHS_LIMIT which is constant. So the peak current limit of the HS switch is not affected by the
slope compensation and remains constant over the full duty-cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch is not turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until
the inductor current ramps below the LS current limit ILS_LIMIT. The LS switch is then turned OFF, and the HS
switch turned on after a dead time. This is somewhat different than the more typical peak-current limit, and
results in Equation 10 for the maximum load current.
VIN VOUT
V
IOUT _ MAX ILS _ LIMIT
u OUT
2 u fSW u L
VIN
(10)
If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup currentprotection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms typically before the
LMR23630-Q1 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the
fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over-heating and potential damage to the device.
For FPWM option, the inductor current is allowed to go negative. If this current exceeds IL_NEG, the LS switch is
turned off until the next clock cycle. This is used to protect the LS switch from excessive negative current.
8.3.11 Thermal Shutdown
The LMR23630-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature
falls below 155°C (typical), the device reinitiates the power-up sequence controlled by the internal soft-start
circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR23630-Q1. When VEN is below 1 V (typical), the
device is in shutdown mode. The LMR23630-Q1 also employs VIN and VCC UVLO protection. If VIN or VCC
voltage is below their respective UVLO level, the regulator is turned off.
8.4.2 Active Mode
The LMR23630-Q1 is in active mode when VEN is above the precision enable threshold, VIN and VCC are above
their respective UVLO level. The simplest way to enable the LMR23630-Q1 is to connect the EN pin to VIN pin.
This allows self startup when the input voltage is in the operating range: 4 V to 36 V. See VCC, UVLO and
Enable/Synchronization for details on setting these operating levels.
In active mode, depending on the load current, the LMR23630-Q1 is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple (for both PFM and FPWM options).
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation (only for PFM option).
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM option).
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM option).
8.4.3 CCM Mode
CCM operation is employed in the LMR23630-Q1 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum
in this mode and the maximum output current of 3 A can be supplied by the LMR23630-Q1.
8.4.4 Light Load Operation (PFM Option)
For PFM option, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
LMR23630-Q1 operates in DCM, also known as Diode Emulation Mode (DEM). In DCM, the LS switch is turned
off when the inductor current drops to IL_ZC (–40 mA typical). Both switching losses and conduction losses are
reduced in DCM, compared to forced PWM operation at light load.
At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum
HS switch ON-time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN (300 mA typical) is reached, the
switching frequency decreases to maintain regulation. In PFM, switching frequency is decreased by the control
loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM
operation due to less frequent switching actions. The external clock synchronizing is not be valid when
LMR23630-Q1 enters into PFM mode.
8.4.5 Light Load Operation (FPWM Option)
For FPWM option, LMR23630-Q1 is locked in PWM mode at full load range. This operation is maintained, even
at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light
load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In
this mode, a negative current limit of IL_NEG is imposed to prevent damage to the regulators LS FET. When in
FPWM mode the converter synchronizes to any valid clock signal on the EN/SYNC input.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR23630-Q1 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LMR23630-Q1. Alternately, the WEBENCH software may be used to generate complete
designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses
comprehensive databases of components. See Custom Design With WEBENCH® Tools and ti.com for more
details.
9.2 Typical Applications
The LMR23630-Q1 only requires a few external components to convert from a wide voltage range supply to a
fixed output voltage. Figure 23 shows a basic schematic.
VIN 12 V
BOOT
VIN
CBOOT
0.1 F
L
10 H
CIN
10 F
SW
EN/
SYNC
PAD
CFF
47 pF
FB
CVCC
2.2 F
VOUT
5 V/3 A
RFBT
88.7 kŸ
RFBB
22.1 kŸ
VCC
PGND
COUT
100 F
AGND
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Figure 23. Application Circuit
The external components have to fulfill the needs of the application, but also the stability criteria of the device
control loop. Table 2 can be used to simplify the output filter component selection.
Table 2. L, COUT and CFF Typical Values
(1)
(2)
(3)
(4)
fSW (kHz)
VOUT (V)
L (µH) (1)
COUT (µF) (2)
CFF (pF)
RFBT (kΩ) (3)
400
3.3
6.8
150
75
51
400
5
10
100
47
88.7
400
12
15
68
See note (4)
243
400
24
15
47
See note (4)
510
Inductance value is calculated based on VIN = 36 V.
All the COUT values are after derating. Add more when using ceramic capacitors.
RFBT = 0 Ω for VOUT = 1 V. RFBB = 22.1 kΩ for all other VOUT setting.
High ESR COUT gives enough phase boost, and CFF not needed.
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9.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 3 as the input parameters.
Table 3. Design Example Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, VIN
12 V typical, range from 8 V to 28 V
Output voltage, VOUT
5V
Maximum output current IO_MAX
3A
Transient Response 0.3 A to 3 A
5%
Output voltage ripple
50 mV
Input voltage ripple
400 mV
Switching frequency fSW
400 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR23630-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Output Voltage Setpoint
The output voltage of LMR23630-Q1 is externally adjustable using a resistor divider network. The divider network
is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 11 is used to determine
the output voltage:
VOUT VREF
u RFBB
RFBT
VREF
(11)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1 V, the RFBB
value can then be calculated using Equation 11. The formula yields to a value 88.7 kΩ.
9.2.2.3 Switching Frequency
The default switching frequency of the LMR23630-Q1 is 400 kHz. For other required switching frequency, adjust
RT value or synchronize the device to an external clock to get the target frequency, refer to Adjustable Frequency
andEnable/Synchronization for more details.
20
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9.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 13 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND should be 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating should be higher than the current limit of the device.
'iL
LMIN
VOUT u VIN _ MAX
VOUT
VIN _ MAX u L u fSW
VIN _ MAX
VOUT
IOUT u KIND
u
(12)
VOUT
VIN _ MAX u fSW
(13)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor
current ripple also implies larger output voltage ripple with same output capacitors. With peak-current-mode
control, TI recommends not to have an inductor current rippple that is too small. A larger peak current ripple
improves the comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 8.56 µH. Choose the
nearest standard 8.2-μH ferrite inductor with a capability of 4-A RMS current and 6-A saturation current.
9.2.2.5 Output Capacitor Selection
Choose the output capacitor(s), COUT, with care since it directly affects the steady state output voltage ripple,
loop stability, and the voltage over/undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the ESR of the output capacitors:
'VOUT_ESR 'iL u ESR KIND u IOUT u ESR
(14)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
KIND u IOUT
'iL
'VOUT _ C
8 u fSW u COUT
8 u fSW u COUT
(15)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The regulator’s control loop usually needs four or more clock cycles to respond to the output voltage droop. The
output capacitance must be large enough to supply the current difference for four clock cycles to maintain the
output voltage within the specified range. Equation 16 shows the minimum output capacitance needed for
specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy
stored in the inductor. which results in an output voltage overshoot. Equation 17 calculates the minimum
capacitance required to keep the voltage overshoot within a specified range.
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COUT !
COUT !
www.ti.com
4 u IOH IOL
fSW u VUS
IOH2
(VOUT
(16)
IOL
2
VOS )2
VOUT 2
where
•
•
•
•
•
KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
VOS = Target output voltage overshoot
(17)
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. Equation 14 yields ESR no larger than 41.7 mΩ and Equation 15 yields COUT no smaller than
7.5 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be
calculated to be no smaller than 108 μF and 28.5 μF by Equation 16 and Equation 17 respectively. Consider of
derating, one 47-μF, 16-V and one 100-μF, 10-V ceramic capacitor with 5-mΩ ESR are used in parallel.
9.2.2.6 Feed-Forward Capacitor
The LMR23630-Q1 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor
COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the
phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that
phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency
(fX) without CFF is shown in Equation 18, assuming COUT has very small ESR, and COUT value is after derating.
8.32
fX
VOUT u COUT
(18)
Equation 19 for CFF was tested:
1
CFF
4S u fX u RFBT
(19)
For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from
Equation 19 should be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 47-pF, 50-V, COG capacitor is selected.
9.2.2.7 Input Capacitor Selection
The LMR23630-Q1 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high-frequency decoupling capacitor is 4.7
μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating. To
compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR23630-Q1 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R ceramic
capacitors are used. Use 0.1-μF for high-frequency filtering and place it as close as possible to the device pins.
9.2.2.8 Bootstrap Capacitor Selection
Every LMR23630-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
22
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9.2.2.9 VCC Capacitor Selection
The VCC pin is the output of an internal LDO for LMR23630-Q1. To insure stability of the device, place a
minimum of 2.2-μF, 16-V, X7R capacitor from this pin to ground.
9.2.2.10 UVLO Setpoint
The system UVLO is adjusted using the external voltage divider network of RENT and RENB. The UVLO has two
thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the
input voltage is falling. Use Equation 20 to determine the VIN UVLO level.
R
RENB
VIN _ RISING VENH u ENT
RENB
(20)
The EN rising threshold (VENH) for LMR23630-Q1 is set to be 1.55 V (typical). Choose the value of RENB to be
287 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6 V, then the value of RENT
can be calculated using Equation 21:
§ VIN _ RISING
·
RENT ¨¨
1¸¸ u RENB
© VENH
¹
(21)
Equation 21 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by
Equation 22, where EN hysteresis (VEN_HYS) is 0.4 V (typical).
R
RENB
VIN _ FALLING
VENH VEN _ HYS u ENT
RENB
(22)
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25 °C.
VOUT = 5 V
IOUT = 3 A
fSW = 400 kHz
VOUT = 5 V
Figure 24. CCM Mode
VOUT = 5 V
IOUT = 0 mA
VOUT = 5 V
fSW = 400 kHz
VOUT = 5 V
IOUT = 0 mA
fSW = 400 kHz
Figure 27. FPWM Mode
IOUT = 2 A
VIN = 12 V
Figure 28. Start-Up by VIN
24
fSW = 400 kHz
Figure 25. DCM Mode
Figure 26. PFM Mode
VIN = 12 V
IOUT = 150 mA
VOUT = 5 V
IOUT = 2 A
Figure 29. Start-Up by EN
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Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25 °C.
VIN = 12 V
VOUT = 5 V
IOUT = 0.3 A to 3 A,
100 mA / μs
VIN = 7 V to 36 V,
2 V / μs
Figure 30. Load Transient
VOUT = 5 V
VOUT = 5 V
IOUT = 3 A
Figure 31. Line Transient
IOUT = 1 A to short
VOUT = 5 V
Figure 32. Short Protection
IOUT = short to 1 A
Figure 33. Short Recovery
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10 Power Supply Recommendations
The LMR23630-Q1 is designed to operate from an input voltage supply range between 4 V and 36 V. This input
supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the
input supply rail must be low enough that an input current transient does not cause a high enough drop at the
LMR23630-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply
is located more than a few inches from the LMR23630-Q1, additional bulk capacitance may be required in
addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding
for both the input and output capacitors must consist of localized top side planes that connect to the PGND
pin and PAD.
2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
3. Minimize trace length to the FB pin net. Locate both feedback resistors, RFBT and RFBB close to the FB pin.
Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is
made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other
side of a shielded layer.
4. Use ground plane in one of the middle layers as noise shielding and heat-dissipation path.
5. Have a single point ground connection to the plane. Route the ground connections for the feedback and
enable components to the ground plane. This prevents any switched or load currents from flowing in the
analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat sinking
to keep the junction temperature below 125°C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Use short, thick traces or copper pours (shapes) for high current conduction
path to minimize parasitic resistance. The output capacitors must be placed close to the VOUT end of the inductor
and closely grounded to PGND pin and exposed PAD.
Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the
exposed PAD.
26
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Layout Guidelines (continued)
11.1.2 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the
AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is
connected to the source of the internal LS switch. They must be connected directly to the grounds of the input
and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load
variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The
other side of the ground plane contains much less noise and should be used for sensitive routes.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat
sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground
plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the LMR23630-Q1 are specified using the parameter RθJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use Equation 23:
TJ = PD × RθJA + TA
where
•
•
•
•
•
TJ = Junction temperature in °C
PD = VIN × IIN × (1 – Efficiency) – 1.1 x IOUT2 × DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
RθJA = Junction to ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C
(23)
The maximum operating junction temperature of the LMR23630-Q1 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.
11.1.3 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the
load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the
feedback signal with switch noise, while also minimizing the trace length. This is most important when high value
resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the
resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in
between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage
feedback path from EMI noises.
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11.2 Layout Examples
Output Bypass
Capacitor
Output Inductor
SW
Input Bypass
Capacitor
PGND
BOOT Capacitor
BOOT
VCC
Capacitor
VIN
VCC
AGND
FB
EN/
SYNC
UVLO Adjust Resistor
Output Voltage Set
Resistor
Thermal VIA
VIA (Connect to GND Plane)
Figure 34. SOIC Layout
Output
Inductor
Output Bypass
Capacitor
BOOT
Capacitor
VCC
Capacitor
SW
PGND
SW
NC
BOOT
VIN
VCC
VIN
FB
EN/SYNC
RT
AGND
Input Bypass
Capacitor
UVLO Adjust
Resistor
RT
Thermal VIA
Output Voltage
Set Resistor
VIA (Connect to GND Plane)
Figure 35. WSON Layout
28
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12 Device and Documentation Support
12.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR23630-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMR23630AFQDDAQ1
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
F30AFQ
LMR23630AFQDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
F30AFQ
LMR23630APQDRRRQ1
ACTIVE
SON
DRR
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
363PQ
LMR23630APQDRRTQ1
ACTIVE
SON
DRR
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
363PQ
LMR23630AQDDAQ1
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
F30AQ
LMR23630AQDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
F30AQ
LMR23630FQDRRRQ1
ACTIVE
SON
DRR
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
363FQ
LMR23630FQDRRTQ1
ACTIVE
SON
DRR
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
363FQ
LMR23630QDRRRQ1
ACTIVE
SON
DRR
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3630Q
LMR23630QDRRTQ1
ACTIVE
SON
DRR
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3630Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
12-Mar-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMR23630-Q1 :
• Catalog: LMR23630
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMR23630AFQDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LMR23630APQDRRRQ1
SON
DRR
12
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
LMR23630APQDRRTQ1
SON
DRR
12
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
LMR23630AQDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LMR23630FQDRRRQ1
SON
DRR
12
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
LMR23630FQDRRTQ1
SON
DRR
12
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
LMR23630QDRRRQ1
SON
DRR
12
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
LMR23630QDRRTQ1
SON
DRR
12
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMR23630AFQDDARQ1
SO PowerPAD
LMR23630APQDRRRQ1
SON
DDA
8
2500
366.0
364.0
50.0
DRR
12
3000
370.0
355.0
55.0
LMR23630APQDRRTQ1
SON
DRR
LMR23630AQDDARQ1
SO PowerPAD
DDA
12
250
195.0
200.0
45.0
8
2500
366.0
364.0
LMR23630FQDRRRQ1
SON
50.0
DRR
12
3000
370.0
355.0
55.0
LMR23630FQDRRTQ1
LMR23630QDRRRQ1
SON
DRR
12
250
195.0
200.0
45.0
SON
DRR
12
3000
370.0
355.0
LMR23630QDRRTQ1
55.0
SON
DRR
12
250
195.0
200.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRR0012D
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
1.7 0.1
6
7
A
13
2X
2.5
A
2.5 0.1
1
12
10X 0.5
PIN 1 ID
(OPTIONAL)
12X
12X
0.38
0.28
0.3
0.2
0.1
0.05
C A B
C
4223146/D 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRR0012D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.7)
12X (0.53)
SYMM
1
12
12X (0.25)
13
SYMM
10X (0.5)
(2.5)
(1)
(R0.05) TYP
6
7
(0.6)
( 0.2) VIA
TYP
(2.87)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL EDGE
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223146/D 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRR0012D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.47)
12X (0.53)
1
12
12X (0.25)
METAL
TYP
(0.675)
SYMM
13
10X (0.5)
(1.15)
(R0.05) TYP
6
7
(0.74)
(2.87)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80.1% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223146/D 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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