Texas Instruments | LP8758-B0 Four-Phase DC/DC Step-Down Converter (Rev. C) | Datasheet | Texas Instruments LP8758-B0 Four-Phase DC/DC Step-Down Converter (Rev. C) Datasheet

Texas Instruments LP8758-B0 Four-Phase DC/DC Step-Down Converter (Rev. C) Datasheet
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LP8758-B0
SNVSA06C – MARCH 2015 – REVISED AUGUST 2018
LP8758-B0 Four-Phase DC/DC Step-Down Converter
1 Features
3 Description
•
The LP8758 is designed to meet the power
management requirements of the latest application
processors in mobile phones and similar portable
applications. The device contains four step-down
DC/DC converter cores, which are bundled together
in a single 4-phase buck converter. The device is
controlled by an I2C-compatible serial interface.
1
•
•
•
•
•
•
•
•
High-Efficiency Step-Down Four-Phase DC/DC
Converter Cores:
– Maximum Output Current 16 A
– Auto PWM-PFM and Forced-PWM Operations
– Auto Phase Adding/Shedding and Force MultiPhase Operations
– Remote Differential Feedback Voltage Sensing
– Programmable Output Voltage Slew-Rate from
30 mV/µs to 0.5 mV/µs
– VOUT Range = 0.5 V to 3.36 V with DVS
Programmable Start-up and Shutdown Delays
with Enable Signal
I2C-Compatible Interface which Supports Standard
(100 kHz), Fast (400 kHz), Fast+ (1 MHz), and
High-Speed (3.4 MHz) Modes
Interrupt Function with Programmable Masking
Load Current Measurement
Output Short-Circuit and Overload Protection
Spread-Spectrum Mode and Phase Interleaving
for EMI Reduction
Overtemperature Warning and Protection
Undervoltage Lockout (UVLO)
The automatic PWM-PFM (AUTO mode) operation,
together with the automatic phase adding/shedding,
maximizes efficiency over a wide output-current
range. The LP8758 supports remote differential
voltage sensing to compensate IR drop between the
regulator output and the point-of-load, thus improving
the accuracy of the output voltage.
The LP8758 supports programmable start-up and
shutdown delays synchronized to Enable signal.
The protection features include short-circuit
protection, current limits, input supply UVLO, and
temperature warning and shutdown functions.
Several error flags are provided for status information
of the device. In addition, the LP8758 device supports
load current measurement without the addition of
external current sense resistors. During start-up and
voltage change, the device controls the output slew
rate to minimize output voltage overshoot and the
inrush current.
2 Applications
•
•
Device Information (1)
Smart Phones, eBooks and Tablets
Gaming Devices
PART NUMBER
LP8758-B0
(1)
PACKAGE
DSBGA (35)
BODY SIZE (NOM)
2.88 mm × 2.13 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Output Current (VIN = 3.7 V)
4 Simplified Schematic
95
LP8758
90
VIN_B0
VIN_B1
VIN_B2
VIN_B3
VANA
NRST
SDA
SCL
nINT
EN1
EN2
85
SW_B0
SW_B1
SW_B2
SW_B3
FB_B0
FB_B1
FB_B2
FB_B3
GNDs
VOUT
LOAD
Efficiency (%)
VIN
80
75
70
65
60
1.2 V
1.0 V
55
50
0.001
0.01
0.1
1
Output Current (A)
10 20
D038
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8758-B0
SNVSA06C – MARCH 2015 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
I2C Serial Bus Timing Parameter.............................. 9
Switching Characteristics ........................................ 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 25
8.6 Register Maps ......................................................... 29
9
Application and Implementation ........................ 40
9.1 Application Information............................................ 40
9.2 Typical Application .................................................. 40
10 Power Supply Recommendations ..................... 47
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 49
12 Device and Documentation Support ................. 50
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
50
50
13 Mechanical, Packaging, and Orderable
Information ........................................................... 50
5 Revision History
Changes from Revision B (May 2016) to Revision C
Page
•
Changed logic low level to 0 V and high level to VANA up to 3.6 V ...................................................................................... 5
•
Added support for I2C signals up to 3.3V ............................................................................................................................. 5
•
Changed "700 µs" to "1.2 ms" .............................................................................................................................................. 17
Changes from Revision A (May 2015) to Revision B
Page
Changes from Original (March 2015) to Revision A
Page
•
first WEB release ................................................................................................................................................................... 1
•
Added Community Resources section ................................................................................................................................ 50
2
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SNVSA06C – MARCH 2015 – REVISED AUGUST 2018
6 Pin Configuration and Functions
YFF Package
35-Pin DSBGA
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
G
VIN
_B3
SW
_B3
PGND
_B23
SW
_B2
VIN
_B2
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
F
VIN
_B3
SW
_B3
PGND
_B23
SW
_B2
VIN
_B2
SCL
FB
_B2
PGND
_B23
FB
_B3
VANA
E
VANA
FB
_B3
PGND
_B23
FB
_B2
SCL
SDA
NRST
EN2
nINT
AGND
D
AGND
nINT
EN2
NRST
SDA
EN1
FB
_B0
PGND
_B01
FB
_B1
SGND
C
SGND
FB
_B1
PGND
_B01
FB
_B0
EN1
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
B
VIN
_B1
SW
_B1
PGND
_B01
SW
_B0
VIN
_B0
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
A
VIN
_B1
SW
_B1
PGND
_B01
SW
_B0
VIN
_B0
5
4
3
2
1
1
2
3
4
5
Top View (Bump-side down)
Bottom View
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Pin Functions
PIN
TYPE
DESCRIPTION
VIN_B1
P
Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
SW_B1
A
Buck 1 switch node.
NUMBER
NAME
A1, B1
A2, B2
A3, B3, C3
PGND_B01
G
Power Ground for Buck 0 and Buck 1.
A4, B4
SW_B0
A
Buck 0 switch node.
A5, B5
VIN_B0
P
Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
C1
SGND
G
Substrate Ground.
C2
FB_B1
A
Output ground feedback (negative) for Buck 0.
C4
FB_B0
A
Output voltage feedback (positive) for Buck 0.
C5
EN1
D/I
Programmable Enable signal for Buck regulator. Can be also configured to switch between two
output voltage levels.
D1
AGND
G
Ground.
D2
nINT
D/O
Open-drain interrupt output. Active LOW.
D3
EN2
D/I
Programmable Enable signal for Buck regulator. Can be also configured to switch between two
output voltage levels.
D4
NRST
D/I
Reset signal for the device.
D5
SDA
D/I/O
E1
VANA
P
Supply voltage for Analog and Digital blocks. VANA pin must be connected to same voltage as
VIN_Bx pins.
E2
FB_B3
A
Output voltage feedback (positive) for Buck 3 - Connect to ground in 4-phase configuration.
E4
FB_B2
A
Output voltage feedback (positive) for Buck 2. - Connect to ground in 4-phase configuration.
E5
SCL
D/I
VIN_B3
P
Input for Buck 3. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
F1, G1
F2, G2
Serial interface data input and output for system access. Connect a pull-up resistor.
Serial interface clock input for system access. Connect a pull-up resistor.
SW_B3
A
Buck 3 switch node.
PGND_B23
G
Power Ground for Buck 2 and Buck 3.
F4, G4
SW_B2
A
Buck 2 switch node.
F5, G5
VIN_B2
P
Input for Buck 2. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
E3, F3, G3
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_Bx, VANA
Voltage on power connections
–0.3
6
V
SW_Bx
Voltage on buck switch nodes
–0.3
(VIN_Bx + 0.3 ) with 6 V
max
V
FB_Bx
Voltage on buck voltage sense nodes
–0.3
(VANA + 0.3 ) with
6 V max
V
NRST
Voltage on NRST input
–0.3
3.6
V
–0.3
3.6
ENx, SDA, SCL, nINT Voltage on logic pins (input or output pins)
CURRENT
VIN_Bx, SW_Bx,
PGND_Bx
Current on power pins (average current over 100k hour
lifetime, TJ = 125°C)
0.62
A/pin
TEMPERATURE
Junction temperature, TJ-MAX
−40
150
°C
Storage temperature, Tstg
–65
150
°C
260
°C
Maximum lead temperature (soldering, 10 sec.)
(1)
(2)
(3)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground.
For detailed soldering specifications and information, refer to AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_Bx, VANA
Voltage on power connections
2.5
5.5
V
NRST
Voltage on NRST
0
VANA up to
3.6
V
ENx, nINT
Voltage on logic pins (input or output pins)
0
VANA up to
3.6
V
0
1.95
V
SCL, SDA
Voltage on I2C interface, standard (100 kHz), fast (400
khz),
fast+ (1 MHz), and high-speed (3.4 MHz) modes
Voltage on I2C interface, standard (100 kHz), fast (400
kHz), and fast+ (1 MHz) modes
0
VANA up to
3.6
V
Junction temperature, TJ
−40
125
°C
Ambient temperature, TA
−40
85
°C
TEMPERATURE
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7.4 Thermal Information
LP8758
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
35 PINS
RθJA
Junction-to-ambient thermal resistance
56.1
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
0.2
°C/W
RθJB
Junction-to-board thermal resistance
8.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
8.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
CIN
Input filtering capacitance
Connected from VIN_Bx to PGND_Bx
1.9
10
µF
COUT
Output filtering capacitance,
local
Capacitance per phase
10
22
µF
COUT-TOTAL
Output capacitance, total
(local and remote)
Total output capacitance, 4-phase
configuration
40
ESRC
Input and output capacitor
ESR
[1-10] MHz
L
Inductor
Inductance of the inductor
DCRL
Inductor DCR
TOKO, DFE252010F-R33M
2
200
µF
10
mΩ
0.33 or 0.47
–30%
µH
30%
16
mΩ
BUCK REGULATOR
VIN
Input voltage range
VOUT
IOUT
Output voltage
Voltage between VIN_Bx and ground
pins. VANA must be connected to the
same supply as VIN_Bx.
2.5
Programmable voltage range
0.5
Step size, 0.5 V ≤ VOUT < 0.73 V
6
V
1
3.36
V
10
5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
20
mV
Output current, 4-phase configuration
12 (3)
Output current
Output current, 4-phase configuration,
VIN > 3 V, VOUT < 2 V
16 (3)
Dropout voltage
VIN – VOUT
DC output voltage accuracy,
includes voltage reference,
DC load and line regulations,
PFM mode, the average output voltage
process and temperature
level is increased by max. 20 mV
(3)
5.5
Step size, 0.73 V ≤ VOUT < 1.4 V
Forced PWM mode, 0.8 V ≤ VOUT ≤ 1.2
V, 2.5 V ≤ VIN ≤ 4.5 V, TJ = 25°C, 0 ≤
IOUT ≤ IOUT(max)
(1)
(2)
3.7
0.7
A
V
-1%
1.5%
min (–2%,
–15 mV)
max ( 2%,
15 mV) 20
mV
All voltage values are with respect to network ground.
Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power
dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current
pulse, efficiency, board and ambient temperature. The maximum average current/pin over lifetime is described in Absolute Maximum
Ratings.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
Ripple, 4-phase
configuration
PWM mode, L = 0.33 µH
10
PFM mode, L = 0.33 µH
10
DCLNR
DC line regulation
IOUT = IOUT(max)
±0.05
DCLDR
DC load regulation in PWM
mode
IOUT from 0 to IOUT(max)
0.3%
IOUT = 1 A to 8 A, TR = 400 ns, PWM
mode, COUT = 100 µF, L = 0.33 µH
TLNSR
Transient line response
ILIM
FWD
NEG
RDS(ON) HS
FET
RDS(ON) LS
Forward current limit (peak
for every switching cycle)
%/V
–35
mV
–45
mV
IOUT = 8 A to 1 A, TF = 400 ns, PWM
mode, COUT = 100 µF, L = 0.33 µH
45
mV
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2
V, IOUT = 4.1 A to 0.1 A, TF = 100 ns,
AUTO mode, COUT = 100 µF, L = 0.33
µH
25
mV
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V,
IOUT from 12 A to 1 A, TF = 1000 ns,
COUT = 100 µF, L = 0.33 µH
50
mV
VIN stepping 2.5 V ↔ 3 V, TR = TF = 10
µs, IOUT = IOUT(max)
±20
mV
Programmable range
ILIM
mVp-p
mV
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V,
IOUT from 1 A to 12 A, TR = 1000 ns,
COUT = 100 µF, L = 0.33 µH
Overshoot for transient load
step response, 4-phase
configuration
UNIT
-45
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2
Undershoot for transient load V, IOUT = 0.1 A to 4.1 A, TR = 100 ns,
step response, 4-phase
AUTO mode, COUT = 100 µF, L = 0.33
configuration
µH
TLDSR
MAX
1.5
Step size
5
0.5
A
Accuracy, 3 V ≤ VIN ≤ 5.5 V, ILIM = 5 A
–5%
7.5%
20%
Accuracy, 2.5 V ≤ VIN < 3 V, ILIM = 5 A
–20%
7.5%
20%
1.6
2
2.4
A
Negative current limit
On-resistance, high-side
FET
Each phase, between VIN_Bx and
SW_Bx pins (I = 1 A)
40
90
mΩ
On-resistance, low-side FET
Each phase, between SW_Bx and
PGND_Bx pins (I = 1 A)
33
50
mΩ
Current balancing
Current mismatch between phases, IOUT
> 1000 mA / phase, 0.8 V ≤ VOUT ≤ 1.2
V
Overshoot during start-up
VOUT = 1 V, Slew rate = 10 mV/µs
FET
10%
50
mV
IPFM-PWM
PFM-to-PWM transition current threshold (4)
600
mA
IPWM-PFM
PWM-to-PFM transition current threshold (4)
240
mA
IADD
Phase-adding level
ISHED
Phase-shedding level
Output pulldown resistance
(4)
From 1-phase to 2-phase
1000
From 2-phase to 3-phase
2000
From 3-phase to 4-phase
3000
From 2-phase to 1-phase
750
From 3-phase to 2-phase
1500
From 4-phase to 3-phase
2300
Regulator disabled
150
250
mA
mA
350
Ω
The final PFM-to-PWM and PWM-to-PFM transition current varies slightly and is dependant on the output voltage, input voltage, and the
magnitude of inductor's ripple current.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
Powergood threshold for
interrupt
BUCKx_INT(BUCKx_SC_IN
T), difference from final
voltage
Powergood threshold for
status signal
BUCKx_STAT(BUCKx_PG_
STAT)
TEST CONDITIONS
Rising ramp voltage, enable or voltage
change
MIN
TYP
MAX
–23
–17
–10
10
17
23
–23
–17
–10
UNIT
mV
Falling ramp, voltage change
During operation, status signal is forced
to '0' during voltage change
mV
PROTECTION FEATURES
Thermal warning
Temperature rising,
CONFIG(TDIE_WARN_LEVEL) = 0
125
Temperature rising,
CONFIG(TDIE_WARN_LEVEL) = 1
105
Hysteresis
Thermal shutdown
VANAUVLO
VANA undervoltage lockout
15
Temperature rising
150
Hysteresis
Voltage falling
Hysteresis
°C
°C
15
2.3
2.4
50
2.5
V
mV
LOAD CURRENT MEASUREMENT
Current measurement range
Maximum code
Resolution
LSB
Measurement accuracy
IOUT ≥ 2 A
20.46
20
A
mA
<10%
CURRENT CONSUMPTION
8
Shutdown current
consumption
V(NRST) = 0 V
1
µA
Standby current
consumption, regulator
disabled
V(NRST) = 1.8 V
6
µA
Active current consumption
during PFM operation
V(NRST) = 1.8 V, IOUT = 0 mA, not
switching
71
µA
Active current consumption
during PWM operation
V(NRST) = 1.8 V, IOUT = 0 mA
18
mA
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA
VIL
Input low level
0.4
VIH
Input high level
1.2
VHYS
Hysteresis of Schmitt trigger
inputs (SCL, SDA)
10
80
800
1200
ENx pulldown resistance
ENx_PD = 1
NRST pulldown resistance
Always present
V
V
160
mV
500
kΩ
1700
kΩ
0.4
V
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL
Output low level
ISOURCE = 2 mA
RP
External pullup resistor for
nINT
To VIO Supply
10
kΩ
ALL DIGITAL INPUTS
ILEAK
Input current
All logic inputs over pin voltage range
−1
1
µA
7.6 I2C Serial Bus Timing Parameter
See (1) and Figure 1.
MIN
ƒSCL
Serial clock frequency
MAX
UNIT
Standard mode
100
kHz
Fast mode
400
kHz
1
MHz
3.4
MHz
1.7
MHz
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
tLOW
SCL low time
Standard mode
4.7
Fast mode
1.3
Fast mode +
0.5
High-speed mode, Cb = 100 pF
160
High-speed mode, Cb = 400 pF
320
Standard mode
Fast mode
tHIGH
tSU;DAT
tHD;DAT
(1)
SCL high time
Data setup time
Data hold time
µs
ns
4
0.6
Fast mode +
µs
0.26
High-speed mode, Cb = 100 pF
60
High-speed mode, Cb = 400 pF
120
Standard mode
250
Fast mode
100
Fast mode +
50
High-speed mode
10
ns
ns
Standard mode
0
3.45
Fast mode
0
0.9
Fast mode +
0
High-speed mode, Cb = 100 pF
0
70
High-speed mode, Cb = 400 pF
0
150
µs
ns
Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
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I2C Serial Bus Timing Parameter (continued)
See(1) and Figure 1.
MIN
Standard mode
tSU;STA
Setup time for a start or
a repeated start
condition
Fast mode
0.6
0.26
High-speed mode
160
tBUF
Hold time for a start or a Fast mode
repeated start condition Fast mode +
High-speed mode
160
Standard mode
4.7
tfDA
Rise time of SDA signal
Fall time of SDA signal
Rise time of SCL signal
Fast mode
trCL1
tfCL
Capacitive load for each
bus line (SCL and SDA)
tSP
Pulse width of spike
suppressed in SCL and
SDA lines (spikes that
are less than the
indicated width are
suppressed)
10
4
Fast mode +
0.26
High-speed mode
160
µs
ns
1000
Fast mode
300
Fast mode +
120
High-speed mode, Cb = 100 pF
80
High-speed mode, Cb = 400 pF
160
Standard mode
250
Fast mode
250
Fast mode +
120
High-speed mode, Cb = 100 pF
80
High-speed mode, Cb = 400 pF
160
300
Fast mode +
120
High-speed Mode, Cb = 100 pF
40
High-speed Mode, Cb = 400 pF
80
ns
ns
1000
Fast mode
300
Fast mode +
120
High-speed mode, Cb = 100 pF
80
High-speed mode, Cb = 400 pF
160
Standard mode
300
Fast mode
300
120
High-speed mode, Cb = 100 pF
40
High-speed mode, Cb = 400 pF
80
400
Fast mode, fast mode +
50
High-speed mode
10
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ns
1000
Fast mode
Fall time of a SCL signal Fast mode +
Cb
µs
0.6
Standard mode
Rise time of SCL signal
after a repeated start
condition and after an
acknowledge bit
ns
0.5
Standard mode
trCL
µs
1.3
Standard mode
trDA
ns
4
0.6
Bus free time between a
Fast mode
stop and start condition
Fast mode +
Setup time for a stop
condition
µs
0.26
Standard mode
tSU;STO
UNIT
4.7
Fast mode +
Standard mode
tHD;STA
MAX
ns
ns
pF
ns
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7.7 Switching Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted. (1)
PARAMETER
TEST CONDITIONS
ƒSW
Switching frequency, PWM
mode
ƒSW-MAX
Maximum switching
frequency, PWM mode
Automatically limited to
smaller of ƒSW and ƒSW-MAX
MIN
TYP
MAX
2.7
3
3.3
VOUT ≥ 0.6 V
2.7
3
3.3
VOUT < 0.6 V
1.8
2
2.2
From ENx to VOUT = 0.225 V (slew-rate
Regulator start-up time (soft
control begins), COUT_TOTAL = 88 µF, no
start)
load
Output voltage slew-rate (2)
Load current measurement
time
(1)
(2)
UNIT
MHz
MHz
90
µs
SLEW_RATEx[2:0] = 000, VOUT ≥ 0.5 V
–15%
30
15%
SLEW_RATEx[2:0] = 001, VOUT ≥ 0.5 V
–15%
15
15%
SLEW_RATEx[2:0] = 010, VOUT ≥ 0.5 V
–15%
10
15%
SLEW_RATEx[2:0] = 011, VOUT ≥ 0.5 V
–15%
7.5
15%
SLEW_RATEx[2:0] = 100, VOUT ≥ 0.5 V
–15%
3.8
15%
SLEW_RATEx[2:0] = 101, VOUT ≥ 0.5 V
–15%
1.9
15%
SLEW_RATEx[2:0] = 110, VOUT ≥ 0.5 V
–15%
0.94
15%
SLEW_RATEx[2:0] = 111, VOUT ≥ 0.5 V
–15%
0.4
15%
PFM mode (automatically changing to
PWM mode for the measurement)
mV/µs
50
PWM mode
µs
4
Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
tfCL
trDA
tSP
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
S
tHD;DAT
START
tSU;DAT
RS
P
S
REPEATED
START
STOP
START
Figure 1. I2C Timing
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7.8 Typical Characteristics
2
8
1.8
7.6
1.6
7.2
1.4
6.8
Input Current (PA)
Input Current (PA)
Unless otherwise specified: TA = 25°C, VIN = 3.7 V, ƒSW = 3 MHz.
1.2
1
0.8
0.6
6
5.6
5.2
0.4
4.8
0.2
4.4
0
2.5
3
3.5
4
4.5
Input Voltage (V)
5
4
2.5
5.5
3
3.5
D011
V(NRST) = 0 V
V(NRST) = 1.8 V
Figure 2. Shutdown Current Consumption vs Input Voltage
25
78
24
76
23
74
22
72
70
68
66
64
4
4.5
Input Voltage (V)
5
5.5
D010
Regulator disabled
Figure 3. Standby Current Consumption vs Input Voltage
80
Input Current (mA)
Input Current (PA)
6.4
21
20
19
18
17
62
16
60
2.5
15
2.5
3
V(NRST) = 1.8 V
Load = 0 mA
3.5
4
4.5
Input Voltage (V)
5
5.5
3
3.5
D012
V(EN1) = 1.8 V
L = 330 nH
VOUT = 1 V
Figure 4. PFM Mode Current Consumption vs Input Voltage
4
4.5
Input Voltage (V)
V(NRST) = 1.8 V
Load = 0 mA
V(EN1) = 1.8 V
1 phase active
5
5.5
D039
VOUT = 1 V
L = 330 nH
Figure 5. PWM Mode Current Consumption vs Input Voltage
80
78
Input Current (mA)
76
74
72
70
68
66
64
62
60
2.5
V(NRST) = 1.8 V
Load = 0 mA
3
3.5
4
4.5
Input Voltage (V)
V(EN1) = 1.8 V
4 phases active
5
5.5
D040
VOUT = 1 V
L = 330 nH
Figure 6. Forced Multi-Phase Current Consumption vs Input Voltage
12
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8 Detailed Description
8.1 Overview
The LP8758 is a high-efficiency, high-performance power supply device with four step-down DC-DC converter
cores. The cores are configured for a single 4-phase configuration. The device delivers 0.5-V to 3.36-V regulated
voltage rail from 2.5-V to 5.5-V battery or supply voltage to portable devices such as cell phones, tablets, and
PDAs.
There are two modes of operation for the converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 400 mA or higher. When operating in PWM mode the phases are automatically
added/shedded based on the load current level. Lighter output current loads will cause the converter to
automatically switch into PFM mode for reduced current consumption and a longer battery life when forced PWM
mode is disabled. The forced multi-phase mode can be enabled for highest transient performance.
Additional features include soft-start, undervoltage lockout, overload protection, thermal warning, and thermal
shutdown.
8.1.1 Buck Information
The LP8758 has four integrated high-efficiency buck converter cores. The cores are designed for flexibility; most
of the functions are programmable, thus giving a possibility to optimize the regulator operation for each
application.
8.1.1.1 Operating Modes
• OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pulldown resistor.
• PWM: Converter operates in buck configuration with fixed switching frequency.
• PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current
is discontinuous.
8.1.1.2 Features
• Output voltage
• Forced PWM operation
• Forced multi-phase operation (forces also the PWM operation)
• Switch current limit
• Output voltage slew rate
• Enable and disable delays
8.1.1.3 Programmability
The following parameters can be programmed via registers:
• DVS support with programmable slew-rate
• Automatic mode control based on the loading
• Synchronous rectification
• Current mode loop with PI compensator
• Optional spread spectrum technique to reduce EMI
• Soft start
• Power good flag with maskable interrupt
• Phase control for optimized EMI
• Average output current sensing (for PFM entry, phase shedding/adding, and load current measurement)
• Current balancing between the phases of the converter
• Differential voltage sensing from point of the load
• Dynamic phase shedding/adding, each output being phase shifted
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8.2 Functional Block Diagram
VANA
Buck0
nINT
Interrupts
ILIM Det
Pwrgood Det
Overload and
SC Det
Enable,
Roof/Floor,
Slew-Rate
Control
EN1
EN2
Iload ADC
Buck1
ILIM Det
Pwrgood Det
SDA
SCL
I2C
Overload and
SC Det
Iload ADC
Registers
UVLO
OTP
EPROM
Buck2
ILIM Det
Pwrgood Det
Digital
Logic
Overload and
SC Det
Oscillator
NRST
Iload ADC
Buck3
SW
Reset
Ref &
Bias
Thermal
Monitor
ILIM Det
Pwrgood Det
Overload and
SC Det
Iload ADC
8.3 Feature Description
8.3.1 Multi-Phase DC-DC Converters
8.3.1.1 Overview
A multi-phase synchronous buck converter offers several advantages over a single power stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, since the load current is evenly shared among multiple
channels, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional
to square of current. Physical size of the output inductor shrinks significantly due to this heat reduction. A block
diagram of a single core is shown in Figure 7.
Interleaving switching action of the converters and channels in a four-phase configuration is illustrated in
Figure 8.
14
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Feature Description (continued)
+
FBN
-
Slave
Phase
Control
±
+
Voltage
Setting
Slew Rate
Control
VIN
POS
Current
Limit
Ramp
Generator
±
VOUT
Gate
Control
Error
Amp
SW
Loop
Comp
NEG
Current
Limit
Power
Good
+
-
VDAC
+
FBP
PMOS
Current
Sense
Differential to SingleEnded
Programmable
Parameters
Control
Block
Zero
Cross
Detect
NMOS
Current
Sense
Master
Interface
Slave
Interface
IADC
GND
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Figure 7. Detailed Block Diagram Showing One Core
IL_TOT_4PH
IL0
IL1
IL2
IL3
0
90
180
270
360
450
540
630
720
360
450
540
630
720
PWM0
PWM1
PWM2
PWM3
Switching Cycle 360º
0
90
180
270
Phase (Degrees)
Figure 8. PWM Timings and Inductor Current Waveforms in 4-phase Configuration
(1)
(1)
Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
Under heavy load conditions, the 4-phase converter switches each channel 90° apart. As a result, the 4-phase
converter has an effective ripple frequency four times greater than the switching frequency of any one phase.
However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this
operational inefficiency, the LP8758 can change the number of active phases to optimize efficiency for the
variations of the load. This is called phase adding/shedding. The concept is illustrated below in Figure 9.
The converter can be forced to multi-phase operation by the BUCK0_CTRL1.BUCK0_FPWM_MP bit. If the
regulator operates in forced multi-phase mode the forced PWM operation is automatically used. If the multiphase operation is not forced, the number of phases are added and shedded automatically to follow the required
output current.
4-Phase
Operation
3-Phase
Operation
2-Phase
Operation
1-Phase
Operation
Best efficiency obtained with
N=1
Efficiency
N=2
N=3
N=4
Load Current
Figure 9. Multi-Phase Buck Converter Efficiency vs Number of Phases All Converters in PWM Mode (2)
8.3.1.3 Transition Between PWM and PFM Modes
Normal PWM mode operation with phase-adding or phase-shedding optimizes efficiency at mid-to-full load at the
expense of light-load efficiency. The LP8758 converter operates in PWM mode at load current of about 400 mA
or higher. At lighter load current levels the device automatically switches into PFM mode for reduced current
consumption when Forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the
PWM modes a high efficiency is achieved over a wide output-load current range.
8.3.1.4 Multi-Phase Switcher Configurations
In the multi-phase configuration the control of the multi-phase regulator settings is done using the control
registers of the master buck. The following slave registers are ignored:
• BUCKx_CTRL1
• BUCKx_CTRL2, except ILIMx[2:0] bits
• interrupt bits related to the slave buck, except BUCKx_ILIM_INT
(2)
16
Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
8.3.1.5 Buck Converter Load Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
SEL_I_LOAD.LOAD_CURRENT_BUCK_SELECT[1:0] register bits. A write to this selection register starts a
current measurement sequence. The measurement sequence is typically 50 µs long. The LP8758 device can be
configured to give out an interrupt INT_TOP.I_LOAD_READY after the load current measurement sequence is
finished. Load current measurement interrupt can be masked with TOP_MASK.I_LOAD_READY_MASK bit. The
measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits
BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8]
the MSB bits. The measurement result BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the
measurement is 20.46 A. The measured current is the total value of the master and slave phases.
8.3.1.6 Spread-Spectrum Mode
Radiated Energy
Power Spectrum is
Spread and Lowered
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8758's register selectable spread-spectrum mode minimizes the
need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies
randomly by ±5% (depending on selected switching frequency) about the center frequency, reducing the EMI
emissions radiated by the converter and associated passive components and PCB traces (see Figure 10). This
feature is enabled with the CONFIG.EN_SPREAD_SPEC bit, and it affects all the buck cores.
Frequency
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8758 spreads that energy over a large bandwidth.
Figure 10. Spread-Spectrum Modulation
8.3.2 Power-Up
The power-up sequence for the LP8758 is as follows:
• VANA (and VIN_Bx) reach min recommended levels (V(VANA) > VANAUVLO).
• NRST is set to high level. This initiates power-on-reset (POR), OTP reading and enables the system I/O
interface. The I2C host allows at least 1.2 ms before writing or reading data to the LP8758.
• Device enters STANDBY mode.
• The host can change the default register setting by I2C if needed.
• The regulator can be enabled/disabled by ENx pin(s) and by I2C interface.
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Feature Description (continued)
8.3.3 Regulator Control
8.3.3.1 Enabling and Disabling Regulator
The regulator can be enabled when the device is in STANDBY state. There are two ways for enable and disable
the regulator:
• Using BUCK0_CTRL1.EN_BUCK0 register bit (BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '0').
• Using
EN1/2
control
pins
(BUCK0_CTRL1.EN_BUCK0
register
bit
is
'1'
AND
BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '1').
If the EN1/2 control pins are used for enable and disable then the delay from the control signal rising edge to
startup is set by BUCK0_DELAY.BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling
edge to shutdown is set by BUCK0_DELAY.BUCK0_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for
EN1/2 signal and not for control with BUCK0_CTRL1.EN_BUCK0 bit. The delay time implemented by EN1/2 has
overall +/-10% timing accuracy.
The control of the regulator (with 0 ms delays) is shown in Table 1. The multi-phase regulator is controlled with
registers of the master phase.
Table 1. Regulator Control
CONTROL
METHOD
ROW
EN_BUCKx0
BUCK0_CTRL1
EN_PIN_CTRL0
BUCK0_CTRL1
EN_PIN_SELECT0
BUCK0_CTRL1
EN_ROOF_FLOOR0
EN1 PIN
EN2 PIN
BUCK0
OUTPUT VOLTAGE
Enable/disable
control with
EN_BUCK0 bit
1
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Disabled
2
1
0
Don't Care
Don't Care
Don't Care
Don't Care
BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable
control with EN1
pin
3
1
1
0
0
Low
Don't Care
Disabled
4
1
1
0
0
High
Don't Care
BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable
control with EN2
pin
5
1
1
1
0
Don't Care
Low
Disabled
6
1
1
1
0
Don't Care
High
BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor
control with EN1
pin
7
1
1
0
1
Low
Don't Care
BUCK0_FLOOR_VOUT.BUCK0_F
LOOR_VSET[7:0]
8
1
1
0
1
High
Don't Care
BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor
control with EN2
pin
9
1
1
1
1
Don't Care
Low
BUCK0_FLOOR_VOUT.BUCK0_F
LOOR_VSET[7:0]
10
1
1
1
1
Don't Care
High
BUCK0_VOUT.BUCK0_VSET[7:0]
The following configuration allows the enable/disable control using ENx pin:
• BUCK0_CTRL1.EN_BUCK0 = 1
• BUCK0_CTRL1.EN_PIN_CTRL0 = 1
• BUCK0_CTRL1.EN_ROOF_FLOOR0 = 0
• BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
• The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0
When the ENx pin is low, Table 1 row 3 (or 5) is valid, and the regulator is disabled. By setting ENx pin high,
Table 1 row 4 (or 6) is valid, and the regulator is enabled with required voltage.
If the regulator is enabled all the time, and the ENx pin controls selection between two voltage level, the following
configuration is used:
• BUCK0_CTRL1.EN_BUCK0 = 1
• BUCK0_CTRL1.EN_PIN_CTRL0 = 1
• BUCK0_CTRL1.EN_ROOF_FLOOR0 = 1
• BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
• The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0
When the ENx pin is low, Table 1 row 7(or 9) is valid, and the regulator is enabled with a voltage defined by
BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 1 row 8 (or 10) is valid,
and the regulator is enabled with a voltage defined by BUCK0_VOUT.BUCK0_VSET[7:0] bits.
18
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If the regulator is controlled by I2C writings, the BUCK0_CTRL1.EN_PIN_CTRL0 bit is set to 0. The
enable/disable is controlled by the BUCK0_CTRL1.EN_BUCK0 bit, and when the regulator is enabled, the output
voltage is defined by the BUCK0_VOUT.BUCK0_VSET[7:0] bits. The Table 1 rows 1 and 2 are valid for I2C
controlled operation (ENx pins are ignored).
The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 11. The soft-start circuit limits the inrush current during start-up. Output voltage increase rate is around 30 mV/μsec during soft-start. When the
output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short
circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the regulator is
disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the
INT_BUCK_0_1.BUCK0_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using
BUCK_0_1_MASK.BUCK0_PG_MASK bit.
The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host
can disable those with CONFIG.ENx_PD bits.
Voltage decrease because of load
No new Powergood interrupt
Voltage
BUCK0_VSET[7:0]
Powergood
Ramp
BUCK0_CTRL2.SLEW_RATE0[2:0]
0.6V
0.35V
Resistive pull-down
(if enabled)
Soft start
Time
Enable
BUCK_0_1_STAT.BUCK0_STAT
0
BUCK_0_1_STAT.BUCK0_PG_STAT
0
1
INT_BUCK_0_1.BUCK0_PG_INT
0
1
1
0
0
1
0
0
nINT
Powergood
interrupt
Host clears
interrupt
Figure 11. Regulator Enable and Disable
8.3.3.2 Changing Output Voltage
The regulator's output voltage can be changed by the ENx pin (voltage levels defined by the BUCK0_VOUT and
BUCK0_FLOOR_VOUT registers) or by writing to the BUCK0_VOUT and BUCK0_FLOOR_VOUT registers. The
voltage change is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_CTRL2.SLEW_RATE[2:0] bits. During voltage change the Forced PWM mode is used automatically. If
the multi-phase operation is forced by the BUCK0_CTRL1. BUCK0_FPWM_MP bit, the regulator operates in
multi-phase mode (four phases active). If the multi-phase operation is not forced, the number of phases are
added and shedded automatically to follow the required slew rate. When the programmed output voltage is
achieved, the mode becomes the one defined by load current, and the BUCK0_CTRL1.BUCK0_FPWM and
BUCK0_CTRL1.BUCK0_FPWM_MP bits.
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Voltage
BUCK0_VSET
Powergood
Ramp
Powergood
BUCK0_CTRL2.SLEW_RATE0[2:0]
BUCK0_FLOOR_VSET
Time
ENx
BUCK_0_1_STAT.BUCK0_STAT
1
BUCK_0_1_STAT.BUCK0_PG_STAT
1
INT_BUCK_0_1.BUCK0_PG_INT
0
0
1
1
0
0
1
1
nINT
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
Figure 12. Regulator Output Voltage Change
8.3.4 Device Reset Scenarios
There are three reset methods implemented on the LP8758:
• Software reset with RESET.SW_RESET register bit
• Reset from low logic level of NRST signal
• Undervoltage lockout (UVLO) reset from VANA supply
An SW reset occurs when RESET.SW_RESET bit is written '1'. The bit is automatically cleared after writing. This
event disables the regulator immediately, resets all the register bits to the default values and OTP bits are loaded
(see Figure 14). I2C interface is not reset during software reset.
If VANA supply voltage falls below UVLO threshold level or NRST signal is set low, then the regulator is disabled
immediately, and all the register bits are reset to the default values. When the VANA supply voltage is above
UVLO threshold level and NRST signal rises above threshold level an internal power-on reset (POR) occurs.
OTP bits are loaded to the registers, and a start-up is initiated according to the register settings.
8.3.5 Diagnosis and Protection Features
The LP8758 is capable of providing three levels of protection features:
• Warnings for diagnosis which sets interrupt;
• Protection events which are disabling the regulator; and
• Faults which are causing the device to shutdown.
When the device detects warning/protection condition(s), the LP8758 sets the flag bits indicating what protection
or warning conditions have occurred, and the nINT pin will be pulled low. nINT will be released again after a
clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.
When a fault is detected, it is indicated by a INT_TOP.RESET_REG interrupt flag after next start-up.
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Table 2. Summary of Interrupt Signals
EVENT
RESULT
INTERRUPT REGISTER
AND BIT
INTERRUPT MASK
STATUS BIT
RECOVERY /
INTERRUPT CLEAR
Current limit
triggered (20 µs
debounce)
No effect
INT_TOP.INT_BUCKx = 1
INT_BUCKx.BUCKx_ILIM_I
NT = 1
BUCKx_MASK.BUCKx_ILI BUCKx_STAT.BUCKx_IL Write 1 to
M_MASK
IM_STAT
INT_BUCKx.BUCKx_ILI
M_INT bit
Interrupt is not cleared if
current limit is active
Short circuit (VOUT <
0.35 V at 1 ms after
enable) or Overload
(VOUT decreasing
below 0.35V during
operation, 1 ms
debounce)
Regulator disable
INT_TOP.INT_BUCK0 = 1
INT_BUCK_0_1.BUCK0_SC
_INT = 1
N/A
Thermal Warning
No effect
INT_TOP.TDIE_WARN = 1
TOP_MASK.TDIE_WARN
_MASK
Thermal Shutdown
Regulator disabled
INT_TOP.TDIE_SD = 1
N/A
Powergood, output
voltage reaches the
programmed value
No effect
Load current
measurement ready
No effect
INT_TOP.I_LOAD_READY
=1
TOP_MASK.I_LOAD_REA
DY_MASK
N/A
Write 1 to
INT_TOP.I_LOAD_REA
DY bit
Start-up (NRST
rising edge)
Device ready for
operation, registers
reset to default values
INT_TOP.RESET_REG = 1
TOP_MASK.RESET_REG
_MASK
N/A
Write 1 to
INT_TOP.RESET_REG
bit
Glitch on supply
voltage and UVLO
triggered (VANA
falling and rising)
Immediate shutdown
followed by powerup,
registers reset to
default values
INT_TOP.RESET_REG = 1
TOP_MASK.RESET_REG
_MASK
N/A
Write 1 to
INT_TOP.RESET_REG
bit
Software requested
reset
Immediate shutdown
followed by powerup,
registers reset to
default values
INT_TOP.RESET_REG = 1
TOP_MASK.RESET_REG
_MASK
N/A
Write 1 to
INT_TOP.RESET_REG
bit
INT_TOP.INT_BUCK0 = 1 BUCK_0_1_MASK.BUCK0
INT_BUCK_0_1.BUCK0_PG
_PG_MASK
_INT = 1
N/A
Write 1 to
INT_BUCK_0_1.BUCK0_
SC_INT bit
TOP_STAT.TDIE_WARN Write 1 to
_STAT
INT_TOP.TDIE_WARN
bit
Interrupt is not cleared if
temperature is above
thermal warning level
TOP_STAT.TDIE_SD_S
TAT
Write 1 to
INT_TOP.TDIE_SD bit
Interrupt is not cleared if
temperature is above
thermal shutdown level
BUCK_0_1_STAT.BUCK Write 1 to
0_PG_STAT
INT_BUCK_0_1.BUCK0_
PG_INT bit
8.3.5.1 Warnings for Diagnosis (Interrupt)
8.3.5.1.1 Output Current Limit
The buck regulators have programmable output peak current limits. The limits are individually programmed for all
buck regulators with BUCKx_CTRL2.ILIMx[2:0] bits. The current limit settings of master and slave regulators
used for the same output voltage rail must be identical. If the load current is increased so that the current limit is
triggered, the regulator continues to regulate to the limit current level (current peak regulation). The voltage may
decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP8758
device sets the INT_BUCKx.BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read
BUCKx_STAT.BUCKx_ILIM_STAT bits to see if the regulator is still in peak current regulation mode.
If the load is so high that the output voltage decreases below a 350-mV level, the LP8758 device disables the
regulator and sets the INT_BUCK_0_1.BUCK0_SC_INT bit. In addition the BUCK_0_1_STAT.BUCK0_STAT bit
is set to 0. The interrupt is cleared when the host processor writes 1 to INT_BUCK_0_1.BUCK0_SC_INT bit. The
overload situation is shown in Figure 13.
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New startup if
enable is valid
Regulator disabled
by digital
Voltage
BUCK0_VSET
350mV
Resistive
pull-down
1ms
Time
Current
ILIMx
Time
25Ps
INT_BUCKx.BUCKx_ILIM_INT
0
1
0
INT_BUCK_0_1.BUCK0_SC_INT
0
1
0
BUCK_0_1_STAT.BUCK0_STAT
1
0
1
nINT
Host clearing the interrupt by writing to flags
Figure 13. Overload Situation
8.3.5.1.2 Thermal Warning
The LP8758 device includes protection feature against over-temperature by setting an interrupt for host
processor. The threshold level of the thermal warning is selected with CONFIG.TDIE_WARN_LEVEL bit.
If the LP8758 device temperature increases above thermal warning level the device sets INT_TOP.TDIE_WARN
bit and pulls nINT pin low. The status of the thermal warning can be read from TOP_STAT.TDIE_WARN_STAT
bit and the interrupt is cleared by writing 1 to INT_TOP.TDIE_WARN bit.
8.3.5.2 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, or undervoltage lockout), the output power FETs are set to high-impedance mode, and the output pulldown resistor is enabled (if enabled with BUCKx_CTRL1.EN_RDISx bits). The turn-off time of the output voltage
is defined by the output capacitance, load current, and the resistance of the integrated pulldown resistor.
8.3.5.2.1
Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP8758 to protect itself and external components against short circuit
at the output or against overload during start-up. The fault threshold is 350 mV, and the protection is triggered,
and the regulator disabled, if the output voltage is below the threshold level 1 ms after the regulator is enabled.
In a similar way the overload situation is protected during normal operation. If the regulator's feedback-pin
voltage falls below 0.35 V, and remains below the threshold level for 1 ms, the regulator is disabled.
In the short-circuit and overload situations the INT_BUCK_0_1.BUCK0_SC_INT and the INT_TOP.INT_BUCK0
bits are set to 1, the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0 and the nINT signal is pulled low. The host
processor clears the interrupt by writing 1 to the INT_BUCK_0_1.BUCK0_SC_INT bit. Upon clearing the interrupt
the regulator makes a new start-up attempt if the enable register bits and/or ENx control signal is valid.
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8.3.5.2.2 Thermal Shutdown
The LP8758 has an overtemperature protection function that operates to protect itself from short-term misuse
and overload conditions. When the junction temperature exceeds around 150°C, the regulator is disabled, the
INT_TOP.TDIE_SD bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT will be
cleared by writing 1 to the INT_TOP.TDIE_SD bit. If the temperature is above thermal shutdown level the
interrupt is not cleared. The host can read the status of the thermal shutdown from the
TOP_STAT.TDIE_SD_STAT bit. Regulator cannot be enabled as long as the junction temperature is above
thermal shutdown level or the thermal shutdown interrupt is pending.
8.3.5.3 Fault (Power Down)
8.3.5.3.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck converters are disabled immediately,
and the output capacitor is discharged using the pulldown resistor and the LP8758 device enters SHUTDOWN.
When VANA voltage is above UVLO threshold level and NRST signal is high, the device powers up to STANDBY
state.
If the reset interrupt is unmasked by default (TOP_MASK.RESET_REG_MASK = 0) the INT_TOP.RESET_REG
interrupt indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by
writing 1 to the INT_TOP.RESET_REG bit. If the host processor reads the INT_TOP.RESET_REG flag after
detecting an nINT low signal, it knows that the input supply voltage has been below UVLO level (or the host has
requested reset), and the registers are reset to default values.
8.3.6 Digital Signal Filtering
The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
Table 3. Digital Signal Filtering
EVENT
SIGNAL / SUPPLY
Enable/Disable/Voltage Select for
BUCK0
EN1
Enable/Disable/Voltage Select for
BUCK0
EN2
VANA undervoltage lockout
Thermal warning
RISING EDGE LENGTH
FALLING EDGE LENGTH
3µs
(1)
3µs
(1)
3µs
(1)
3µs
(1)
VANA
Immediate
Immediate
TDIE_WARN
20 µs
20 µs
Thermal shutdown
TDIE_SD
20 µs
20 µs
VOUTx_ILIM
20 µs
20 µs
Overload
FB_B0 - FB_B1, FB_B2 FB_F3
1 ms
1 ms
Powergood
FB_B0 - FB_B1, FB_B2 FB_F3
20 µs
20 µs
Current limit
(1)
No glitch filtering, only synchronization.
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8.4 Device Functional Modes
8.4.1 Modes of Operation
SHUTDOWN: The V(NRST) voltage is below threshold level. All switch, reference, control and bias circuitry of the
LP8758 device are turned off.
WAIT-ON:
The V(NRST) voltage is above threshold level. The reference and bias circuitry are enabled. The
regulator of the LP8758 device is turned off.
READ OTP: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. The regulator is disabled and the reference and bias circuitry of the LP8758 are enabled. The
OTP bits are loaded to registers.
STANDBY: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. The regulator is disabled and the reference, control and bias circuitry of the LP8758 are
enabled. All registers can be read or written by the host processor via the system serial interface.
The regulator can be enabled if needed.
ACTIVE:
The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. At least one regulated DC-DC converter is enabled. All registers can be read or written by the
host processor via the system serial interface.
The operating modes and transitions between the modes are shown in Figure 14.
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Device Functional Modes (continued)
SHUTDOWN
NRST high
NRST low
FROM ANY STATE
EXCEPT SHUTDOWN
V(VANA) > VANAUVLO
WAIT-ON
V(VANA) < VANAUVLO
READ
OTP
FROM ANY STATE
EXCEPT SHUTDOWN
REG
RESET
STANDBY
2
I C RESET
REGULATOR
ENABLED
REGULATOR(S)
DISABLED
ACTIVE
Figure 14. Device Operation Modes
8.5 Programming
8.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor
placed somewhere on the line and remain HIGH even when the bus is idle. The LP8758 supports standard mode
(100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).
8.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
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Programming (continued)
SCL
SDA
data
change
allowed
data
change
allowed
data
valid
data
change
allowed
data
valid
Figure 15. Data Validity Diagram
8.5.1.2 Start and Stop Conditions
The LP8758 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is
HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master
always generates the START and STOP conditions.
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 16. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 17 shows the
SDA and SCL signal timing for the I2C-Compatible Bus. See the I2C Serial Bus Timing Parameter for timing
values.
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
trDA
tSP
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
S
tHD;DAT
START
tSU;DAT
RS
P
S
REPEATED
START
STOP
START
Figure 17. I2C-Compatible Timing
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Programming (continued)
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8758 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8758 generates an
acknowledge after each byte has been received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
NOTE
If the NRST signal is low during I2C communication the LP8758 device does not drive
SDA line. The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
START
MSB Chip Address LSB
ACK from slave
W ACK MSB Register Address LSB ACK
MSB
Data LSB
ACK STOP
W ACK
address 0x40 data
ACK STOP
SCL
SDA
START
id = 0x60
address = 0x40
ACK
Figure 18. Write Cycle (w = write; SDA = '0'), id = Device Address = 60Hex for LP8758
ACK from slave
START
MSB Chip Address LSB
W
id = 0x60
W
ACK from slave
MSB Register Address LSB
REPEATED START
ACK from slave Data from slave NACK from master
RS
MSB Chip Address LSB
R
RS
id = 0x60
R
MSB
Data
LSB
STOP
SCL
SDA
START
ACK
address = 0x3F
ACK
ACK
address 0x3F data
NACK
STOP
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 19. Read Cycle ( r = read; SDA = '1'), id = Device Address = 60Hex for LP8758
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Programming (continued)
8.5.1.4 I2C-Compatible Chip Address
The device address for the LP8758 is 0x60. After the START condition, the I2C master sends the 7-bit address
followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The
second byte following the device address selects the register address to which the data will be written. The third
byte contains the data for the selected register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Here device address is 110 0000Bin = 60Hex.
Figure 20. Device Address
8.5.1.5 Auto Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP8758, the internal address index counter will be incremented by one and the next
register will be written. Table 4 below shows writing sequence to two consecutive registers. Note that the autoincrement feature does not work for read.
Table 4. Auto-Increment Example
Master
Action
Start
Device
Address
= 60H
Write
LP8758
Action
28
Register
Address
ACK
Data
ACK
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ACK
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8.6 Register Maps
8.6.1 Register Descriptions
The LP8758 is controlled by a set of registers through the system serial interface port. The device registers, their
addresses and their abbreviations are listed in Table 5. A more detailed description is given in sections
DEV_REV to I_LOAD_1.
Table 5. Summary of LP8758 Control Registers
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
0x01
OTP_REV
R
0x02
BUCK0_
CTRL1
R/W
Reserved
BUCK0_
FPWM
BUCK0
_FPWM
_MP
0x03
BUCK0_
CTRL2
R/W
Reserved
ILIM0[2:0]
SLEW_RATE0[2:0]
0x05
BUCK1_
CTRL2
R/W
Reserved
ILIM1[2:0]
Reserved
0x07
BUCK2_
CTRL2
R/W
Reserved
ILIM2[2:0]
Reserved
0x09
BUCK3_
CTRL2
R/W
Reserved
ILIM3[2:0]
Reserved
0x0A
BUCK0_
VOUT
R/W
BUCK0_VSET[7:0]
0x0B
BUCK0_
FLOOR_
VOUT
R/W
BUCK0_FLOOR_VSET[7:0]
0x12
BUCK0_
DELAY
R/W
0x16
RESET
R/W
0x17
CONFIG
R/W
0x18
INT_TOP
R/W
0x19
INT_BUCK_
0_1
R/W
0x1A
INT_BUCK_
2_3
R/W
0x1B
TOP_
STAT
R
0x1C
BUCK_0_1_
STAT
R
Reserved
BUCK1_
ILIM_
STAT
0x1D
BUCK_2_3_
STAT
R
Reserved
BUCK3_
ILIM_STAT
0x1E
TOP_
MASK
R/W
0x1F
BUCK_0_1_
MASK
R/W
Reserved
BUCK1_
ILIM_
MASK
0x20
BUCK_2_3_
MASK
R/W
Reserved
BUCK3_
ILIM_
MASK
0x21
SEL_I_
LOAD
R/W
Reserved
LOAD_CURRENT_
BUCK_SELECT[1:0]
0x22
I_LOAD_2
R/W
Reserved
BUCK_LOAD_CURRENT[
9:8]
0x23
I_LOAD_1
R/W
OTP_ID[7:0]
EN_BUCK0
EN_PIN_
CTRL0
EN_PIN_
SELECT0
EN_ROOF
_FLOOR0
EN_RDIS0
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
SW_
RESET
Reserved
TDIE
_WARN
_LEVEL
EN2_PD
EN1_PD
EN_
SPREAD
_SPEC
INT_
BUCK0
TDIE_SD
TDIE_
WARN
RESET_
REG
I_LOAD_
READY
Reserved
BUCK1_
ILIM_INT
Reserved
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
Reserved
BUCK3_
ILIM_INT
Reserved
INT_
BUCK3
INT_
BUCK2
INT_
BUCK1
Reserved
BUCK2_
ILIM_INT
Reserved
TDIE_SD
_STAT
TDIE_
WARN_
STAT
BUCK0_
STAT
BUCK0_
PG_STAT
Reserved
Reserved
BUCK2_
ILIM_STAT
Reserved
Reserved
Reserved
BUCK0_
ILIM_
STAT
TDIE_WAR
N_MASK
RESET_
REG_MASK
I_LOAD_
READY_
MASK
BUCK0_
PG_MASK
Reserved
BUCK0_
ILIM_
MASK
Reserved
BUCK2_
ILIM_
MASK
BUCK_LOAD_CURRENT[7:0]
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8.6.1.1 DEV_REV
Address: 0x00
D7
D6
D5
DEVICE_ID[1:0]
D4
D3
D2
ALL_LAYER[1:0]
D1
D0
METAL_LAYER[3:0]
Bits
Field
Type
Default
7:6
DEVICE_ID[1:0]
R
00
Device specific ID code.
Description
5:4
ALL_LAYER[1:0]
R
00
Shows the all layer version of the device:
00 - First all layer version
01 - Second all layer version
10 - Third all layer version
11 - Fourth all layer version
3:0
METAL_LAYER
[3:0]
R
0001
Shows the metal layer version of the device:
0000 - All layer version
0001 - First metal layer spin
...
1111 - 15th metal layer spin
8.6.1.2 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
OTP_ID[7:0]
Bits
Field
Type
7:0
OTP_ID[7:0]
R
Default
Description
1011 0000 Identification Code of the OTP EPROM Version.
8.6.1.3 BUCK0_CTRL1
Address: 0x02
D7
D6
D5
D4
D3
D2
EN_BUCK0
EN_PIN_
CTRL0
EN_PIN_
SELECT0
EN_ROOF_
FLOOR0
EN_RDIS0
Reserved
BUCK0_FPWM BUCK0_FPWM
_MP
Bits
Field
Type
Default
7
EN_BUCK0
R/W
1
Enable BUCK0 regulator:
0 - BUCK0 regulator is disabled
1 - BUCK0 regulator is enabled.
6
EN_PIN_CTRL0
R/W
1
Enable EN1/2 pin control for BUCK0:
0 - only EN_BUCK0 bit controls BUCK0
1 - EN_BUCK0 bit AND EN1/2 pin control BUCK0.
5
EN_PIN_SELECT0
R/W
0
Select which ENx pin controls BUCK0 if EN_PIN_CTRL0 = 1:
0 - EN1 pin
1 - EN2 pin.
4
EN_ROOF_
FLOOR0
R/W
0
Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL0 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control.
3
EN_RDIS0
R/W
1
Enable output discharge resistor when BUCK0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
2
Reserved
R/W
0
1
BUCK0_FPWM
R/W
0
Forces the BUCK0 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation.
0
BUCK0_FPWM
_MP
R/W
0
Forces the BUCK0 regulator to operate always in multi-phase and forced PWM
operation mode:
0 - Automatic phase adding and shedding.
1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration, 3 phases
in the 3-phase configuration and 4 phases in the 4-phase configuration.
30
Description
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8.6.1.4 BUCK0_CTRL2
Address: 0x03
D7
D6
D5
Reserved
D4
D3
D2
D1
ILIM0[2:0]
D0
SLEW_RATE0[2:0]
Bits
Field
Type
Default
7:6
Reserved
R/W
00
Description
5:3
ILIM0[2:0]
R/W
111
Sets the switch current limit of BUCK0. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
2:0
SLEW_RATE0[2:0]
R/W
010
Sets the output voltage slew rate for BUCK0 regulator (rising and falling edges):
000 - 30 mV/µs
001 - 15 mV/µs
010 - 10 mV/µs (Default)
011 - 7.5 mV/µs
100 - 3.8 mV/µs
101 - 1.9 mV/µs
110 - 0.94 mV/µs
111 - 0.4 mV/µs
8.6.1.5 BUCK1_CTRL2
Address: 0x05
D7
D6
D5
Reserved
D4
D3
D2
D1
ILIM1[2:0]
Bits
Field
Type
Default
7:6
Reserved
R/W
00
5:3
ILIM1[2:0]
R/W
111
2:0
Reserved
R/W
010
D0
Reserved
Description
Sets the switch current limit of BUCK1. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
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8.6.1.6 BUCK2_CTRL2
Address: 0x07
D7
D6
D5
Reserved
D4
D3
D2
ILIM2[2:0]
Bits
Field
Type
Default
7:6
Reserved
R/W
00
5:3
ILIM2[2:0]
R/W
111
2:0
Reserved
R/W
010
D1
D0
Reserved
Description
Sets the switch current limit of BUCK2. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
8.6.1.7 BUCK3_CTRL2
Address: 0x09
D7
D6
D5
Reserved
D4
D3
D2
ILIM3[2:0]
Bits
Field
Type
Default
7:6
Reserved
R/W
00
5:3
ILIM3[2:0]
R/W
111
2:0
Reserved
R/W
010
D1
D0
Reserved
Description
Sets the switch current limit of BUCK3. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
8.6.1.8 BUCK0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
7:0
BUCK0_VSET[7:0]
R/W
32
Default
Description
0110 0001 Sets the output voltage of BUCK0 regulator
0.5 V - 0.73 V, 10 mV steps
0000 0000 - 0.5V
...
0001 0111 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0001 1000 - 0.735 V
...
1001 1101 - 1.4 V
1.4 V - 3.36 V, 20 mV steps
1001 1110 - 1.42 V
...
1111 1111 - 3.36 V
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8.6.1.9 BUCK0_FLOOR_VOUT
Address: 0x0B
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_FLOOR
_VSET[7:0]
Bits
Field
Type
7:0
BUCK0_FLOOR
_VSET[7:0]
R/W
Default
Description
0000 0000 Sets the output voltage of BUCK0 regulator when Floor state is used
0.5 V - 0.73 V, 10 mV steps
0000 0000 - 0.5V
...
0001 0111 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0001 1000 - 0.735 V
...
1001 1101 - 1.4 V
1.4 V - 3.36 V, 20 mV steps
1001 1110 - 1.42 V
...
1111 1111 - 3.36 V
8.6.1.10 BUCK0_DELAY
Address: 0x12
D7
D6
D5
D4
D3
BUCK0_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
0000
Shutdown delay of BUCK0 from falling edge of ENx signal:
0000 - 0 ms
0001 - 1 ms
...
1111 - 15 ms
Description
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
0000
Start-up delay of BUCK0 from rising edge of ENx signal:
0000 - 0 ms
0001 - 1 ms
...
1111 - 15 ms
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8.6.1.11 RESET
Address: 0x16
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
SW_RESET
R/W
0
D0
SW_RESET
Description
Software commanded reset. When written to 1, the registers will be reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
8.6.1.12 CONFIG
Address: 0x17
D7
D6
D5
D4
Reserved
D3
D2
D1
D0
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
EN_SPREAD
_SPEC
Bits
Field
Type
Default
7:4
Reserved
R/W
0000
Description
3
TDIE_WARN_
LEVEL
R/W
0
Thermal warning threshold level.
0 - 125°C
1 - 105°C.
2
EN2_PD
R/W
1
Selects the pull down resistor on the EN2 input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
1
EN1_PD
R/W
1
Selects the pull down resistor on the EN1 input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
0
EN_SPREAD
_SPEC
R/W
0
Enable spread spectrum feature:
0 - Disabled
1 - Enabled
8.6.1.13 INT_TOP
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
D0
INT_BUCK3
INT_BUCK2
INT_BUCK1
INT_BUCK0
TDIE_SD
TDIE_WARN
RESET_REG
I_LOAD_
READY
Bits
Field
Type
Default
7
INT_BUCK3
R
0
Interrupt indicating that output BUCK3 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK3 register.
This bit is cleared automatically when INT_BUCK3 register is cleared to 0x00.
6
INT_BUCK2
R
0
Interrupt indicating that output BUCK2 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK2 register.
This bit is cleared automatically when INT_BUCK2 register is cleared to 0x00.
5
INT_BUCK1
R
0
Interrupt indicating that output BUCK1 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK1 register.
This bit is cleared automatically when INT_BUCK1 register is cleared to 0x00.
4
INT_BUCK0
R
0
Interrupt indicating that output BUCK0 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK0 register.
This bit is cleared automatically when INT_BUCK0 register is cleared to 0x00.
3
TDIE_SD
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulator has been disabled if it was enabled. The
regulator cannot be enabled if this bit is active. The actual status of the thermal
warning is indicated by TOP_STAT.TDIE_SD_STAT bit.
Write 1 to clear interrupt.
34
Description
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Bits
Field
Type
Default
2
TDIE_WARN
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TOP_STAT.TDIE_WARN_STAT bit.
Write 1 to clear interrupt.
Description
1
RESET_REG
R/W
0
Latched status bit indicating that either startup (NRST rising edge) has done, VANA
supply voltage has been below undervoltage threshold level or the host has requested
a reset (RESET.SW_RESET). The regulator has been disabled, and registers are
reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt.
0
I_LOAD_READY
R/W
0
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
8.6.1.14 INT_BUCK_0_1
Address: 0x19
D7
D6
D5
Reserved
D4
D3
D2
D1
D0
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
Field
Type
Default
7:5
Reserved
R/W
000
Description
4
BUCK1_ILIM_INT
R/W
0
3
Reserved
R/W
0
2
BUCK0_PG_INT
R/W
0
Latched status bit indicating that BUCK0 output voltage has reached powergood
threshold level.
Write 1 to clear.
1
BUCK0_SC_INT
R/W
0
Latched status bit indicating that the BUCK0 output voltage has fallen below 0.35V
level during operation or BUCK0 output didn't reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
0
BUCK0_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
8.6.1.15 INT_BUCK_2_3
Address: 0x1A
D7
D6
D5
D4
Reserved
D3
BUCK3_ILIM
_INT
Bits
Field
Type
Default
7:5
Reserved
R/W
000
4
BUCK3_ILIM_INT
R/W
0
3:1
Reserved
R/W
000
0
BUCK2_ILIM_INT
R/W
0
D2
D1
Reserved
D0
BUCK2_ILIM
_INT
Description
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
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8.6.1.16 TOP_STAT
Address: 0x1B
D7
D6
D5
D4
Reserved
Bits
D3
D2
TDIE_SD
_STAT
TDIE_WARN
_STAT
Field
Type
Default
7:4
Reserved
R
0000
3
TDIE_SD_STAT
R
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level.
2
TDIE_WARN
_STAT
R
0
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level.
1:0
Reserved
R
00
D1
D0
Reserved
Description
8.6.1.17 BUCK_0_1_STAT
Address: 0x1C
D7
D6
D5
Reserved
D4
D3
D2
D1
D0
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
7:5
Reserved
R
000
Description
4
BUCK1_ILIM
_STAT
R
0
Status bit indicating BUCK1 current limit status (raw status)
0 - BUCK1 output current is below current limit level
1 - BUCK1 output current limit is active.
3
BUCK0_STAT
R
0
Status bit indicating the enable/disable status of BUCK0:
0 - BUCK0 regulator is disabled
1 - BUCK0 regulator is enabled.
2
BUCK0_PG_STAT
R
0
Status bit indicating BUCK0 output voltage validity (raw status)
0 - BUCK0 output is above powergood threshold level
1 - BUCK0 output is below powergood threshold level.
1
Reserved
R
0
0
BUCK0_ILIM
_STAT
R
0
Status bit indicating BUCK0 current limit status (raw status)
0 - BUCK0 output current is below current limit level
1 - BUCK0 output current limit is active.
8.6.1.18 BUCK_2_3_STAT
Address: 0x1D
D7
D6
D5
D4
Reserved
Bits
Field
Type
Default
7:5
Reserved
R
000
4
BUCK3_ILIM
_STAT
R
0
3:1
Reserved
R
000
0
BUCK2_ILIM
_STAT
R
0
36
D3
BUCK3_ILIM
_STAT
D2
Reserved
D1
D0
BUCK2_ILIM
_STAT
Description
Status bit indicating BUCK3 current limit status (raw status)
0 - BUCK3 output current is below current limit level
1 - BUCK3 output current limit is active.
Status bit indicating BUCK2 current limit status (raw status)
0 - BUCK2 output current is below current limit level
1 - BUCK2 output current limit is active.
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8.6.1.19 TOP_MASK
Address: 0x1E
D7
D6
D5
D4
D3
Reserved
Bits
D2
D1
D0
TDIE_WARN
_MASK
RESET_REG
_MASK
I_LOAD_
READY_MASK
Field
Type
Default
Description
7:3
Reserved
R/W
0 0000
2
TDIE_WARN
_MASK
R/W
0
Masking for thermal warning interrupt INT_TOP.TDIE_WARN:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect TOP_STAT.TDIE_WARN_STAT status bit.
1
RESET_REG
_MASK
R/W
1
Masking for register reset interrupt INT_TOP.RESET_REG:
0 - Interrupt generated
1 - Interrupt not generated.
0
I_LOAD_
READY_MASK
R/W
0
Masking for load current measurement ready interrupt INT_TOP.I_LOAD_READY.
0 - Interrupt generated
1 - Interrupt not generated.
8.6.1.20 BUCK_0_1_MASK
Address: 0x1F
D7
D6
D5
Reserved
Bits
Field
Type
Default
7:5
Reserved
R/W
000
4
BUCK1_ILIM
_MASK
R/W
1
3
Reserved
R/W
0
2
BUCK0_PG_MASK
R/W
0
1
Reserved
R
0
0
BUCK0_ILIM
_MASK
R/W
0
D4
D3
D2
D1
D0
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Description
Masking for BUCK1 current limit detection interrupt INT_BUCK_0_1.BUCK1_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit.
Masking for BUCK0 power good interrupt INT_BUCK_0_1.BUCK0_PG_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_PG_STAT status bit.
Masking for BUCK0 current limit detection interrupt INT_BUCK_0_1.BUCK0_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit.
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8.6.1.21 BUCK_2_3_MASK
Address: 0x20
D7
D6
D5
D4
Reserved
Bits
D3
BUCK3_ILIM
_MASK
Field
Type
Default
7:5
Reserved
R/W
000
4
BUCK3_ILIM
_MASK
R/W
1
3:1
Reserved
R/W
000
0
BUCK2_ILIM
_MASK
R/W
1
D2
D1
Reserved
D0
BUCK2_ILIM
_MASK
Description
Masking for BUCK3 current limit detection interrupt INT_BUCK_2_3.BUCK3_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_2_3_STAT.BUCK3_ILIM_STAT status bit.
Masking for BUCK2 current limit detection interrupt INT_BUCK_2_3.BUCK2_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_2_3_STAT.BUCK1_ILIM_STAT status bit.
8.6.1.22 SEL_I_LOAD
Address: 0x21
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:2
Reserved
R/W
00 0000
1:0
LOAD_CURRENT_
BUCK_SELECT
[1:0]
R/W
00
D1
D0
LOAD_CURRENT_BUCK
_SELECT[1:0]
Description
Start the current measurement on the selected regulator:
00 - BUCK0
01 - BUCK1
10 - BUCK2
11 - BUCK3
The measurement is started when register is written.
If the selected buck is master, the measurement result is a sum current of master and
slave bucks.
If the selected buck is slave, the measurement result is a current of the selected slave
bucks.
8.6.1.23 I_LOAD_2
Address: 0x22
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:2
Reserved
R
00 0000
1:0
BUCK_LOAD_
CURRENT[9:8]
R
00
D1
D0
BUCK_LOAD_CURRENT[9:8]
Description
This register describes 3 MSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max 20 A current.
8.6.1.24 I_LOAD_1
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
38
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Bits
Field
Type
7:0
BUCK_LOAD_
CURRENT[7:0]
R
Default
Description
0000 0000 This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 10 mA per LSB and max 20 A current.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP8758 is a multi-phase step-down converter with four switcher cores bundled together.
9.2 Typical Application
4-Phase configuration
0.33PH
VBAT
VIN_B0
SW_B0
VIN_B1
0.33PH
VIN_B2
SW_B1
PF
VIN_B3
PF
PF
PF
PF
CPOL
PF
Load
0.33PH
VANA
SW_B2
AGND
SW_B3
100nF
0.33PH
PF
1.8V IO
PF
SGND
10k:
1.8k:
1.8k:
FB_B0
FB_B1
SDA
SCL
FB_B2
FB_B3
nINT
Host
Processor
NRST
Digital
Control
EN1
EN2
PGND_B23
PGND_B01
Figure 21. LP8758 Typical Application Circuit
9.2.1 Design Requirements
Table 6. Design Parameters
40
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 5.5 V
Output voltage
1.1 V
Converter operation mode
Auto mode (PWM-PFM)
Maximum load current
16 A
Inductor current limit
5A
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9.2.2 Detailed Design Procedure
The performance of the LP8758 device depends greatly on the care taken in designing the printed circuit board
(PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while
proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling capacitors
must be connected close to the device and between the power and ground pins to support high peak currents
being drawn from system power rail during turn-on of the switching MOSFETs. Keep input and output traces as
short as possible, because trace inductance, resistance, and capacitance can easily become the performance
limiting items. The separate power pins VIN_Bx are not connected together internally. The VIN_Bx power
connections shall be connected together outside the package using power plane construction.
9.2.2.1 Application Components
9.2.2.1.1 Inductor Selection
DC bias current characteristics of inductors must be considered. Different manufacturers follow different
saturation current rating specifications, so attention must be given to details. DC bias curves should be requested
from them as part of the inductor selection process. Minimum effective value of inductance to ensure good
performance is 0.22 μH at 4-A bias current over the inductor's operating temperature range. The inductor’s DC
resistance should be less than 0.05 Ω for good efficiency at high current condition. The inductor AC loss
(resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better
efficiency at light load to middle load. See Table 7. Shielded inductors are preferred as they radiate less noise.
Table 7. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS L×W×H
(mm)
DCR (mΩ)
TOKO
DFE252010F-R33M
0.33 µH
2.5 × 2.0 × 1.0
16 (typ), 21 (max)
TDK
VLS252010HBX-R33M
0.33 µH
2.5 × 2.0 × 1.0
25 (typ), 31 (max)
TDK
VLS252010HBX-R47M
0.47 µH
2.5 × 2.0 × 1.0
29 (typ), 35 (max)
TDK
TFM2016GHM-0R47M
0.47 µH
2.0 × 1.6 × 1.0
46 (max)
TOKO
DFE322512C R47
0.47 µH
3.2 × 2.5 × 1.2
21 (typ), 31 (max)
9.2.2.1.2 Input Capacitor Selection
A ceramic input capacitor of 10 μF, 6.3 V is sufficient for most applications. Place the power input capacitor as
close as possible to the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating may
be used to improve input voltage filtering. Use X7R or X5R types, do not use Y5V or F. DC bias characteristics of
ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input
capacitance to ensure good performance is 1.9 μF per buck input at maximum input voltage DC bias including
tolerances and over ambient temp range, assuming that there are at least 22 μF of additional capacitance
common for all the power input pins on the system power rail. See Table 8.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance (ESR)
provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input
filter capacitor with sufficient ripple current rating.
The VANA input is used to supply analog and digital circuits in the device. See recommended components from
Table 9 for VANA input supply filtering.
Table 8. Recommended Power Input Capacitors (X5R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
VOLTAGE
RATING
Murata
GRM188R60J106ME47
10 µF (20%)
0603
1.6 × 0.8 × 0.8
6.3 V
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Table 9. Recommended VANA Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
VOLTAGE RATING
Samsung
CL03A104KP3NNNC
100 nF (10%)
0201
0.6 × 0.3 × 0.3
10 V
Murata
GRM033R61A104KE84
100 nF (10%)
0201
0.6 × 0.3 × 0.3
6.3 V
9.2.2.1.3 Output Capacitor Selection
Use ceramic capacitors, X7R or X5R types; do not use Y5V or F. DC bias voltage characteristics of ceramic
capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias
curves should be requested from them as part of the capacitor selection process. The output filter capacitor
smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient
load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance
and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure
good performance is 10 μF per phase at the output voltage DC bias including tolerances and over ambient temp
range.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 10.
A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as
decreases the PFM switching frequency. For most 4-phase applications 4 x 22 μF 0603 capacitors for COUT are
suitable. A point-of-load (POL) capacitance CPOL can be added with remove feedback as shown in Figure 21.
Although a converter's loop compensation can be programmed to adapt to virtually several hundreds of
microfarads COUT, it is preferable for COUT to be < 200 µF (4-phase configuration). Choosing higher than that is
not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output voltage
ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might
be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the
output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be
longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required
to settle VOUT down as a consequence of the increased time constant.
Table 10. Recommended Output Capacitors (X5R Dielectric)
MANUFACTURER
42
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
Samsung
CL10A226MP8NUNE
22 µF (20%)
0603
1.6 × 0.8 × 0.8
10 V
Murata
GRM188R60J226MEA0
22 µF (20%)
0603
1.6 × 0.8 × 0.8
6.3 V
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VOLTAGE
RATING
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9.2.3 Application Curves
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Unless otherwise specified: VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25 °C, ƒSW = 3 MHz, L = 330 nH
(TOKO DFE252010F-R33M), CPOL = 22 µF. Measurements done with connections in Figure 21.
80
75
70
80
75
70
65
65
60
60
VOUT = 1.2V
VOUT = 1V
VOUT = 0.8V
55
VOUT = 1.2V
VOUT = 1V
VOUT = 0.8V
55
50
50
0
1
2
3
4
5
0
6 7 8 9 10 11 12 13 14 15 16
Output Current (A)
D014
VIN = 3.7 V
2
4
5
6 7 8 9 10 11 12 13 14 15 16
Output Current (A)
D015
Inductor = TDK VLS252010HBX-R47M
Figure 23. Efficiency in Forced PWM Mode
100
95
95
90
90
85
85
Efficiency (%)
100
80
75
70
65
80
75
70
65
60
50
0.001
0.01
0.1
1
Output Current (A)
VIN = 3.7 V
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
60
AUTO
FPWM
FMP
55
55
50
2.5
10 20
VOUT = 1 V
95
90
90
85
85
Efficiency (%)
95
80
75
70
55
3
3.5
4
4.5
Input Voltage (V)
5
5.5
D016
5
80
75
70
65
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
50
2.5
4
4.5
Input Voltage (V)
Figure 25. Efficiency vs Input Voltage
100
60
3.5
Load = 1 A
100
65
3
D002
Figure 24. Efficiency in PFM, PWM and Forced Multi-Phase
Mode
Efficiency (%)
3
VIN = 3.7 V
Figure 22. Efficiency in Forced PWM Mode
Efficiency (%)
1
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
60
55
5.5
50
2.5
3
D017
Load = 8 A
3.5
4
4.5
Input Voltage (V)
5
5.5
D018
Load = 12 A
Figure 26. Efficiency vs Input Voltage
Figure 27. Efficiency vs Input Voltage
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1.005
1.01
1.004
1.008
1.003
1.006
1.002
1.004
Output Voltage (V)
Output Voltage (V)
SNVSA06C – MARCH 2015 – REVISED AUGUST 2018
1.001
1
0.999
0.998
0.997
1
0.998
0.996
0.994
VIN = 2.5V
VIN = 3.7V
VIN = 5.5V
0.996
1.002
VIN = 2.5V
VIN = 3.7V
VIN = 5.5V
0.992
0.995
0.99
0
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
Output Current (A)
D005
0
VOUT = 1 V
0.1
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
D004
VOUT = 1 V
Figure 28. Output Voltage vs Load Current in Forced PWM
Mode
Figure 29. Output Voltage vs Load Current in PWM-PFM
Mode
1.015
1.005
PWM Mode
PFM Mode
1.004
1.010
Output Voltage (V)
1.003
Output Voltage (V)
0.2
1.002
1.001
1
0.999
0.998
1.005
1.000
0.995
0.997
0.996
0.995
2.5
3
3.5
VOUT = 1 V
4
4.5
Input Voltage (V)
5
5.5
D044
Load = 1 A
Figure 30. Output Voltage vs Input Voltage in PWM Mode
0.990
-50
-25
0
25
50
Temperature (qC)
75
100
125
D048
VOUT = 1 V
Load = 3 A (PWM Mode) and 100 mA (PFM Mode)
Figure 31. Output Voltage vs Temperature
5
V(EN1) (500 mV/div)
Phases
4
3
VOUT (200 mV/div)
2
1
V(SW_B0) (2 V/div)
SHEDDING
ADDING
0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
D041
Figure 32. Phase Adding and Shedding vs Load Current
44
Time (40 µs/div)
Load = 0 A
Figure 33. Start-up with EN1, Forced PWM
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V(EN1) (500 mV/div)
V(EN1) (500 mV/div)
VOUT (200 mV/div)
VOUT (200 mV/div)
ILOAD (2 A/div)
ILOAD (2 A/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2 V/div)
Time (40 µs/div)
Time (20 µs/div)
Load = 3 A
Load = 3 A
Figure 34. Start-up with EN1, Forced PWM
Figure 35. Shutdown with EN1, Forced PWM
VOUT (10 mV/div)
VOUT (10 mV/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2 V/div)
Time (40 µs/div)
Time (200 ns/div)
Load = 10 mA
Load = 200 mA
Figure 36. Output Voltage Ripple, PFM Mode
Figure 37. Output Voltage Ripple, Forced PWM Mode
VOUT (10 mV/div)
VOUT (10 mV/div)
V(SW_B0) (1 V/div)
V(SW_B0) (1 V/div)
Time (2 µs/div)
Time (4 µs/div)
Figure 38. Transient from PFM-to-PWM Mode
Figure 39. Transient from PWM-to-PFM Mode
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VOUT (10 mV/div)
VOUT (10 mV/div)
V(SW_B1) (2 V/div)
V(SW_B1) (2 V/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2V/div)
Time (10 µs/div)
Figure 40. Transient from 1-Phase to 2-Phase Operation
Time (10 µs/div)
Figure 41. Transient from 2-Phase to 1-Phase Operation
VOUT (20 mV/div)
VOUT (20 mV/div)
ILOAD (1 A/div)
ILOAD (4 A/div)
Time (40 µs/div)
Load = 0.1 A → 4.1 A → 0.1 A
Time (40 µs/div)
Load = 1 A → 8 A → 1 A
TR = TF = 100 ns
Figure 42. Transient Load Step Response, AUTO Mode
TR = TF = 400 ns
Figure 43. Transient Load Step Response, FPWM Mode
VIN 500 mV/DIV
VOUT (20 mV/div)
VOUT 20 mV/DIV
ILOAD (4 A/div)
Time (40 µs/div)
Load = 1 A → 12 A → 1 A
TIME 400 µs/DIV
TR = TF = 1 µs
Load = 12 A
VIN = 2.5 V → 3 V → 2.5 V
Figure 44. Transient Load Step Response, FPWM Mode
46
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Figure 45. Transient Line Response
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VOUT (200 mV/div)
VOUT (200 mV/div)
Time (400 µs/div)
Time (400 µs/div)
Figure 46. VOUT Transition from 0.6 V to 1.4 V with
Different Slew Rate Settings
Figure 47. VOUT Transition from 1.4 V to 0.6 V with
Different Slew Rate Settings
V(EN1) (1 V/div)
V(nINT) (1 V/div)
VOUT (50 mV/div)
IOUT (5 A/div)
Time (200 µs/div)
Figure 48. Start-up with Short on Output
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input supply
should be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that
the input current transient does not cause too high drop in the LP8758 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP8758 additional bulk capacitance
may be required in addition to the ceramic bypass capacitors.
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11 Layout
11.1 Layout Guidelines
The high frequency and large switching currents of the LP8758 make the choice of layout important. Good power
supply results only occur when care is given to proper design and layout. Layout affects noise pickup and
generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to 10 A and over, good power supply layout is much more difficult than most general
PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage
and current regulation across its intended operating voltage and current range.
1. Place CIN as close to the VIN_Bx pin and the PGND_Bxx pin as possible. Route the VIN trace wide and thick
to avoid IR drops. The trace between the input capacitor's positive node and LP8758’s VIN_Bx pin(s) as well
as the trace between the input capacitor's negative node and power PGND_Bxx pin(s) must be kept as short
as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The
inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic
inductance on these traces must be kept as tiny as possible for proper device operation.
2. The output filter, consisting of Lx and COUTx, converts the switching signal at SW_Bx to the noiseless output
voltage. Place the output filter as close to the device as possible, keeping the switch node small, for best
EMI behavior. Route the traces between the LP8758's output capacitors and the load's input capacitors
direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close to the VANA pin as possible. VANA must be connected to the same power node as
VIN_Bx pins.
4. If the processor load supports remote voltage sensing, connect the LP8758’s feedback pins FB_Bx to the
respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away
from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the
I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short, direct and close to
each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if
possible. TI recommends running the signal as a differential pair.
5. Route PGND_Bxx, VIN_Bx and SW_Bx on thick layers. They must not surround inner signal layers which are
not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. Performing a careful systemlevel 2D or full 3D dynamic thermal analysis at the beginning product design process is strongly recommended,
using a thermal modeling analysis software.
48
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11.2 Layout Example
Via to GND plane
Via to VIN plane
COUT2
L2
COUT3
L3
VIN
GND
CIN2
VIN
VOUT
VIN
CIN0
CIN3
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
SCL
FB
_B2
PGND
_B23
FB
_B3
VANA
SDA
NRST
EN2
nINT
AGND
EN1
FB
_B0
PGND
_B01
FB
_B1
SGND
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
GND
CIN5
VIN
VIN
GND
GND
CVANA
VIN
CIN1
CIN4
Pin A1
VIN
COUT0
L0
COUT1
L1
Figure 49. LP8758 Board Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
AN-1112 DSBGA Wafer Level Chip Scale Package
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
LP8758A1B0YFFR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
35
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
8758A1B0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LP8758A1B0YFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
35
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
2.28
B0
(mm)
K0
(mm)
P1
(mm)
3.03
0.74
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP8758A1B0YFFR
DSBGA
YFF
35
3000
182.0
182.0
20.0
Pack Materials-Page 2
D: Max = 2.91 mm, Min = 2.85 mm
E: Max = 2.16 mm, Min = 2.1 mm
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