Texas Instruments | UCC28780 High Frequency Active Clamp Flyback Controller (Rev. A) | Datasheet | Texas Instruments UCC28780 High Frequency Active Clamp Flyback Controller (Rev. A) Datasheet

Texas Instruments UCC28780 High Frequency Active Clamp Flyback Controller (Rev. A) Datasheet
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UCC28780
SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
UCC28780 High Frequency Active Clamp Flyback Controller
1 Features
3 Description
•
UCC28780 is a high-frequency active-clamp flyback
controller that enables high-density AC-to-DC power
supplies that comply with stringent global efficiency
standards such as DoE Level VI and EU CoC V5
Tier-2. User programmable advanced control law
features allow performance to be optimized for both
Silicon (Si) and Gallium Nitride (GaN) power FETs.
Direct operation with switching devices that combine
driver and GaN FETs is further enhanced with logiclevel gate signals and enable outputs.
Full and Partial Zero Voltage Switching (ZVS) of
Primary FET with Adaptive Control
Programmable Timing for External Si or GaN
FETs
High Switching Frequency up to 1 MHz
Programmable Adaptive Burst Control and
Standby Mode for Light-Load Efficiency with Low
Output Ripple and Audible Noise Mitigation
Brownout Detection without Direct Line Sensing
Accurate Programmable Over-Power Protection
(OPP) to Support Peak Power Mode
Fault Protections: Over-Temperature, Output
Over-Voltage, Output Short-Circuit, Over-Current,
and Pin Fault
Direct Interface with Optocoupler Based Feedback
Allows for Dynamically Scalable Output Voltage
Internal Soft Start
NTC Thermistor Interface with External Enable
1
•
•
•
•
•
•
•
•
•
2 Applications
•
UCC28780 works with VDS-sensing synchronous
rectifier controllers, such as UCC24612, to achieve
higher conversion efficiency and very compact
designs.
High-Density AC-to-DC Adapters for Notebook,
Tablet, TV, Set-Top Box and Printer
USB Power Delivery, Direct and Fast Mobile
Chargers
AC-to-DC or DC-to-DC Auxiliary Power Supply
•
•
Zero voltage switching (ZVS) is achieved over a wide
operating
range
with
advanced
auto-tuning
techniques, adaptive dead-time optimization, and
variable switching frequency control law. Using
adaptive multimode control that changes the
operation based on input and output conditions,
UCC28780 enables high efficiency while mitigating
audible noise. With a variable switching frequency of
up to 1 MHz and accurate programmable over-power
protection, which provides consistent power for
thermal design across wide line range, the size of
passive components can be further reduced and
enable high power density.
Device Information(1)
ORDERABLE
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC28780RTE
WQFN-16
3.00 mm × 3.00 mm
UCC28780D
SOIC-16
10.33 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
DBD
CCLAMP
NP
~
RBLEED
+
±
VO
NPS:1
VBULK
RCCS
VD
Half-bridge Driver
VS
VG
UCC24612
CVDD
ROPP
VDD
VS
RUN
PWMH PWML
NTC
RVS2
GND
RCS
CREG
CS
SWS
HV Startup +
ZVS Sense
CDIFF
RDIFF
HVG
CC/CV
Regulator
RFB
RBUR2
RBUR1
4-Point Avg. Efficiency:
93.9% at 115VAC
92.5% at 230VAC
82
CoC 10%
load
REF
BUR
RBIAS2
RRTZ
DOE Level VI Average
86
RBIAS1
FB
SET
CoC V5 Tier 2 Average
88
84
UCC28780
RDM
RTZ
90
VDD
REG
CHVG
RRDM
230VAC
92
QL
DAUX
RVS1
94
VSW
CBULK
NA
115VAC
CO
QSEC
QH
~
VAUX
96
Efficiency (%)
VAC
45-W, 20-V GaN-ACF Adapter Efficiency
NS
CREF
80
78
Copyright © 2018, Texas Instruments Incorporated
0
25
50
75
100
Output Load (%)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28780
SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.4 Device Functional Modes........................................ 21
1
1
1
2
3
5
8
Application and Implementation ........................ 37
8.1 Application Information............................................ 37
8.2 Typical Application Circuit ....................................... 37
9 Power Supply Recommendations...................... 51
10 Layout................................................................... 52
10.1 Layout Guidelines ................................................. 52
10.2 Layout Example .................................................... 54
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information of SOIC .................................... 6
Thermal Information of WQFN.................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
11 Device and Documentation Support ................. 58
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Detailed Pin Description.......................................... 14
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
58
12 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February, 2018
A
Initial release.
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SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
5 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
1 VDD
REF 16
2 GND
BUR 15
3 CS
RDM 14
4 PWML
RTZ 13
5 PWMH
FB 12
6 RUN
NTC 11
7 SWS
SET 10
8 HVG
VS 9
GND
VDD
REF
BUR
RTE Package
16-Pin WQFN
Top View
16
15
14
13
PWML
2
11
RTZ
PWMH
3
10
FB
RUN
4
9
NTC
5
6
7
8
SET
RDM
VS
12
HVG
1
SWS
CS
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Pin Functions
PIN
TYPE (1)
DESCRIPTION
13
I
This pin is used to program the burst level of the converter at light load. A resistive divider
between REF and GND is used to set a voltage at this pin to determine the peak current level
when the converter enters the adaptive burst mode. In addition, the Thevenin resistance on
BUR pin (equivalent resistance of the divider resistors in parallel) is used to set an offset
voltage for smooth mode transition which increases the peak current level when the converter
enters the low power mode.
3
1
I
This is the current sense input pin. This pin couples through a line-compensation resistor to a
current-sense resistor to sense and control the peak primary current in each switching cycle. A
current sourced from this pin, which magnitude is proportional to the converter’s input voltage
derived from the VS-pin input signal, creates an offset voltage across the line-compensation
resistor to program an OPP level at high line.
FB
12
10
I
The feedback current signal to close the converter’s regulation loop is coupled to this pin. This
pin presents a 4-V output that is designed to have 0-µA to 75-µA current pulled out of the pin
corresponding to the converter operating from full-power to zero-power conditions.
GND
2
16
G
Ground reference and return for all controller signals.
HVG
8
6
O
The high-voltage gate pin is used to control the gate of an external depletion-mode MOSFET
for start-up and switch-node voltage sensing. A 2.2-nF ceramic bypass capacitor to ground is
required.
NTC
11
9
I
This is an interface to an external NTC (negative temperature coefficient) thermistor for remote
temperature sensing. Pulling this pin low shuts down PWM action and initiates a fault
response.
PWMH
5
3
O
The PWMH pin is a logic-level output signal used to control the gate of the high-side clamp
switch through an external gate driver.
PWML
4
2
O
The PWML pin is a logic-level output signal used to control the gate of the low-side primary
switch through an external gate driver.
RDM
14
12
I
A resistor to ground on this pin programs a synthesized demagnetization time used to control
the on-time of the high-side switch to achieve zero voltage switching on the low-side switch.
The controller applies a voltage on this pin that varies with the output voltage derived from the
VS pin signal.
REF
16
14
O
5V reference output that requires a 0.1-µF ceramic bypass capacitor to ground. This reference
is used to power internal circuits and can supply a limited external load current.
RTZ
13
11
I
A resistor to ground on this pin programs an adaptive transition-to-zero delay from the turn-off
edge of the high-side clamp switch to the turn-on edge of the low-side switch.
RUN
6
4
O
This output pin is high when the controller is in a run state. During start-up and wait states this
output is low. It can be used to enable and disable the external gate drivers to reduce the
static power consumption. There is a preset delay, tD(RUN-PWML), of about 2.2 µs that delays
the initiation of PWML switching after this pin has gone high.
SET
10
8
I
This pin is used to configure the controller to be optimized for Gallium Nitride (GaN) power
FETs or silicon (Si) power FETs on the primary side. Depending on setting, it will optimize
parameters of the ZVS control loop, dead-time adjustment, and protection features. When
pulled high to REF pin, it is optimized for Si FETs. When pulled low to GND, it is optimized for
GaN FETs .
SWS
7
5
I
This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal
operation. During start-up, this pin is connected to the VDD pin internally to allow the highvoltage sensing network to provide start-up current.
VDD
1
15
P
Bias power input to the controller. A hold-up capacitor to ground is required for the bias power
supplied from the transformer auxiliary winding to this pin.
VS
9
7
I
This voltage sensing input pin is coupled to the auxiliary winding of the converter’s transformer
via a resistor divider. The pin and the associated external resistors are used to monitor the
output and input voltages of the converter.
NAME
SOIC
WQFN
BUR
15
CS
(1)
4
I = Input, O = Output, P = Power, G = Ground
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SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
Input Voltage
VDD
Source Current
V
–6
VDD-SWS (Run state)
-20
38
CS
–0.3
3.6
NTC
–0.3
7
FB
–0.3
7
VS (Continuous)
–0.75
7
38
–1
7
RTZ
–0.3
7
BUR
–0.3
7
SET
–0.3
7
RDM
–0.3
7
REF
–0.3
7
HVG
–0.3
25
PWML, PWMH, RUN
–0.3
7
V
REF
5
HVG
Self-limiting
VS (Continuous)
mA
2
VS (Transient, 100ns Max.)
Sink Current
UNIT
38
SWS
VS (Transient, 100ns Max.)
Output Voltage
MAX
2.5
FB
1
PWML, PWMH, RUN
1
RTZ
Self-limiting
RDM
Self-limiting
PWML, PWMH, RUN
SWS
1
mA
5
mA
Operating junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
34
UNIT
VVDD
Bias-supply operating voltage
12
CVDD
VDD capacitor
0.3
µF
CREF
REF bypass capacitor
0.1
µF
CHVG
HVG bypass capacitor
2.2
nF
TJ
Operating Junction temperature
-40
125
V
°C
6.4 Thermal Information of SOIC
D
THERMAL METRIC (1)
SOIC
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
83.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.0
°C/W
RθJB
Junction-to-board thermal resistance
42.6
°C/W
ψJT
Junction-to-top characterization parameter
10.9
°C/W
ψJB
Junction-to-board characterization parameter
42.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information of WQFN
RTE + PAD
THERMAL METRIC
(1)
WQFN
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
47.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.9
°C/W
RθJB
Junction-to-board thermal resistance
22.0
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
22.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
6.6 Electrical Characteristics
Over operating free-air temperature range, VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR= 1.2 V, VSET = 0 V, RNTC = 50
kΩ, VVS = 4 V, VSWS = 0 V, IFB = 0 μA, IHVG = 25 μA, and -40 ⁰C < TJ = TA < 125 ⁰C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
BIAS SUPPLY INPUT CURRENT
IRUN(STOP)
Supply current, run
No switching
2.3
3
mA
IRUN(SW)
Supply current, run
Switching, IVSL = 0 µA
2.5
3.3
mA
IWAIT
Supply current, wait
IFB = -85 µA
400
550
µA
ISTART
Supply current, start
VVDD = VVDD(ON) – 100 mV, VVS = 0
V
70
140
µA
IFAULT
Supply current, fault
Fault state
265
350
µA
UNDER-VOLTAGE LOCKOUT (UVLO)
VVDD(ON)
VDD turn-on threshold
VVDD increasing
16.7
17.5
18.2
V
VVDD(OFF)
VDD turn-off threshold
VVDD decreasing
9.35
9.8
10.4
V
VVDD(PCT)
Offset to power cycle for long output
voltage overshoot
Offset above VVDD(OFF), IFB = -85 μA
0.3
1
1.5
V
VVSNC
Negative clamp level
IVSL = -1.25 mA, voltage below
ground
170
250
325
mV
VZCD
Zero-crossing detection (ZCD) level
VVS decreasing
tZC
Zero-crossing timeout delay
tD(ZCD)
Propagation delay from ZCD high to
PWML high
VVS step from 4 V to -0.1 V
IVSB
Input bias current
VVS = 4 V
VCST(MAX)
Maximum CS threshold voltage
VCST(MIN)
tCSLEB
VS INPUT
10
30
55
mV
1.8
2.2
2.7
µs
20
45
ns
-0.25
0
0.25
µA
VCS increasing
765
800
825
mV
Minimum CS threshold voltage
VCS decreasing, IFB = -85 μA
123
150
170
mV
Leading-edge blanking time
VSET = 5 V, VCS = 1 V
175
200
225
ns
VSET = 0 V, VCS = 1 V
115
130
145
15
25
ns
22.5
25
27
A/A
4.4
5
CS INPUT
tD(CS)
Propagation delay of CS comparator VCS step from 0 V to 1 V
high to PWML low
KLC
Line-compensation current ratio
IVSL = -1.25 mA, IVSL / current out of
CS pin
RUN, PWML, PWMH
VPWMLH
High level of PWML, PWMH, and
RUN pins
IPWML(H) = -1 mA, IRUN= -1 mA
Low level of PWML, PWMH, and
RUN pins
IPWML(H) = +1 mA, IRUN = +1 mA
0.5
V
tRISE
Turn-on rise time, 10% to 90% (1)
CLOAD = 10 pF
10
ns
tFALL
Turn-off fall time, 90% to 10% (1)
CLOAD = 10 pF
10
ns
tD(RUN-
Delay from RUN high to PWML high
5.4
µs
VPWMHH
V
VRUNH
VPWMLL
VPWMHL
VRUNL
1.8
PWML)
tD(VS-PWMH) Dead-time between VS high and
PWMH high
VSET = 5 V
44
55
70
ns
tD(PWML-H)
Dead-time between PWML low and
PWMH high
VSET = 0 V
34
42
51
ns
tON(MIN)
Minimum on-time of PWML in low
power mode
VSET = 5 V, IFB = -85 μA, VCS = 1 V
70
90
115
ns
VSET = 0 V, IFB = -85 μA, VCS = 1 V
48
65
80
ns
(1)
Not tested in protection, and limits guaranteed by design.
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Electrical Characteristics (continued)
Over operating free-air temperature range, VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR= 1.2 V, VSET = 0 V, RNTC = 50
kΩ, VVS = 4 V, VSWS = 0 V, IFB = 0 μA, IHVG = 25 μA, and -40 ⁰C < TJ = TA < 125 ⁰C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PROTECTION
VOVP
Over-voltage threshold
VVS increasing
4.4
4.5
4.6
VOCP
Over-current threshold
VCS increasing
0.97
1.2
1.35
VCST(OPP)
Over-power threshold on CS pin
IVSL = 0 μA
574
600
627
IVSL = -333 μA
492
545
595
IVSL = -666 μA
426
460
492
IVSL = -1.25 mA
405
425
452
V
mV
KOPP
OPP threshold voltage ratio
VCST(OPP) ratio between IVSL = 0 μA
and IVSL = -1.25 mA
1.36
1.4
1.44
V/V
tOPP
OPP fault timer
IFB = 0 A
115
160
200
ms
IVSL(RUN)
VS line-sense run current
Current out of VS pin increasing
330
365
400
µA
IVSL(STOP)
VS line-sense stop current
Current out of VS pin decreasing
275
305
335
KVSL
VS line-sense ratio
IVSL(STOP) / IVSL(RUN)
0.81
0.836
0.85
A/A
tBO
Brown-out detection delay time
IVSL < IVSL(STOP)
35
60
75
ms
RRDM(TH)
RRDM threshold for CS pin fault
41
50
59
kΩ
tCSF1
Max. PWML on time for detecting
CS pin fault
VSET = 5 V
1.6
2
2.3
µs
tCSF0
Max. PWML on time for detecting
CS pin fault
RRDM < RRDM(TH) for VSET = 0 V
0.8
1
1.15
µs
tFDR
Fault-reset delay timer
OCP, OPP, OVP, SCP, or CS pin
fault
1
1.5
1.9
s
TJ(STOP)
Thermal shut-down temperature
Internal junction temperature
125
VNTCTH
NTC shut-down voltage
Voltage decreasing
0.9
1.0
1.1
V
RNTCTH
NTC shut-down resistance
RNTC decreasing
8.7
9.5
10.3
kΩ
RNTCR
NTC recovery resistance
RNTC increasing
19.5
21.7
24
kΩ
INTC
NTC pull-up current, out of pin
RNTC = 12 kΩ
85
105
120
µA
VCST between VCST(OPP1) and 0.7 V
°C
NTC INPUT
BUR INPUT AND LOW POWER MODE
KBUR-CST
Ratio from VBUR to VCST
3.9
4
4.13
V/V
fBR(UP)
Upper threshold of burst rate
frequency in adaptive burst mode (1)
29
34
39
kHz
fBR(LR)
Lower threshold of burst rate
frequency in adaptive burst mode (1)
21
25
29
kHz
fLPM
Burst rate frequency in low power
mode
22
25
28
kHz
IBUR
Bias current of VBUR offset in LPM
2.1
2.7
3.4
µA
380
480
565
ns
66
72
86
ns
RTZ INPUT
tZ(MAX)
Maximum programmable dead-time
from PWMH low to PWML high
RRTZ = 280 kΩ, IVSL = -1 mA, VSET =
5V
tZ(MIN)
Minimum programmable dead-time
from PWMH low to PWML high
RRTZ = 78.4 kΩ, IVSL = -1 mA, VSET
=0V
tZ
Dead-time from PWMH low to
PWML high
IVSL = -150 μA
144
172
205
ns
IVSL = -450 μA
123
150
177
ns
IVSL = -733 μA
110
125
145
ns
TZ ratio between IVSL = -200 μA and
IVSL = -733 μA
1.26
1.4
1.57
s/s
KTZ
8
TZ compensation ratio
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Electrical Characteristics (continued)
Over operating free-air temperature range, VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR= 1.2 V, VSET = 0 V, RNTC = 50
kΩ, VVS = 4 V, VSWS = 0 V, IFB = 0 μA, IHVG = 25 μA, and -40 ⁰C < TJ = TA < 125 ⁰C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SWS INPUT
VTH(SWS)
tD(SWS-
SWS zero voltage threshold
VSET = 5 V
8.8
9
9.6
VSET = 0 V
3.7
4
4.3
V
V
12
28
ns
Time between SWS low to PWML
high
VSWS step from 5 V to 0 V
IFB(SBP)
Maximum control FB current
IFB increasing
75
95
µA
VFB(REG)
Regulated FB voltage level
4
4.3
4.65
V
RFBI
FB input resistance
7
8
9.5
kΩ
4.9
5
5.1
V
8
14
PWML)
FB INPUT
REF OUTPUT
VREF
REF voltage level
IREF = 0 A
IS(REF)
Short current of REF pin
Short REF pin
VR(LINE)
Line regulation of VREF
VVDD = 12 V to 35 V
VR(LOAD)
Load regulation of VREF
18
mA
-5
7
mV
IREF = 0 mA to 1 mA, change in
VREF
-10
10
mV
IHVG = +/-200 μA, run state
9.7
10.5
11.4
V
55
90
140
µA
1
1.6
mA
25
mV
HVG OUTPUT
VHVG
HVG voltage level
ISE(HVG)
HVG max sink current during startup VHVG = 13 V, start state
IS(HVG)
Short current of HVG pin
Short HVG pin
0.4
VHR(LINE)
Line regulation of VHVG
VVDD = 12 V to 35 V
-25
VHVG(OV)
HVG over voltage threshold
13.0
13.8
14.6
V
RDM INPUT
tDM(MAX)
Maximum PWMH pulse width with
maximum tuning
VSWS = 12 V
6.08
6.76
7.6
µs
tDM(MIN)
Minimum PWMH pulse width with
minimum tuning
VSWS = 0 V
3.05
3.4
3.8
µs
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6.7 Typical Characteristics
VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VSET = 0 V, and TJ = TA = 25 ⁰C (unless otherwise noted)
10
10
IRUN
IWAIT
IVDD - Bias Supply Current (mA)
IVDD - Bias Supply Current (mA)
IRUN(STOP)
1
IFAULT
0.1
ISTART
0.01
0.001
1
IRUN(WAIT)
ISTART
0.1
0.01
0
5
10
15
20
25
30
35
40
-50
-25
0
25
VVDD - Bias Supply Voltage (V)
Figure 1. VDD Bias-Supply Current vs. VDD Bias-Supply
Voltage
75
100
125
Figure 2. VDD Bias-Supply Current vs. Junction
Temperature
8
395
IVSL(RUN)
6
Variation of Max. and Min. CS Threshold (%)
375
VS Line-Sense Currents (JA)
50
TJ - d u‰ Œ šµŒ ~ö •
355
335
IVSL(STOP)
315
295
4
(VCST(MIN) - 0.15 V) / 0.15 V
2
(VCST(MAX) - 0.8 V) / 0.8 V
0
-2
-4
-6
275
-8
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - d u‰ Œ šµŒ ~ö •
TJ - d u‰ Œ šµŒ ~ö •
Figure 3. VS Line-Sense Currents vs. Temperature
Figure 4. Percentage Variation of Maximum and Minimum
CS Thresholds vs. Temperature
0.65
1.5
KTZ - TZ Compensation Ratio (V/V)
VCS(OPP) - CS Over-Power Threshold (V)
1.4
KTZ at 25öC
0.6
VCST(OPP) at 25öC
VCST(OPP) at -40öC
0.55
VCST(OPP) at 125öC
0.5
0.45
KTZ at -40öC
1.3
KTZ at 125öC
1.2
1.1
1
0.9
0.4
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Figure 5. CS Over-Power Threshold vs. VS Line-Sense
Currents
10
200
400
600
800
1000
1200
1400
1600
IVSL - VS Line-Sense Current (JA)
IVSL - VS Line-Sense Current (mA)
Figure 6. tZ Compensation Ratio (KTZ) vs. VS Line-Sense
Currents
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Typical Characteristics (continued)
VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VSET = 0 V, and TJ = TA = 25 ⁰C (unless otherwise noted)
4.6
5.06
4.56
5.04
VREF - REF Voltage Level (V)
VOVP - VS Over-Voltage Threshold (V)
IREF = 0 A
4.52
4.48
5.02
5
4.98
4.44
4.96
4.4
-50
-50
-25
0
25
50
75
100
-25
0
25
125
50
75
100
125
TJ - d u‰ Œ šµŒ ~ö •
TJ - d u‰ Œ šµŒ ~ö •
Figure 8. REF Voltage vs. Temperature
11
11.5
10.8
11
VHVG - HVG Voltage Level (V)
VHVG - HVG Voltage Level (V)
Figure 7. VS Over-Voltage Threshold vs. Temperature
10.6
10.4
10.5
10
10.2
9.5
-50
-25
0
25
50
75
100
125
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
IHVG - HVG Current (mA)
TJ - d u‰ Œ šµŒ ~ö •
Figure 10. HVG Voltage vs. HVG Current
Figure 9. HVG Voltage vs. Temperature
25
NTC Shutdown and Recovery Resistance (kQ)
23
RNTCR
21
19
17
15
13
11
RNTCTH
9
7
5
-50
-25
0
25
50
75
100
125
TJ - d u‰ Œ šµŒ ~ö •
Figure 11. NTC Thresholds vs. Junction Temperature
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7 Detailed Description
7.1 Overview
The UCC28780 is a transition-mode (TM) active clamp flyback (ACF) controller, equipped with advanced control
schemes to enable significant size reduction of passive components for higher power density and higher average
efficiency. The control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a half-bridge
configuration and is capable of driving high-frequency AC/DC converters up to 1 MHz. The zero voltage
switching (ZVS) control of the UCC28780 is capable of auto-tuning the on-time of a high-side clamp switch (QH)
by using a unique lossless ZVS sensing network connected between the switch-node voltage (VSW) and SWS
pin. The ACF controller is designed to adaptively achieve targeted full-ZVS or partial-ZVS conditions for the lowside main switch (QL) with minimum circulating energy over wide operating conditions. Auto-tuning eliminates the
risk of losing ZVS due to component tolerance, input/output voltage changes, and temperature variations, since
the QH on-time is corrected cycle-by-cycle.
Dead-times between PWML (controls QL) and PWMH (controls QH) are optimally adjusted to help minimize the
circulating energy required for ZVS. Therefore, the overall system efficiency can be significantly improved and
more consistent efficiency can be obtained in mass production of the soft-switching topology. The programming
features of the RTZ, RDM, BUR, and SET pins provide rich flexibility to optimize the power stage efficiency
across a range of output power and operating frequency levels.
The UCC28780 uses four different operating modes to maximize efficiency over wide load and line ranges.
Adaptive amplitude modulation (AAM) adjusts the peak primary current at the higher load levels. Adaptive burst
mode (ABM) modulates the pulse count of each burst packet in the medium to light load range. Low power mode
(LPM) reduces the peak primary current of each two-pulse burst packet in the very light load range. Standby
power (SBP) mode minimizes the loss during no load conditions.
The unique burst mode control of the UCC28780 maximizes the light load efficiency of the ACF power stage,
while avoiding the concerns of conventional burst operation - such as output ripple and audible noise. The burst
control provides an enable signal through the RUN pin to dynamically manage the static current of the half-bridge
driver and also adaptively disables the on-time of QH. These functions can be used to manage the quiescent
power consumed by the half-bridge driver, further improving the converter’s light-load efficiency and reducing its
standby power.
Instead of using a conventional high-voltage resistor, the UCC28780 starts up the VDD supply voltage with an
external high-voltage depletion-mode MOSFET between the SWS pin and the switch node. Fast startup is
achieved with low standby power overhead. Moreover, the HVG pin controls the gate of the depletion-mode FET
to also allow this MOSFET to be used in a lossless ZVS sensing. This arrangement avoids additional sensing
devices.
The UCC28780 also integrates a robust set of protection features tailored to maximize the reliability. These
features include internal soft start, brown in/out, output over-voltage, output over-power, system overtemperature, switch over-current, output short-circuit protection, and pin open/short.
12
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7.2 Functional Block Diagram
OCP FAULT
VDD_OK
UVLO
VVDD(ON) / VVDD(OFF)
VDD
LINE FAULT
OP FAULT
OV FAULT
Power and
Fault Management
HVG FAULT
WAIT
GND
S
R S
+
OTP FAULT
VNTCTH /
VNTCR
INTC
NTC
±
TSH FAULT
Thermal
Shutdown
R
TJ
RUN_EN
QH_EN
PWMH
HVG
SWS
R
S
VCST
S = Start
R = RUN
TZ COMP
Adaptive
ZVS
Control
HVG Regulator
HVG FAULT
S
Q
R
Q
PWML
IVSL
KLC
+
RDM
CS
VCST
±
RTZ
TDM COMP
NVo
Sensing
VS
tCSLEB
OCP FAULT
TZ
+
OV FAULT
±
TUNE
Zero Crossing
Detect
ZCD
SWS
ZVS
Discriminator
SET
OP FAULT
WAIT
OP COMP
Line
Sense
VOCP
Over-Power
Protection
TZ COMP
LINE FAULT
IVSL
FB
ZCD
QH_EN
Control Law
VCST
BUR
NSW END
IBUR
PWML
REF
REF Regulator
WAIT
RUN_EN
Adaptive Burst
Control
RUN
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7.3 Detailed Pin Description
7.3.1 BUR Pin (Programmable Burst Mode)
The voltage at the BUR pin (VBUR) sets a target peak current threshold (VCST(BUR)) which programs the onset of
adaptive burst mode (ABM) and determines the clamped peak current level of switching cycles in each burst
packet. When VBUR is designed higher, ABM will start at heavier output load conditions with higher peak current,
so the benefit is the higher light-load efficiency but the side effect is a larger burst output voltage ripple.
Therefore, 50% to 60% of output load at high line is the recommended highest load condition entering into ABM
(Io(BUR)) for both Si and GaN-based ACF designs. The gain between VBUR and VCST(BUR) is a constant gain of
KBUR-CST, so setting VCST(BUR) just requires properly selecting the resistor divider on the BUR pin formed by RBUR1
and RBUR2. VBUR should be set between 0.7 V and 2.4 V. If VBUR is less than 0.7 V, VCST(BUR) holds at 0.7 V /
KBUR-CST. If VBUR is higher than 2.4 V, VCST(BUR) stays at 2.4 V / KBUR-CST.
RBUR 2
RBUR1K BUR
VREF
K BUR
V
4 u RBUR1VCST ( BUR )
V
5V
CST CST ( BUR )
CST CST ( BUR )
4 u VCST ( BUR )
(1)
In order to enhance the mode transition between ABM and Low Power Mode (LPM), a programmable offset
voltage (ΔVBUR) is generated on top of the VBUR setting in ABM through an internal 2.7-μA current source (IBUR),
as shown in Figure 12. In ABM mode, VBUR is set through the resistor voltage divider to fulfill the target average
efficiency. After transition from ABM to LPM, the current source is enabled in LPM and flows out of the BUR pin,
so ΔVBUR can be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as
'VBUR
I BUR u
RBUR1RBUR 2
RBUR1 RBUR 2
(2)
IO
IBUR
REF
RBUR1
LPM
SBP
BUR
VBUR
ûVBUR
KCST-BURVCST(BUR)
LPM
RBUR2
CBUR
PWMH
Copyright © 2018, Texas Instruments Incorporated
Figure 12. Hysteresis Voltage Generation on BUR Pin
When VBUR becomes higher after transition to LPM, the initial peak magnetizing current in LPM is increased with
larger energy per switching cycle in a burst packet, which forces UCC28780 to stay in LPM with a higher
feedback current than ABM. If ΔVBUR is designed too small, it is possible that mode toggling between LPM and
ABM can occur resulting in audible noise. For that situation, ΔVBUR greater than 100 mV is recommended. To
minimize the noise coupling effect on VBUR, a filter capacitor on the BUR pin (CBUR) may be needed. CBUR needs
to be properly designed to minimize the delay of generating ΔVBUR in time during mode transition. It is
recommended that CBUR should be sized small enough to ensure ΔVBUR settles within 40 μs, corresponding to
the burst frequency of 25 kHz in LPM (fLPM). Based on three RC time constants representing 95% of a settled
steady state value from a step response, the design guide of CBUR is expressed as
CBUR d 40P s u
14
RBUR1 RBUR 2
3RBUR1RBUR 2
(3)
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Detailed Pin Description (continued)
7.3.2 FB Pin (Feedback Pin)
The FB pin connects to the collector of an optocoupler output transistor through an external current-limiting
resistor (RFB). Depending on the operating mode, the controller uses different content of the collector current
flowing out of the FB pin (IFB) to regulate the output voltage. For the operating modes based on peak current
control, IFB is converted into an internal peak current threshold (VCST) to modulate the amplitude of the current
sense signal on the CS pin. For example, when the output voltage (VO) is lower than the regulation level set by
the shunt regulator, the “current level” of IFB moves to lower value, so VCST goes up to deliver more power to the
output load.
As the burst control takes over the VO regulation, where VCST is clamped to VCST(BUR), the “current ripple” of IFB is
used to modulate burst off time, as shown in Figure 13. Specifically, after a group of pulses stop bursting, the
output load current starts to discharge the output capacitor, which makes VO start to decay. A proper type-III
compensation on the secondary side of VO feedback loop minimizes the phase-delay between IFB current ripple
and output voltage ripple. For a detailed design guide on each passive component of the type-III compensator,
please refer to Application and Implementation. When the decaying IFB intersects with an internal reference
current (ITH(FB)), the ripple regulator generates a new set of grouped burst pulses to deliver more power, which
makes VO and IFB ripples move upward.
IFB
ITH(FB)
RUN
PWML
VCST(BUR)
CS
Figure 13. Concept of Burst Control
The nature of ripple-based control in burst mode requires additional care on the noise level of IFB to improve the
consistency of burst off-time between burst cycles. Firstly, a high-quality ceramic-bypass capacitor between FB
pin and REF pin (CFB) is required for decoupling IFB noise. A minimum of 100 pF is recommended. There is an
internal 8-kΩ resistor (RFBI) connected to the FB pin that in conjunction with an external CFB forms an effective
low-pass filter. On the other hand, too strong low-pass filtering with too large CFB can attenuate the IFB ripple
creating slope distortion of the intersection point between IFB and ITH(FB), which can cause inconsistent burst offtimes, even though VO stays in regulation and the IFB noise is low. Secondly, since ABM utilizes the falling-edge
burst-ripple content of IFB to determine the beginning of every burst packet, the operation is affected if the burstripple content of the output voltage is too small due to using a low-ESR output capacitor, or if there is an
additional low-frequency ringing on the output ripple due to using a second-order output filter.
Compared with an electrolytic-type of output capacitor, the advantage of ACF using a low-ESR output capacitor
such as a polymer capacitor is to minimize the switching-ripple content of the output voltage to meet the ripple
specification, but the burst-ripple content is also reduced. Therefore, the switching ripple and noise on IFB may be
very close to ITH(FB), which triggers the next burst event prematurely. For a converter using a second-order output
filter, a π filter design as example, even though both switching-ripple and burst-ripple contents are further
attenuated, additional low-frequency ringing caused by the resonance between the output filter inductor and one
of the output filter capacitors is generated, which may trigger the next burst event too early as well. Therefore,
applying an active ripple compensation (ARC) technique is recommended to generate a noise-free burst ripple
artificially to stabilize the ABM operation of ACF using either a low-ESR output capacitor or a second-order
output filter.
Figure 14 illustrates the implementation of ARC formed by a high-impedance resistor (RCOMP) in series with a
small-signal enhancement MOSFET (QCOMP) where its gate is controlled by the RUN pin of UCC28780. When
RUN pin is in a high state which turns on QCOMP, RCOMP connected to FB pin creates a compensation current
(ICOMP), with a magnitude around VFB / RCOMP. When RUN pin changes to a low state which turns off QCOMP,
RCOMP and the drain-source junction capacitor of QCOMP creates a slow falling edge of ICOMP, with a ramp slope
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Detailed Pin Description (continued)
dependent on the RC time constant. Then, the summation of the current from the optocoupler (IOPTO) and ICOMP
becomes the total feedback current out of FB pin (IFB) to compare with ITH(FB). As the ARC operation in Figure 15
explains, the magnitude of ICOMP helps to push any switching and noise content of IFB away from ITH(FB), and the
slow falling edge of ICOMP further pushes the undesirable ripple content away from ITH(FB), especially the lowfrequency ringing of the π output filter. The magnitude of ICOMP can be adjusted by RCOMP, and 1 MΩ to 2 MΩ is
the recommended value which injects around 2 μA to 4 μA of compensation ripple current into the loop.
VO
REF
IFB
Passive Ripple
Compensation
CFB
IOPTO
VFB(REG)
FB
IFB
RFBI
RFB
ICOMP
RUN
Control
Law
RCOMP
QCOMP
OPTO
COUPLER
Regulator
Active Ripple
Compensation
Copyright © 2018, Texas Instruments Incorporated
Figure 14. Implementation of Active Ripple Compensation (ARC)
IFB
ITH(FB)
ICOMP
IOPTO
Vo
PWML
RUN
Figure 15. Concept of Burst Control with ARC
7.3.3 VDD Pin (Device Bias Supply)
The VDD pin is the primary bias for the internal 5-V REF regulator, internal 11-V HVG regulator, other internal
references, and the undervoltage lock-out (UVLO) circuit. As shown in Functional Block Diagram, the UVLO
circuit connected to the VDD pin controls three power-path switches among VDD, HVG, and SWS pins, in order
to allow QS to be able to perform both VVDD startup and VSW sensing for ZVS control after startup. During startup,
SWS and HVG pins are connected to VDD pin allowing an external depletion-mode MOSFET (QS) to charge the
16
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Detailed Pin Description (continued)
VDD capacitor (CVDD) from the switch-node voltage (VSW). After VDD startup competes, the ZVS discriminator
block is enabled, so as switching logics. Then, the transformer starts delivering energy to the output capacitor
(CO) every switching cycle, so both output voltage (VO) and auxiliary winding voltage (VAUX) increase. As VAUX is
high enough, the auxiliary winding will take over to power VVDD. The UVLO circuit provides a turn-on threshold of
VVDD(ON) at 17.5 V and turn-off threshold of VVDD(OFF) at 9.8 V. The range can accommodate lower values of VDD
capacitor (CVDD) and support shorter power-on delays. 38-V maximum operating level on VVDD alleviates
concerns with leakage energy charging of CVDD and gives added flexibility when a varying output voltage must be
supported.
As VVDD reaches VVDD(ON) , SWS pin is disconnected from the VDD pin, so the CVDD size has to be sufficient to
hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power
delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)) needs to consider the
discharging effect from the sink current of the UCC28780 during switching in its run state (IRUN(SW)), the average
operating current of driver (IDR), and the average gate charge current of half-bridge FETs (IQg) throughout the
longest time of VO soft start (tSS(MAX)).
( I RUN ( SW )
CVDD ( MIN )
I DR
I Qg )tSS ( MAX )
VVDD (ON ) VVDD (OFF )
(4)
tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of ACF, the
constant-current output load (IO(SS)) (if any), maximum output capacitance (CO(MAX)), and a 1-ms time-out
potentially being triggered in the startup sequence.
tSS ( MAX )
CO ( MAX )VO
I SEC ( SS )
I O ( SS )
1ms
(5)
During VO soft start, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so ISEC(SS) at the
minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:
I SEC ( SS )
N PSVCST ( MAX )
2 RCS
VBULK ( MIN )
VBULK ( MIN )
N PS (VO VF )
(6)
where RCS is the current sense resistor, NPS is primary-to-secondary turns ratio, and VF is the forward voltage
drop of the secondary rectifier.
For details of the startup sequencing, one can refer to the Device Functional Modes of this datasheet.
7.3.4 REF Pin (Internal 5-V Bias)
The output of the internal 5-V regulator of the controller is connected to this pin. It requires a high-quality
ceramic-bypass capacitor (CREF) to GND for decoupling switching noise and lowering the voltage droop as the
controller transitions from wait state to run state. The minimum CREF value is 0.1 μF, and a high quality dielectric
material should be used, such as a X7R. The output short current (IS(REF)) of the REF regulator is self-limited to
approximately 14 mA. 5-V bias is only available after the under-voltage lock-out (UVLO) circuit enables the
operation of UCC28780 after VVDD reaches VVDD(ON).
7.3.5 HVG and SWS Pins
The HVG pin provides a controlled voltage to the gate of the depletion-mode MOSFET (QS), enabling QS to
serve both VVDD startup and lossless ZVS sensing from the high-voltage switch node (VSW). During VVDD startup,
the UVLO circuit commands two power-path switches connecting SWS and HVG pins to VDD pin with two
internal current-limit resistors (RDDS and RDDH) separately, as shown in Figure 16. In this configuration, QS
behaves as a current source to charge the VDD capacitor (CVDD). RDDS is set at 12 kΩ when VVDD is below 1 V to
limit the maximum fault current under VDD pin short events. RDDS is reduced to 1 kΩ when VVDD rises above 1 V
to allow VVDD to charge faster. The maximum charge current (ISWS) is affected by RDDS, the external series
resistance (RSWS) from SWS pin to QS, and the threshold voltage of QS (VTH(Qs)). ISWS can be calculated as
I SWS
VTH (Qs )
RDDS
RSWS
(7)
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Detailed Pin Description (continued)
CVDD
UVLO
VDD
ISWS
RDDS
RSWS
SWS
VSW
+
VTH(Qs)
- QS
RDDH
HVG
CHVG
Copyright © 2018, Texas Instruments Incorporated
Figure 16. Operation of the VDD Startup Circuit
After VVDD reaches VVDD(ON), the two power-path switches open the connections among SWS, HVG, and VDD
pins. At this point, a third power-path switch connects an internal 11-V regulator to the HVG pin for configuring
QS to perform lossless ZVS sensing. As QS gate is fixed at 11 V and the drain pin voltage of QS becomes higher
than the sum of QS threshold voltage (VTH(Qs)) and the 11-V gate voltage, QS turns off and the source pin voltage
of QS can no longer follow the drain pin voltage change, so this gate control method makes QS act as a highvoltage blocking device with the drain pin connected to VSW. When the controller is switching, VSW can be lower
than 11 V, so QS turns on and forces the source pin voltage to follow VSW, becoming a replica of the VSW
waveform at the lower voltage level, as illustrated in Figure 17.
The limited window for monitoring the VSW waveform suffices for ZVS control of the UCC28780, since the ZVS
tuning threshold (VTH(SWS)) is lower than that, which is at 9 V for VSET = 5 V and at 4 V for VSET = 0 V. The 9-V
threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial ZVS condition
on the ACF using Si primary switches. On the other hand, performing full ZVS operation is more suitable for the
ACF with GaN primary switches. The 4-V threshold can help to better compensate sensing delay between VSW
and the SWS pin more than using a 0-V threshold. The internal 11-V regulator requires a high quality ceramic
bypass capacitor (CHVG) between the HVG pin and GND for noise filtering and providing compensation to the
regulator circuitry. The minimum CHVG value is 2.2 nF and an X7R-type dielectric capacitor is recommended. The
controller enters a fault state if the HVG pin is open or shorted to GND during VVDD start-up, or if VHVG overshoot
is higher than VHVG(OV) of 13.8 V in run state. The output short current of HVG regulator (IS(HVG)) is self-limited to
around 1mA.
CVDD
VDD
VSW
RSWS
ZVS
Discriminator
SWS
VSW
+
VTH(Qs)
- QS
HVG
11-V Regulator
VBULK+NPS(VO+VF)
VSWS
11V+VTH(Qs)
CHVG
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Figure 17. ZVS Sensing by Reusing the VDD Startup Circuit
18
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Detailed Pin Description (continued)
7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
The dead-time between PWMH falling edge and PWML rising edge (tZ) serves as the wait time for VSW transition
from its high level down to the target ZVS point. Since the optimal tZ varies with VBULK, the internal dead-time
optimizer automatically extends tZ as VBULK is less than the highest voltage of the input bulk capacitor
(VBULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line versus
a fixed dead-time over a wide line voltage range. A resistor on RTZ pin (RRTZ) programs the minimum tZ (tZ(MIN))
at VBULK(MAX), which is the sum of the propagation delay of the high-side driver (tD(DR)) and the minimum resonant
transition time of VSW falling edge (tLC(MIN)).
RRTZ
KTZ u tZ ( MIN )
KTZ u (tD ( DR )
11
tLC ( MIN ) )
(8)
-1
11
-1
where KTZ is equal to 11.2×10 (unit: F ) for VSET = 0 V, and 5.6×10 (unit: F ) for VSET = 5 V. As illustrated in
Figure 18, after PWMH turns off QH after tD(DR) delay, the negative magnetizing current (iM-) becomes an initial
condition of the resonant tank formed by magnetizing inductance (LM) and the switch-node capacitance (CSW).
CSW is the total capacitive loading on the switch-node, including all junction capacitance (COSS) of switching
devices, stray capacitance of the boot-strap diode, intra-winding capacitance of the transformer, the snubber
capacitor, and parasitic capacitance of the PCB traces between switch-node and ground. Unlike a conventional
valley-switching flyback converter, the resonance of an active clamp flyback converter at high line does not begin
at the peak of the sinusoidal trajectory. The transition time of VSW takes less than half of the resonance period.
The following tLC(MIN) expression quantifies the transition time for RRTZ calculation, where an arccosine term
represents the initial angle at the resonance beginning. The value of π minus the arccosine term at VBULK(MAX) of
375 V, VO of 20 V, and NPS of 5 is around 0.585π, which is close to one quarter of the resonance period.
tLC ( MIN )
[S
cos 1 (
N PS (VO VF )
)] u LM CSW
VBULK ( MAX )
(9)
VSW
NPS(VO+VF)
VBULK(MAX)
IM
tD(DR)
PWMH
PWML
IMtLC(MIN)
tZ(MIN)
Figure 18. RTZ Setting for the Falling-edge Transition of VSW
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Detailed Pin Description (continued)
7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
The RRDM resistor provides the power stage information to the tDM optimizer for auto-tuning the on-time of PWMH
to achieve ZVS within a given tZ discharge time. The following equation calculates the resistance, based on the
knowledge of the primary magnetizing inductance (LM), auxiliary-to-primary turns ratio (NA/NP), the values of the
resistor divider (RVS1 and RVS2) from the auxiliary winding to VS pin, and the current sense resistor (RCS). Among
those parameters, LM contributes the most variation due to its typically wider tolerance. The optimizer is
equipped with wide enough on-time tuning range of PWMH to cover tolerance errors. Therefore, just typical
values are enough for the calculation.
RRDM
N A RVS 2
K DM LM
N P ( RVS 1 RVS 2 ) RCS
9
(10)
-1
where KDM is equal to 5×10 (unit: F ) for both VSET = 5 V and 0 V.
7.3.8 RUN Pin (Driver Enable Pin)
The RUN pin is a logic-level output signal to enable the gate driver. It generates a 5-V logic output when the
driver should be active, and pulls down to less than 0.5 V when the driver should be disabled. During burst mode
operation, the RUN pin serves as a power management function to dynamically reduce the static current of the
driver, so light-load efficiency can be further improved and standby power can be minimized. In addition, there
are two delays between RUN going high to first PWML pulse going high in each burst packet. The first delay is a
fixed 2.2-μs delay time, intended to provide an appropriate wake-up time for UCC28780 and the gate driver to
transition from a wait state to a run state. The second delay is another 2.2-μs timeout, tZC in the electrical table,
intended to turn on the low-side switch of the first switching cycle per burst packet around the valley point of
DCM ringing by waiting for the zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX). Therefore,
the minimum total delay time is 2.2 μs typically if ZCD is detected immediately after the first 2.2-μs wake-up time,
while the maximum total delay time is 4.4 μs if ZCD is not triggered after the timeout. The total delay time with
tolerance over temperature are listed as tD(RUN-PWML) in the electrical table. RUN pin can also be used to control
the external active ripple compensation network to enhance the stability of the burst regulation loop.
7.3.9 SET Pin
Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation
delays of their drivers, SET pin is provided to program critical parameters of UCC28780 for the two distinctive
power stages. Firstly, this pin sets the zero voltage threshold (VTH(SWS)) at the SWS input pin to be two different
auto-tuning targets for ZVS control. When SET pin is tied to GND, VTH(SWS) is set at its low level of 4 V for
realizing full ZVS, which allows the low-side switch (QL) to be turned on when the switch-node voltage drops
close to 0 V. When SET pin is tied to REF pin, VTH(SWS) is set at 9 V for implementing partial ZVS, which makes
QL turn on at around 9V. Secondly, this pin generates different PWML-to-PWMH dead-time (tD(PWML-H)) to achieve
ZVS on the high-side clamp switch (QH). A fixed 40ns for VSET = 0 V and an adaptive adjustment for VSET = 5 V.
Thirdly, this setting also selects the current sense leading edge blanking time (tCSLEB) to accommodate different
delays of the gate drivers; 130 ns for VSET = 0 V and 200 ns for VSET = 5 V. Fourthly, the minimum PWML ontime (tON(MIN)) in low-power mode and standby-power mode varies based on the driver capability; 65 ns for VSET =
0 V and 90 ns for VSET = 5 V. Finally, the maximum PWML on-time for detecting CS pin fault (tCSF). tCSF for VSET
= 5 V (tCSF1) is set at 2 μs. tCSF for VSET = 0 V (tCSF0) depends on RRDM, which is configured to 1 μs under RRDM <
RRDM(TH) and to 2 μs under RRDM ≥ RRDM(TH).
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7.4 Device Functional Modes
7.4.1 Adaptive ZVS Control with Auto-Tuning
Figure 19 shows the simplified block diagram explaining the ZVS control of UCC28780. A high-voltage sensing
network provides the replica of the switch node voltage waveform (VSW) with a limited “visible” voltage range that
the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment
direction for the on-time of PWMH (tDM) by detecting if VSW reaches a predetermined ZVS threshold, VTH(SWS),
within tZ, where tZ is the targeted zero voltage transition time of VSW controlled by the PWMH-to-PWML deadtime optimizer.
In Figure 19, VSW of the current switching cycle in the dashed line has not reached VTH(SWS) after tZ expires. The
ZVS discriminator sends a TUNE signal to increase tDM for the next switching cycle in the solid line, such that the
negative magnetizing current (IM-) can be increased to bring VSW down to a lower level in the same tZ. After a few
switching cycles, the tDM optimizer settles and locks into ZVS operation of the low-side switch (QL). In steadystate, there is a fine adjustment on tDM, which is the least significant bit (LSB) of the ZVS tuning loop. This small
change of tDM in each switching cycle is too small to significantly move the ZVS condition away from the desired
operating point. Figure 20 demonstrates how fast the ZVS control can lock into ZVS operation. Before the ZVS
loop is settled, UCC28780 starts in a valley-switching mode as tDM is not long enough to create sufficient IM-.
Within 15 switching cycles, the ZVS tuning loop settles and begins toggling tDM with an LSB.
tD(PWML-H)
VCST
IM / RCS
LK
VBULK
DSEC
NP:NS
VO
IM
PWML
RCo
PWMH
CCLAMP
tDM
Adaptive ZVS Control
LM
SET
VS
RO
CO
QH
RTZ
PWMH
RDM
tDM
Optimizer
SET
Dead-Time Optimizer
(tD(PWML-H) and tZ)
PWML
tZ
QL
Driver
VSW
TUNE
RCS
tZ
Peak Current
Loop
VTH(SWS)
VCST
ZVS Discriminator
SET
PWMH
SWS
HV Sense
PWML
HVG
Copyright © 2018, Texas Instruments Incorporated
Figure 19. Block Diagram of Adaptive ZVS Control
PWML
PWMH
1.2
0.8
IM (A)
0.4
0
18
12
VSWS (V)
6
VTH(SWS)
0
400
VSW (V)
300
200
100
0
5 µs/div
VSWS (V)
VSW (V)
12
12
12
6
6
6
0
0
0
400
400
400
200
200
200
0
0
0
Figure 20. Auto-Tuning Process of Adaptive ZVS Control
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Device Functional Modes (continued)
7.4.2 Dead-Time Optimization
The dead-time optimizer in Figure 19 controls the two dead-times: the dead-time between PWMH falling edge
and PWML rising edge (tZ), as well as the dead-time between PWML falling edge and PWMH rising edge
(tD(PWML-H)).
The adaptive control law for tZ of UCC28780 utilizes the line feed-forward signal to extend tZ as VBULK reduces,
as shown in Figure 21. The VS pin senses VBULK through the auxiliary winding voltage (VAUX) when the low-side
switch (QL) is on. The auxiliary winding creates a line-sensing current (IVSL) out of the VS pin flowing through the
upper resistor of the voltage divider on VS pin (RVS1). Minimum tZ (tZ(MIN)) is set at VBULK(MAX) through the RTZ
pin. When IVSL is lower than 666 μA, tZ linearly increases and the maximum tZ extension is 140% of tZ(MIN).
tZ(IVSL)
140%
tZ(MIN)
100%
233 µA
IVSL
666 µA
Figure 21. tZ Control Optimized for Wide Input Voltage Range
The control law for tD(PWML-H) of UCC28780 is programmable based on the SET pin voltage. When VSET = 0 V, a
fixed delay around 40 ns is used to fit a GaN-based ACF with a fast dV/dt on the VSW rising edge. With VSET = 5
V, the dead-time optimization is enabled to intelligently adapt to the effect of nonlinear junction capacitance of Si
MOSFETs on the dV/dt of VSW rising edge. The high capacitance region of the COSS curve for the Si QL creates a
shallow ramping on VSW after PWML turns off. When COSS of Si QL moves to the low capacitance region with
VSW increasing, VSW starts to ramp up very quickly. Since the changing slope varies with different peak
magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on
the high-side clamp switch (QH) if the dead-time is not long enough. UCC28780 utilizes the zero crossing detect
(ZCD) signal on the auxiliary-winding voltage to identify if VSW overcomes the shallow ramping, and generates a
50-ns delay (tD(VS-PWMH)) before turning on PWMH. This feature allows cycle-by-cycle dead-time adjustment to
avoid hard-switching of QH, while providing fast turn-on timing for QH to minimize the body-diode conduction time.
Si FET (VSET = 5 V)
GaN FET (VSET = 0 V)
Heavy Load
Light Load
Heavy Load
Light Load
VSW
VSW
0V
VAUX
40-ns
delay
ZCD
PWML
50-ns
delay
tD(VS-PWMH)
PWMH
tD(PWML-H)
PWML
PWMH
tD(PWML-H)
tD(PWML-H)
Figure 22. tD(PWML-H) Control Optimized for GaN and Si FETs
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Device Functional Modes (continued)
7.4.3 Control Law across Entire Load Range
UCC28780 contains four modes of operation summarized in Table 1. Starting from heavier load, the AAM mode
forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a group
of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output voltage. At
the same time, the burst frequency variation is confined above 20kHz by adjusting the number of PWML and
PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In LPM and SBP modes,
PWMH and the ZVS tuning loop are disabled, so the converter operates in valley-switching.
Table 1. Functional Modes
PWMH
ZVS
AAM
Adaptive
Amplitude
Modulation
MODE
ACF operation with PWML and PWMH in complementary
switching
OPERATION
Enabled
Yes
ABM
Adaptive Burst
Mode
Variable fBUR > 20 kHz, ACF operation in complementary
switching
Enabled
Yes
LPM
Low Power Mode
Fix fBUR ≈ 25 kHz, valley-switching
Disabled
No
SBP
StandBy Power
Variable fBUR < 25 kHz, valley-switching
Disabled
No
Figure 23 addresses the critical parameter changes among the four operating modes, where VCST is the peak
current threshold compared with the current-sense voltage from CS pin, fSW is the switching frequency of PWML,
fBUR is the burst frequency, and NSW is the pulse number of PWML per burst packet. The following section
explains the detailed operation of each mode.
VCST
SBP
LPM
ABM
AAM
VCST(OPP)
VCST(BUR)
VCST(MIN)
IO
Frequency
fSW
fBUR
fBUR(UP)
fLPM
fBUR(LR)
IO
NSW
9
2
IO(BUR)
IO(OPP)
IO
Figure 23. Control Law Over Entire Load Range
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7.4.4 Adaptive Amplitude Modulation (AAM)
The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time
in between, as shown in Figure 24. As the load current reduces, the negative magnetizing current (IM-) stays the
same, while the positive magnetizing current (IM+) reduces by the internal peak current loop to regulate the output
voltage. IM+ generates a current-feedback signal (VCS) on CS pin through a current-sense resistor (RCS) in series
with QL, and a peak current threshold (VCST) in the current loop controls the peak current variation. Due to the
nature of transition-mode (TM) operation, lowering the peak current with lighter load conditions results in higher
switching frequency. When the load current increases to an over-power condition (IO(OPP)) where VCST
correspondingly reaches an OPP threshold (VCST(OPP)) of the peak current loop, the OPP fault response will be
triggered after a 160-ms timeout. The RUN signal stays high in AAM, so the half-bridge driver remains active.
Heavy Load
IM
Light Load
0A
IM-
PWML
PWMH
RUN
Figure 24. PWM Pattern in AAM
7.4.5 Adaptive Burst Mode (ABM)
As the load current reduces to IO(BUR) where VCS reaches to VCST(BUR) threshold, ABM starts and VCS is clamped.
The peak magnetizing current and the switching frequency (fSW) of each switching cycle are fixed for a given
input voltage level. VCST(BUR) is programmed by the BUR pin voltage (VBUR). The PWM pattern of ABM is shown
in Figure 25. When RUN goes high, a delay time between RUN and PWML (tD(RUN-PWML)) is given to allow both
the gate driver and the UCC28780 time to wake up from a wait state to a run state. PWML is set as the first
pulse to build up the bootstrap voltage of the high-side driver before PWMH starts switching. The first PWML
pulse turns on QL close to a valley point of the DCM ringing on the switch-node voltage (VSW) by sensing the
condition of zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX). The following switching cycles
operate in a ZVS condition, since PWMH is enabled. As the number of PWML pulses (NSW) in the burst packet
reaches its target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces
the half-bridge driver and UCC28780 into a wait state for the quiescent current reduction of both devices. In this
mode, the minimum off-time of the RUN signal is 2.2 µs and the minimum on-time of PWML is limited to the
leading-edge blanking time (tCSLEB) of the peak current loop. However, more grouped pulses means more risk of
higher output ripple and higher audible noise. The following equation estimates how burst frequency (fBUR) varies
with output load and other parameters.
f BUR
IO
I O ( BUR )
f SW
N SW
(11)
As IO < IO(BUR), fBUR can become lower than the audible noise range if NSW is fixed. In ABM, NSW is modulated to
ensure fBUR stays above 20 kHz by monitoring fBUR in each burst period. As IO reduces, fBUR becomes lower and
reaches a predetermined low-level frequency threshold (fBUR(LR)) of 25 kHz. The ABM loop commands Nsw of
both PWML and PWMH to be reduced by one pulse to maintain fBUR above fBUR(LR). At the same time, the burst
frequency ripple on the output voltage reduces as NSW drops with the load reduction. As IO increases, fBUR
becomes higher and reaches a predetermined high-level frequency threshold (fBUR(UP)) of 34 kHz. The ABM loop
commands NSW to be increased by one pulse to push fBUR back below fBUR(UP).
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This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also
limiting the burst output ripple and audible noise. As IO moves below the boundary between AAM and ABM, the
maximum NSW is nine and the minimum NSW is two. As IO is close to the boundary between AAM and ABM, the
maximum NSW can be higher than nine, to provide a smoother mode transition. When the load slightly increases
in this boundary, more than nine pulses are generated in a burst packet as Figure 26 shows. fBUR starts to move
lower than 20kHz. The burst pattern with disordered NSW and inconsistent fBUR among the asymmetric burst
packets generates a frequency spreading effect to weaken the strength of potential audible noise, when the
controller operates in the transition region. It is found that dip varnishing the transformer is a very effective way to
mitigate the minor audible noise around the mode transition. ABM operation with lower peak magnetizing current
through lower BUR-pin voltage can also help to minimize the potential audible noise. Generally speaking,
entering ABM at around 50 to 60% of output load and using a varnished transformer provides good balance
between the light-load efficiency and smooth mode transitions with minimal audible noise.
tD(RUN-PWML)
VCST(BUR) / RCS
IM
0A
fSW
ZCD
through Vaux
ZVS
tCSLEB
PWML
fBUR
PWMH
2.2 µs
RUN
Figure 25. PWM Pattern in ABM
RUN
PWML
PWMH
Output load increasing
RUN
PWML
PWMH
RUN
PWML
PWMH
RUN
PWML
PWMH
RUN
PWML
PWMH
Figure 26. Mode Transition Behavior between AAM and ABM
7.4.6 Low Power Mode (LPM)
As NSW drops to two in ABM and the condition of fBUR less than fBUR(LR) is qualified under two consecutive burst
periods, UCC28780 enters into LPM mode and disables PWMH. The purpose of LPM is to provide a soft peak
current transition between VCST(BUR) and VCST(MIN). LPM fixes NSW at two and sets fBUR equal to fLPM of 25 kHz. In
LPM mode, VCST is controlled to regulate the output voltage. At the start of each burst packet, after RUN pulls
high, tD(RUN-PWML) is used to wake up both the gate driver and UCC28780. With PWMH disabled, the two PWML
pulses turn on QL close to valley-switching by sensing ZCD. When ZCD is detected again at the end of the
second pulse, the RUN pin goes low and the UCC28780 enters its low-power wait state. In LPM mode, the
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minimum on-time of PWML can be further reduced to tON(MIN), to allow the peak magnetizing current to be
reduced beyond the level limited by tCSLEB of the peak current loop. In this condition, operation of the LPM control
loop is changed from a current-mode control to a voltage-mode control, so the on-time adjustment of PWML is
not limited to tCSLEB. With this feature, before fBUR starts to fall below fLPM and enters the audible frequency range
of SBP mode, the peak current is low enough to limit the magnitude of audible excitation.
tD(RUN-PWML)
VCST(BUR) / RCS
VCST(MIN) / RCS
IM
0A
tON(MIN)
ZCD through VAUX
PWML
fBUR = fLPM
PWMH
RUN
Figure 27. PWM Pattern in LPM
7.4.7 Standby Power Mode (SBP)
As VCST drops to VCST(MIN), UCC28780 enters into SBP mode and PWMH continues to stay disabled. The
purpose of SBP is to lower fBUR in order to minimize standby power. SBP fixes NSW at two and VCST to VCST(MIN),
while the burst off-time is adjusted to regulate the output voltage. As fBUR is well below fLPM, the switching-related
loss can be minimized. In addition, lowering fBUR forces both the gate driver and UCC28780 to remain in wait
states longer to minimize the static power loss. The equivalent static current of the UCC28780 in SBP can be
represented as
IVDD ( SBP )
( I RUN
IWAIT )(
2
f SW ( SBP )
tD ( RUN
PWML )
) f BUR
IWAIT
(12)
tD(RUN-PWML)
VCST(MIN) / RCS
IM
tON(MIN)
PWML
fBUR
PWMH
RUN
IRUN
IWAIT
IVDD
Figure 28. PWM Pattern in SBP
7.4.8 Startup Sequence
Figure 29 shows the simplified block diagram related with the VDD startup function of UCC28780, and Figure 30
addresses the startup sequence. The detailed description on the startup waveforms is :
1. Time interval A: The UVLO circuit commands the two internal power-path switches (QDDS and QDDH) to build
connections among SWS, VDD, and HVG pins through two serial current-limiting resistors (RDDS and RDDH).
The depletion-mode MOSFET (QS) starts sourcing charge current (ISWS) safely from the high-voltage switchnode voltage (VSW) to the VDD capacitor (CVDD). Before VVDD reaches 1 V, ISWS is limited by the highresistance RDDS of 12 kΩ to prevent potential device damage if CVDD or VDD pin is shorted to ground.
2. Time interval B: After VVDD rises above 1 V, RDDS is reduced to a smaller resistance of 1 kΩ. ISWS is
increased to charge CVDD faster. The maximum charge current during VDD startup can be quantified by
Equation 7.
3. Time interval C: As VVDD reaches VVDD(ON) of 17.5 V, the ULVO circuit turns-off QDDS to disconnect the
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4.
5.
6.
7.
8.
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source pin of QS to CVDD, and turns-off QDDH to break the gate-to-source connection of QS, so QS loses its
current-charge capability. VDD then starts to drop, because the 5-V regulator on REF pin starts to charge up
the reference capacitor (CREF) to 5 V, which maximum charge current (ISE(REF)) is self-limited at around 14
mA. After VREF is settled, the UVLO circuit turns-on another power-path switch (Q11H), so an internal 11-V
regulator is connected to the HVG pin. The voltage on the HVG pin capacitor (CHVG) starts to be discharged
by the regulator.
Time interval D: During discharging CHVG of the recommended 2.2 nF, the sink current of the 11-V regulator
(ISE(HVG)) is self-limited at around 90 μA, so it takes longer than 25 μs for settling to 11 V. If VHVG reaches 11
V in less than 10 to 25 μs, the HVG pin open fault is triggered to protect the device. Once VHVG is settled to
11 V without the fault event, RUN pin goes high and UCC28780 enters a run state with IVDD = IRUN.
Time interval E: There is a 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up
the gate driver and UCC28780.
Time interval F: This is the soft-start region of peak magnetizing current. The first purpose is to limit the
supply current if the output is short. The second purpose is to push the switching frequency higher than the
audible frequency range during repetitive startup situations. At the beginning of VO soft-start, the peak
current is limited by two VCST thresholds. The first VCST startup threshold (VCST(SM1)) is clamped at 0.28 V and
the following second threshold (VCST(SM2)) is 0.6 V. When VCST = VCST(SM1), PWMH is disabled if the VS pin
voltage (VVS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After VVS
exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from
VCST(SM1) to VCST(SM2). In case of the inability to build up VO with VCST(SM1) at the beginning of the VO soft-start
due to excessively large output capacitor and/or constant-current output load, there is an internal time-out of
1ms to force VCST to switch to VCST(SM2).
Time interval G: When VVS rises above 0.6 V, VCST is allowed to reach VCST(MAX) of 0.8 V, so the rising rate
of VO startup becomes faster. When PWML is in a high state, IVDD can be larger than IRUN, because the 5-V
regulator provides the line-sensing current pulse (IVSL) on the VS pin to sense VBULK condition.
Time interval H: VO and VCST settle, and the auxiliary winding takes over the VDD supply. There is a
switching ripple on CHVG during PWML switching, due to the dV/dt coupling of VSW through the junction
capacitance of QS. UCC28780 provides an over-voltage protection on HVG pin to avoid the risk of high
overshoot under high dV/dt conditions. The over-voltage threshold of HVG pin (VHVG(OV)) is 13.8V.
DAUX
VAUX
ISWS
IVDD
QDDS
VDD
RSWS
RDDS
QS
SWS
VSW
DSWS
CSWS
CVDD
5-V
Regulator
NA
IREF
REF
UVLO
11-V
Regulator
RHVG
QDDH
RDDH
HVG
Q11H
CHVG
IHVG
CREF
DHVG
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Figure 29. Functional Startup Block Diagram
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VVDD(ON)
VTH(Qs)
VVDD(OFF)
VVDD
VHVG
VHVG(OV)
11V
VREF
1V
IHVG
ISE(HVG)
ISWS
RUN
PWML
IVSL
IRUN
IVDD
VCST(SM2)
VCST(MAX)
VCST
VCST(SM1)
VO
(A)
(B)
(C)
(D)
(E)
(F)
(G)
(H)
Figure 30. Startup Timing Waveforms
7.4.9 Survival Mode of VDD
When the output voltage overshoot occurs during step-down load transients, the VO feedback loop commands
the UCC28780 to stop switching quickly through increasing IFB, in order to prevent additional energy from
aggravating the overshoot. Since VVDD keeps dropping during this time, the conventional way to prevent a
controller from shutting down is to oversize the VDD capacitor so as to hold VVDD above VVDD(OFF). Instead,
UCC28780 is equipped with the survival-mode operation to hold VVDD above VVDD(OFF) during the transient event,
so the size of VDD capacitor can be significantly reduced and the PCB footprint for the auxiliary power can be
minimized. Specifically, there is a ripple comparator to regulate VVDD above a 11-V threshold, which is VVDD(OFF)
plus VVDD(PTC) in the electrical table. The ripple regulator is enabled when the VO feedback loop requests the
UCC28780 to stop switching due to VO overshoot.
The regulator initiates unlimited PWML pulses when VVDD drops lower than 11 V, and stops switching after VVDD
rises above 11 V. Since VVDD is lower than the reflected output voltage overshoot, most of the magnetizing
energy is delivered to the auxiliary winding and brings VVDD above the 11-V threshold quickly. After VO moves
back to the regulation level, VO feedback loop forces the UCC28780 to begin switching again by reducing IFB,
and the PWML and PWMH pulses are then controlled by the normal operating mode.
To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival
mode at zero load, some guidelines on the auxiliary power delivery path to VDD can be considered:
1. The normal VVDD level under regulated VO must be away from the 11-V threshold.
2. VDD capacitor should not be over-sized, but designed just big enough to hold VVDD > VVDD(OFF) under the
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longest VO soft-start time.
3. The current-limiting resistor (RVDD1) in series with the auxiliary rectifier diode (DAUX) should not be too large,
so the delivery path with lower series impedance can help the VDD capacitor charge faster.
4. Ensure good coupling between the auxiliary winding (NAUX) and the secondary winding (NS) of the
transformer.
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7.4.10 System Fault Protections
The UCC28780 provides extensive protections on different system fault scenarios. The protection features are
summarized in Table 2.
Table 2. System Fault Protection
PROTECTION
SENSING
THRESHOLD
DELAY TO ACTION
ACTION
VDD UVLO
VDD
voltage
VVDD(OFF) ≤ VVDD ≤ VVDD(ON)
None
UVLO reset
Over-power
protection (OPP)
CS voltage
VCST(OPP) ≤ VCST ≤ VCST(MAX)
tOPP (160 ms)
tFDR restart (1.5s)
Peak current limit
(PCL)
CS voltage
VCST ≤ VCST(MAX)
Over-current
protection (OCP)
CS voltage
VCS ≥ VOCP
3 PWML pulses
tFDR restart
Output short-circuit
protection (SCP)
CS, VS,
and VDD
voltages
(1) VVDD = VVDD(OFF) & VCST ≥ VCST(OPP) ; (2) VVDD
= VVDD(OFF) & VVS ≤ 0.6 V
≤ tOPP
tFDR restart
Output over-voltage
protection (OVP)
VS voltage
VVS ≥ VOVP
3 PWML pulses
tFDR restart
Brown-in detection
VS current
IVSL ≤ IVSL(RUN)
4 PWML pulses
UVLO reset
Brown-out detection
VS current
IVSL ≤ IVSL(STOP)
tBO (60ms)
UVLO reset
Over-temperature
protection (OTP)
NTC
voltage
RNTC ≤ RNTCTH
3 PWML pulses
UVLO reset until RNTC ≥
RNTCR
Thermal shutdown
Junction
TJ ≥ TJ(STOP)
temperature
3 PWML pulses
UVLO reset
7.4.10.1 Brown-In and Brown-Out
The VS pin senses the negative voltage level of the auxiliary winding during the on-time of low-side switch (QL)
to detect an under-voltage condition of the input AC line. When the bulk voltage (VBULK) is too low, UCC28780
stops switching and no VO restart attempt is made until the AC input line voltage is back into normal range. As QL
turns on with PWML, the negative voltage level of auxiliary winding voltage (VAUX) is equal to VBULK divided by
primary-to-auxiliary turns ratio (NPA) of the transformer, which is NP / NA,. During this time, the voltage on VS pin
is clamped to about 250 mV below GND. As a result, VAUX can create a line-sensing current (IVSL) out of the VS
pin flowing through the upper resistor of the voltage divider on VS pin (RVS1). With IVSL proportional to VBULK, it
can be used to compare against two under-voltage thresholds, IVSL(RUN) and IVSL(STOP).
The target brown-in AC voltage (VAC(BI)) can be programmed by the proper selection of RVS1. For every UVLO
cycle of VDD, there are at least four initial test pulses from PWML to check IVSLcondition. IVSL of the first test
pulse is ignored. If IVSL ≤ IVSL(RUN) is valid for the rest three consecutive test pulses, the controller stops switching,
the RUN pin goes low, and a new UVLO start cycle is initiated after VVDD reaches VVDD(OFF). On the other hand, if
IVSL > IVSL(RUN) occurs, VO soft start sequence is initiated.
RVS 1
VAC ( BI ) 2
N PA u IVSL ( RUN )
N A VAC ( BI ) 2
N P 365P A
(13)
The brown-out AC voltage (VAC(BO)) is set internally by around 83% of VAC(BI), which provides enough hysteresis
to compensate for possible sensing errors through the auxiliary winding. A 60-ms timer (tBO) is used to bypass
the effect of line ripple content on the IVSL sensing. Only when the IVSL ≤ IVSL(STOP) condition lasts longer than 60
ms, i.e. typically three line cycles of 50 Hz, the brown-out fault is triggered. The fault is reset after VVDD reaches
VVDD(OFF). Figure 31 shows an example of the timing sequence of brown-in and brown-out protections.
VAC ( BO )
30
IVSL ( STOP )
IVSL ( RUN )
VAC ( BI )
0.83 u VAC ( BI )
(14)
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VBULK
VAC(BI)¥2
VAC(BO)¥2
tBO Timer
60 ms
Brown-Out Fault
VVDD(ON)
VVDD
VVDD(OFF)
PWML
Figure 31. Timing Diagram of Brown In/Out
7.4.10.2 Output Over-Voltage Protection
VS pin senses the positive voltage level of the auxiliary winding voltage (VAUX) to detect an over-voltage
condition of VO. When an OVP event is triggered, UCC28780 stops switching and there is a 1.5-s fault recovery
time (tFDR) before any VO restart attempt is made. As QL turns off, the settled VAUX is equal to (VO+VF) x NAS,
where NAS is the auxiliary-to-secondary turns ratio of the transformer, NA / NS, and VF is the forward voltage drop
of the secondary-side rectifier. The VS pin senses VAUX through a voltage divider formed by RVS1 and RVS2. The
pin voltage (VVS) is compared with an internal OVP threshold (VOVP). If VVS ≥ VOVP condition is qualified for three
consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay.
During this long delay time, only the UVLO-cycle of VVDD is active, and there are no test pulses of PWML. After
the 1.5-s timeout is completed and VVDD reaches the next VVDD(OFF), a normal start sequence begins. The
calculation of RVS2 is
RVS 2
RVS1 u VOVP
N AS u (VO (OVP ) VF ) VOVP
RVS1 u 4.5V
( N A / N S )(VO (OVP ) VF ) 4.5V
(15)
The long tFDR timer helps to protect the power stage components from the large current stress during every
restart. After OVP is triggered, VO may be brought down quickly by the output load current. If OVP were reset
directly after one UVLO cycle of VDD without the 1.5-s delay, the first PWMH pulse turns on QH under the
condition of a large voltage difference between the high clamp capacitor voltage (VCLAMP) and the low reflected
voltage. A large current can flow through the clamp switch (QH) and secondary rectifier. Therefore, the 1.5-s
timer of UCC28780 allows VCLAMP to drop to a lower voltage level through a bleeding resistor (RBLEED) in parallel
with CCLAMP before the next VO restart attempt, such that the current stress can be minimized. A large RBLEED can
be used with the long time-out to minimize the impact on standby power. For example, to discharge VCLAMP to
10% of its normal level in 1.5 s, only 3 mW of additional standby power is added with RBLEED = 2.8 MΩ and
CCLAMP = 220 nF. Figure 32 illustrates the timing sequence as VCLAMP is discharged to a residual voltage
(VRESIDUAL) in 1.5 s. RBLEED also helps to reduce the voltage overcharge on the clamp capacitor in LPM and SBP
modes in which PWMH is disabled, so the voltage stress in the passive-clamp operation can be controlled.
During LPM to ABM mode transition, it is possible to falsely trigger OVP if the setting does not have enough
design margin. In LPM mode with a disabled PWMH, the leakage energy of the transformer charges VCLAMP
higher than the reflected voltage. When the controller enters into ABM and the PWMH is enabled, the activeclamp circuit of ACF needs to take some time to balance the voltage difference, depending on the clamp
capacitor value. As a result, VAUX can sense the higher VCLAMP condition during the voltage balancing and the
controller may treat this as an OVP event, even though VO still stays in regulation and does not reach the actual
OVP point. It may only happen with a large CCLAMP design, so slightly increasing the OVP setting can resolve the
problem.
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1.5 s
VVDD(ON)
VVDD
VVDD(OFF)
VCLAMP
NPS(VO+VF)
VRESIDUAL
PWML
Figure 32. Timing Diagram of CCLAMP Discharging During 1.5-s Recovery Time
7.4.10.3 Over-Temperature Protection
The UCC28780 uses an external NTC resistor (RNTC) tied to the NTC pin to program a thermal shutdown
temperature near the hotspot of the converter. The NTC shutdown threshold (VNTCTH) of 1 V with an internal 105μA current source flowing through RNTC results in a 9.5-kΩ thermistor shutdown threshold. If the NTC resistance
stays lower than 9.5 kΩ for more than three consecutive PWML pulses, an OTP fault event is triggered, and the
1-V threshold is increased to 2.25 V. The NTC resistance has to increase above 21.7 kΩ to reset the OTP fault.
This threshold change provides a safe temperature hysteresis to help the hot-spot temperature cool down before
the next VO restart attempt, reducing the thermal stress to the components. This pin can also be used as an
electrical shutdown function by shorting this pin with a controlled switch to GND. With the pin shorted to GND,
VVDD performs UVLO cycling, and there is at least three consecutive PWML pulses generated to check the state.
The NTC pin can be left floating or tied to the REF pin if not used.
2.25 V
VNTC
1V
OTP Fault
VVDD(ON)
VVDD
VVDD(OFF)
PWML
Figure 33. Timing Diagram of OTP with NTC
7.4.10.4 Programmable Over-Power Protection
The over-power protection (OPP) enables the ACF to operate in an over-power condition for a limited amount of
time, so the UCC28780 can support a power stage design with peak power requirements. As shown in
Figure 34, when VCST is higher than the threshold voltage of the OPP curve (VCST(OPP)), a 160-ms timer starts. If
VCST remains higher than VCST(OPP) continuously for 160 ms, the long 1.5-s timer starts and the controller stays in
fault state without switching. This long recovery time reduces the average current during a sustained over-power
event. The system benefits includes the reduction of thermal stress in high density adapters and the protection of
its output cable.
The OPP function uses IVSL as a line feed-forward signal to vary VCST(OPP) depending on VBULK, in order to make
the OPP trigger point constant over a wide line voltage range. The UCC28780 allows programing of the OPP
curve by adding a line-compensation offset voltage on the CS pin through a resistor (ROPP) connected between
the CS pin and current-sense resistor (RCS). An internal current source flowing out of CS pin creates the offset
voltage on ROPP. This current level is equal to IVSL divided by a constant gain of KLC. As ROPP increases, the OPP
trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run continuously.
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The highest threshold of OPP curve (VCST(OPP1)) of 0.6 V helps to determine RCS value at VBULK(MIN).
RCS
VCST (OPP1)
PO (OPP )
VBULK ( MIN )tD ( CST )
2
VBULK ( MIN )K DMAX
LM
(16)
where PO(OPP) is the output power that triggers OPP, and tD(CST) is the sum of all delays in the peak current loop
which contributes additional peak current overshoot. tD(CST) consists of propagation delay of the low-side driver,
current sense filter delay (ROPP x CCS), internal CS comparator delay (tD(CS)), and nonlinear capacitance delay of
QL. After RCS is determined, ROPP can be adjusted to keep a similar OPP point at highest line. Note that setting
the OPP trigger point too far away from the full power may introduce more challenge on the thermal design,
since the converter runs continuously with more power as long as the corresponding peak current is slightly less
than OPP threshold.
VOCP
OCP
VCS(MAX)
PCL
VCST(OPP1)
VCST(OPP4)
OPP (ROPP = 0 Ÿ)
OPP (ROPP > 0 Ÿ)
233 µA 433 µA
966 µA
IVSL
Figure 34. CS-Pin Related Faults
tOPP Timer
160ms
tFDR Timer
1.5s
VVDD(ON)
VVDD
VVDD(OFF)
IO
VCST(MAX)
VCST(OPP)
VCST
VCST(SM2)
VCST(SM1)
PWML
VO
Figure 35. Timing Diagram of OPP
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7.4.10.5 Peak Current Limit
The peak current threshold of the OPP curve is used to initiate the 160-ms timer, while the peak current limit
(PCL) determines the highest controllable peak current of the peak current loop, VCST(MAX) = 0.8 V. In other
words, this feature provides the highest “short duration” peak power (PO(MAX)) that the converter can reach. For
example, to supply a highest peak power of 150%, RCS should be chosen to ensure that the peak current at
150% load and VBULK(MIN) must not be above VCST(MAX). Then, the threshold of the OPP power (PO(OPP)) can be
programmed to around 112% to support 150% peak power design, based on the following equation. Additionally,
before VO reaches steady state during a VO soft-start, the highest VCST can also reach to VCST(MAX). The
transformer must have enough design margin separating its maximum flux density from the saturation limit of the
core material under the peak current level in PCL.
PO (OPP )
VCST (OPP1)
VCST ( MAX )
PO ( MAX )
0.6V
PO ( MAX )
0.8V
(17)
7.4.10.6 Output Short-Circuit Protection
When an output short-circuit is applied, the peak current reaches the PCL limit and triggers the 160-ms OPP fault
timer. During this event, the VDD power supply is lost due to the auxiliary winding voltage being close to 0 V.
Without additional short-circuit detection, if VVDD reaches VVDD(OFF) before the 160-ms timeout, the 1.5-s recovery
time for the OPP fault cannot be triggered but only a UVLO recycle is performed. To remedy this scenario, as
VVDD reaches VVDD(OFF), UCC28780 checks two additional parameters to identify the short-circuit event at the
output, and initiates the 1.5-s recovery without waiting for 160 ms to expire. Specifically, when VVDD reaches
VVDD(OFF), if either VCST is greater than the OPP threshold (VCST(OPP)) or the VS-pin voltage is less than 0.6 V, the
1.5-s recovery delay is initiated. With this additional layer of intelligence, the average load current during
continued short-circuit event can be greatly reduced, and thus also the thermal stress on the power supply.
7.4.10.7 Over-Current Protection
The UCC28780 operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS
pin is 0.15 V to 0.8 V. If the CS-pin voltage exceeds the 1.2-V over-current level, any time after the internal
leading edge blanking time (tCSLEB) and before the end of the transformer demagnetization, for three consecutive
PWML cycles, the device stop switching, RUN pin goes low, and 1.5-s recovery time is initiated. Similar to OVP,
OPP, and SCP, only the UVLO-cycle of VDD is active, there are no test PWML pulses at all. After the 1.5-s timeout is completed and VVDD reaches the next VDD(OFF), a normal start sequence begins.
7.4.10.8 Thermal Shutdown
The internal over-temperature shutdown threshold is higher than 125°C. If the junction temperature of the device
reaches this threshold, the device initiates a UVLO reset and re-start fault cycle. If the temperature is still high at
the end of the UVLO cycle, the protection cycle repeats. This internal protection is not suitable to substitute for
the NTC for the hotspot temperature protection. The NTC thermistor can provide more accurate and remote
temperature sensing with less compromise on PCB layout.
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7.4.11 Pin Open/Short Protections
As summarized in Table 3, UCC28780 strengthens the protections of several critical pins under open and short
conditions, such as CS, HVG, RDM and RTZ pins.
Table 3. Protections for Open and Short of Critical Pins
PROTECTION
SENSING
CS pin short
PWML on-time at first PWML
pulse only
CONDITION
DELAY TO
ACTION
ACTION
none
tFDR restart (1.5 s)
> 2 μs (VSET = 5 V)
> 2 μs (VSET = 0 V, RRDM ≥ RRDM(TH))
> 1 μs (VSET = 0V, RRDM < RRDM(TH))
CS pin open
CS voltage
VCS ≥ VOCP
3 PWML
pulses
tFDR restart (1.5 s)
HVG pin open
HVG voltage at UVLOON
VHVG drops to 12 V within 10 μs
none
UVLO reset
HVG pin over
voltage
HVG voltage
VHVG ≥ VHVG(OV)
3 PWML
pulses
UVLO reset
RDM pin short
RDM current at UVLOON
VRDM = 0 V, self-limited IRDM
none
UVLO reset
RDM pin open
RDM current at UVLOON
RDM = Open
none
UVLO reset
RTZ pin short
RTZ current at UVLOON
VRTZ = 0 V, self-limited IRTZ
none
UVLO reset
RTZ pin open
RTZ current at UVLOON
RTZ = Open
none
UVLO reset
7.4.11.1 Protections on CS pin Fault
UCC28780 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML
pulse after VVDD startup is completed. As shown in Figure 30, the normal first on-time pulse width should be
limited by the clamped VCST(SM1) level of 0.28 V and the rising slope of the current-loop feedback signal from the
current-sense resistor (RCS) to the CS pin. When the current feedback path is gone due to a CS pin short to
GND, the peak magnetizing current increases and potentially can damage the power stage. Therefore, a
maximum on-time of the first PWML pulse under VSET = 5 V, tCSF1 of 2 μs in the electrical table, is used to limit
the first peak-current stress of the silicon-based converter and then will trigger a CS pin short protection which
initiates the tFDR recovery of 1.5 s.
Additionally, tCSF0 in the electrical table confines the maximum on-time of the first PWML pulse on the GaNbased converter with VSET = 0 V. There are two corresponding values based on two predetermined ranges of the
RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically, tCSF0 is
set at 2 μs with RRDM higher than the RRDM(TH) threshold of 50 kΩ, while tCSF0 is reduced to 1 μs under RRDM <
RRDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency by lowering the
magnetizing inductance (LM), it is possible that the peak current can increase higher than a lower switchingfrequency design under the same VCST(SM1) level and same on-time of PWML. The RDM pin can provide a good
indication on the switching frequency range of a GaN power stage, since the lower LM requires smaller RRDM
setting. With a different tCSF0 setting, the CS pin fault adapts to a wide switching frequency range.
Unlike a CS pin short protection which senses the first on-time pulse width of PWML only, CS pin open
protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is
used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition.
When the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML
pulses, the CS pin open protection is triggered which initiates the 1.5-s recovery.
7.4.11.2 Protections on HVG pin Fault
As shown in Figure 30, after VVDD reaches VVDD(ON), an internal 11-V regulator on the HVG pin should force VHVG
back to the regulation level before PWML starts switching. If the recommended HVG-pin capacitor (CHVG) of 2.2
nF and the connection to the depletion-mode MOSFET (QS) are in place, the settling time of VHVG to 11 V is
much longer than 10 μs with a limited sink current of the regulator (ISE(HVG)) to discharge CHVG.
The first fault scenario is that if CHVG is too small, or the HVG pin is open, the pin is not able to control QS
correctly for the high-voltage sensing function of ZVS control, so no switching action will be performed. When
either two situations happen, VHVG settles to 11 V very quickly instead. Therefore, after a 10-μs delay from the
instance of VVDD reaching VVDD(ON), UCC28780 checks if VHVG is below 12 V for the pin-fault detection, and then
performs one UVLO cycle of VDD directly without switching as the protection response. The above protection is
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to prevent the controller from generating PWM signals. However, when the HVG pin is open and disconnected
from the QS gate, the source voltage of QS keeps increasing until the TVS on the SWS pin (DSWS) starts to clamp
the voltage continuously. To shrink the size of DSWS without incurring too much thermal stress in the small
package in this fault condition, it is highly recommended that a small Zener diode (DHVG) between QS gate to
ground should be used to limit the QS source voltage. Same as DSWS, DHVG should be higher than VVDD(ON), so
as to prevent interference with normal VDD startup.
The second fault scenario is the over-voltage condition of HVG pin after the converter starts switching. When the
switch-node voltage (VSW) rises with a high dV/dt condition, there is a charge current flowing through the junction
capacitance of QS, and part of the current can charge up CHVG. If the overshoot is too large, the voltage on the
SWS pin also increases due to the nature of the depletion-mode MOSFET operation. UCC28780 detects the
overshoot event on HVG pin with an over-voltage threshold (VHVG(OV)) of 13.8V cycle-by-cycle. When VHVG is
higher than VHVG(OV) for three consecutive PWML pulses, the HVG over-voltage protection is triggered which
performs one UVLO cycle of VDD.
The third fault scenario is an HVG pin short event at the beginning of VDD startup, and QS is not able to charge
up the VDD capacitor to VDD(ON), so there is no chance to enable the controller.
7.4.11.3 Protections on RDM and RTZ pin Faults
Since RDM and RTZ pins are the critical programming pins for ZVS control, UCC28780 offers both open and
short protections to those pins. After VVDD reaches VVDD(ON), a fixed voltage level is applied to the pin and the
corresponding current level flowing out of the pin is sensed to detect the pin fault event. As a result, too small of
a current represents the pin-open state, and too large of a current represents the pin-short state where the short
current level is self-limited. When the fault event is identified, one UVLO cycle of VDD is triggered as the
protection response.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A typical application of a high-frequency active-clamp AC-to-DC flyback converter is to enable high-density ACto-DC power supply design which complies with stringent global efficiency standards. Both Silicon (Si) and
Gallium Nitride (GaN) power FETs may be used, with appropriate drivers for each.
8.2 Typical Application Circuit
The following application circuit applies to a GaN-based power stage with SET pin connected to ground, and to a
Si-based power stage with SET pin tied to the REF pin.
LDAMP
DBG
RSWS
CBULK
+
CSWS
QS
NP
CO1
QSEC
CCLAMP
LO
RCo1
NS
RCo2
CO2
CHVG
VD
DHVG
PWML
RVDD2
RBIAS1
Half Bridge
FET + Driver
GND
CS
RVo1
RBIAS2
PGND
CVDD2
CVDD1
CFB
RDIFF
CDIFF
VDD
NTC VS
CREF
RBUR2
VDD
VSW
RFB
REF
FB
REG
PWMH
UCC28780
SET
RBUR1
VIN
RUN
RTZ
(Si)
VOVG VS
UCC24612
RUN
HVG
RDM
RRTZ
(GaN)
SWS
BUR
RRDM
CBUR
VO
LM
RHVG
-
LK
RBLEED
DSWS
VIN
RDAMP
Transformer
VBULK
RVDD1
CCS
NTC
RVS2
ROPP
RCOMP
RCS
QCOMP
DAUX
RVS1
RUN
Opto
coupler
CINT
RINT
ATL431
RVo2
NA
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Figure 36. Typical Application Circuit
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Typical Application Circuit (continued)
8.2.1 Design Requirements
Table 4. UCC28780 Electrical Performance Specifications for GaN FET (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
264
V
63
Hz
INPUT CHARACTERISTICS
VIN
Input line voltage (RMS)
90 115 / 230
fLINE
Input line frequency
47
PSTBY
Input power at no-load
P0.25W
Input power at 0.25W load
VIN = 115 VRMS, IO = 0 A
VIN = 230 VRMS, IO = 0 A
50 / 60
41.1
mW
52.8
mW
VIN = 115 VRMS, PO = 250.6 mW
383.8
mW
VIN = 230 VRMS, PO = 250.6 mW
435.0
mW
OUTPUT CHARACTERISTICS
VO
Output voltage
IO(FL)
Full-load rated output current
VO_pp
Output ripple voltage
VIN = 115 VRMS, IO = 2.25 A
19.853
VIN = 230 VRMS, IO = 2.25 A
19.852
VIN = 115 VRMS, IO = 0 A
19.943
VIN = 230 VRMS, IO = 0 A
19.948
VIN = 90 to 264 VRMS
2.25
V
A
VIN = 115 V / 230 VRMS, IO = 0 A to 2.25 A
80
VIN = 115 V / 230 VRMS, IO = 2.25 A
45
VIN = 115 V / 230 VRMS, IO = 0 A
50
55
W
mVpp
PO(OPP)
Over-power protection power
limit
VIN = 90 to 264 VRMS
tOPP
Over-power protection duration
VIN = 90 to 264 VRMS, PO = PO(OPP)
160
ms
ΔVO
Output voltage deviation during
step load transient
IO step between 0 A to 2.25 A
<5
%
VIN = 115 VRMS, IO = 2.25 A
94.59
%
VIN = 230 VRMS, IO = 2.25 A
94.74
%
VIN = 90 VRMS, IO = 2.25 A
93.98
%
VIN = 115 VRMS
93.88
%
VIN = 230 VRMS
92.47
%
VIN = 115 VRMS, IO = 10% of IO(FL)
88.69
%
VIN = 230 VRMS, IO = 10% of IO(FL)
85.86
%
25
°C
SYSTEMS CHARACTERISTICS
Full-load efficiency
η
4-point average efficiency (2)
η
η
Efficiency at 10% load
TAMB
Ambient operating temperature
range
(1)
(2)
38
VIN = 90 to 264 VRMS, IO = 0 to 2.25 A
The performance listed in this table is achieved using secondary-resonance and based on the test results from a single board.
Average efficiency of four load points, IO = 25%, 50%, 75%, and 100% of IO(FL).
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
In an offline application, the input bulk capacitor (CBULK) should be sized for the minimum input AC line voltage
(VIN(MIN)) and minimum voltage of the input bulk capacitor (VBULK(MIN)). Due to the transition-mode operation, too
low of VBULK(MIN) selection results in higher RMS current at VIN(MIN) and affects the full load efficiency, while too
high of VBULK(MIN) enlarges the volume of the bulk capacitor. This equation does not account for the hold-up time
requirement over line drop-outs.
PO
K
CBULK ( MIN )
u [0.5
1
S
VBULK ( MIN )
u arcsin(
2 u VIN ( MIN )
)]
(2 u VIN ( MIN ) 2 VBULK ( MIN ) 2 ) u f LINE
(18)
8.2.2.2 Transformer Calculations
8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
NPS influences the design tradeoffs on the voltage rating between primary and secondary switches, and the
balance between the magnetic core and winding loss of the transformer, which are explained in detail as follows:
1. Maximum NPS (NPS(MAX)) is limited by the maximum derated drain-to-source voltage of QL (VDS_QL(MAX)). In
the expression below, ∆VCLAMP is the voltage above the reflected output voltage. It can be either the ripple
voltage of CCLAMP in AAM mode, or the voltage over-charge of CCLAMP by the leakage energy as QH is
disabled in LPM mode. VO is the output voltage, and VF is the forward voltage drop of the secondary rectifier.
N PS ( MAX )
VDS _ QL ( MAX ) VBULK ( MAX )
'VCLAMP
VO VF
(19)
2. Minimum NPS (NPS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier
(VDS_SR(MAX)). In the expression for NPS(MIN), ∆VSPIKE should account for any additional voltage spike higher
than VBULK(MAX)/NPS that occurs when QH is active and turns-off at non-zero current in AAM mode.
N PS ( MIN )
VBULK ( MAX )
VDS _ SR ( MAX ) VO
'VSPIKE
(20)
3. Since the high-frequency transformer is usually a core-loss limited design instead of a saturation-limited
design, the minimum duty cycle (DMIN) at VBULK(MAX) is more important. Lower DMIN increases core loss at
VBULK(MAX), so this constraint creates another limitation on NPS(MIN).
N PS ( MIN )
DMINVBULK ( MAX )
(1 DMIN )(VO VF )
(21)
4. The winding loss distribution between the primary and secondary side of the transformer is the final
consideration. As NPS increases, primary RMS current reduces, while secondary RMS current increases.
8.2.2.2.2 Primary Magnetizing Inductance (LM)
After NPS is chosen, LM can be estimated based on minimum switching frequency (fSW(MIN)) at VBULK(MIN),
maximum duty cycle (DMAX), and output power at nominal full load current (PO(FL)). KRES represents the duty cycle
loss to wait for the switch-node voltage transition from the reflected output voltage to zero. 5% to 6% of KRES is
used as a initial estimated value. The selection of minimum switching frequency (fSW(MIN)) has to consider the
impact on full-load efficiency and EMI filter design.
DMAX
N PS (VO VF )
VBULK ( MIN ) N PS (VO VF )
2
LM
2
DMAX VBULK ( MIN ) K
2 PO ( FL )
u
(22)
(1 K RES )
f SW ( MIN )
(23)
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8.2.2.2.3 Primary Turns (NP)
The turn number on the primary side of the transformer (NP) is determined by two design considerations:
1. The maximum flux density (BMAX) must be kept below the saturation limit (BSAT) of the magnetic core under
the highest peak magnetizing current (IM+(MAX)) condition, a given cross-section area (AE) of the core
geometry, and highest core temperature. When IFB = 0 A, such as VO soft-start or step-up load transient, the
peak magnetizing current reaches IM+(MAX), since VCST = VCST(MAX) in those conditions. IM+(MAX) can be
calculated based on the output power triggering an OPP fault (PO(OPP)) with VCST = VCST(OPP1) at VBULK(MIN).
After NP is chosen, NS can be calculated through NPS.
IM
2 PO ( OPP )
( MAX )
BMAX
VCST ( MAX )
DMAXVBULK ( MIN )K VCST (OPP1)
LM I M
( MAX )
(24)
BSAT
N P AE
(25)
2. The AC flux density (ΔB) affects the core loss of a transformer. For a transition-mode active clamp flyback,
the core loss at high line is usually highest, since the switching frequency is highest and duty cycle is
smallest for a given load condition. The following equation is the ΔB calculation including the contribution of
negative magnetizing current (IM-), used to put into the Steinmetz equation for more accurate core loss
estimation. For VBULK ≥ NPS(VO+VF), IM- is calculated with VBULK divided by the characteristic impedance of LM
and the lumped time-related switch-node capacitance (CSW). The expression of fSW is derived based on the
triangular approximation of the magnetizing current, which also considers IM- effect over wide AC line
condition.
CSW
VBULK
LM
IM
I IN
D
PO ( FL )
(26)
1
VBULK
N PS (VO VF )
VBULK N PS (VO VF )
K
(27)
(28)
2
f SW
IM
'B
2 LM I IN
2 PO ( FL )
DLM I M
I
D VBULK
DVBULK u 0.5S LM CSW
(29)
2
M
K LM f SW
LM ( I M
IM )
N P AE
(30)
(31)
8.2.2.2.4 Secondary Turns (NS)
NS and NP are adjusted to the nearest suitable integers. With the new NPS, Primary Magnetizing Inductance (LM)
is recalculated to update the parameter change.
NS
NP
N PS
(32)
8.2.2.2.5 Turns of Auxiliary Winding (NA)
Turns of the auxiliary winding (NA) is an integer value usually chosen to provide a nominal VVDD that satisfies all
devices powered from VVDD, such as the gate driver, UCC28780, etc. NA is determined by the following design
considerations:
1. VVDD must be lower than the maximum rating voltage of VDD pin (VVDD(MAX)) at maximum output voltage
(VO(MAX)). VVDD(MAX) is limited by the lowest voltage rating of the devices connected to VDD pin.
40
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N A( MAX )
SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
VVDD ( MAX )
VO ( MAX ) VF
NS
(33)
2. The nominal VVDD should consider the impact on the standby power. Higher VVDD results in the static-loss
increase with the total bias current of the devices connected to VDD pin.
3. VVDD should be higher than the 11-V threshold voltage of survival mode, which is the sum of VVDD(OFF) and
VVDD(PCT), at the minimum sustained output voltage (VO(MIN)). ΔV represents the voltage difference between
the nominal VVDD and the survival-mode threshold. A minimum of 3 V is a recommended design margin of
ΔV.
N A( MIN )
VVDD ( OFF ) VVDD ( PCT )
'V
VO ( MIN ) VF
NS
(34)
8.2.2.2.6 Winding and Magnetic Core Materials
Not only by the control of AC flux density (ΔB) with LM and NP design, the core loss of the transformer can also
be significantly reduced by a proper selection of the magnetic core material. For a converter operating at 200
kHz to 400 kHz of switching frequencies (at full load condition), core materials such as 3F36 from Ferroxcube
and N49 from TDK exhibit low core loss density in the frequency range. Litz wires are recommended for both
primary and secondary windings, in order to reduce the AC winding loss caused by the proximity effect and the
skin effect of the transformer windings.
8.2.2.3 Clamp Capacitor Calculation
There are two resonance approaches for an active clamp flyback (ACF) converter, primary resonance and
secondary resonance, which affect the design guide on the clamp capacitor (CCLAMP). Referring to Figure 36, if
CO1 serves as the energy-storage capacitor at the output with larger capacitance and CO2 is a high-frequency
decoupling capacitor, leakage inductance of transformer (LK) mainly resonates with CCLAMP during the
demagnetization time of the magnetizing inductance (LM). This configuration is called the primary-resonance ACF
converter. On the other hand, if CO2 serves as the energy-storage capacitor at the output with larger capacitance
and CO1 is much smaller than the equivalent capacitance of CCLAMP reflected to the secondary side
(CCLAMP/NPS2), LK mainly resonates with CO1. This configuration is called the secondary-resonance ACF
converter.
For primary-resonance ACF, the design tradeoff between conduction loss and turn-off switching loss of QH needs
to be considered. Higher CCLAMP results in less RMS current flowing through the transformer windings and
switching devices, so the conduction loss can be reduced. However, a higher CCLAMP design results in QH
turning-off before the clamp current returns to 0 A. The condition of non zero current switching (ZCS) increases
the turn-off switching loss of QH. This is aggravated if the turn-off speed of QH is not fast enough. Therefore,
CCLAMP needs to be fine-tuned based on the loss attribution. If the resonance between LK and CCLAMP is designed
to be completed by the time QH is turned-off, the clamp current should reach close to 0 A around three quarters
of the resonant period. The following equation can be used to design CCLAMP for obtaining ZCS at VBULK(MIN) and
full load. This design results in a non-ZCS condition at VBULK(MAX), since the switching frequency at VBULK(MAX) is
higher in transition-mode operation. A low-ESR clamp capacitor is recommended to minimize the conduction
loss. If a ceramic capacitor is used as the low-ESR capacitor, the DC bias effect on the capacitance reduction
also needs to be considered.
CCLAMP
LM I M ( FL )
1
[
]2
LK 1.5S N PS (VO VF )
(35)
For secondary-resonance ACF, CO1 is used to adjust the resonance time with LK to fulfill the ZCS condition, so a
large CCLAMP will not compromise ZCS. Besides, during the on-time of low-side switch (QL), the small CO1 is
partially discharged by the load current at the same time. After QL turns off and the resonance begins, the
discharged CO1 makes the initial resonance voltage lower than the reflected clamp capacitor voltage across
CCLAMP, which forces more magnetizing current delivered to output, so the conduction loss is reduced with less
RMS current flowing through QH and the primary winding.
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8.2.2.4 Bleed-Resistor Calculation
RBLEED is used to discharge the clamp capacitor voltage to a residual voltage (VRESIDUAL) during the 1.5-s fault
delay recovery time (tFDR). After the converter recovers from the fault mode, lower VRESIDUAL reduces the
maximum current stress (ISHORT(MAX)) flowing through the switching devices within their respective safe operating
areas, even if the output voltage is shorted. VRESIDUAL can be determined by the target ISHORT(MAX) multiplied with
the characteristic impedance between the leakage inductance (LK) and the clamp capacitor (CCLAMP). ISHORT(MAX)
is based on the de-rated maximum pulse current of QH or the output-rectifier current reflected to the primary side,
whichever is lower. This design guide can be applied to both primary and secondary resonance ACF converters.
An excessively low value of RBLEED results in over-discharging of CCLAMP, and introduces excess continuous
power loss which affects standby power.
VRESIDUAL | I SHORT ( MAX )
LK
CCLAMP
tFDR
N (V VF ) 'VCLAMP
CCLAMP ln[ PS O
]
VRESIDUAL
RBLEED
(36)
(37)
8.2.2.5 Output Filter Calculation
The bulk output capacitor of active clamp flyback (ACF) converters, CO1 of the primary-resonance ACF or CO2 of
the secondary-resonance ACF, is often determined by the transient-response requirement from no load to full
load transition. For a target output voltage undershoot (ΔVO) with the load step-up transient of ΔIO, the minimum
bulk output capacitance (CO(MIN)) can be expressed as
CO ( MIN )
'I O tRESP
'VO
(38)
where tRESP is the time delay from the moment ΔIO is applied to the moment when IFB falls below 1 μA.
The output filter inductor (LO) is an essential component for the secondary-resonance ACF, not only to filter the
large switching voltage ripple across CO1 but also to decouple the effect of CO2 on the resonance period. The
sum of LO impedance, ESR of CO2 (RCo2), and CO2 impedance at minimum switching frequency (fSW(MIN)) must be
much higher than CO1 impedance at the same frequency to force most of switching resonance current to flow
through CO1.
LO !!
1
1
2
(2S f SW ( MIN ) ) CO1
2
(2S f SW ( MIN ) ) CO 2
RCo 2
2S f SW ( MIN )
(39)
One benefit of lowering the ESR on CO1 (RCo1) is to help to reduce the switching ripple on the output voltage.
Another benefit is reducing the conduction loss of CO1 for the secondary-resonance ACF converter. However, the
issue is that the damping between LO and CO1 is weakened. Without proper damping, the magnitude of lowfrequency resonance ripple between LO and CO1 enlarges output ripple, affects the loop stability, and affects the
operation of synchronous rectifier (QSEC). The secondary-resonance ACF converter is the most vulnerable since
CO1 with low capacitance significantly weakens the damping. To resolve this issue, it is found that a serial
damping network formed by LDAMP and RDAMP is a very effective way to minimize the impact. However, too strong
of a damping design results in noticeable conduction loss increase and full load efficiency drop. Therefore, it is
recommended that LDAMP and RDAMP should be higher than the theoretical strong damping value as the following
equations suggest. Even though the damping network is an additional component, the physical size or the
footprint is much smaller than LO, not only because of the small value but also the wide selection of a small-size
chip inductor which winding resistance can be a free RDAMP. For the 45W secondary-resonance ACF design with
primary GaN FETs and a polymer-type CO2, when a 0.68-µH chip inductor is in parallel with a 1-µH output filter
inductor, there is only 0.15% full-load efficiency drop at 90-V AC input, and there is a negligible efficiency
difference at 230-V AC input.
LDAMP ! 0.13 u LO
RDAMP !
42
(40)
LO
CO1
(41)
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8.2.2.6
SLUSD12A – OCTOBER 2017 – REVISED FEBRUARY 2018
Calculation of ZVS Sensing Network
There are four components in the application circuit to help the depletion MOSFET (QS) perform ZVS sensing
safely, CSWS, RSWS, DSWS, and RHVG. Design considerations and selection guidelines for the values of these
components are given here.
At the rising edge of the switch node, the fast dV/dt coupling through the drain-to-source capacitance of QS
(COSS(Qs)) generates a charge current flowing into the capacitive loading of the QS source pin. The result is a
voltage overshoot on both the SWS pin and across the gate-to-source of QS (VGS(Qs)). The SWS pin, with an
absolute maximum voltage of 38 V, can handle higher voltage stress than VGS(Qs). Therefore, a capacitor
between the SWS pin and GND (CSWS) should be selected properly to prevent the voltage overshoot from
damaging the QS gate. Since COSS(Qs) and CSWS form a voltage divider, the minimum CSWS (CSWS(MIN)) can be
derived as
CSWS ( MIN )
COSS (Qs ) u [VBULK ( MAX )
N PS (VO VF )]
VHVG VGS _ MAX (Qs )
CDsws
(42)
where VGS_MAX(Qs) is the de-rated maximum gate-to-source voltage of QS, VHVG is the steady-state voltage level
of 11 V, and CDsws is the parasitic capacitance of TVS diode (DSWS) on the SWS pin.
Without resistive damping, both the charge current on the rising edge of VSW and the discharge current on the
falling edge of VSW are oscillatory with the parasitic inductance within the ZVS sensing network resonating with
CSWS. Therefore, a series resistor (RSWS) between SWS pin and source-pin of QS is used to dampen the highfrequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency
current from interfering with other noise-sensitive signals. RSWS can be expressed as:
RSWS !
LSWS
CSWS CDz
(43)
where LSWS is the lumped parasitic inductance including the packaging of QS and PCB traces of QS and CSWS
return path.
Based on the above design guide, even though RSWS and CSWS may be sufficient to manage the voltage
overshoot in normal operation, a low-capacitance TVS diode (DSWS) is still highly recommended to serve as a
safety backup of the ZVS sensing network. A regular Zener diode is not suitable due to its high capacitance and
slow clamping response.
Based on the above equations, a general recommendation is that a 50 V C0G-type ceramic capacitor of 22 pF
for CSWS, a chip resistor no higher than 120 Ω for RSWS, and a TVS diode with the clamp voltage between 18 V
to 24 V for DSWS. Too large of RSWS or CSWS introduces a sensing delay between VSW and SWS pin, so the ZVS
control pulls down VSW earlier than expected before the end of tZ by unnecessarily extending tDM. The
recommended RSWS and CSWS values only introduce a minor 2.6-ns delay, so the ZVS control is not be affected.
Another issue with too large of RSWS is that an additional voltage drop may be created by the charge current
through COSS(Qs) during high dV/dt events of VSW, which becomes another voltage stress onto the gate-to-source
voltage of QS . For the power stage that can generate very high dV/dt, lowering RSWS and increasing CSWS may
be necessary to enhance the protection on QS. Alternatively, a back-to-back TVS can be added between the
gate and source pins of QS to provide a direct clamping to the possible over-voltage stress condition.
Furthermore, a high-impedance discharge resistor (RHVG) between the gate and source pins of QS helps to
discharge the residual voltage on the gate capacitance, and RHVG around 1 MΩ should be enough to serve the
purpose. Note that too small RHVG can hurt standby power, since it creates a continuous current flowing through
QS.
8.2.2.7 Calculation of Compensation Network
UCC28780 integrates two control concepts to benefit high-efficiency operation: peak current-mode control and
burst ripple control. The peak current loop in AAM can be analyzed based on the linear control theory, so the
compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic
of an active clamp flyback converter. For transition-mode operation, the power stage can be modeled as a
voltage-controlled current source charging an output capacitor (CO) with an equivalent-series resistance (RCo)
and the output load (RO) as shown in Figure 37. The first-order plant characteristic and high switching frequency
operation in AAM make the peak current loop easier to stabilize than ABM.
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^
VO
Equivalent Circuit of ACF
^
KFVBULK
^
KEIFB
RCo
RO
RE
CO
^
IFB
HV (s)
VO(REF)
Compensation
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Figure 37. Small-Signal Model of ACF in AAM Loop
The adaptive burst mode (ABM) is a ripple-based control, so the linear control theory for AAM cannot be applied.
The most critical stability criterion of burst control is to make the burst ripple content of IFB to be in-phase with the
burst ripple voltage of VO. In normal operation, the fundamental burst frequency (fBUR) in ABM varies between 20
kHz and 40 kHz. An example of normal burst operation is illustrated in Figure 38.
fBUR
RUN
PWML
VCST(BUR)
VCS
Figure 38. Expected Burst Pattern Example
Strong phase-delay in the frequency range creates slope distortion around the intersection point between IFB and
ITH(FB), so the ripple regulator generates inconsistent burst off-times. As shown in Figure 39, the sub-harmonic
oscillation at half of fBUR is a typical phenomenon of an unstable ABM loop. Two burst packets are adjacent to
each other and the pulse count (NSW) is different by one pulse count.
fBUR / 2
RUN
PWML
VCST(BUR)
VCS
Figure 39. Typical Behavior of Unstable ABM Loop
44
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Passive Ripple
Compensation
VO
RDIFF
RBIAS1
REF
IFB
CDIFF
CFB
IOPTO
VFB(REG)
FB
IFB
RVo1
CTR
ID
RFB
RFBI
ICOMP
RBIAS2
RUN
Copto
Control
Law
Active Ripple
Compensation
CINT
ATL431
RINT
RVo2
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Figure 40. Compensation Network, Hv(s)
In order to minimize the phase-delay of IFB, the transfer function from IFB to VO guides the pole/zero placement of
the secondary-side passive ripple compensation network in Figure 40. In the primary-side control circuitry, two
poles at ωFB and ωOPTO introduce phase-delay on IFB. ωFB pole is formed by the external filter capacitor CFB and
the parallel resistance of the internal RFBI and the external current-limiting resistor (RFB). ωOPTO pole is formed by
the parasitic capacitance of the optocoupler output (COPTO) and the series resistance of RFBI and RFB. For CFB =
100 pF, RFBI = 8 KΩ, and RFB = 20 KΩ, the delay effect of ωFB pole located at 278 kHz is negligible. However,
ωOPTO pole is located less than 10 kHz, and introduces large phase delay in the interested fBUR range of ABM,
since COPTO is in a few nF range contributed by the Miller effect of the collector-to-base capacitance of the BJT in
the optocoupler output. Therefore, an RC network (RDIFF and CDIFF) in parallel with RBIAS1 is used to compensate
the phase-delay of the optocoupler, which introduces an extra pole/zero pair located at ωP1 and ωZ1 respectively.
The basic design guide is to place the ωZ1 zero close to the ωOPTO pole, and to place ωP1 pole away from highest
fBUR.
I FB ( s )
VO ( s )
ZZ 0
ZZ 1
ZP1
ZOPTO
ZFB
CTR 1 ( s / ZZ 0 )
1
1 ( s / ZZ 1 )
1
RBIAS 1 ( s / ZZ 0 ) 1 ( s / ZP1 ) 1 ( s / ZOPTO ) 1 ( s / ZFB )
1
( RVo1 RINT )C INT
1
( RDIFF RBIAS 1 )CDIFF
1
RDIFF CDIFF
1
( RFB RFBI )COPTO
1
( RFBI / / RFB )CFB
(44)
(45)
(46)
(47)
(48)
(49)
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Case 2: Larger IFB ripple
Case 1: Small IFB ripple
IFB
¨,FB
IFB
Noise
floor
IREF
¨,FB
RUN
Noise
floor
IREF
RUN
¨WBUR
¨WBUR
Figure 41. Effect of Signal-to-Noise Ratio of iFB to ABM Operation
Another guideline of obtaining a more consistent burst off-time is to maintain large enough ripple amplitude of IFB
in ABM mode (ΔIFB) for better signal-to-noise ratio. Figure 41 shows that when the noise floor alters the
intersection point of each burst cycle, larger ΔIFB performs much less burst off-time variation if the noise floor
stays the same. ΔIFB around 10 μA is a recommended initial design value. The ripple ratio (KRIPPLE) between ΔIFB
and the burst voltage ripple of VO in ABM (ΔVO(ABM)) is obtained by simplifying the small-signal gain of
IFB(s)/VO(s) transfer function between 20 kHz and 40 kHz.
'I FB
K RIPPLE u 'VO ( ABM ) | 10P A
K RIPPLE {
I FB ( s)
Vo ( s) 20kHz
|
f 40 kHz
(50)
CTR ZOPTO
RBIAS1 ZZ 1
CTR ( RDIFF RBIAS 1 )CDIFF
RBIAS1 ( RFB RFBI )COPTO
(51)
With the above understanding on burst control, the step-by-step design procedure is:
1. RFB selection needs to consider both the output voltage regulation and compensation challenge on the lowfrequency pole at ωOPTO. RFB should be less than the maximum value of 28 kΩ to provide a sufficient
feedback current of 95 μA for the output voltage regulation in SBP mode, under the worst-case VFB(REG) and
RFBI. RFB = 28 kΩ and COPTO = 2 nF result in the ωOPTO pole located at 2.8 kHz. Such a low-frequency pole
forces the ωZ1 zero to be designed around 2.8 kHz to compensate the phase-delay.
RFB ( MAX )
VFB ( REG ) VCE (OPTO )
I FB ( SBP )
RFBI
(52)
2. RBIAS1 is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔVO(ABM), and target
10 μA of ΔIFB as example.
RBIAS1
CTR
'VO ( ABM )
'I FB
CTR
'VO ( ABM )
10P A
(53)
3. CDIFF is designed to position ωZ1 ≈ ωOPTO and locate ωP1 at least two-times higher frequency than 2π x
fBUR(UP) as example.
CDIFF
1
ZP1 ZZ 1
RBIAS 1 ZP1 u ZZ 1
1
(4S f BUR (UP ) ) ZOPTO
RBIAS 1 (4S f BUR (UP ) ) u ZOPTO
(54)
4. RDIFF is designed to position ωP1 two-times higher than 2π x fBUR(UP), but lower than the switching frequency
in ABM (2π x fSW(BUR)). Too small of RDIFF moves ωP1 higher than 2π x fSW(BUR), so the high differentiation gain
on the secondary-side compensator amplifies the switching ripple and increases the noise floor. Therefore,
RDIFF should be fine-tuned based on the actual noise level of a given design.
RDIFF
1
ZP1CDIFF
1
4S f BUR (UP )CDIFF
(55)
5. RINT selection is not designed for the small-signal compensation, but to resolve the slow large-signal
response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load
occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage
continuously by the integrator configuration of ATL431 until the output voltage gets back to normal regulation
level. If the load step-up transient happens before the output voltage is settled from the previous load stepdown event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a
46
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new steady-state. Since the time for ATL431 moving from lower voltage to a high voltage delays iFB
reduction, the controller response from SBP mode to AAM mode is delayed as well, which slows down the
energy delivery to the output and results in a large voltage undershoot. To resolve this problem, RINT
behaves like a current-limiting resistor for CINT, which slows down the reduction on the cathode voltage of
ATL431. RINT needs to be adjusted based on the voltage undershoot requirement under the lowest repetitive
rate of load change.
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8.2.3 Application Curves
96
97
115VAC
95
90VAC
93
95
Efficiency (%)
Efficiency (%)
230VAC
91
89
264VAC
94
87
85
93
83
85
115
145
175
205
235
265
0
25
AC Input Voltage (VAC)
Figure 42. Full-Load Efficiency in Universal AC Line
75
100
Figure 43. Light-Load Efficiency in Universal AC Line
VO
VO
PWML
PWML
Figure 44. Output Voltage Ripple at VIN = 115 VRMS and IO =
2.25 A
48
50
Output Load (%)
Figure 45. Output Voltage Ripple at VIN = 115 VRMS and IO =
0.9 A
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350
PWML
Switching Frequency (kHz)
300
PWMH
VSW
250
200
IPRI
150
85
115
145
175
205
235
265
AC Input Voltage (VAC)
Figure 47. Switching Frequency in Universal Line and IO =
2.25 A
Figure 46. AAM Waveforms at VIN = 230 VRMS and IO = 2.25
A
PWML
PWML
PWMH
PWMH
VSW
VSW
IPRI
IPRI
IPRI
Figure 48. ABM Waveforms at VIN = 115 VRMS and IO = 0.9
A
Figure 49. ABM Waveforms at VIN = 115 VRMS and IO = 0.2
A
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PWML
PWMH
VO
VSW
IO
IPRI
Figure 51. Load Transient between 0 A to 2.25 A at VIN =
115 VRMS
Figure 50. SBP Waveforms at VIN = 115 VRMS and IO = 0 A
140
Over-Power Protection Level (%)
PWML
130
RUN
120
VDD
110
IPRI
100
85
115
145
175
205
235
265
AC Input Voltage (VAC)
Figure 52. OPP Level in Universal AC Line
Figure 53. Fault Delay Recovery of OPP
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9 Power Supply Recommendations
The UCC28780 is intended to control active clamp flyback (ACF) converters in high efficiency offline applications,
and is optimized to be used with universal AC input, from 85 VAC to 265 VAC, at 47 Hz to 63 Hz. An external
depletion-mode MOSFET connected between the switch node of the converter and the SWS / HVG pins of this
controller is required to charge the VDD capacitor during start-up, and to perform ZVS sensing during normal
operation. Once the VVDD reaches the UVLO turn-on threshold at 17.5 V, the VDD rail should be kept within the
limits of the Bias Supply Input section of Specifications. To avoid the possibility that the device might stop
switching, VVDD must not be allowed to fall below the UVLO turn-off threshold at 9.8 V.
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10 Layout
10.1 Layout Guidelines
The active clamp flyback converter (ACF) designed with the UCC28780 not only recovers clamp energy but also
eliminates switching loss with minimum circulating energy, so higher switching frequencies, efficiencies, and
greater power densities can be achieved. However, when designing for higher switching frequencies, good layout
practices as discussed below need to be followed to ensure for a more reliable and robust design.
10.1.1 General Considerations
Designing for high power density requires to consider noise coupling and thermal management. A four-layer PCB
structure is highly recommended to use inner layers to help reduce current loop areas and provide heatspreading for surface-mount semiconductors.
• Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for
MOSFETs and power diodes.
• To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas with high-frequency
switching voltage.
• To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal
tracks in parallel with such loops.
Figure 54 summarizes the critical layout guidelines, and more detail will be also be further elaborated in the
descriptions below.
52
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Layout Guidelines (continued)
Minimize the high di/dt switching loops to reduce EMI, voltage
stress on power devices, and noise coupling on control loop.
VAC
VBULK
+
LO
RBLEED
CCLAMP
NP
NS
VO
CO1
CO2
DBG
t
CBULK
QH
QSEC
UCC24612
High-Side Driver
+ Level Shifter
Star grounding for less common ground noise:
- Keep signal and power ground separate
- Connect grounds close to CBULK and RCS
Control loop away
from dB/dt coupling
of transformer
RCS
VSW
QL
Power
Ground
Separate CSWS and
DSWS ground return
Shorten high dV/dt
traces for less EMI
and noise coupling;
Orthogonally across
other traces
Low-side
Driver
Shorten VSWS trace with
dV/dt; away from
feedback loop
Enable
Keep signal and
power ground
separate
Output
Power
Ground
Keep compensator
away from dV/dt, di/dt,
or dB/dt noise sources
RBIAS1
CSWS
RSWS
VSWS
RHVG
HVG
RVDD1
ROPP and RFB
close to IC and the
filter capacitor for less
dV/dt coupling
DHVG
Shorten VAUX trace with
dV/dt; away from
feedback loop
VAUX
RDIFF
QS
DSWS
CHVG
CVDD
PWML
RUN
SWS
Minimize the high
di/dt switching loops
UCC28780
CFB
GND
RVS2
BUR NTC
REF
RDM RTZ
RVo1
RINT
ATL431
RVo2
Secondary Signal
Ground Plane
RCOMP
CCS
QCOMP
CREF
CBUR
Minimize FB loop and
away from dV/dt, di/dt,
or dB/dt noise sources
RUN
Primary Signal
Ground Plane
CINT
CDIFF
FB
SET
RVS1
OPTO
COUPLER
RFB
VS
DAUX
ROPP
PWMH CS
VDD
NA
RBIAS2
RBUR2
RBUR1
Figure 54. Schematic with Layout Considerations
10.1.2 RDM and RTZ Pins
Minimize stray capacitance to RDM and RTZ pins.
• Place RRDM and RRTZ as close as possible between the controller pins and GND pin.
• Avoid putting ground plane under RDM and RTZ pins to reduce parasitic capacitance. This can be
accomplished by putting cutouts in the ground plane below these pins.
10.1.3 SWS Pin
Minimize potential stray noise coupling from SWS pin to noise-sensitive signals.
• Keep some distance between SWS pin and other connections.
• The RC damping network (Rsws, Csws) and the TVS diode (DSWS) should be as close to the source pin of QS
as possible instead of SWS pin, so the gate-to-source pin of QS can be effectively protected.
• Keep the return path for di/dt current through CSWS and DSWS separate from the IC local GND and FB signal
return paths.
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Layout Guidelines (continued)
10.1.4 VS Pin
Minimize stray capacitance at the VS pin to reduce the time delay effect on ZVS control.
• Avoid putting GND plane under VS Pin to reduce parasitic capacitance. This can be accomplished by putting
a cutout in the ground plane below this pin.
10.1.5 BUR Pin
The resistor divider (RBUR1 and RBUR2) and the filter capacitor (CBUR) on the BUR pin should to be as close to the
BUR pin and IC GND as possible.
• It is recommended to provide shielding on the BUR-pin trace with ground planes to minimize the noisecoupling effect on peak current variation during burst-mode operation. This can be accomplished by adding a
ground plane under the BUR traces and pins.
10.1.6 FB Pin
This pin can be noise-sensitive to capacitive coupling from the high dV/dt switch nodes, or the flux coupling from
magnetic components and high di/dt switching loops.
• Minimize the loop area for the PCB traces from the opto-coupler to the FB pin in order to avoid the possible
flux coupling effect.
• Keep PCB traces away from the high dV/dt signals, such as the switch node of the converter (VSW), the
auxiliary winding voltage (VAUX), and the SWS-pin voltage (VSWS). If possible, it is recommended to provide
shielding for the FB trace with ground planes.
• The filter capacitor between FB pin and REF pin (CFB) needs to be as close to the two IC pins as possible.
• The current-limiting resistor of FB pin (RFB) should be as close to the FB pin as possible to enhance the noise
rejection of nearby capacitively-coupled noise sources.
10.1.7 CS Pin
The OPP-programming resistor (ROPP) and the filter capacitor (CCS) should be as close to the CS pin as possible
to improve the noise rejection of nearby capacitively-coupled noise sources, and to filter any ringing that may be
present during non-ZVS conditions.
10.1.8 GND Pin
The GND pin is the bias-power and signal ground connection for the controller. The effectiveness of the filter
capacitors on the signal pins depends upon the integrity of the ground return.
• Place the decoupling and filter capacitors on VDD, REF, CS, and HVG pins as close as possible to the device
pins and GND pin with short traces.
• The device ground and power ground should meet at the return of the current-sense resistor (RCS). Try to
ensure that high frequency/high current from the power stage does not go through the signal ground.
• The thermal pad of the QFN package should be tied to the IC GND pin with a short trace, and be connected
to the signal ground plane with multiple vias which becomes a low-impedance ground return of external
components to the GND pin.
10.2 Layout Example
The layout techniques described in above sections were applied to the layout of the 45-W 20-V high-density GaN
active clamp flyback converter. Figure 55 and Figure 56 are the schematics of the evaluation module (EVM), the
other figures are the layout of each layer, which critical traces are highlighted.
54
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Layout Example (continued)
Figure 55. Schematic A of the 45-W EVM
Figure 56. Schematic B of the 45-W EVM
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Layout Example (continued)
Isolation Boundary
Make Current Loops as Small and Short as Possible
Ground Plane Shielding
Figure 57. Top Assembly and First Layer of PCB
Add Multiple Vias to Increase Current Handling Capability and Dissipate Heat Through PCB and PCB Copper
Figure 58. Second Layer of PCB
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Layout Example (continued)
Remove Ground Plane Under RDM, RTZ and VS Pins to Reduce Capacitance
Signal Ground Plane
C13 and R5 Snubber
Need to be as Close to
SR FET as Possible
Keep Current Loops as Small as Possible
Figure 59. Third Layer of PCB
Get Supporting Resistors and Capacitors as Close
to the UCC28780 as Possible
Figure 60. Bottom Assembly and Fourth Layer of PCB
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Using the UCC28780EVM-002 45-W 20-V High Density GaN Active-Clamp Flyback Converter
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
58
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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9-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC28780D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28780
UCC28780DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28780
UCC28780RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28780
UCC28780RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28780
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC28780DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
UCC28780RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
UCC28780RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28780DR
SOIC
D
16
2500
333.2
345.9
28.6
UCC28780RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
UCC28780RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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