Texas Instruments | TPS791 Ultralow Noise, High PSRR, Fast RF 100-mA Low-Dropout Linear Regulators (Rev. D) | Datasheet | Texas Instruments TPS791 Ultralow Noise, High PSRR, Fast RF 100-mA Low-Dropout Linear Regulators (Rev. D) Datasheet

Texas Instruments TPS791 Ultralow Noise, High PSRR, Fast RF 100-mA Low-Dropout Linear Regulators (Rev. D) Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
TPS791
Ultralow Noise, High PSRR, Fast RF 100-mA Low-Dropout Linear Regulators
1 Features
3 Description
•
•
•
•
•
•
•
•
The TPS791 device is a low-dropout (LDO) lowpower linear voltage regulator that features high
power-supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in a small outline, SOT23 package. The
device is stable, with a small 1-µF ceramic capacitor
on the output. The TPS791 uses an advanced,
proprietary BiCMOS fabrication process to yield
extremely low dropout voltages (for example, 38 mV
at 100 mA, TPS79147). This device achieves fast
start-up times (approximately 63 µs with a 0.001-µF
bypass capacitor) while consuming very low
quiescent current (170 µA typical). Moreover, when
the device is placed in standby mode, the supply
current is reduced to less than 1 µA. The TPS79118
exhibits approximately 15 µVRMS of output voltage
noise with a 0.1-µF bypass capacitor. Applications
with analog components that are noise sensitive,
such as portable RF electronics, benefit from the high
PSRR and low noise features as well as the fast
response time.
1
•
•
100-mA Low-Dropout Regulator With EN
Available in 1.8-V, 3.3-V, 4.7-V, and Adj.
High PSRR (70 dB at 10 kHz)
Ultralow Noise (15 µVRMS)
Fast Start-Up Time (63 µs)
Stable With Any 1-µF Ceramic Capacitor
Excellent Load, Line Transient
Very Low Dropout Voltage (38 mV at Full Load,
TPS79147)
5-Pin SOT23 (DBV) Package
TPS792xx Provides EN Options
2 Applications
•
•
•
Powering VCOs and PLLs
Bluetooth and Wireless LAN
Portable and Battery Operated
Device Information(1)
PART NUMBER
TPS791
PACKAGE
BODY SIZE (NOM)
SOT23 (5)
2.90 mm × 1.60 mm
SOT23 (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic: Fixed Output
IN
VIN
OUT
VIN
IN
1 PF
VOUT
OUT
100 pF
1 PF
R2
TPS79101
VEN
1 PF
FB
TPS791
EN
R1
1 PF
VOUT
Simplified Schematic: Adjustable Output
BYPASS
GND
0.1 PF
VEN
EN
BYPASS
GND
PF
Copyright © 2018, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagrams ..................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
8.3 Do's and Don'ts ....................................................... 17
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2002) to Revision D
Page
•
Added Device Information table, Simplified Schematic figures to page 1, ESD Ratings table, Thermal Information
table, Pin Configuration and Functions section, Overview section, Feature Description section, Device Functional
Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................... 1
•
Changed TPS791xx to TPS791 throughout document ......................................................................................................... 1
•
Changed Applications section ............................................................................................................................................... 1
•
Changed Description section ................................................................................................................................................. 1
•
Deleted Ordering Information table ........................................................................................................................................ 3
•
Changed EN pin description .................................................................................................................................................. 3
•
Added I/O data for GND pin .................................................................................................................................................. 3
•
Deleted Package Dissipation Rating table ............................................................................................................................. 3
•
Changed VI to VIN, IO to IOUT, CO to COUT, Co(byp) and C(byp) to CBYPASS throughout document .............................................. 3
•
Changed formula in footnote 1 of Recommended Operating Conditions table...................................................................... 4
•
Added VREF parameter to Electrical Characteristics table.................................................................................................... 5
•
Changed VCC to VIN in test conditions of UVLO threshold and UVLO hysteresis parameters ............................................... 5
•
Added PSRR and VDO symbols to Power-supply ripple rejection and Dropout voltage parameters...................................... 5
•
Added conditions statement to Typical Characteristics section ............................................................................................ 6
•
Changed IOUT to CBYPASS in TPS79118 Output Spectral Noise Density vs Frequency figure ................................................ 7
•
Changed IOUT to CBYPASS in TPS79133 Output Spectral Noise Density vs Frequency figure ................................................ 7
•
Changed third bullet in Normal Operation section ............................................................................................................... 15
•
Changed first bullet in Disabled section .............................................................................................................................. 15
•
Changed VEN column in Device Functional Mode Comparison table................................................................................... 15
•
Added active-low to Application Information description ..................................................................................................... 16
2
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
5 Pin Configuration and Functions
DBV Package: Adjustable Output
6-Pin SOT23
Top View
IN
1
6
OUT
GND
2
5
FB
EN
3
4
BYPASS
DBV Package: Fixed Output
5-Pin SOT23
Top View
IN
1
GND
2
EN
3
5
OUT
4
BYPASS
Not to scale
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
ADJ
FIXED
BYPASS
4
4
—
An external bypass capacitor connected to this pin, in conjunction with an internal
resistor, creates a low-pass filter to further reduce regulator noise.
EN
3
3
I
The EN pin is an input which enables or shuts down the device. The enable signal
is an active-low digital control that enables the device, so when EN is a logic high
(> 2 V), the device is in shutdown mode. When EN is logic low (< 0.7 V), the
device is enabled.
FB
5
N/A
I
This pin is the feedback input voltage for the adjustable device.
GND
2
2
—
IN
1
1
I
The IN pin is the input to the device.
OUT
6
5
O
The OUT pin is the regulated output of the device.
Regulator ground.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input voltage range (2)
–0.3
6
V
Voltage range at EN
–0.3
VIN + 0.3
V
Voltage on OUT
–0.3
6
V
Peak output current
Internally limited
See Thermal Information
table
Continuous total power dissipation
Operating virtual junction temperature, TJ
–40
Operating ambient temperature, TA
Storage temperature, Tstg
(1)
(2)
150
°C
–40
85
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground pin.
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
3
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
(1)
VIN
Input voltage
IOUT
Continuous output current (2)
TJ
Operating junction temperature
(1)
(2)
NOM
MAX
UNIT
2.7
5.5
V
0
100
mA
–40
125
°C
To calculate the minimum input voltage for your maximum output current, use the following formula:
VIN(min) = VOUT(max) + dropout voltage (VDO) at maximum load.
Continuous output current and operating junction temperature are limited by internal protection circuitry, but the device is not
recommended to be operated under conditions beyond those specified in this table for extended periods of time.
6.4 Thermal Information
TPS791
THERMAL METRIC (1)
DBV (SOT23)
DBV (SOT23)
UNIT
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
192.6
168.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
104.2
87.1
°C/W
RθJB
Junction-to-board thermal resistance
55.2
36.9
°C/W
ψJT
Junction-to-top characterization parameter
24.1
17.1
°C/W
ψJB
Junction-to-board characterization parameter
54.8
36.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
6.5 Electrical Characteristics
over recommended operating free-air temperature range, (TJ = –40°C to 125°C), VIN = VOUT(typ) + 1 V, IOUT= 1 mA, EN = 0 V,
COUT = 10 µF, CBYPASS= 0.01 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C, 1.22 V ≤ VOUT ≤ 5.2 V
TPS79101
TPS79118
Output voltage
TPS79133
TPS79147
VREF
0.98
VOUT
TJ = 25°C
1.764
TJ = 25°C
Output noise voltage (TPS79118)
0 µA < IOUT < 100 mA, 4.3 V < VIN < 5.5 V
3.234
TJ = 25°C
0 µA < IOUT < 100 mA, 5.2 V < VIN < 5.5 V
V
170
0 µA < IOUT < 100 mA
250
5
VOUT + 1 V < VIN ≤ 5.5 V, TJ = 25°C
VOUT + 1 V < VIN ≤ 5.5 V
0.12
CBYPASS = 0.001 µF
32
CBYPASS = 0.0047 µF
17
CBYPASS = 0.01 µF
16
CBYPASS = 0.1 µF
15
CBYPASS = 0.001 µF
53
CBYPASS = 0.0047 µF
67
VOUT = 0 V (1)
285
600
UVLO threshold
VIN rising
2.25
2.65
UVLO hysteresis
TJ = 25°C, VIN rising
Standby current
EN = VIN, 2.7 V < VIN < 5.5 V
High level enable input voltage
2.7 V < VIN < 5.5 V
Low level enable input voltage
2.7 V < VIN < 5.5 V
Input current (EN)
EN = VIN
TPS79133
Dropout voltage (3)
TPS79147
100
0.07
mA
V
mV
1
2
µA
V
–1
80
f = 100 Hz, TJ = 25°C, IOUT = 100 mA
75
f = 10 kHz, TJ = 25°C, IOUT = 100 mA
72
f = 100 kHz, TJ = 25°C, IOUT = 100 mA
45
f = 100 Hz, TJ = 25°C, IOUT = 10 mA
70
f = 100 Hz, TJ = 25°C, IOUT = 100 mA
75
f = 10 kHz, TJ = 25°C, IOUT = 100 mA
73
f = 100 kHz, TJ = 25°C, IOUT = 100 mA
37
IOUT = 100 mA, TJ = 25°C
50
IOUT = 100 mA
IOUT = 100 mA
µs
98
f = 100 Hz, TJ = 25°C, IOUT = 10 mA
IOUT = 100 mA, TJ = 25°C
%/V
µVRMS
Output current limit
Power-supply ripple
rejection
µA
mV
0.05
RL = 33 Ω, COUT =
1 µF, TJ = 25°C
TPS79133
(2)
(3)
4.794
Time, start-up (TPS79133)
TPS79118
(1)
3.366
4.606
0 µA < IOUT < 100 mA, TJ = 25°C
BW = 100 Hz to
100 kHz, IOUT =
100 mA, TJ = 25°C
V
4.7
CBYPASS = 0.01 µF
VDO
1.836
3.3
0 µA < IOUT < 100 mA, TJ = 25°C
Output voltage line regulation (2)
UNIT
1.02
VOUT
1.2246
Load regulation
PSRR
MAX
1.8
0 µA < IOUT < 100 mA, 2.8 V < VIN < 5.5 V
Reference voltage
Quiescent current (GND current)
ΔVOUT/
VOUT
0 µA < IOUT < 100 mA (1) ,1.22 V ≤ VOUT ≤ 5.2 V
TYP
VOUT
0.7
V
1
µA
dB
90
38
mV
70
The minimum VIN operating voltage is 2.7 V or VOUT(typ) + 1 V, whichever is greater. The maximum VIN voltage is 5.5 V. The maximum
output current is 100 mA.
If VOUT ≤ 1.8 V then VINmin = 2.7 V and VINmax = 5.5 V.
Equals VIN voltage – VOUT(typ) – 100 mV; the TPS79118 dropout voltage is limited by the minimum input voltage range limitations.
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
5
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
6.6 Typical Characteristics
1.803
3.303
1.802
3.302
V OUT – Output Voltage – V
VOUT – Output Voltage – V
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
1.801
1.8
1.799
3.301
3.3
3.299
3.298
1.798
1.797
3.297
0
20
40
60
80
IOUT – Output Current – mA
100
0
20
40
60
80
100
IOUT – Output Current – mA
VIN = 2.8 V, COUT = 10 µF, TJ = 25°C
VIN = 4.3 V, COUT = 10 µF, TJ = 25°C
Figure 1. TPS79118 Output Voltage vs Output Current
Figure 2. TPS79133 Output Voltage vs Output Current
1.82
3.32
V OUT – Output Voltage – V
V OUT – Output Voltage – V
1.815
1.81
1.805
IOUT = 1 mA
1.8
1.795
IOUT = 100 mA
1.79
3.31
IOUT = 1 mA
3.3
3.29
IOUT = 100 mA
3.28
1.785
1.78
–40 –25 –10 5
3.27
–40 –25 –10 5
20 35 50 65 80 95 110 125
VIN = 4.3 V, COUT = 10 µF
VIN = 2.8 V, COUT = 10 µF
Figure 4. TPS79133 Output Voltage vs
Junction Temperature
Figure 3. TPS79118 Output Voltage vs
Junction Temperature
260
Hz
0.2
Output Spectral Noise Density – mV/
Ground Current – m A
240
220
200
IOUT = 1 mA
180
IOUT = 100 mA
160
140
120
100
–40 –25 –10 5
20 35 50 65 80 95 110 125
VIN = 4.3 V, COUT = 10 µF
0.18
0.16
0.14
0.12
IOUT = 100 mA
0.1
0.08
IOUT = 1 mA
0.06
0.04
0.02
0
100
TJ – Junction Temperature – °C
1k
10k
f – Frequency – Hz
100k
VIN = 2.8 V, COUT = 1 µF, CBYPASS = 0.1 µF
Figure 5. TPS79133 Ground Current vs
Junction Temperature
6
20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 6. TPS79118 Output Spectral Noise Density vs
Frequency
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
1.2
0.2
IOUT = 1 mA
0.15
IOUT = 100 mA
0.1
0.05
0
100
1k
10k
f – Frequency – Hz
C BYPASS = 0.001 mF
1
Output Spectral Noise Density – mV/
Output Spectral Noise Density – mV/
Hz
Hz
0.25
0.8
Figure 7. TPS79118 Output Spectral Noise Density vs
Frequency
0.2
0
VIN = 2.8 V, IOUT = 100 mA, COUT = 10 µF
Figure 8. TPS79118 Output Spectral Noise Density vs
Frequency
Hz
Hz
Output Spectral Noise Density – mV/
Output Spectral Noise Density – mV/
0.25
IOUT = 100 mA
0.2
0.15
IOUT = 1 mA
0.1
0.05
0
100
1k
10k
f – Frequency – Hz
Figure 9. TPS79133 Output Spectral Noise Density vs
Frequency
C BYPASS = 0.001 mF
1.6
1.4
C BYPASS = 0.0047 mF
C BYPASS = 0.1 mF
0.8
C BYPASS = 0.01 mF
0.4
0.2
0
1k
10k
0.3
0.25
IOUT = 100 mA
0.2
0.15
IOUT = 1 mA
0.1
0.05
0
100
1k
10k
f – Frequency – Hz
100k
VIN = 4.3 V, COUT = 10 µF, CBYPASS = 0.1 µF
Figure 10. TPS79133 Output Spectral Noise Density vs
Frequency
RMS – Root Mean Squared Output Noise –
m V (RMS)
Output Spectral Noise Density – mV/
Hz
2
0.6
0.35
100k
VIN = 4.3 V, COUT = 1 µF, CBYPASS = 0.1 µF
100
100k
0.4
0.3
1
1k
10k
f – Frequency – Hz
100
0.35
1.2
C BYPASS = 0.01 mF
0.4
0.4
1.8
C BYPASS = 0.1 mF
0.6
100k
VIN = 2.8 V, COUT = 10 µF, CBYPASS = 0.1 µF
C BYPASS = 0.0047 mF
100k
f – Frequency – Hz
70
60
50
VOUT = 3.3 V
40
30
VOUT = 1.8 V
20
10
0
0.001
0.01
0.1
C(BYPASS ) – Bypass Capacitance – mF
VIN = 4.3 V, IOUT = 100 mA, COUT = 10 µF
Figure 11. TPS79133 Output Spectral Noise Density vs
Frequency
BW = 100 Hz to 100 kHz
Figure 12. Root Mean Squared Output Noise vs
Bypass Capacitance
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
7
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
80
3
V DO – Dropout Voltage – mV
Z o – Output Impedance – W
70
2.5
2
IOUT = 1 mA
1.5
1
IOUT = 100 mA
0.5
60
50
IOUT = 100 mA
40
30
20
IOUT = 10 mA
10
0
0
10
100
1k
1M
100k
10k
–40 –25 –10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
10M
f – Frequency – Hz
VIN = 3.2 V, COUT = 10 µF
VIN = 4.3 V, COUT = 10 µF, TJ = 25°C
Figure 14. TPS79133 Dropout Voltage vs
Junction Temperature
Figure 13. TPS79133 Output Impedance vs Frequency
120
100
V DO – Dropout Voltage – mV
V DO – Dropout Voltage – mV
90
80
TJ = 125°C
70
60
TJ = 25°C
50
40
30
20
TJ = –40°C
100
TJ = 125°C
80
60
TJ = 25°C
40
TJ = –40°C
20
10
0
2.5
0
0
0.02
0.04
0.06
0.08
0.1
IOUT – Output Current – A
3
3.5
4
4.5
5
VIN – Input Voltage – V
VIN = 3.2 V, COUT = 10 µF
IOUT = 100 mA
Figure 15. TPS79133 Dropout Voltage vs Output Current
Figure 16. TPS79101 Dropout Voltage vs Input Voltage
5.2
90
4.2
Ripple Rejection – dB
Minimum Required Input Voltage – V
IOUT = 1 mA
80
4.7
TJ = 125°C
3.7
TJ = –40°C
3.2
TJ = 25°C
60
IOUT = 100 mA
50
40
30
20
2.7
10
2.2
1.5
2
2.5
3
3.5
4
4.5
0
100
5
1k
10k
100k
1M
10M
f – Frequency – Hz
VOUT – Output Voltage – V
VIN = 3.2 V, COUT = 10 µF
VIN = 2.8 V, COUT = 10 µF, CBYPASS = 0.01 µF
Figure 17. Minimum Required Input Voltage vs
Output Voltage
8
70
Figure 18. TPS79118 Ripple Rejection vs Frequency
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
90
90
80
IOUT = 10 mA
IOUT = 10 mA
70
60
50
40
IOUT = 100 mA
30
70
Ripple Rejection – dB
Ripple Rejection – dB
80
60
50
40
30
20
20
10
10
0
100
1k
10k
100k
1M
IOUT = 100 mA
0
100
10M
1k
f – Frequency – Hz
VIN = 2.8 V, COUT = 1 µF, CBYPASS = 0.01 µF
100
90
90
IOUT = 100 mA
80
70
60
10M
IOUT = 10 mA
40
IOUT = 100 mA
70
60
IOUT = 10 mA
50
40
30
30
20
20
10
100
100k
1k
10k
f – Frequency – Hz
1M
10M
VIN = 4.3 V, COUT = 10 µF, CBYPASS = 0.01 µF
Figure 21. TPS79133 Ripple Rejection vs Frequency
10
1k
10k 100k
f – Frequency – Hz
1M
10M
Figure 22. TPS79133 Ripple Rejection vs Frequency
Enable Voltage – V
90
80
100
VIN = 4.3 V, COUT = 1 µF, CBYPASS = 0.01 µF
100
IOUT = 100 mA
70
3
2
1
0
CBYPASS = 0.001 mF
60
V OUT –
Output Voltage – V
Ripple Rejection – dB
1M
Figure 20. TPS79118 Ripple Rejection vs Frequency
100
50
100k
VIN = 2.8 V, COUT = 1 µF, CBYPASS = 0.1 µF
Ripple Rejection – dB
Ripple Rejection – dB
Figure 19. TPS79118 Ripple Rejection vs Frequency
80
10k
f – Frequency – Hz
IOUT = 10 mA
50
40
30
20
10
100
1k
10k 100k
f – Frequency – Hz
1M
Figure 23. TPS79133 Ripple Rejection vs Frequency
CBYPASS = 0.0047 mF
2
1
CBYPASS = 0.01 mF
0
0
10M
VIN = 4.3 V, COUT = 1 µF, CBYPASS = 0.1 µF
3
20 40
60 80 100 120 140 160 180 200
t – Time – ms
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 100 mA, COUT = 1 µF, TJ = 25°C
Figure 24. TPS79133 Output Voltage, Enable Voltage vs
Time (Start-Up)
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
9
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
Typical Characteristics (continued)
10
0
20
0
–20
–40
Current Load – mA
V IN –
Input Voltage – V
–10
Output Voltage – mV
DV OUT – Change In
VOUT –
Output Voltage – mV
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
3.8
100
2.8
0
10 20
30 40 50
0
60 70 80 90 100
0 200 400 600 800 1k 12k 14k 16k 18k 20k
t – Time – ms
t – Time – ms
IOUT = 100 mA, COUT = 1 µF, CBYPASS = 0.01 µF
VIN = 2.8 V, COUT = 10 µF
– Change In
OUT
Output Voltage – mV
Figure 26. TPS79118 Load Transit Response
20
0
20
0
–20
DV
–20
–40
5.3
4.3
0
5
10
15 20
25
30
35 40
45 50
I OUT –
Output Current – mA
V IN –
Input Voltage – V
VOUT –
Output Voltage – mV
Figure 25. TPS79118 Line Transient Response
100
0
0
50 100 150 200 250 300 350 400 450 500
t – Time – ms
t – Time – ms
IOUT = 100 mA, COUT = 1 µF, CBYPASS = 0.01 µF,
dv / dt = 0.4 V / ms
Figure 27. TPS79133 Line Transient Response
VIN = 4.3 V, COUT = 10 µF
Figure 28. TPS79133 Load Transit Response
100
ESR – Equivalent Series Resistance – W
ESR – Equivalent Series Resistance – W
100
10
Region of Instability
1
0.1
Region of
Instability
0.01
0
0.02
0.04
0.06
0.08
0.1
Region of Instability
1
0.1
Region of Stability
0.01
0
IOUT – Output Current – A
0.02
0.04
0.06
0.08
0.1
IOUT – Output Current – A
VIN = 5.5 V, COUT = 0.47 µF, TJ = –40°C to 125°C
Figure 29. TPS79118 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
10
10
VIN = 5.5 V, COUT = 1 µF, TJ = –40°C to 125°C
Figure 30. TPS79118 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(typ) + 1 V, IOUT = 1 mA, EN = 0 V, COUT = 10 µF, and CBYPASS = 0.01 µF (unless otherwise noted)
ESR – Equivalent Series Resistance – W
100
10
Region of Instability
1
0.1
Region of Stability
0.01
0
0.02
0.04
0.06
0.08
0.1
IOUT – Output Current – A
VIN = 5.5 V, COUT = 10 µF, TJ = –40°C to 125°C
Figure 31. TPS79118 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
11
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TPS791 device is a high PSRR, ultra-low noise, 100-mA linear regulator (LDO). The fast start-up time and
the excellent load and line transient behavior of this device qualify the TPS791 to be an ideal solution for signal
RF and signal-chain applications.
7.2 Functional Block Diagrams
VOUT
VIN
UVLO
Current
Sense
SHUTDOWN
ILIM
R1
_
GND
+
FB
EN
R2
UVLO
Thermal
Shutdown
External to
the Device
Bandgap
Reference
VIN
250 kW
Bypass
Copyright © 2018, Texas Instruments Incorporated
Figure 32. Functional Block Diagram: Adjustable Version
VOUT
VIN
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
R1
+
UVLO
R2
Thermal
Shutdown
VIN
Bandgap
Reference
250 kW
VREF
Bypass
Copyright © 2018, Texas Instruments Incorporated
Figure 33. Functional Block Diagram: Fixed Version
12
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
7.3 Feature Description
7.3.1 Power Dissipation and Junction Temperature
Specified regulator operation is confirmed at a junction temperature of 125°C; restrict the maximum junction
temperature to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
T J max T A
PD max
R TJA
where
•
•
•
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Information table)
TA is the ambient temperature
(1)
The regulator dissipation is calculated using:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
7.3.2 Programming the TPS79101 Adjustable Regulator
The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider; see
Figure 32. The output voltage is calculated using:
R1 ·
§
VOUT VREF u ¨ 1
¸
© R2 ¹
where
•
VREF = 1.2246 V typ (the internal reference voltage)
(3)
Select resistors R1 and R2 for approximately a 50-µA divider current. Lower value resistors can be used for
improved noise performance, but the solution consumes more power. Avoid higher resistor values because
leakage current into or out of FB across R1, R2 creates an offset voltage that artificially increases or decreases
the feedback voltage and thus erroneously decreases or increases VOUT. The recommended design procedure is
to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and then calculate R1 using:
§ V
·
R1 ¨ OUT 1¸ u R2
VREF
©
¹
(4)
In order to improve the stability of the adjustable version, a small compensation capacitor is suggested to be
placed between OUT and FB. For voltages < 1.8 V, the value of this capacitor must be 100 pF. For voltages >
1.8 V, the approximate value of this capacitor can be calculated as:
3 u 10
C1
7
u R1 R2
R1u R2
(5)
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
13
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
Feature Description (continued)
The table in Figure 34 shows the suggested value of this capacitor for several resistor ratios. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum
recommended output capacitor is 2.2 µF instead of 1 µF.
TPS79101
VI
OUTPUT VOLTAGE
PROGRAMMING GUIDE
IN
1 µF
≥2V
EN
OUT
VO
C1
R1
≤ 0.7 V
0.01 µF
BYPASS FB
GND
1 µF
OUTPUT
VOLTAGE
R1
R2
C1
2.5 V
31.6 kΩ 30.1 kΩ
22 pF
3.3 V
51 kΩ 30.1 kΩ
15 pF
3.6 V
59 kΩ 30.1 kΩ
15 pF
R2
Figure 34. TPS79101 Adjustable LDO Regulator Programming
7.3.3 Regulator Protection
The TPS791 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting may
be appropriate.
The TPS791 features internal current limiting and thermal protection. During normal operation, the TPS791 limits
output current to approximately 400 mA. When current limiting engages, the output voltage scales back linearly
until the overcurrent condition ends. Although current limiting is designed to prevent gross device failure, care
must be taken not to exceed the power dissipation ratings of the package or the absolute maximum voltage
ratings of the device. If the temperature of the device exceeds approximately 165°C, thermal-protection circuitry
shuts the device down. When the device cools down to below approximately 140°C, regulator operation
resumes.
14
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as the |VIN(min)|
• The input voltage magnitude is greater than the nominal output voltage magnitude added to the dropout
voltage
• |VEN| < low-level enable pin input voltage (0.7 V)
• The output current is less than the current limit
• The device junction temperature is less than the maximum specified junction temperature
7.4.2 Dropout Operation
If the input voltage magnitude is lower than the nominal output voltage magnitude plus the specified dropout
voltage magnitude, but all other conditions are met for normal operation, the device operates in dropout mode. In
this mode of operation, the output voltage magnitude is the same as the input voltage magnitude minus the
dropout voltage magnitude. The transient performance of the device is significantly degraded because the pass
device (such as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through
the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• |VEN| > high-level enable pin input voltage (2 V)
• The device junction temperature is greater than the thermal shutdown temperature
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
|VIN| > { |VOUT(nom)| + |VDO|, |VIN(min)| }
|VEN| < 0.7 V
I OUT < ICL
T J < 125°C
Dropout mode
|VIN(min)| < |VIN| < |VOUT(nom)| + |VDO|
|VEN| < 0.7 V
—
TJ < 125°C
Disabled mode
(any true condition disables the device)
—
|VEN| > 2 V
—
TJ > 170°C
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
15
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS791 low-dropout (LDO) regulator is optimized for use in noise-sensitive battery-operated equipment. The
device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (170 µA
typically), and an active-low, enable input to reduce supply currents to less than 1 µA when the regulator is
turned off.
8.1.1 External Capacitor Requirements
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS791, is required for stability and to improve transient response, noise rejection, and ripple rejection. A highervalue electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the
device is located several inches from the power source.
Like all low dropout regulators, the TPS791 requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1-µF or larger ceramic
capacitor is suitable. The device is also stable with a 0.47-µF ceramic capacitor with at least 75 mΩ of ESR.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS791 has a BYPASS pin that
is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low-pass filter to reduce
the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the BYPASS pin must be at a minimum because any leakage current creates an
IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current.
For example, the TPS79118 exhibits approximately 15 µVRMS of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 1-µF ceramic output capacitor. The output starts up slower as the bypass capacitance
increases because of the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and
external capacitor.
8.2 Typical Application
Figure 35 shows a typical application circuit.
IN
OUT
0.1 PF
VOUT
1 PF
TPS791
EN
BYPASS
GND
0.1 PF
Copyright © 2018, Texas Instruments Incorporated
Figure 35. Typical Application Circuit
16
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
Typical Application (continued)
8.2.1 Design Requirements
Table 2 shows the parameters used for this design example.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.3 V to 3.5 V (Lithium Ion battery)
Output voltage
3.3 V
DC output current
10 mA
Peak output current
100 mA
Maximum ambient temperature
60°C
8.2.2 Detailed Design Procedure
Select the desired output voltage option. An input capacitor of 0.1 µF is used because the battery is connected to
the input through a via and a short 10-mil (0.01-in) trace. An output capacitor of 1 mF is used in this design
example. A smaller size output capacitor can be used up to a minimum of 1 µF to stabilize the internal control
loop.
8.2.3 Application Curves
Enable Voltage – V
100
80
IOUT = 100 mA
70
2
1
0
CBYPASS = 0.001 mF
60
V OUT –
Output Voltage – V
Ripple Rejection – dB
90
3
IOUT = 10 mA
50
40
30
20
10
100
1k
10k 100k
f – Frequency – Hz
1M
CBYPASS = 0.0047 mF
2
1
CBYPASS = 0.01 mF
0
0
10M
Figure 36. TPS79133 Ripple Rejection vs Frequency
3
20 40
60 80 100 120 140 160 180 200
t – Time – ms
Figure 37. TPS79133 Output Voltage, Enable Voltage vs
Time (Start-Up)
8.3 Do's and Don'ts
Do place at least one, low-ESR, 1-µF capacitor as close as possible between the OUT pin of the regulator and
the GND pin.
Do place at least one, low-ESR, 0.1-µF capacitor as close as possible between the IN pin of the regulator and
the GND pin.
Do provide adequate thermal paths away from the device.
Do not place the input or output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not float the Enable (EN) pin.
Do not resistively or inductively load the BYPASS pin.
Do not let the output voltage get more than 0.3 V above the input voltage.
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
17
TPS791
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
www.ti.com
9 Power Supply Recommendations
This device is designed to operate from an input voltage supply range from 2.7 V to 5.5 V. The input voltage
range must provide adequate headroom in order for the device to have a regulated output. This input supply
must be well-regulated and stable. A 0.1-µF input capacitor is required for stability; if the input supply is noisy,
additional input capacitors with low ESR can help improve the output noise performance.
10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with a low ESR
ceramic bypass capacitor with an X5R or X7R dielectric.
Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize
performance and ensure stability. Every capacitor (CIN, COUT, CBYPASS, and C1) must be placed as close as
possible to the device and on the same side of the PCB as the regulator itself.
Do not place any capacitors on the opposite side of the PCB from where the regulator is installed. The use of
vias and long traces is strongly discouraged because these circuits can impact system performance negatively,
and even cause instability.
10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac measurements such as PSRR, output noise, and transient response, TI recommends that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
ground pin of the device. In addition, connect the ground connection for the bypass capacitor directly to the
ground pin of the device.
10.2 Layout Example
Output Ground
Output Plane
Input Plane
IN
OUT
GND
FB
EN(1)
BYPASS
Input Ground
NR and FB
Ground
Denotes via
(1)
The EN pin is active low.
Figure 38. Layout Example (6-Pin DBV Package)
18
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
TPS791
www.ti.com
SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: TPS791
19
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS79101DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PEUI
TPS79101DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PEUI
TPS79101DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PEUI
TPS79118DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PERI
TPS79118DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PERI
TPS79118DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PERI
TPS79133DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PESI
TPS79133DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PESI
TPS79133DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PESI
TPS79147DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETI
TPS79147DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETI
TPS79147DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS791 :
• Automotive: TPS791-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS79101DBVR
SOT-23
DBV
6
3000
178.0
9.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
TPS79101DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79118DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79118DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79133DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79133DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79147DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TPS79147DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS79101DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS79101DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS79118DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79118DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TPS79133DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79133DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TPS79147DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79147DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising