Texas Instruments | TPS92830-Q1 3-Channel High-Current Linear LED Controller (Rev. B) | Datasheet | Texas Instruments TPS92830-Q1 3-Channel High-Current Linear LED Controller (Rev. B) Datasheet

Texas Instruments TPS92830-Q1 3-Channel High-Current Linear LED Controller (Rev. B) Datasheet
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TPS92830-Q1
SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
TPS92830-Q1 3-Channel High-Current Linear LED Controller
1 Features
3 Description
•
With the trend of better lighting homogeneity, highcurrent LEDs are often used in automotive front and
rear lamps with lighting diffusers and light-guides.
Meanwhile, in order to meet strict EMC and reliability
requirements, linear LED drivers are popular in
automotive applications. However, it is a challenge to
deliver high current for linear LED drivers with
integrated power transistors. The TPS92830-Q1
device is an advanced automotive-grade high-side
constant-current linear LED controller for delivering
high current using external N-channel MOSFETs. The
device has a full set of features for automotive
applications and is compatible with a wide selection
of N-channel MOSFETs.
1
•
•
•
•
•
•
AEC-Q100 Qualified
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Wide Voltage Input Range From 4.5 V to 40 V
3-Channel High-Side Current Driving and Sensing
– Channel-Independent Current Setting
– Channel-Independent PWM Inputs
– PWM Dimming via Both PWM Inputs and
Power Supply
– Optimized Slew Rate for EMC
High-Precision LED Driving
– Precision Current Regulation With External NChannel MOSFET (2.5% Tolerance)
– 20:1 Analog Dimming Profile With Off-Board
Bin Resistor Support
– Precision PWM Generator With Full DutyCycle Mask (2% Tolerance)
– Open-Drain PWM Output for Synchronization
Protection and Diagnostics
– Adjustable Output Current Derating for
External MOSFET Thermal Protection
– Diagnostics for LED-String Open Circuit or
Short Circuit With Auto Recovery
– Diagnostic-Enable With Adjustable Threshold
for Low-Voltage Operation
– Fault Bus up to 15 Devices, Configurable As
Either One-Fails–All-Fail or Only-FailedChannel-Off
– Low Quiescent Current in Fault Mode (<0.75
mA per Device)
Operating Junction Temperature Range: –40°C to
150°C
TSSOP 28 Package (PW)
Each channel of the TPS92830-Q1 device sets the
channel current independently by the sense-resistor
value. An internal precision constant-current
regulation loop senses the channel current by the
voltage across the sense resistor and controls the
gate voltage of the N-channel MOSFET accordingly.
The device also integrates a two-stage charge pump
for low-dropout operation. The charge-pump voltage
is high enough to support a wide selection of Nchannel iMOSFETs. iPWM idimming iallows imultiple
Device Information(1)
PART NUMBER
PACKAGE
TPS92830-Q1
TSSOP (28)
BODY SIZE (NOM)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Battery
TPS92830-Q1
CP1P
ISP
CP1N
ISN1
GND
CP2N
G1
SENSE1
CP2P
CPOUT
IN
ISN2
G2
SENSE2
DIAGEN
DERATE
2 Applications
•
•
Rear Light – Tail and Stop Light, Rear Turn
Indicator, Fog Light, Reverse Light
Front Light – Position Light, Daytime Running
Light, Front Turn Indicator, Low Beam
ISN3
G3
SENSE3
PWM1
Full Duty Cycle
PWMOUT
PWM2
FAULT
PWM3
PWMCHG
FD
FAULT Bus
IREF
ICTRL
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92830-Q1
SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 29
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Applications ................................................ 30
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2017) to Revision B
•
Page
Changed timing specification for PWM duty cycle ................................................................................................................. 9
Changes from Original (July 2017) to Revision A
Page
•
Changed tolerances for current regulation and PWM generator in the Features section ..................................................... 1
•
Changed values for several parameters throughout the Electrical Characteristics table....................................................... 7
•
Changed parameter definitions for I(DRV_source) and I(DRV_sink) in the Electrical Chaaracteristics table ..................................... 7
•
Changed parameter symbols for analog dimming accuracy in the Electrical Characteristics table....................................... 8
•
Changed parameter descriptions for V(OPEN_th_rising), V(OPEN_th_falling), ....................................................................................... 8
•
Changed parameter descriptions for t(SG_retry_OFF) and t(OPEN_retry_OFF) in the Timing Requirements table............................... 9
•
Added a condition for Typical Characteristic Figure 6 ......................................................................................................... 11
•
Deleted a condition from Typical Characteristic Figure 8 .................................................................................................... 12
•
Deleted a Fast Power Down and Slow Power Up typical characteristic graph .................................................................... 12
•
Added a Fast Power Down and Slow Power Up typical characteristic graph ...................................................................... 13
•
Added a condition for Typical Characteristic Figure 17 ....................................................................................................... 13
•
Added a condition for Typical Characteristic Figure 18........................................................................................................ 13
•
Changed heat dissipation to current distribution in Parallel MOSFET Driving ..................................................................... 17
•
Deleted a sentence from the PWM Dimming by Input section............................................................................................. 18
•
Added resistor and capacitor reference designators............................................................................................................ 19
•
Deleted percentage values for V(ICTRL_LIN_BOT) and V(ICTRL_LIN_TOP) in the Analog Dimming Topology section ...................... 21
•
Changed V(SG_th_rising) and V(SG_th_falling) with each other in the LED Short-to-GND Detection section .................................. 25
•
Changed symbol of short-to-ground retry current to I(Retry_short) ............................................................................................ 26
•
Changed symbol of LED-open retry current to I(Retry_open) in the LED Open-Circuit Auto Retry section............................... 26
•
Changed some FAULT TYPE names in Table 4.................................................................................................................. 29
•
Updated application schematic. ........................................................................................................................................... 30
•
Changed the value of R8 from 75 kΩ to 76 kΩ for the PWM threshold setting ................................................................... 31
2
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SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
•
Changed the equation for calculating K(RES_DiagEn) ................................................................................................................ 31
•
Changed the values of R13 and R6 for ............................................................................................................................... 31
•
Changed the equation for calculating K(RES_DERATE) .............................................................................................................. 31
•
Changed component values inthe PWM equations of the Detailed Design Procedure ....................................................... 33
•
Added an application curve .................................................................................................................................................. 34
•
Added text in the Layout Guidelines for keeping LED ground separate from device ground .............................................. 36
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SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
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5 Description (Continued)
sources for flexibility—internal PWM generator, external PWM inputs, or power supply dimming. Various
diagnostics and protection features specially designed for automotive applications help improve system
robustness and ease of use. A one-fails–all-fail fault bus supports TPS92830-Q1 operation together with the
TPS92630-Q1, TPS92638-Q1, and TPS9261x-Q1 family to fulfill various fault-handling requirements.
6 Pin Configuration and Functions
PW Package
28-Pin TSSOP
Top View
CP1P
1
28
ISP
CP1N
2
27
ISN1
GND
3
26
G1
CP2N
4
25
SENSE1
CP2P
5
24
ISN2
CPOUT
6
23
G2
IN
7
22
SENSE2
DIAGEN
8
21
ISN3
DERATE
9
20
G3
PWM1
10
19
SENSE3
PWM2
11
18
PWMOUT
PWM3
12
17
FAULT
FD
13
16
PWMCHG
ICTRL
14
15
IREF
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CP1N
2
O
Charge pump first-stage flying capacitor negative output, charge pump to provide gate-drive
voltage for external MOSFET. Connect a 10-nF flying capacitor between CP1P and CP1N.
CP1P
1
O
Charge pump first-stage flying capacitor positive output
CP2N
4
O
Charge pump second-stage flying capacitor negative output. Connect a 10-nF flying
capacitor between CP2P and CP2N.
CP2P
5
O
Charge pump second-stage flying capacitor positive output
CPOUT
6
O
Charge-pump output voltage. Connect a 150-nF storage capacitor between CPOUT and IN.
DERATE
9
I
Voltage input for current derating. Connect to GND to disable the derate feature.
DIAGEN
8
I
Input pin with comparator to enable diagnostics to avoid false open-fault diagnostics when
the device works in low-dropout mode. Use a resistor divider to set a threshold according to
the LED forward voltage.
FAULT
17
I/O
Fault bus pin to support one-fails–all-fail feature. Float: one-fails–all-fail; strong pullup: onlyfails-off
FD
13
I
Full duty-cycle input, HIGH: 100% PWM; LOW: using external resistor-capacitor network to
set PWM duty cycle
4
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SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
G1
26
O
Channel 1 gate driver output, connect to CH 1 N-channel MOSFET gate
G2
23
O
Channel 2 gate driver output, connect to CH 2 N-channel MOSFET gate
G3
20
O
Channel 3 gate driver output, connect to CH 3 N-channel MOSFET gate
GND
3
—
GND
ICTRL
14
I
Analog dimming input, modulates the regulation voltage across the current-sense resistor.
Apply a voltage source or connect a resistor between ICTRL and GND to set the analog
dimming ratio.
IN
7
I
Power supply for the device. LED current only flows from the external MOSFET to the LED.
ISN1
27
I
Channel 1 current-sense negative input. Connect a current-sense resistor between ISP and
ISN1 to set the CH 1 current.
ISN2
24
I
Channel 2 current-sense negative input. Connect a current-sense resistor between ISP and
ISN2 to set the CH 2 current.
ISN3
21
I
Channel 3 current-sense negative input. Connect a current-sense resistor between ISP and
ISN3 to set the CH 3 current.
IREF
15
O
Internal current reference. Connect an 8-kΩ resistor between IREF and GND,
ISP
28
I
Channel current-sense positive input. Kelvin-sense to LED sense-resistor positive node.
PWM1
10
I
Channel 1 PWM input
PWM2
11
I
Channel 2 PWM input
PWM3
12
I
Channel 3 PWM input
PWMCHG
16
I/O
On-chip PWM generator pin for external R-C. Connect a resistor and a capacitor between
PWMCHG and GND to set the PWM duty cycle and frequency.
PWMOUT
18
O
High-voltage PWM open-drain output. Connect a 10-kΩ resistor between IN and PWMOUT
SENSE1
25
I/O
Channel 1 diagnostics pin. Connect to the CH 1 MOSFET source terminal
SENSE2
22
I/O
Channel 2 diagnostics pin. Connect to the CH 2 MOSFET source terminal
SENSE3
19
I/O
Channel 3 diagnostics pin. Connect to the CH 3 MOSFET source terminal
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SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range TJ= –40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
IN (2)
–0.3
45 (3)
V
Input voltage
DERATE, DIAGEN, FD, ICTRL, ISN1, ISN2,
ISN3, ISP, PWM1, PWM2, PWM3, PWMOUT,
SENSE1, SENSE2, SENSE3 (2)
–0.3
V(IN) + 0.3
V
Output voltage
CP1P, CP2P, CPOUT, G1, G2, G3 (2)
–0.3
V(IN) + 10
V
Current-sense voltage
V(ISP) – V(ISNx)
–0.3
1
V
Gate-source voltage
V(Gx) – V(SENSEx)
–1
12
V
–0.3
22
V
FAULT (2)
I/O
–0.3
6
V
Storage temperature, Tstg
–65
150
°C
Junction temperature, TJ
-40
150
°C
(1)
(2)
(3)
CP1N, CP2N, IREF, PWMCHG
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
Absolute maximum voltage 45 V for 200 ms.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (CP1P,
ICTRL, IREF, ISP)
±750
Other pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range TJ= –40°C to 150°C (unless otherwise noted)
MIN
MAX
4.5
40
V
ISP
0
V(IN)
V
PWM inputs
PWMx
0
V(IN)
V
Diagnostics enable pin
DIAGEN
0
V(IN)
V
Current-sense voltage
V(ISP) – V(ISNx)
0
1
V
Fault bus
FAULT
0
20
V
PWM open-drain output
PWMOUT
0
V(IN)
V
Analog dimming input
ICTRL
0
V(IN)
V
Current derating input
DERATE
0
V(IN)
V
Full duty-cycle input
FD
0
V(IN)
V
Device supply voltage
IN
Sense voltage
6
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UNIT
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SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
7.4 Thermal Information
TPS92830-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
79.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.1
°C/W
RθJB
Junction-to-board thermal resistance
37.4
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
36.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
7.5 Electrical Characteristics
VIN = 5 V to 40 V, VICTRL = 3 V, VDERATE = 0 V, TJ= –40°C to 150°C, (1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS
V(POR_rising)
Supply voltage POR, rising
threshold
I(Quiescent)
Device standby current
PWMx = HIGH, FD = HIGH
3.5
I(FAULT)
Device current in fault mode
PWMx = HIGH, FAULT = LOW
0.5
I(IREF)
Reference current
R(IREF) = 8 kΩ
C(IREF)
IREF loading capacitance
R(IREF) = 8 kΩ
4.5
mA
0.75
99
0
V
mA
µA
4.3
nF
10
V
CHARGE PUMP
V(cp_drv)
Charge-pump operating voltage
f(cp_sw)
Charge-pump switching
frequency
C(cp_flying)
Charge-pump flying capacitor
C(cp_storage)
Charge-pump storage capacitor
6.1
8.5
2.65
MHz
10
nF
150
nF
HIGH-PRECISION LOGIC INPUTS (DIAGEN, PWMx, FD)
VIL(DIAGEN)
Input logic-low voltage, DIAGEN
1.105
1.145
1.185
V
VIH(DIAGEN)
Input logic-high voltage,
DIAGEN
1.193
1.224
1.255
V
VIL(PWMx)
Input logic-low voltage, PWMx
1.094
1.128
1.161
V
VIH(PWMx)
Input logic-high voltage, PWMx
1.176
1.212
1.248
V
VIL(FD)
Input logic-low voltage, FD
1.105
1.133
1.161
V
VIH(FD)
Input logic-high voltage, FD
1.186
1.216
1.246
V
CONSTANT-CURRENT EXTERNAL N-CHANNEL MOSFET DRIVER
V(CS_REG_FULL)
∆V(CS)
(2) (3)
I(DRV_source)
(1)
Current-sense-resistor
regulation voltage
Current-sense-resistor
regulation-voltage accuracy
295
mV
V(ICTRL) = 3 V, V(DERATE) = 0 V,
channel accuracy
–1.5%
1.5%
V(ICTRL) = 3 V, V(DERATE) = 0 V,
device accuracy
–2.5%
2.5%
Gate-driver current-source
capability at Gx
190
230
270
µA
External N-channel MOSFET Ciss = 200 pF, Coss = 70 pF, at VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz, Vth= 4 V, compensation capacitor
Cgs = 4 nF
'V CS _ Channel _ CHx
'V CS _ Device _ CHx
3 u V CS _ REG _ x
1
V CS _ REG _1
(2)
(3)
V(ICTRL) = 3 V, V(DERATE) = 0 V
1
V CS _ REG _ x
0.295
V CS _ REG _ 2
,x
,x
1,2,3
V CS _ REG _ 3
1,2,3
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Electrical Characteristics (continued)
VIN = 5 V to 40 V, VICTRL = 3 V, VDERATE = 0 V, TJ= –40°C to 150°C,(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I(DRV_sink)
Gate-driver current-sink
capability at Gx
190
230
270
µA
V(GS_clamp_neg)
Gate-source negative clamp
voltage
–0.9
–0.7
–0.5
V
V(GS_clamp_pos)
Gate-source positive clamp
voltage
9.8
10.4
11.3
V
I(ISNx_leakage)
Leakage current sink on ISNx
pins
1.3
2.3
µA
INTERNAL PWM DIMMING
V(PWMCHG_th_rising)
Internal PWM generator, rising
threshold
1.45
1.48
1.51
V
V(PWMCHG_th_falling)
Internal PWM generator, falling
threshold
0.78
0.8
0.82
V
V(PWMCHG_th_hys)
Internal PWM generator
hysteresis
I(PWMCHG)
PWM generator pullup current
V(PWMCHG) = 0 V, FD = LOW
VOL(PWMOUT)
Open-drain PWMOUT pulldown
voltage
V(PWMCHG) = 3 V, I(PWMOUT) pullup
current = 4 mA
rDS(on)(PWMOUT)
Open-drain PWMOUT pulldown
MOSFET rDS(on)
0.68
194
40
200
55
V
206
µA
0.4
V
90
Ω
1.65
V
ANALOG DIMMING
V(ICTRL_FULL)
Full-range ICTRL voltage
V(ICTRL_LIN_TOP)
Upper boundary for linear
ICTRL dimming
1.425
V(ICTRL_LIN_BOT)
Lower boundary for linear
ICTRL dimming
75
∆V(CS_ ICTRL_H)
Analog dimming accuracy
V(ICTRL) = 1.35 V, V(DERATE) = 0 V,
accuracy: 1 – (V(CS_REG_x) / 0.27), x =
1, 2, 3
–2.5%
2%
∆V(CS_ ICTRL_M)
Analog dimming accuracy
V(ICTRL) = 0.75 V, V(DERATE) = 0 V,
accuracy: 1 – (V(CS_REG_x) / 0.15), x =
1, 2, 3
–4%
4%
∆V(CS_ ICTRL_L)
Analog dimming accuracy
V(ICTRL) = 0.15 V, V(DERATE) = 0 V,
accuracy: 1 –V(CS_REG_x) / 0.03, x =
1, 2, 3
–18%
18%
I(ICTRL_pullup)
ICTRL internal pullup current
0.95
0.985
V
mV
1.02
mA
CURRENT DERATING
V(DERATE_FULL)
Full-range DERATE voltage
1.83
V(DERATE_HALF)
Half-range DERATE voltage
2.38
K(DERATE)
Derate dimming ratio
V
V
V(DERATE) = 1.966 V
81%
87%
95%
V(DERATE) = 2.316 V
51%
58%
65%
DIAGNOSTICS
V(OPEN_th_rising)
LED open rising threshold,
device triggers open-circuit
diagnostics V(SG_th_rising), and
V(SG_th_falling) in the Electrical
Characteristics table
V(ISNx) – V(SENSEx), x = 1, 2, 3
100
145
190
mV
V(OPEN_th_falling)
LED open falling threshold,
device releases from opencircuit diagnostics
V(ISNx) – V(SENSEx), x = 1, 2, 3
240
280
320
mV
V(OPEN_th_hyst)
I(Retry_open)
8
135
LED-open retry current
8
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10
mV
12
mA
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Electrical Characteristics (continued)
VIN = 5 V to 40 V, VICTRL = 3 V, VDERATE = 0 V, TJ= –40°C to 150°C,(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(SG_th_rising)
Channel output VSENSEx shortto-ground rising threshold,
device triggers short-to-ground
diagnostics
0.885
0.92
0.95
V
V(SG_th_falling)
Channel output VSENSEx shortto-ground falling threshold,
device releases from short-toground diagnostics
1.17
1.215
1.26
V
V(SG_th_hyst)
Channel output VSENSEx shortto-ground hysteresis
I(Retry_short)
Channel output VSENSEx shortto-ground retry current
295
0.75
1
mV
1.25
mA
0.7
V
FAULT
VIL(FAULT)
Logic-input low threshold
VIH(FAULT)
Logic-input high threshold
VOL(FAULT)
Logic-output low threshold
With 500-µA external pullup
VOH(FAULT)
Logic-output high threshold
With 1-µA external pulldown
I(FAULT_pulldown)
FAULT internal pulldown
current
650
I(FAULT_pullup)
FAULT internal pullup current
6.5
2
V
0.4
V
3.4
V
750
800
µA
7.6
9.5
µA
2.7
THERMAL PROTECTION
T(TSD)
Thermal shutdown threshold
176
ºC
T(TSD_HYS)
Thermal shutdown hysteresis
15
ºC
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
t(OPEN_deg)
LED open-circuit deglitch time, described in LED open-circuit
diagnostics section
100
125
150
µs
t(SG_deg)
LED short-to-GND detection deglitch time, described in the LED shortto-GND diagnostics section
100
125
150
µs
t(SG_retry_ON)
Channel output SENSEx short-to-ground retry on-time, described in the
LED short-to-GND auto retry section
100
125
150
µs
t(SG_retry_OFF)
Channel output SENSEx short-to-ground retry off-time, described in
LED short-to-GND auto retry section
tOPEN_retry_ON) Channel output SENSEx open-circuit retry on-time
t(OPEN_retry_OF
10.8
100
Channel output SENSEx open-circuit retry off-time
125
ms
150
10.8
µs
ms
F)
D(PWM_10)
PWM duty cycle generated internally, nominal 10% duty cycle, as
measured on output channel; see Figure 1, T(J) = 25ºC
9.8%
10%
10.2%
PWM duty cycle generated internally, nominal 10% duty cycle, as
measured on output channel; see Figure 1, T(J) = -40ºC to 150ºC
9.75%
10%
10.25%
td(DERATE)
Derate current-response delay time when DERATE steps from 1.8 V to
2.4 V
25
µs
t(CP_STARTUP)
V(IN) = 14 V, Cs = 150 nF, CPOUT voltage reaches 18 V as shown in
Device Start-Up Delay diagram
25
µs
f(DRV_PWM)
Recommended PWM driving-frequency range
2000
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Input On-Time
PWMx
90%
90%
Channel
Current
IOUTx
Output On-Time
10%
t1
10%
t2
t3
t4
t5
t6
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Figure 1. Channel-Current Output Timing Diagram
10
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7.7 Typical Characteristics
TA = 25 ºC unless otherwise noted
300
300
298
V(CS_REG_FULL) (mV)
298
V(CS_REG_FULL) (mV)
40qC
25qC
125qC
296
294
296
294
292
292
290
-40
290
-25
-10
5
V(IN) = 14 V
20 35 50 65
Temperature (qC)
80
95
4
110 125
10
16
22
28
Supply Voltage (V)
D001
V(ICTRL) = 1.8 V
34
40
D002
V(ICTRL) = 1.8 V
Figure 2. Full-Range Current-Sense Voltage vs Ambient
Temperature
Figure 3. Full-Range Current-Sense Voltage vs Supply
Voltage
0.35
5
40qC
25qC
125qC
0.3
Current (mA)
V(CS_REG) (V)
0.25
0.2
0.15
40qC, I(FAULT)
25qC, I(FAULT)
125qC, I(FAULT)
40qC, I(Quiescent)
25qC, I(Quiescent)
125qC, I(Quiescent)
1
0.1
0.05
0.4
0
0
0.2
0.4
0.6
0.8
1
V(ICTRL) (V)
1.2
1.4
1.6
4
1.8
10
16
22
28
Supply Voltage (V)
D001
34
40
D003
V(IN) = 14 V
Figure 5. Device Current vs Supply Voltage
102%
50%
96%
30%
20%
90%
Output Cutrrent Ratio
Output Current Duty Cycle
Figure 4. Current-Sense Voltage vs ICTRL Input Voltage
100%
10%
5%
3%
2%
1%
78%
72%
66%
60%
0.5%
0.3%
0.2%
1%
84%
54%
2% 3%
V(IN) = 14 V
5% 7% 10%
20% 30%
Input Duty Cycle
f(PWM)= 200 Hz
50%
100%
48%
1.7
1.8
D002
V(ICTRL) = 1.8 V
Figure 6. Duty Cycle of PWM Dimming-Current Output vs
PWM Input Duty Cycle
1.9
2
2.1
2.2
2.3
Derate Voltage (V(DERATE))
2.4
2.5
D003
V(IN) = 14 V
Figure 7. Current-Derating Profile; Output-Current Ratio vs
DERATE Voltage
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Typical Characteristics (continued)
TA = 25 ºC unless otherwise noted
Ch. 1 = PWM1
Ch. 4 = I(OUT1)
Ch. 2 = G1
V(IN) = 14 V
Ch. 3 = SENSE1
Ch. 1 = PWMCHG
V(IN) = 14 V
Ch. 2 = G1
Ch. 3 = SENSE1
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Figure 10. Undervoltage
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = G1
Figure 12. Jump Start
12
Ch. 4 = I(OUT1)
Figure 9. PWM Generator
Figure 8. PWM Dimming
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = PWMOUT
Ch. 2 = G1
Ch. 3 = SENSE1
Figure 11. Transient Overvoltage
Ch. 3 = SENSE1
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = G1
ƒ = 15 Hz
Ch. 3 = SENSE1
Figure 13. Superimposed Alternating Voltage
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Typical Characteristics (continued)
TA = 25 ºC unless otherwise noted
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = G1
Ch. 3 = SENSE1
Figure 14. Fast Power Down and Slow Power Up
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = G1
Ch. 3 = SENSE1
Figure 16. Slow Decrease and Slow Increase of Supply
Voltage
Ch. 1 = FAULT
Ch. 4 = I(OUT1)
Ch. 2 = SENSE1
Ch. 3 = G1
LED short-to-ground on SENSE1
Ch. 1 = V(IN)
Ch. 4 = I(OUT1)
Ch. 2 = G1
Ch. 3 = SENSE1
Figure 15. Slow Decrease, Quick Increase of Supply Voltage
Ch. 1 = FAULT
Ch. 4 = SENSE3
Ch. 2 = SENSE1
Ch. 3 = SENSE2
LED open-circuit on SENSE1
Figure 17. LED Open-Circuit Protection and One-Fails–AllFail
Ch. 1 = V(IN)
Figure 18. LED Hard Short Protection and One-Fails–All-Fail
Ch. 2 = CP1N
Ch. 3 = CPOUT
Figure 19. Device Start-Up Delay
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8 Detailed Description
8.1 Overview
The TPS92830-Q1 device is an advanced automotive-grade high-side constant-current linear LED controller for
delivering high current using external N-channel MOSFETs. The device has a full set of features for automotive
applications. Each channel of the TPS92830-Q1 device sets the channel current independently by the senseresistor value. An internal precision constant-current regulation loop senses the channel current by the voltage
across the sense resistor and controls the gate voltage of the N-channel MOSFET accordingly. The device also
integrates a two-stage charge pump for low-dropout operation. The charge-pump voltage is high enough to
support a wide selection of N-channel MOSFETs. PWM dimming allows multiple sources for flexibility—internal
PWM generator, external PWM inputs, or power-supply dimming. Various diagnostics and protection features
specially designed for automotive applications help improve system robustness and ease of use. A one-fails–allfail fault bus supports TPS92830-Q1 operation together with the TPS92630-Q1, TPS92638-Q1, and TPS9261xQ1 family to fulfill various fault-handling requirements.
8.2 Functional Block Diagram
SUPPLY
CP1N
CP1P CP2N
CP2P
CPOUT
TPS92830-Q1
IN
Charge Pump
ICTRL
CURRENT
REGULATION
DRIVER X3
ISP
Analog
Dimming
DERATE
Current Sense
ISNx
DIAGEN
RSNSx
PWM1
Gx
MNx
Gate Driver
PWM2
Clamp
Control
Logic
SENSEx
Diagnostics
PWM3
IREF
PWMCHG
FD
PWM
Generator
Temperature
Sensor
PWMOUT
FAULT Bus
Input / Output
FAULT
GND
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8.3 Feature Description
The TPS92830-Q1 device uses IN voltage to generate device bias. A two-stage charge pump provides gate
driving voltage above the IN voltage for the high-side N-channel MOSFET. Each channel current is
independently set by sense resistors. The analog-dimming ICTRL input supports off-board resistors as binsetting resistors as well as direct voltage input. An integrated precision PWM generator could be used for PWM
dimming locally.
8.3.1 Device Bias
The TPS92830-Q1 device has internal bias-generation and power-on-reset circuits for internal bias.
8.3.1.1 Power-On-Reset (POR)
The TPS92830-Q1 device has an internal power-on-reset (POR) function. When power is applied to IN, the
internal POR holds the device in the reset condition until VIN reaches V(POR_rising).
When the supply rises above POR threshold V(POR_rising), the charge pump starts working. The maximum gatedrive voltage is determined by the charge-pump voltage between CPOUT and IN.
8.3.1.2 Current Reference (IREF)
The TPS92830-Q1 device has a constant reference-voltage output on the IREF pin and uses current I(IREF) as
the internal current reference. The analog-dimming internal-pullup current on ICTRL, and the PWM-generator
internal charge current on PWMCHG, use I(IREF) as a reference current. The recommended value of reference
resistor R(IREF) for IREF is 8 kΩ.
8.3.1.3 Low-Current Fault Mode
The TPS92830-Q1 device consumes minimal quiescent current when it is in fault mode. If the FAULT voltage is
pulled low either by internal diagnostics or externally, the device performs as follows:
• The charge pump is shut down.
• All drivers are turned off with their gates internally pulled down.
• The PWM generator and PWMOUT are turned off.
• IREF current is turned off.
• ICTRL current is turned off.
8.3.2 Charge Pump
8.3.2.1 Charge Pump Architecture
The TPS92830-Q1 device uses a two-stage charge pump to generate the high-side gate-drive voltage. The
charge pump is a voltage tripler using external flying and storage capacitors.
CP1 is the first-stage flying capacitor, connected between CP1P and CP1N, which are the positive and negative
nodes, respectively. CP2 is the second-stage flying capacitor, connected between CP2P and CP2N, which are
the positive and negative nodes, respectively. CS is the storage capacitor, connected between CPOUT and IN.
CS stores charge for the high-side gate driver.
The charge pump switches at frequency f(cp_sw) to optimize EMI performance.
Negative nodes CP1N and CP2N are driven by a 5-V driver, thus the maximum voltage on charge-pump output
node CPOUT is approximately V(IN) + V(CP_drv). The charge pump voltage across storage capacitor CS is not
dependent on V(IN).
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Feature Description (continued)
VIN
CP1
CP1N
CP2
CP1P CP2N
Cs
CP2P
CPOUT
TPS92830-Q1
IN
Charge Pump
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Charge Pump
8.3.3 Constant-Current Driving
The TPS92830-Q1 device has three independent constant-current driving channels. Each channel sets channel
current with an external high-side current-sense resistor, RSNSx. Channel current is set as V(CS_REG) / RSNSx.
Considering that both ICTRL and DERATE voltages reduce current-sense voltage V(CS_REG) independently,
channel current can be calculated using the following equation. Each of the dimming ratios is described
separately in following sections.
V(CS _ REG _ FULL) ´ k (ICTRL _ DIM) ´ k (DERATE _ DIM)
I(CHx) =
R SNSx
(1)
8.3.3.1 High-Side Current Sense
The sense voltage across external current-sense resistor RSNSx feeds back current information to the controller.
An internal feedback control loop within the TPS92830-Q1 device regulates the external gate-overdrive voltage of
the N-channel MOS transistor to keep the sense voltage at the desired level. By setting the external currentsense resistance value, the output current can be set individually on each channel.
8.3.3.2
High-Side Current Driving
To regulate the output current, the gate-source voltage of the external MOSFET must be regulated accordingly.
The constant-current source is used to charge and discharge the N-channel MOSFET gate. During the currentslewing period, constant-current sourcing and sinking ensures the smooth slewing of the output current. The
control loop requires sufficient MOSFET gate capacitance to ensure loop stability. In case the MOSFET gate
capacitance is insufficient, a capacitor CGS must be added across Gx and SENSEx. TI also recommends always
putting a CSENSE of 10 nF from each of the SENSEx pins to GND, and close to the device for EMC.
When a channel is switched on, current source I(DRV_source) charges the gate of the external N-channel MOSFET.
When a channel is switched off, current sink I(DRV_sink) discharges the gate of the external MOSFET transistor
down to ground.
16
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Feature Description (continued)
SUPPLY
STOP
TPS92830-Q1
IN
ISP
CPOUT
CP2P
RSNS1
ISN1
CP2N
MN1
CP1P
G1
CP1N
CGS
FD
IREF
SENSE1
CSENSE
PWMCHG
PWMOUT
Copyright © 2017, Texas Instruments Incorporated
Figure 21. MOSFET Gate Capacitance Compensation
8.3.3.3 Gate Overdrive Voltage Protection
A bidirectional clamp is used to protect the gate-source path of the external N-channel MOSFETs from
overstress conditions. Gate-source voltage V(GS) is clamped between V(GS_clamp_neg) and V(GS_clamp_pos) for
MOSFET protection.
8.3.3.4 High-Precision Current Regulation
The TPS92830-Q1 device has a high-precision current-regulation loop. Its precision is at the maximum when the
voltage across the current-sense resistor is set to maximum. The analog-dimming or current-derating function
reduces the current-sense voltage, thus decreasing current-regulation accuracy.
8.3.3.5 Parallel MOSFET Driving
The TPS92830-Q1 device is designed to support parallel N-channel MOSFETs driving within the same channel.
To balance heat dissipation, multiple MOSFETs could be paralleled together. A ballast resistor for each MOSFET
is recommended to balance current distribution among parallel MOSFETs.
Larger variation on threshold mismatches requires larger ballast resistors. V(TH_MISMATCH) is the threshold for
mismatches within the same batch of MOSFETs. I(CH_MISMATCH) is the allowed mismatch current between the
parallel channels. Typically, I(CH_MISMATCH) can be set to 10% of full-range current. The ballast resistor value is set
as calculated in the following equation.
V(TH _ MISMATCH)
R (Ballast) =
I(CH _ MISMATCH)
(2)
The ballast resistor typically ranges from hundreds of milliohms to several ohms depending on the channel
current and MOSFET threshold-voltage variations.
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Feature Description (continued)
SUPPLY
TPS92830-Q1
IN
ISP
RSNSx
ISNx
MN1
MN2
MN3
Gx
FAULT
SENSEx
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 22. Parallel MOSFET Driving
8.3.4 PWM Dimming
The TPS92830-Q1 device supports a variety of PWM dimming methods, including PWM supply dimming,
external PWM dimming by inputs, and internal PWM dimming by the internal PWM generator. Each PWM cycle
should allow enough positive cycle time for gate charging and enough negative cycle time for gate discharging in
order to achieve an accurate PWM dimming duty cycle.
8.3.4.1 Supply Dimming
In the case of supply dimming, the supply of the whole LED driver module is PWM dimmed, for example by
body-control-module (BCM) high-side switches. The TPS92830-Q1 device supports supply dimming with a short
power-on delay. Device supply VIN should be always equal to V(ISP) to ensure that the charge pump voltage is
high enough to turn on the MOSFET.
When supply dimming is used, it is recommended to be used together with PWM input, so that the channel is
only turned on when the input voltage is above the device UVLO threshold. By keeping enough delay time
between device power up and channel turnon, output current spikes can be avoided to ease EMC design.
8.3.4.2 PWM Dimming by Input
Each channel has individual PWM dimming by inputs.
The internal thresholds for PWM1–PWM3 are designed with high precision. With external resistor dividers, each
channel threshold can be set flexibly and independently.
8.3.4.3 Internal Precision PWM Generator
The TPS92830-Q1 device has an integrated precision PWM generator for on-chip PWM dimming as shown in .
The device supports open-drain PWMOUT for synchronization between devices. Each device can be connected
as a master, generating PWM, or as a slave, relying on external PWM sources. An external RC circuit precisely
sets the duty cycle of the PWM generator across a wide duty-cycle range. Variation of the capacitor value affects
the output frequency but not the duty cycle.
The PWM generator uses reference current 2 × I(IREF) as the internal charge current, I(PWMCHG).
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Feature Description (continued)
When V(PWMCHG) increases above rising threshold V(PWMCHG_th_rising), the constant-current source is turned off and
V(PWMCHG) decays through the external resistor-capacitor circuit. The PWM output is set LOW. The PWMCHG
threshold is set to V(PWMCHG_th_falling). When V(PWMCHG) decreases below falling threshold V(PWMCHG_th_falling), the
constant-current source is turned on again to charge up the external capacitor. The PWM output is HIGH and the
threshold is set to V(PWMCHG_th_rising).
TAIL
STOP
TPS92830-Q1
IN
ISP
CPOUT
RSNS1
ISN1
CP2P
CP2N
MN1
CP1P
G1
CP1N
SENSE1
FD
IREF
PWMCHG
PWMOUT
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 23. PWM Generator Dual-Brightness Configuration
An external resistor R(PWMEXT) and capacitor C(PWMEXT) are used to set the PWM cycle time.
t PWM _ ON
t PWM _ OFF
f PWMEXT
D PWMEXT
§ V PWMCHG _ th _ falling
R PWMEXT u C PWMEXT u ln ¨
¨V
© PWMCHG _ th _ ri sin g
R PWMEXT u C PWMEXT
§ V PWMCHG _ th _ ri sin g
u ln ¨
¨ V PWMCHG _ th _ falling
©
I PWMCHG u R PWMEXT ·
¸
I PWMCHG u R PWMEXT ¸
¹
(3)
·
¸
¸
¹
(4)
1
ª §V
PWMCHG _ th _ falling
R PWMEXT u C PWMEXT u «ln ¨
« ¨ V PWMCHG _ th _ ri sin g
¬ ©
§V
I PWMCHG u R PWMEXT ·
¸ ln ¨ PWMCHG _ th _ ri sin g
I PWMCHG u R PWMEXT ¸
¨ V PWMCHG _ th _ falling
¹
©
§ V PWMCHG _ th _ falling I PWMCHG u R PWMEXT ·
¸
ln ¨
¨ V PWMCHG _ th _ ri sin g I PWMCHG u R PWMEXT ¸
©
¹
§ V PWMCHG _ th _ ri sin g
§ V PWMCHG _ th _ falling I PWMCHG u R PWMEXT ·
¸ ln ¨
ln ¨
¨ V PWMCHG _ th _ falling
¨ V PWMCHG _ th _ ri sin g I PWMCHG u R PWMEXT ¸
©
©
¹
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·º
¸»
¸»
¹¼
(5)
·
¸
¸
¹
(6)
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Feature Description (continued)
PWM OFF
V(th_PWM_rising)
V(th_PWM_falling)
PWM ON
ON-time
t(PWM_ON)
t
OFF-time
t(PWM_OFF)
Figure 24. PWM Dimming Profile
8.3.4.4 Full Duty-Cycle Switch
The TPS92830-Q1 device can flexibly switch between the internal PWM modulation mode and the 100% dutycycle mode by using the FD input. Once V(FD) is higher than threshold VIH(FD), the internal PWM generator is
bypassed and output is merely controlled by the PWM inputs.
If FD is HIGH, the PWMCHG current source is turned off and V(PWMCHG) decays to GND through the external
resistor-capacitor circuit. When FD falls below the threshold, V(PWMCHG) increases from GND due to the internal
charge current.
If FD is HIGH, PWM generator oscillation stops, and PWMOUT is controlled by PWM1 only.
External PWM inputs and internal PWM inputs are combined together for channel PWM dimming, or external
PWM inputs can be used as channel enable inputs.
PWMx
PWMx
Channelx
PWM
FD
FD
PWMCHG
PWM
Generator
PWMOUT
PWM1
Copyright © 2017, Texas Instruments Incorporated
Figure 25. PWM Dimming Internal Block Diagram
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Feature Description (continued)
Table 1. Truth Table When Driving With PWM
PWMx
FD
PWMCHG
CHANNELx PWM
LOW
X
X
LOW
HIGH
HIGH
X
HIGH
HIGH
LOW
R-C
PWM generated with RC
Table 2. Truth Table When Driving With PWMOUT
PWM1
FD
PWMCHG
PWMOUT
LOW
X
X
LOW
HIGH
HIGH
X
HIGH
HIGH
LOW
R-C
PWM generated with RC
8.3.5 Analog Dimming
The TPS92830-Q1 device has a linear analog input pin, ICTRL, for output-current dimming. Voltage across the
sense resistors is linearly reduced if the ICTRL input voltage V(ICTRL) decreases. Analog dimming can be used for
brightness control, LED bin brightness correction, and thermal protection with a thermistor. ICTRL also supports
off-board connection for LED binning and thermistor connection.
8.3.5.1 Analog Dimming Topology
Voltage at the ICTRL pin, V(ICTRL), is used for analog dimming control. To set V(ICTRL), either a reference input
voltage can be applied or a resistor between ICTRL and GND can be used.
When V(ICTRL) is greater than V(ICTRL_FULL), analog dimming is not enabled; thus the analog dimming ratio is at
100%.
When V(ICTRL) is between V(ICTRL_LIN_BOT) and V(ICTRL_LIN_TOP), the analog dimming ratio is directly proportional to
V(ICTRL). The analog dimming ratio can be calculated using the following equation. V(ICTRL_LIN_BOT) and
V(ICTRL_LIN_TOP) represent the ICTRL voltage boundaries of the linear region.
V ICTRL
k ICTRL _ DIM
u 100%
1.475 V
(7)
When VICTRL is between V(ICTRL_LIN_TOP) and V(ICTRL_FULL) or between V(ICTRL_LIN_BOT) and 0, analog dimming is in
a transition region, and linearity is not assured. Thus it is not recommended to use ICTRL in these regions.
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k(DERATE_Dim)
100%
Linear Region
Full Range Region
0%
0.075V
1.25V
1.475V
V(ICTRL_FULL)
V(ICTRL_MAX)
V(ICTRL)
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Analog Dimming Ratio
8.3.5.2 Internal High-Precision Pullup Current Source
An internal precision pullup current I(ICTRL_pullup) is provided within the device to minimize external component
count. I(ICTRL_pullup) uses current reference I(IREF) as reference. With the internal pullup current source, only an
external resistor between the ICTRL pin and GND is needed to set the ICTRL voltage and the analog dimming
ratio.
If a voltage source or resistor divider is used, the internal pullup current must be taken into account to set the
analog dimming ratio accurately.
The pullup current source pulls the ICTRL pin voltage up to input voltage V(IN) if the ICTRL pin is unconnected.
When ICTRL is not used, it is recommended to leave the ICTRL pin floating.
I(ICTRL_pullup)
Analog
Dimming
ICTRL
TPS92830-Q1
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Internal High-Precision Pullup Current Source
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8.3.6 Output Current Derating
The TPS92830-Q1 device has an integrated output-current derating function. Voltage across the sensing
resistors is reduced if DERATE input voltage VDERATE increases. The output current derating function can be
used for supply overvoltage protection and thermal protection with a thermistor. The DERATE current curves are
divided into 32 steps between 100% and 50% with hysteresis.
In the case where DERATE is used for battery voltage sensing, the resistor-divider ratio can be set in a typical
application as follows.
• In the normal supply-voltage range, for example, (9 V–16 V), the output-current-derating function is disabled.
• In the overvoltage range, for example, (18 V–24 V), the output current starts to derate and reaches 50%
when VIN is at 24 V.
• When the voltage is even higher, for example, (24 V–26 V), the output current is saturated at 50%.
8.3.6.1 Output-Current Derating Topology
Voltage at the DERATE pin, V(DERATE), is used for output-current-derating control. To set the V(DERATE) voltage, a
resistor divider on supply voltage VIN is typically used for supply overvoltage protection.
• When VDERATE is lower than V(DERATE_FULL), output current derating is not enabled; thus, output-current
derating ratio k(DERATE_Dim) is at 100%.
• When VDERATE is higher than V(DERATE_HALF), output current derating is limited to 50%; thus, output-current
derating ratio k(DERATE_Dim) is at 50%.
• When V(DERATE) is between V(DERATE_FULL) and V(DERATE_HALF), the output-current-derating ratio is negatively
proportional to V(DERATE) with 32 steps. Current derating is rounded to the next-lower step. The output-currentderating ratio can be calculated using the following equations.
V DERATE _ HALF V DERATE _ FULL
V DERATE _ STEP
32
(8)
k
DERATE _ Dim
§ V DERATE V DERATE _ FULL
100% ¨
¨
V DERATE _ STEP
©
· 50%
¸u
¸ 32
¹
(9)
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Output Current Derating Ratio
100%
32 steps
50%
0%
V(DERATE_FULL)
V(DERATE_HALF)
V(DERATE)
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Output-Current Derating Profile
8.3.7 Diagnostics and Fault
The TPS92830-Q1 device provides advanced diagnostics and fault protection methods for automotive exterior
lighting systems. The device is able to detect and protect from LED output short-to-GND as well as from LED
output open-circuit scenarios. The device also supports a one-fails–all-fail fault bus that could flexibly fit different
legislative requirements.
24
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SUPPLY
TPS92830-Q1
ISP
Rsnsx
ISNx
MNx
Gx
SENSEx
FAULT
GND
Copyright © 2017, Texas Instruments Incorporated
SUPPLY
TPS92830-Q1
ISP
RSNSx
ISNx
MNx
Gx
SENSEx
FAULT
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 29. LED Open and Short Scenarios
8.3.7.1 LED Short-to-GND Detection
The TPS92830-Q1 device has channel-independent LED short-to-GND detection. Short-to-GND detection is only
enabled during channel on-time. Once an LED short-to-GND failure is detected, the device turns off the faulty
channel and retries automatically. If the auto-retry mechanism detects that the LED short-to-GND fault has been
removed, the device resumes normal operation. section
The device monitors voltage V(SENSEx) and compares it with the internal reference voltage to detect short-to-GND
failures. If the period during which V(SENSEx) falls below V(SG_th_rising) is longer than the deglitch time of t(SG_deg), the
device asserts a short-to-GND fault on this channel. During the deglitch time period, if VSENSEx rises above
V(SG_th_falling), the timer is reset.
If a fault is detected, a constant-current source pulls the fault bus down. If FAULT is low, all devices connected to
the fault bus are off in the fault mode.
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8.3.7.2 LED Short-to-GND Auto Retry
Once the channel has asserted a short-to-GND fault, it automatically retries periodically. In PWM mode, the
device sources I(Retry_short) through the SENSEx pin to pull up the LED loads with a pulse duration of t(SG_retry_ON).
The device waits for t(SG_retry_OFF) until the next retry pulse. Once auto retry detects that the short-to-GND fault is
removed, the device resumes normal operation. During auto retry mode, the device ignores PWM inputs.
8.3.7.3 LED Open-Circuit Detection
The TPS92830-Q1 device has channel-independent LED open-circuit detection. Once an LED open-circuit failure
is detected, the device turns off the faulty channel and retries automatically. If the retry mechanism detects that
the LED open-circuit fault is removed, the device resumes normal operation.
The device monitors MOSFET dropout voltage differences between the ISNx and SENSEx pins. Voltage
difference V(ISNx) – V(SENSEx) is compared with internal reference voltage V(OPEN_th_rising) to detect an LED opencircuit failure. If V(ISNx) – V(SENSEx) falls below the V(OPEN_th_rising) voltage and it stays there longer than the deglitch
time of t(OPEN_deg), the device asserts an open-load fault on this channel. During the deglitching time period, if
V(ISNx) – V(SENSEx) rises above V(OPEN_th_falling), the deglitch timer is reset.
In normal operation, the N-channel MOSFET operates in the saturation region with a gate-source voltage close
to its threshold voltage. In this case, the drain-source voltage of the N-channel MOSFET is typically much higher
than open-circuit threshold V(OPEN_th_rising). In the LED open-circuit condition, the N-channel MOSFET operates in
the linear region with a gate-source voltage much higher than its threshold voltage. The N-channel MOSFET is
fully on.
If a fault is detected, a constant-current source pulls the fault bus down. If the FAULT pin is low, all devices
connected to the fault bus are off in the fault mode.
8.3.7.4 LED Open-Circuit Auto Retry
Once the channel has asserted an open-circuit fault, it automatically retries periodically. The device sources
I(Retry_open) through the SENSEx pin to pull up the LED loads with a pulse duration of t(OPEN_retry_ON). In PWM
mode, the device waits for t(OPEN_retry_OFF) until the next retry pulse. Once auto retry detects that the open-circuit
fault has been removed, the device resumes normal operation. During auto retry mode, the device ignores PWM
inputs. In the open-circuit scenario, the retry current cannot find a path to ground; thus, total current consumption
does not increase.
8.3.7.5 Dropout-Mode Diagnostics
When the input voltage is not high enough to keep the external N-channel MOSFET in the constant-current
saturation region, the TPS92830-Q1 device tries to regulate current by driving the external N-channel MOSFET
in the linear region. This state is called the dropout mode, because voltage across the sense resistor is not able
to reach the regulation threshold.
In dropout mode, LED open-circuit detection must be disabled via the DIAGEN input. Otherwise, the dropout
mode would be treated as an LED open-circuit fault. The DIAGEN pin is used to avoid false diagnostics on an
output channel due to low supply voltage.
When the DIAGEN voltage is low, the LED open-circuit detection is ignored. When the DIAGEN voltage is high,
LED open-circuit detection resumes normal operation.
In dropout mode, the MOSFET is driven at maximum gate-source voltage to regulate current to the desired
value. When the supply voltage increases, the MOSFET gate voltage is pulled down internally by a control loop.
If the supply-voltage slew rate is fast, a high-current pulse can be observed on the LED for a short period of time.
At the same time, the current-sense voltage may exceed the normal operating range and damage internal
circuitry. A parallel diode or a current-limiting resistor less than 1 kΩ is recommended to clamp the voltage
across the sensing resistor in the case of a large pulse current.
26
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SUPPLY
TPS92830-Q1
ISP
RSNSx
ISNx
Gx
SENSEx
FAULT
GND
Copyright ©2017, Texas Instruments Incorporated
Figure 30. Resistor and Diode for Sense-Resistor Protection
8.3.7.6 Overtemperature Protection
The TPS92830-Q1 device monitors device junction temperature. When the junction temperature reaches the
thermal shutdown threshold T(TSD), all outputs shut down and the charge pump also stops working. Once the
junction temperature falls below T(TSD) – T(TSD_HYS), the device resumes normal operation. During
overtemperature protection, the FAULT bus is pulled low.
8.3.7.7 FAULT Bus Output With One-Fails–All-Fail
The TPS92830-Q1 device has a FAULT bus for diagnostics output. It also supports a one-fails–all-fail function
with other TPS92830-Q1, TPS9261x-Q1, TPS92630-Q1, or TPS92638-Q1 devices.
In normal operation, FAULT is weakly pulled up by internal pullup current source I(FAULT_pullup) to a voltage higher
than VOH(FAULT). If any fault scenario occurs, the FAULT bus is strongly pulled low by internal pulldown current
source I(FAULT_pulldown). Once V(FAULT) falls below VIL(FAULT) , all outputs are shut down for protection. The faulty
channel keeps retrying until the fault condition is removed. The charge pump is shut down, and current
consumption is also reduced to I(FAULT) to save quiescent current.
If FAULT̅ is externally pulled up with a current higher than I(FAULT_pulldown), the one-fails–all-fail function is disabled
and only the faulty channel is turned off. The charge pump remains operating normally, and the device is in
normal operation mode. The FAULT bus is able to support up to 15 pieces of TPS92830-Q1, TPS92630-Q1,
TPS92638-Q1, or TPS9261x-Q1 devices.
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8.3.7.8 Fault Table
Table 3. Fault Table With DIAGEN = HIGH
FAULT TYPE
DETECTION
MECHANISM
CHANNEL
STATE
DEGLITCH TIME
FAULT BUS
FAULT
HANDLING
ROUTINE
FAULT
RECOVERY
FAULT FLOATING
LED open-circuit
VISNx – VSENSEx <
V(OPEN_th_rising)
On
t(OPEN_deg)
LED short-toGND
VSENSEx < V(SG_th_rising)
On
t(SG_deg)
LED short-tobattery
VISNx – VSENSEx <
V(OPEN_th_rising)
On or off
Overtemperature
TJ > T(TSD)
On or off
All channels
turned off. Pulsed
pullup retry of
faulty channel.
Constant-current
pulldown
t(OPEN_deg)
All channels
turned off. Pulsed
pullup retry of
faulty channel.
Auto recover
All channels
turned off. Faulty
channel pulsed
pullup retry of
faulty channel.
All channels
turned off.
FAULT EXTERNALLY PULLED UP
LED open-circuit
LED short-toGND
VISNx – V SENSEx <
V(OPEN_th_rising)
V SENSEx < V(SG_th_rising)
On
On
LED short-tobattery
V ISNx – V(SENSEx) <
V(OPEN_th_rising)
On or off
Overtemperature
TJ > T(TSD)
On or off
t(OPEN_deg)
Only faulty
channel turned
off. Pulsed pullup
retry of faulty
channel.
t(SG_deg)
Only faulty
channel turned
off. Pulsed pullup
retry of faulty
channel.
Externally pulled
up with internal
constant-current
pulldown
t(OPEN_deg)
Auto recover
Only faulty
channel turned
off. Pulsed pullup
retry of faulty
channel.
All channels
turned off.
FAULT EXTERNALLY PULLED DOWN
All outputs disabled
28
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Table 4. Fault Table With DIAGEN = LOW
FAULT TYPE
DETECTION
MECHANISM
CHANNEL
STATE
DEGLITCH TIME
FAULT BUS
Ignored
Ignored
Ignored
Ignored
FAULT
HANDLING
ROUTINE
FAULT
RECOVERY
Ignored
Ignored
FAULT FLOATING
LED open-circuit
LED short-toGND
V(SENSEx) < V(SG_th_rising)
On
t(SG_deg)
LED short-tobattery
Ignored
Ignored
Ignored
Overtemperature
TJ > T(TSD)
On or off
Constant current
pull down
Ignored
Constant current
pull down
All channels
turned off. Pulsed
Auto recover
pullup retry of
faulty channel.
Ignored
All channels
turned off.
Ignored
Auto recover
FAULT EXTERNALLY PULLED UP
LED open-circuit
Ignored
Ignored
Ignored
LED short-toGND
V(SENSEx) < V(SG_th_rising)
On
t(SG_deg)
LED short-tobattery
Ignored
Ignored
Ignored
Overtemperature
TJ > T(TSD)
On or off
Ignored
Externally pulled
up with internal
constant current
pulled down
Ignored
Externally pulled
up with internal
constant current
pulled down
Ignored
Ignored
Only faulty
channel turned
off. Pulsed pullup
retry of faulty
channel.
Auto recover
Ignored
Ignored
All channels
turned off.
Auto recover
FAULT EXTERNALLY PULLED LOW
All outputs
disabled
All outputs disabled
All outputs
disabled
All outputs
disabled
All outputs
disabled
All outputs
disabled
All outputs
disabled
8.4 Device Functional Modes
8.4.1 Undervoltage Lockout, V(IN) < V(UVLO)
When the device is in undervoltage lockout mode, the TPS92830-Q1 device disables all functions until the supply
rises above the UVLO-rising threshold. The device pulls down the Gx outputs. Other outputs are in the highimpedance state.
8.4.2 Normal Operation (V(IN) ≥ 4.5 V, V(IN) > V(LED) + 0.5 V)
The device drives an LED string in normal operation. A 0.5-V minimal dropout voltage is typically more than
enough to maintain LED current regulation.
8.4.3 Low-Voltage Dropout
When the device drives an LED string in low-dropout mode, even with the MOSFETs fully turned on the output
current may not reach target value. The device reports an LED open-circuit failure if DIAGEN is HIGH.
8.4.4 Fault Mode (Fault Is Detected)
When the device detects an open or shorted LED, the device tries to pull down the FAULT pin with a constant
current. If the fault bus is pulled down, the device switches to fault mode and consumes a fault current of I(FAULT).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In automotive applications, linear LED drivers are preferable for various applications, especially exterior lighting,
for their simplicity and electromagnetic compatibility. This section provides a few examples to show the design
process for different features.
9.2 Typical Applications
9.2.1 Typical Application for Automotive Exterior Lighting With One-Fails–All-Fail
Various functions of exterior lighting may use the following circuit. Here is a typical application circuit for a turn
indicator. A TPS92830-Q1 drives a total of nine LEDs with 3s3p configuration at 300 mA each.
Figure 31. TPS92830-Q1 Typical Application Circuit For Automotive Exterior Lighting
9.2.1.1 Design Requirements
With the wide range of battery voltages in modern automotive systems, it is a common requirement among car
OEMs to turn LEDs off when the battery voltage is below the minimal voltage threshold, for example, 6 V.
When the battery voltage is between 6 V and 9 V, LEDs may not achieve full brightness due to low input voltage.
Although a linear LED driver may drive in low-dropout mode, it is required not to treat the low-dropout mode as
an open-circuit fault and to report a false error.
30
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Typical Applications (continued)
When battery voltage ranges between 9 V and 16 V, the LED driver works in normal mode with the one-fails–allfail feature. If any LED strings fail with an open circuit or short circuit, the TPS92830-Q1 device pulls down the
fault bus. All devices connected to the same fault bus turn off their outputs.
When the battery voltage is above 18 V, the TPS92830-Q1 device is able to detect the overvoltage and derate
the output current to reduce the power dissipation of the MOSFETs and prevent thermal damage.
9.2.1.2 Detailed Design Procedure
Fixed Parameters
• Charge pump flying capacitor C6 = 10 nF
• Charge pump flying capacitor C8 = 10 nF
• R(IREF) = 8 kΩ
• Charge pump storage capacitor C10 = 150 nF
Current Setting
• I(LED) = 300 mA
• R(SNS)= V(CS_REG) / I(LED) = 0.983 Ω
PWM Threshold Setting
• PWM enables when V(IN) > 6 V
• K(RES_PWM) = VIH(PWMx, max) / 6 V
• K(RES_PWM) = R15 / (R15 + R8)
• Set R15 = 20 kΩ, R8 = 76 kΩ
DiagEN Setting (Enables LED-Open Detection When V(IN) > 9 V
• K(RES_DiagEN) = VIH(DIAGEN, max) / 9 V
• K(RES_DiagEn) = R13 / (R6 + R13)
• Set R13 = 10 kΩ, R6 = 62 kΩDiagEN setting
DERATE Setting (Reduces Current Output When V(IN) > 18 V
• K(RES_DERATE) = V(DERATE_FULL, min) / 18 V
• K(RES_DERATE) = R7 / (R7+ R14)
• Set R7 = 10 kΩ, R14 = 95 kΩ
To deliver 300 mA with a single MOSFET package, the designer must consider the maximum thermal-dissipation
condition. The power dissipation of a MOSFET is usually at its peak when input voltage is at 16 V in a fullbrightness condition. Assume the minimal LED forward voltage at 300 mA is 6 V.
P MOSFET
I LED u V IN
VF Diode
VF LED,min
V CS _ REG
300mA u (16 0.7 6 0.295)
2.702W
(10)
MOSFET package and layout design must be considered to dissipate 2.702 W at maximum ambient
temperature, usually 85°C.
The TPS92830 device can support a variety of N-channel MOSFETs in the markets. Adding a capacitor between
the gate and source increases the loop phase margin. The recommended total capacitance at Gx is greater than
4 nF.
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Typical Applications (continued)
9.2.1.3 Application Curves
Ch. 1 = V(IN)
Ch. 4 = I(OUT2)
Ch .2 = V(FAULT)
IN HIGH = 14 V, LOW = 0 V, with reverse
blocking diode
Ch. 3 = V(SENSE2)
Pulse duration = 300 µs, period = 2 ms
Figure 32. BCM PWM Dimming Curve
9.2.2 High-Precision Dual-Brightness PWM Generation
9.2.2.1 Dual-Brightness Application
Automotive lighting often reuses the same LEDs for different functions with different brightness, for example,
daytime running lights (DRL) and position lights, or stop and tail lights. Analog dimming by changing the constant
current may affect LED color temperature. PWM dimming could easily achieve the dimming ratio with the same
color temperature.
The TPS92830-Q1 device provides a precision PWM generator with a synchronization PWMOUT output. Its
integrated high-precision PWM generator ensures homogeneity across different devices.
32
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Typical Applications (continued)
SUPPLY
TPS92830-Q1
TPS92830-Q1
IN
IN
ISP
CPOUT
ISP
CPOUT
RSNS1
ISN1
CP2P
CP2N
CP2P
CP2N
MN1
CP1P
G1
PWM
RPWM
MN1
CP1P
G1
CP1N
FD
RSNS1
ISN1
CP1N
SENSE1
SENSE1
FD
FD
PWM1
PWMOUT
PWMx
IREF
IREF
PWMCHG
PWMCHG
FAULT
FAULT
CPWM
Copyright © 2017, Texas Instruments Incorporated
Figure 33. PWM Generator Master-Slave Configuration
9.2.2.2 Design Requirements
When full duty-cycle (FD) is HIGH, the output is at 100% duty cycle.
When full duty-cycle (FD) is LOW, the output is at 10% duty cycle and 250 Hz.
9.2.2.3 Detailed Design Procedure
PWM Equations
• RPU = 10 kΩ
• CPWM = 105.5 nF
• RPWM = 55.5 kΩ
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Typical Applications (continued)
9.2.2.4 Application Curve
Ch. 1 = V(PWMCHG)
Ch. 4 = I(OUT2_1)
Ch. 2 = V(PWMOUT)
Ch. 3 = I(OUT1_1)
Ch. 1 = V(PWMCHG)
Ch. 4 = I(OUT2_1)
Figure 34. Dual Brightness With Integrated High-Precision
PWM Generator at Full Duty-cycle
Ch. 2 = V(PWMOUT)
Ch. 3 = I(OUT1_1)
Figure 35. Dual Brightness With Integrated High-Precision
PWM Generator at 10% Duty-cycle
9.2.3 Driving High-Current LEDs With Parallel MOSFETs
Thermal performance is one key consideration in automotive exterior driving, especially for a linear LED driver.
Due to large variations of automotive battery voltage, a linear LED driver must accommodate thermal dissipation
with a worst-case scenario, which is high ambient temperature and high battery voltage.
LED driver thermal dissipation performance merely depends on the package and PCB thermal dissipation area.
However, if the thermal dissipation performance of a single MOSFET is not able to support the required LED
string current, multiple MOSFETs in parallel are able to dissipate heat for high-current applications.
When a MOSFET is in the saturation region as a current-control device, its current output strongly depends on its
threshold. MOSFET threshold Vth can vary from one device to another. When MOSFETs are in parallel, even a
small threshold mismatch could lead to imbalance of current distribution.
With an integrated charge pump, the TPS92830-Q1 device provides sufficient headroom even when the supply
voltage is as low as 5 V. Thus adding ballast resistors between the N-channel MOSFET source and the LED
string introduces negative feedback for each parallel MOSFET path to balance the current flows.
Table 5. Thermal Measurement of Parallel MOSFETs
34
WITHOUT CURRENT BALLAST
Resistor
WITH 1-Ω BALLAST RESISTOR
WITH 3-Ω BALLAST RESISTOR
MOSFET1
Temperature (ºC)
105.7
85.3
85.9
MOSFET2
Temperature (ºC)
76.1
82.8
84.2
MOSFET3
Temperature (ºC)
84.8
87.6
85.3
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V(IN)= 16 V, I(Total) = 964 mA, TA= 25 ºC.
SUPPLY
TPS92830-Q1
IN
ISP
RSNSx
ISNx
MN1
MN2
MN3
Gx
FAULT
SENSEx
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Parallel MOSFET Driving
9.2.3.1
Application Curves
Without Ballast Resistors
With 1-W Ballast Resistors
With 3-W Ballast Resistors
Figure 37. Thermal Images of Parallel MOSFETs With Various Ballast Resistors
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10 Layout
10.1 Layout Guidelines
The TPS92830-Q1 device relies on external MOSFETs to dissipate heat for high-current applications. To
effectively dissipate heat on MOSFETs and LEDs, TI recommends to use 0.071-mm-thick (2-oz.) copper PCBs
or metal-based boards. Make the thermal dissipation area with copper as large as possible. Place thermal vias
on the thermal dissipation area to further improve the thermal dissipation capability. The current path starts from
IN through the sense-resistors, MOSFETs, and LEDs to GND. Wide traces are helpful to reduce parasitic
resistance along the current path as shown in the layout example below.
Place capacitors, especially charge pump capacitors, close to the device to make the current path as short as
possible. TI suggests keeping the LED high-current ground path separate from device ground. TI also
recommends kelvin-connection to the connector. The following layout example shows the recommended
guidelines.
10.2 Layout Example
IN
TPS92830-Q1
1
CP1P
ISP
28
2
CP1N
ISN1
27
3
GND
G1
26
4
CP2N
SENSE1
25
5
CP2P
ISN2
24
6
CPOUT
G2
23
7
IN
SENSE2
22
ISN3
21
GND
DIAGEN
8
DIAGEN
9
DERATE
DERATE
G3
20
PWM1
SENSE3
19
PWM1
10
11
PWM2
PWM3
FD
PWM2
PWMOUT
18
12
PWM3
FAULT
17
13
FD
PWMCHG
16
14
ICTRL
IREF
15
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Figure 38. TPS92830-Q1 Example Layout Diagram
36
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Product Folder Links: TPS92830-Q1
TPS92830-Q1
www.ti.com
SLIS178B – OCTOBER 2017 – REVISED JANUARY 2018
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TPS92830-Q1
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS92830QPWRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
28
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TPS92830
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS92830QPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
28
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS92830QPWRQ1
TSSOP
PW
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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