Texas Instruments | CSD95490Q5MC Synchronous Buck NexFET Smart Power Stage (Rev. A) | Datasheet | Texas Instruments CSD95490Q5MC Synchronous Buck NexFET Smart Power Stage (Rev. A) Datasheet

Texas Instruments CSD95490Q5MC Synchronous Buck NexFET Smart Power Stage (Rev. A) Datasheet
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CSD95490Q5MC
SLPS669A – MARCH 2017 – REVISED JANUARY 2018
CSD95490Q5MC Synchronous Buck NexFET™ Smart Power Stage
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
75-A Continuous Operating Current Capability
Over 95% System Efficiency at 30 A
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Function
Temperature Compensated Bi-Directional Current
Sense
Analog Temperature Output
Fault Monitoring
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Switch
Optimized Dead Time for Shoot-Through
Protection
High-Density QFN 5-mm × 6-mm Footprint
Ultra-Low-Inductance Package
System Optimized PCB Footprint
Thermally Enhanced Topside Cooling
RoHS Compliant – Lead-Free Terminal Plating
Halogen Free
Multiphase Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
POL DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR12.x / VR13.x V-Core
Synchronous Buck Converters
High-Current POL for Network Communications
•
•
•
•
3 Description
The CSD95490Q5MC NexFET™ power stage is a
highly optimized design for use in a high-power, highdensity synchronous buck converter. This product
integrates the driver IC and power MOSFETs to
complete the power stage switching function. This
combination produces high-current, high-efficiency,
and high-speed switching capability in a small 5-mm
× 6-mm outline package. It also integrates the
accurate current sensing and temperature sensing
functionality to simplify system design and improve
accuracy. In addition, the PCB footprint has been
optimized to help reduce design time and simplify the
completion of the overall system design.
Device Information(1)
Application Diagram
P12V
AVSP
AVSN
TPS53679
BOOT
VIN
ASKIP#
P5V
EN/FCCM
VOS
QTY
PACKAGE
SHIP
2500
CSD95490Q5MCT
7-Inch Reel
250
QFN
5.00-mm × 6.00-mm
Package
Tape
and
Reel
VSW
VDD
TAO
LSET
MEDIA
13-Inch Reel
BOOT_R
CSD95490Q5MC
PWM
PWM1
DEVICE
CSD95490Q5MC
PGND
LOAD
IOUT REFIN
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ACSP1
Typical Power Stage Efficiency and Power Loss
TSEN
P12V
BOOT
VIN
P5V
VREF
EN/FCCM
21
90
18
VOS
VSW
VDD
ADDR
100
BOOT_R
CSD95490Q5MC
PWM
APWM6
TAO
PGND
IOUT REFIN
80
3.3V
Efficiency (%)
V3P3
ACSP6
VREF
P12V
VIN_CSNIN
CSPIN
VCCIO
BEN_VCCIO
SCLK
SDIO
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VR_FAULT#
RESET#
BVSN
BVSP
P12V
BOOT
VIN
PWM
BPWM1
BSKIP#
P5V
60
12
9
6
VOS
VSW
VDD
PVDD
LSET
70
50
BOOT_R
CSD95492QVM
EN/FCCM
15
VDD = 5 V
VIN = 12 V
VOUT = 1.8 V
LOUT = 150 nH
fSW = 600 kHz
TA = 25qC
Power Loss (W)
LSET
TAO
PGND
LOAD
40
3
IOUT REFIN
30
0
BCSP1
AGND
15
30
45
Output Current (A)
60
0
75
D000
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD95490Q5MC
SLPS669A – MARCH 2017 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
7
Application Schematic .......................................... 5
8
Device and Documentation Support.................... 6
8.1
8.2
8.3
8.4
8.5
9
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
6
6
6
6
6
Mechanical, Packaging, and Orderable
Information ............................................................. 7
9.1 Mechanical Drawing.................................................. 7
9.2 Recommended PCB Land Pattern............................ 8
9.3 Recommended Stencil Opening ............................... 9
4 Revision History
Changes from Original (March 2017) to Revision A
•
2
Page
Updated Mechanical Drawing section .................................................................................................................................... 7
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SLPS669A – MARCH 2017 – REVISED JANUARY 2018
5 Pin Configuration and Functions
Top View
REFIN
1
12
TAO/FLT
IOUT
2
11
EN/FCCM
LSET
3
10
PWM
VDD
4
9
BOOT
VOS
5
8
BOOTR
7
VIN
PGND
13
SW
6
Pin Functions
PIN
DESCRIPTION
NAME
NO.
REFIN
1
External reference voltage input for current sensing amplifier.
IOUT
2
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
LSET
3
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.
VDD
4
Supply voltage for gate drivers and internal circuitry.
VOS
5
Output voltage sensing pin for the internal current sensing circuitry.
SW
6
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
VIN
7
Input voltage pin. Connect input capacitors close to this pin.
BOOTR
8
Return path for HS gate driver. It is connected to VSW internally.
BOOT
9
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins.
The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
PWM
10
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for
greater than the tri-state shutdown hold-off time (t3HT).
11
This dual function pin either enables the diode emulation function or can be used as a simple enable for the
device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time,
Diode Emulation Mode (DEM) is enabled for sync FET. When the pin is high, device operates in Forced
Continuous Conduction Mode (FCCM). When the pin is low, both FETs are held off. An internal resistor pulls this
pin low if left floating.
TAO/FAULT
12
Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is
integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of
all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown,
LSOC, or HSS detection circuit is tripped.
PGND
13
Power ground.
EN/FCCM
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CSD95490Q5MC
SLPS669A – MARCH 2017 – REVISED JANUARY 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise stated) (1)
MIN
MAX
UNIT
VIN to PGND
–0.3
20
V
VIN to VSW
–0.3
20
V
23
V
–0.3
20
V
VIN to VSW (10 ns)
VSW to PGND
VSW to PGND (10 ns)
–7
23
V
VDD to PGND
–0.3
7
V
EN/FCCM, TAO/FLT, LSET to PGND (2)
–0.3
VDD + 0.3
V
IOUT, VOS, PWM to PGND
–0.3
7
V
REFIN
–0.3
3.6
V
BOOT to BOOTR (2)
–0.3
VDD + 0.3
V
BOOT to PGND
–0.3
30
V
TJ
Operating junction temperature
–55
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Should not exceed 7 V.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise stated)
PARAMETER
VDD
CONDITIONS
Driver supply voltage
(1)
VIN
Input supply voltage
VOUT
Output voltage
PWM
PWM to PGND
IOUT
Continuous output current
IOUT-PK
Peak output current (3)
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz (2)
ƒSW
Switching frequency
CBST = 0.1 µF (min), VOUT = 2.5 V (max)
On-time duty cycle
ƒSW = 1 MHz
4
5.5
V
UNIT
16
V
5.5
V
VDD + 0.3
V
75
A
105
A
1250
kHz
85%
20
Operating junction temperature
(2)
(3)
MAX
4.5
4.5
Minimum PWM on-time
(1)
MIN
–40
ns
125
°C
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.
System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.
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Product Folder Links: CSD95490Q5MC
CSD95490Q5MC
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SLPS669A – MARCH 2017 – REVISED JANUARY 2018
7 Application Schematic
P12V
AVSP
TPS53679
BOOT
VIN
AVSN
ASKIP#
EN/FCCM
P5V
BOOT_R
CSD95490Q5MC
PWM1
PWM
VOS
VSW
VDD
LOAD
TAO
LSET
PGND
IOUT REFIN
ACSP1
TSEN
P12V
BOOT
VIN
P5V
VREF
BOOT_R
CSD95490Q5MC
PWM
APWM6
EN/FCCM
VSW
VDD
ADDR
VOS
TAO
LSET
PGND
IOUT REFIN
3.3V
V3P3
ACSP6
VREF
P12V
VIN_CSNIN
CSPIN
BVSN
VCCIO
BEN_VCCIO
BVSP
P12V
SCLK
SDIO
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VR_FAULT#
RESET#
BOOT
VIN
PWM
BPWM1
BSKIP#
P5V
BOOT_R
CSD95492QVM
EN/FCCM
VOS
VSW
VDD
PVDD
LSET
TAO
PGND
LOAD
IOUT REFIN
BCSP1
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 1. Application Schematic
Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components
not shown.
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CSD95490Q5MC
SLPS669A – MARCH 2017 – REVISED JANUARY 2018
www.ti.com
8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
6
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CSD95490Q5MC
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SLPS669A – MARCH 2017 – REVISED JANUARY 2018
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
5.1
4.9
B
A
PIN 1 INDEX AREA
6.1
5.9
NOTE 4
TYP
C
1.0±0.05
SEATING PLANE
(0.51) TYP
0.08 C
(0.51)
3.3±0.1
(0.2) TYP
2X (2)
4X (0.25)
0.05
0
2X 0.6
0.4
2X (0.31)
6
7
EXPOSED
THERMAL
PAD
2X
5
13
5.4±0.1
NOTE 4
1
12
20[.0]X 0.5
PIN 1 ID
(OPTIONAL)
10X 0.6
0.4
22[.0]X 0.3
0.2
0.1
0.05
C A B
C
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Exposed tie bar features may vary.
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CSD95490Q5MC
SLPS669A – MARCH 2017 – REVISED JANUARY 2018
www.ti.com
9.2 Recommended PCB Land Pattern
(3.3)
10X (0.7)
SYMM
(R0.05) TYP
1
12
22X (0.25)
2X
(1.13)
20X (0.5)
8
5
13
SYMM
(5.4)
METAL UNDER
SOLDER MASK
2X
2X
(2.85)
SOLDER MASK
OPENING
2X
( 0.2) VIA
TYP
6X
(1.32)
7
6
(0.05) TYP
6X (1.4)
2X (0.7)
2X (0.31)
(4.7)
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
(PREFERRED FOR PADS 1 - 5 & 8 - 12)
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PADS 6 - 7, OPTIONAL FOR OTHER PADS)
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to
their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
8
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SLPS669A – MARCH 2017 – REVISED JANUARY 2018
9.3 Recommended Stencil Opening
METAL
TYP
10X (0.7)
SYMM
13
8X (1.41)
1
12
8X
(1.12)
22X (0.25)
20X (0.5)
8
5
SYMM
(0.66)
TYP
(R0.05) TYP
METAL UNDER
SOLDER MASK
2X
(1.32)
TYP
7
6
2X (0.31)
(0.8) TYP
2X (0.7)
(4.7)
SOLDER PASTE EXAMPLE
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD95490Q5MC
ACTIVE
VSON-CLIP
DMC
12
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95490MC
CSD95490Q5MCT
ACTIVE
VSON-CLIP
DMC
12
250
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95490MC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CSD95490Q5MC
VSONCLIP
DMC
12
2500
330.0
12.4
5.3
6.3
1.2
8.0
12.0
Q1
CSD95490Q5MCT
VSONCLIP
DMC
12
250
180.0
12.4
5.3
6.3
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD95490Q5MC
VSON-CLIP
DMC
12
2500
370.0
355.0
55.0
CSD95490Q5MCT
VSON-CLIP
DMC
12
250
195.0
200.0
45.0
Pack Materials-Page 2
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