Texas Instruments | TPS56x20 4.5V to 17V Input, 12A/9A/7A/5A Output, Synchronous Step-Down Voltage Regulator with Voltage Scaling (Rev. E) | Datasheet | Texas Instruments TPS56x20 4.5V to 17V Input, 12A/9A/7A/5A Output, Synchronous Step-Down Voltage Regulator with Voltage Scaling (Rev. E) Datasheet

Texas Instruments TPS56x20 4.5V to 17V Input, 12A/9A/7A/5A Output, Synchronous Step-Down Voltage Regulator with Voltage Scaling (Rev. E) Datasheet
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TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
TPS56x20 4.5V to 17V Input, 12A/9A/7A/5A Output, Synchronous Step-Down Voltage
Regulator with Voltage Scaling
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
D-CAP2™ Control
– Input Voltage Range: 4.5V to 17V
– Switching Frequency: 500kHz
– Optimized for a 1.0µH to 2.2µH Inductor
±1% Output Voltage Accuracy
Features via I2C Compatible Interface
– Output Voltage (VID): 0.6V to 1.87V in 10mV
– Auto-Skip Eco-mode™ ON/OFF (Light-load)
– Current Limit Target: 40% to 160%
– Enabling IC, Reading-back Power-good
– Hiccup Mode Protection ON/OFF
IC Terminal Features
– Start-up by Using External Resistors
Output Voltage with VFB Pin: 0.6V to 1.87V
– Adjustable Soft-start,
Monotonic Pre-Biased Start-up
– Power-good
– I2C Address Programming (2bits)
Cycle-by-Cycle Overcurrent Limiting Control
Thermal Shutdown (TSD)
Undervoltage Lockout (UVLO)
TSSOP Package (PWP) with PowerPAD™
Media Processors for Consumer Applications:
Digital TVs, Set Top Boxes (STB, DVD/Blu-ray
Player, Cable/Satellite Modem)
SoC Processors
High Density Power Distribution Systems
•
•
3 Description
The TPS56X20 is a synchronous DC-DC converter IC
(integrated circuit) with a voltage scaling control to
power up micro-processors (MCUs) requiring core
voltage (VCORE) tune-ups. After the initial power-up,
the output voltage can be programmed/scaled by VID
codes sent over an I2C compatible bus.
This step-down (buck) converter employs an adaptive
on-time D-CAP2 mode control which provides a very
fast transient response with no external components.
Unlike traditional voltage-/current-mode controls, the
D-CAP2 supports seamless transition between PWM
mode for higher load and Eco-mode™ for light load.
Eco-mode maintains high efficiency in light-load.
Device Information
PART NUMBER
PACKAGE
TPS56C20
BODY SIZE
HTSSOP (24)
7.80 mm × 4.40 mm
HTSSOP (20)
6.50 mm × 4.40 mm
TPS56920
TPS56720
TPS56520
Typical Application Circuit
3.3 V
U1
R2
1.0kΩ
R3
1.0kΩ
1
VIN
2
SDA
µProcessor
3
SCL
A1
4
A0
5
6
7
VIN
8
C1
10µF
C2
4.7µF
9
10
AGND
EN
PGND
PWRGD
VFB
SDA
VOUT
SCL
SS
A1
GND
A0
VREG5
VIN
PGOOD
PVIN
VBST
PVIN
SW
PGND
SW
20
19
18
PGND
R5
18.2kΩ
17
16
15
C4
2.2µF
14
C5
0.01µF
R6
22kΩ
13
11
21
PGND
R4
10.0k
TPS56520
TPS56720
TPS56920
PWRPAD
R1
1.0kΩ
C3
0.1µF
AGND
L1
VOUT
12
SW
1.5µH
C6
100µF
PGND
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information ................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
8.5 Programming........................................................... 18
8.6 Register Maps ......................................................... 20
9
Applications and Implementation ...................... 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2016) to Revision E
•
Page
Changed TJ MAX from 125°C to 150°C in Absolute Maximum Ratings ................................................................................ 6
Changes from Revision C (July 2014) to Revision D
Page
•
Deleted SWIFT™ From the datasheet title ........................................................................................................................... 1
•
Moved the Storage Temperature to the Absolute Maximum Ratings ................................................................................... 6
•
Changed Handling Ratings To: ESD Ratings ........................................................................................................................ 6
Changes from Revision B (March 2014) to Revision C
•
Page
Changed Figure 57 image for clarification. .......................................................................................................................... 33
Changes from Revision A (January 2014) to Revision B
Page
•
Changed to new data sheet format. ...................................................................................................................................... 1
•
Added Device Information table ............................................................................................................................................ 1
•
Added Table of Contents and moved Revision History to page 2. ....................................................................................... 2
•
Moved Abs Max Ratings, Handling Ratings, Recommended Operating Conditions, Thermal Info, and Elec
Characteristics tables to the "Specifications" section ............................................................................................................ 6
Changes from Original (November 2013) to Revision A
•
2
Page
Changed data sheet title to include "SWIFTTM Voltage Regulator..." .................................................................................... 1
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Copyright © 2013–2017, Texas Instruments Incorporated
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TPS56C20, TPS56920, TPS56720, TPS56520
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
5 Description (Continued)
The TPS56X20 supports both ultra-low ESR ceramic capacitors and low equivalent series resistance (ESR)
output capacitors, such as POSCAP or SP-CAP. The device is optimized for a small 1.0µH to 2.2µH inductor
saving PCB area.
The TPS56X20 devices are available in the HTSSOP package.
List of Devices
TPS56520
Output Current
HS/LS Rdson Numbers
Package
TPS56720
TPS56920
TPS56C20
5A
7A
9A
12A
44mΩ/32mΩ
30mΩ/24mΩ
26mΩ/19mΩ
13mΩ/9mΩ
PWP-20
PWP-20
PWP-20
PWP-24
Copyright © 2013–2017, Texas Instruments Incorporated
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3
TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
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6 Pin Configuration and Functions
TPS56520/720/920
20-Pin PWP Package with PowerPAD
(TOP VIEW)
1
EN
VFB
20
2
SDA
VOUT
19
3
SCL
SS
4
A1
18
GND
17
(PowerPAD)
VREG5
16
PGOOD
15
PVIN
VBST
14
8
PVIN
SW
13
9
PGND
SW
12
5
A0
6
VIN
7
10
HTSSOP-20
SW
PGND
11
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
EN
1
I
SDA
2
I/O
Data I/O terminal.
Clock I/O terminal.
SCL
A1, A0
VIN
Enable. Pull High to enable converter.
3
I/O
4,5
I
Chip address.
6
I
Supply Input for 5.5V linear regulator.
Power inputs and connects to high side MOSFET drains.
PVIN
7,8
I
PGND
9,10
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
11,12,13
I/O
Switch node connections for both the high-side NFETs and low-side NFETs. Input of current
comparator.
VBST
14
I
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBST and SW terminals. An internal diode is connected between VREG5 and VBST.
PGOOD
15
O
Open drain power good output. Low means the output voltage of the corresponding output is
out of regulation.
VREG5
16
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
least 2.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is
active when EN is H-level.
GND
17
I/O
Signal GND. Connect sensitive SS and VFB returns to GND at a single point.
SS
18
O
Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program
Soft-Start time.
VOUT
19
I
Connection to output voltage
VFB
20
I
D-CAP2 feedback input. Connect to output voltage with resistor divider.
Back side
I/O
SW
Exposed Thermal
Pad
4
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Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520
TPS56C20, TPS56920, TPS56720, TPS56520
www.ti.com
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
TPS56C20
24-Pin PWP Package with PowerPAD
(TOP VIEW)
1
EN
VFB
2
SDA
VOUT
23
SCL
SS
22
4
A1
GND
5
A0
6
VIN
3
TPS56C20
24
21
VREG5
20
PGOOD
19
VBST
18
17
HTSSOP 24
7
PVIN
(PowerPAD)
8
PVIN
SW
9
PGND
SW
16
10
PGND
SW
15
11
PGND
SW
14
12
PGND
SW
13
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
EN
1
I
SDA
2
I/O
Data I/O terminal.
SCL
3
I/O
Clock I/O terminal.
4,5
I
Chip address.
A1, A0
VIN
Enable. Pull High to enable according converter.
6
I
Supply Input for 5.5V linear regulator.
PVIN
7,8
I
Power inputs and connects to both high side NFET drains.
PGND
9,10,11,12
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
SW
13,14,15,
16, 17
I/O
Switch node connections for both the high-side NFETs and low-side NFETs. Input of current
comparator.
VBST
18
I
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBST and SW terminals. An internal diode is connected between VREG5 and VBST.
PGOOD
19
O
Open drain power good output. Low means the output voltage of the corresponding output is
out of regulation.
VREG5
20
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
3.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is active
when EN is H-level.
GND
21
I/O
Signal GND. Connect sensitive SS and VFB returns to GND at a single point.
SS
22
O
Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program SoftStart time.
VOUT
23
I
Connection to output voltage
VFB
24
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
Back side
I/O
Exposed Thermal
Pad
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
Copyright © 2013–2017, Texas Instruments Incorporated
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
Input voltage
Overvoltage
Sink Current
MIN
MAX
VIN,PVIN, EN
–0.3
20
VBST
–0.3
26
VBST (10ns transient)
–0.3
28
VFB, VOUT, SDA, SCL
–0.3
3.6
A0, A1
–0.3
6.5
VBST–SW
–0.3
6.5
SW
–2
20
SW (10ns transient)
–3
22
VREG5,SS,PGOOD
–0.3
6.5
PGND
–0.3
0.3
UNIT
V
V
PGOOD
–0.1
5
mA
TJ
Operating Junction temperature
–40
150
°C
TSTG
Storage temperature
–55
150
°C
(1)
(2)
These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those
indicated under Recommended Operating Conditions.
All voltages are with respect to IC GND terminal.
7.2 ESD Ratings
VALUE
Electrostatic
discharge (1)
(1)
(2)
(3)
Human Body Model (HBM) (2)
±2000
Charged Device Model (CDM) (3)
±500
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Operating input voltage
4.5
17
V
VOUT
Output voltage
0.6
1.87
V
TPS56520
0
5
TPS56720
0
7
TPS56920
0
9
IOUT
Output current
TJ
Operating junction temperature range
TPS56C20
6
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0
12
–40
125
A
°C
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
7.4 Thermal Information
THERMAL METRIC (1)
TPS56520/720/920
TPS56C20
PWP (20)
PWP (24)
θJA
Junction-to-ambient thermal resistance
36.8
32.8
θJCtop
Junction-to-case (top) thermal resistance
22.5
16
θJB
Junction-to-board thermal resistance
19.5
14.2
ψJT
Junction-to-top characterization parameter
0.6
0.4
ψJB
Junction-to-board characterization parameter
19.2
14
θJCbot
Junction-to-case (bottom) thermal resistance
1.4
0.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN=4.5V to 17V, PVIN=4.5V to 17V (Unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VIN
Operating input voltage
VIN, PVIN
17
V
IIN
VIN supply current
25°C, EN=5V, VFB=0.8V (non switching), VIN=12V
4.5
920
1150
µA
IVINSDN
VIN shutdown current
25°C, EN=0V, VIN=12V
140
200
µA
FEEDBACK VOLTAGE
VVFB
VFB voltage
25°C, external regulation mode, PVIN=12V,
VOUT=1.1V, IOUT=50mA, pulse skipping
0.594
0.6
0.606
V
25°C, external regulation mode, VOUT=1.1V,
continuous current mode
0.594
0.6
0.606
V
External regulation mode, VOUT=1.1V, continuous
current mode
0.591
0.6
0.609
V
–1%
0%
1%
–1.5%
0%
1.5%
–2%
0%
2%
5.2
5.5
5.7
VOUT VOLTAGE (INTERNAL VID CONTROL)
25°C, relative to target VOUT, PVIN=12V,
VOUT=0.6V~1.87V, LOUT=1.5µH
VVOUT
VOUT voltage
Relative to target VOUT, PVIN=12V, LOUT=1.5µH
Relative to target VOUT, LOUT=1.5µH
Target
VOUT
VREG5 OUTPUT
VVREG5
VREG5 Output Voltage
25°C , 6V< VIN <17V, IVREG5 = 5mA, VFB=1V
V
rDS(on)H
High side switch resistance TPS56520
VBST-SW=5.5V
44
mΩ
rDS(on)L
Low side switch resistance TPS56520
VIN=12V
32
mΩ
rDS(on)H
High side switch resistance TPS56720
VBST-SW=5.5V
30
mΩ
rDS(on)L
Low side switch resistance TPS56720
VIN=12V
24
mΩ
rDS(on)H
High side switch resistance TPS56920
VBST-SW=5.5V
26
mΩ
rDS(on)L
Low side switch resistance TPS56920
VIN=12V
19
mΩ
rDS(on)H
High side switch resistance TPS56C20
VBST-SW=5.5V
13
mΩ
rDS(on)L
Low side switch resistanceTPS56C20
VIN=12V
9
mΩ
MOSFET
POWER GOOD
VOUT or VFB falling (fault) VO=1.1V
VPGOODTH
PGOOD threshold
IPGOODDLY
PGOOD sink current
80%
VOUT or VFB rising (good) VO=1.1V
85%
VOUT or VFB rising (fault) VO=1.1V
115%
VOUT or VFB falling (good) VO=1.1V
110%
VPGOOD=0.5V
Copyright © 2013–2017, Texas Instruments Incorporated
3.15
5.2
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN=4.5V to 17V, PVIN=4.5V to 17V (Unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD
VENH
EN H-level threshold voltage
VENL
EN L-level threshold voltage
1.85
V
0.6
V
CURRENT LIMIT (1)
IOCL
IOCLR
Current Limit TPS56520
LOUT= 1.5µH
5.6
9
A
Current Limit TPS56720
LOUT= 1.5µH
7.8
12
A
Current Limit TPS56920
LOUT= 1.5µH
10
15
A
Current Limit TPS56C20
LOUT= 1.5µH
13.2
20
A
Reverse Current Limit TPS56520
LOUT= 1.5µH
1.25
5.3
A
Reverse Current Limit TPS56720
LOUT= 1.5µH
1.75
6.5
A
Reverse Current Limit TPS56920
LOUT= 1.5µH
2.25
6.2
A
Reverse Current Limit TPS56C20
LOUT= 1.5µH
3
8.2
A
OUTPUT UNDERVOLTAGE PROTECTION (UVP)
VOVP
Output OVP trip threshold
OVP detect (L>H)
125%
VOUT
VUVP
Output UVP trip threshold
UVP detect (H>L)
60%
VOUT
160
°C
23
°C
130
°C
THERMAL SHUTDOWN
Shutdown temperature (1)
TSDN
Thermal shutdown Threshold
Hysteresis (1)
Pre-thermal warning threshold
UVLO
UVLO
(1)
8
UVLO Threshold
Wake up to VREG5 voltage
3.45
3.9
4.2
V
Hysteresis VREG5 voltage
0.45
0.56
0.61
V
Ensured by design. Not production tested.
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
SOFT START
Issc
SS charge current
VSS=0.5V , 25 °C
–6.4
–6
IssD
SS discharge current
VSS=0.5V
0.14
0.2
SERIAL INTERFACE (1)
–5.6
µA
0.26
mA
0.6
V
(2) (3)
VIL
LOW level input voltage
VIH
HIGH level input voltage
Vhys
Hysteresis of Schmitt trigger inputs
VOL
LOW level output voltage (Open drain, 3mA
sink current)
tSP
Pulse width of spikes suppressed by input
filter
fscl
SCL clock frequency
tHD;STA
Hold time (repeated) START condition.
0.6
us
tLOW
LOW period of SCL clock
1.3
us
tHIGH
HIGH period of SCL clock
0.6
us
tSU;STA
Set-up time for a repeated START condition
0.6
us
tHD;DAT
Data Hold time
tSU;DAT
Data set-up time
tr
Rise time (SDA or SCL)
20+0.1Cb(4)
300
ns
tf
Fall time (SDA or SCL)
20+0.1Cb(4)
300
ns
tSU;STO
Set-up time for STOP condition
0.6
us
tBUF
Bus free time between STOP and START
condition
1.3
us
Cb
Capacitive load for each bus line
(1)
(2)
(3)
1.8
V
0.11
V
0.4
V
32
ns
400
50
kHz
900
ns
100
ns
400
pF
Ensured by design. Not production tested.
Refer to Figure 1 below for I2C Timing Definitions
Cb = capacitance of bus line in pF
VIH
VIL
Figure 1. I2C Timing Definitions (reproduced from Phillips I2C spec Version 1.1)
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
TON
TOFF
(1)
(1)
SW On Time
SW=12V, VOUT=1.1V
180
ns
SW Minimum off time
25°C, VFB= 0.5V
285
ns
Ensured by design. Not production tested.
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7.8 Typical Characteristics
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
1,100
60
VIN = 17 V
1,050
ICC - Supply Current (µA)
EN Input Current (µA)
50
40
30
20
10
1,000
950
900
850
0
800
±10
0
2
4
6
8
10
12
14
16
±50
18
EN Input Voltage (V)
Figure 2. TPS56X20 Enable Input Current
150
C001
Figure 3. TPS56520 Quiescent Current
Switching Frequency (kHz)
Ivccsdn - Shutdown Current (µA)
100
700
150
100
50
0
IOUT = 5 A
650
600
VOUT = 0.6V
VOUT = 1.8V
VOUT = 1.0V
550
500
450
400
±50
0
50
100
150
TJ Junction Temperature (ƒC)
4
6
8
10
12
14
16
VIN - Input Voltage (V)
C002
Figure 4. TPS56520 Shutdown Quiescent Current
18
C004
Figure 5. TPS56520 Switching Frequency
600
0.606
IO = 50 mA, VOUT = 1.1 V
VOUT = 1.0V
VOUT = 1.8V
VOUT = 0.6V
550
0.604
VFB Voltage (V)
fsw - Switching Frequency (kHz)
50
TJ Junction Temperature (ƒC)
200
500
0.602
0.600
0.598
450
0.596
400
0.594
0.0
1.0
2.0
3.0
4.0
IO - Output Current (A)
Figure 6. TPS56520 Switching Frequency,
Eco-mode™ = OFF
10
0
C003
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5.0
C005
±50
0
50
100
TJ Junction Temperature (ƒC)
150
C006
Figure 7. TPS56520 Feedback Voltage
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
1,000
8.00
VSS = 0.5 V
ICC - Supply Current (µA)
7.50
ISS Current (µA)
7.00
6.50
6.00
5.50
5.00
950
900
850
4.50
4.00
800
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
Figure 8. TPS56520 Soft Start Charging Current
100
150
C008
Figure 9. TPS56720 Quiescent Current
700
IOUT = 7 A
Switching Frequency (kHz)
Ivccsdn - Shutdown Current (µA)
50
TJ Junction Temperature (ƒC)
200
150
100
50
0
650
600
VOUT = 0.6V
VOUT = 1.0V
VOUT = 1.8V
550
500
450
400
±50
0
50
100
150
TJ Junction Temperature (ƒC)
4
6
8
10
12
14
16
VIN - Input Voltage (V)
C009
Figure 10. TPS56720 Shutdown Quiescent Current
18
C011
Figure 11. TPS56720 Switching Frequency
600
0.606
IO = 50 mA, VOUT = 1.1 V
VOUT = 1.0V
0.604
VOUT = 1.8V
VOUT = 0.6V
550
VFB Voltage (V)
fsw - Switching Frequency (kHz)
0
C006
500
0.602
0.600
0.598
450
0.596
400
0.594
0.0
1.0
2.0
3.0
4.0
5.0
6.0
IO - Output Current (A)
Figure 12. TPS56720 Switching Frequency,
Eco-mode™ = OFF
Copyright © 2013–2017, Texas Instruments Incorporated
7.0
C012
±50
0
50
100
TJ Junction Temperature (ƒC)
150
C013
Figure 13. TPS56720 Feedback Voltage
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
1,100
8.00
VSS = 0.5 V
7.50
ICC - Supply Current (µA)
1,050
ISS Current (µA)
7.00
6.50
6.00
5.50
5.00
1,000
950
900
850
4.50
4.00
800
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
Figure 14. TPS56720 Soft Start Charging Current
150
C015
Figure 15. TPS56920 Quiescent Current
Switching Frequency (kHz)
Ivccsdn - Shutdown Current (µA)
100
700
150
100
50
0
IOUT = 9 A
650
VOUT = 1.0V
VOUT = 0.6V
600
VOUT = 1.8V
550
500
450
400
±50
0
50
100
150
TJ Junction Temperature (ƒC)
4
6
8
10
12
14
16
VIN - Input Voltage (V)
C016
Figure 16. TPS56920 Shutdown Quiescent Current
18
C018
Figure 17. TPS56920 Switching Frequency
600
0.606
IO = 50 mA, VOUT = 1.1 V
VOUT = 1.0V
0.604
VOUT = 0.6V
550
VOUT = 1.8V
VFB Voltage (V)
fsw - Switching Frequency (kHz)
50
TJ Junction Temperature (ƒC)
200
500
0.602
0.600
0.598
450
0.596
400
0.594
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
IO - Output Current (A)
Figure 18. TPS56920 Switching Frequency,
Eco-mode™ = OFF
12
0
C014
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9.0
C019
±50
0
50
100
TJ Junction Temperature (ƒC)
150
C020
Figure 19. TPS56920 Feedback Voltage
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
1,100
8.00
VSS = 0.5 V
7.50
ICC - Supply Current (µA)
1,050
ISS Current (µA)
7.00
6.50
6.00
5.50
5.00
1,000
950
900
850
4.50
4.00
800
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
Figure 20. TPS56920 Soft Start Charging Current
100
150
C022
Figure 21. TPS56C20 Quiescent Current
700
IOUT = 12 A
Switching Frequency (kHz)
Ivccsdn - Shutdown Current (µA)
50
TJ Junction Temperature (ƒC)
200
150
100
50
0
650
VOUT = 1.0V
VOUT = 0.6V
600
VOUT = 1.8V
550
500
450
400
±50
0
50
100
150
TJ Junction Temperature (ƒC)
4
6
8
10
12
14
16
VIN - Input Voltage (V)
C023
Figure 22. TPS56C20 Shutdown Quiescent Current
18
C025
Figure 23. TPS56C20 Switching Frequency
600
0.606
VOUT = 1.0V
VOUT = 0.6V
550
IO = 50 mA, VOUT = 1.1 V
VOUT = 1.8V
0.604
VFB Voltage (V)
fsw - Switching Frequency (kHz)
0
C021
500
450
400
0.602
0.600
0.598
0.596
350
0.594
0.0
2.0
4.0
6.0
8.0
10.0
IO - Output Current (A)
Figure 24. TPS56C20 Switching Frequency,
Eco-mode™ = OFF
Copyright © 2013–2017, Texas Instruments Incorporated
12.0
C026
±50
0
50
100
TJ Junction Temperature (ƒC)
150
C027
Figure 25. TPS56C20 Feedback Voltage
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
8.00
VSS = 0.5 V
7.50
ISS Current (µA)
7.00
6.50
6.00
5.50
5.00
4.50
4.00
±50
0
50
100
150
TJ Junction Temperature (ƒC)
C028
Figure 26. TPS56C20 Soft Start Charging Current
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SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
8 Detailed Description
8.1 Overview
The TPS56X20 is a synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each
channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the
required output capacitance required to meet a specific level of performance. The output voltage of the
TPS56X20 can be set by either VFB with divider resistors (Adjusting the Output Voltage by External Regulation
Mode) or I2C compatible interface (Programming the Output Voltage by Internal Regulation Mode).
When only external regulation mode is used in a TPS56X20 application, the VOUT terminal should be tied to the
output voltage of the converter and SDA & SCL terminals should be grounded. A0 & A1 terminals may be
floating.
When only internal regulation mode is used in a TPS56X20 application, the VFB terminal should be connected to
the output voltage of the converter.
The integrated MOSFETs allow for high efficiency power supply designs. The MOSFETs have been sized to
optimize efficiency for lower duty cycle applications.
8.2 Functional Block Diagram
VIN
6
EN
1
VREG5
EN
Logic
16
VREG5
UVLO
EN
VREG5
+
OV
EN
+25%
-
7
PVIN
8
PVIN
14
VBST
VREG5
INT
VOUT
19
VFB
20
Control Logic
EXT
+ PWM
1 shot
SS
+
18
XCON
ON
0,6V
VREF
4
AO
5
10
PGND
9
PGND
EN
+
OCP
-
17
GND
15
PGOOD
PGND
SW
VALLEY CURRENT LIMIT
+15%
Chip ADDR
01101 A1A0
OV
UVLO
Protection
Logic
PWM
COMPARATOR
INPUT
-
A1
SW
-
3
Serial
Interface
SW
+
+
ZC
-
INT=
VID I2C
Output
Voltage
Selected
OCP
SCL
SW
11
EXT
7 bits
2
SW
INT
DAC
VOUT = 0.6V
to 1.87V
SDA
VREG5
13
12
TSD
+
-15%
Figure 27. TPS56520, TPS56720 and TPS56920 20 Terminal
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Functional Block Diagram (continued)
VIN
6
EN
1
VREG5
EN
Logic
20
VREG5
UVLO
EN
VREG5
+
OV
EN
+25%
-
7
PVIN
8
PVIN
18
VBST
17
SW
16
SW
15
SW
14
SW
13
SW
12
PGND
11
PGND
10
PGND
9
PGND
21
GND
19
PGOOD
VREG5
INT
VOUT
23
VFB
24
Control Logic
EXT
+ PWM
1 shot
SS
+
22
XCON
ON
0,6V
VREF
INT
EXT
OCP
2
SCL
3
A1
4
AO
5
Serial
Interface
EN
+
OCP
-
PGND
SW
VALLEY CURRENT LIMIT
+15%
Chip ADDR
01101 A1A0
OV
UVLO
Protection
Logic
PWM
COMPARATOR
INPUT
-
INT=
VID I2C
Output
Voltage
Selected
SW
-
7 bits
+
ZC
-
+
DAC
VOUT = 0.6V
to 1.87V
SDA
VREG5
TSD
+
-15%
Figure 28. TPS56C20 24 Terminal
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS56X20 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal
timer expires. This timer is set by the converter’s input voltage, VIN, and the output voltage, VOUT, to maintain a
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR
induced output ripple from D-CAP2™ mode control.
8.3.2 PWM Frequency and Adaptive On-Time Control
TPS56X20 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS56X20 runs with a pseudo-constant frequency of 500 kHz by using the input voltage and output voltage to
set the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output
voltage, therefore, when the duty ratio is VO/PVIN, the frequency is constant.
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Feature Description (continued)
8.3.3 VIN and Power VIN Terminals (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN terminals together or separately. The
VIN terminal voltage supplies the internal control circuits of the device. The PVIN terminal voltage provides the
input voltage to the power converter system. The input voltage for VIN and PVIN can range from 4.5V to 17V.
8.3.4 Auto-Skip Eco-mode™ Control
The TPS56X20 is designed with Auto-Skip Eco-mode™ to increase light load efficiency.
8.3.5 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN terminal becomes high, 6-µA current begins charging the
capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained
during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.6 V and SS terminal
source current is 6µA.
C (nF) ´ VFB(V)
Tss(ms) = SS
Issc(mA)
(1)
The TPS56X20 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage, VFB), the controller slowly activates synchronous rectification
by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOUT)
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. When prebiased conditions exist, it is recommended to disable the device by pulling the EN terminal to ground.
8.3.6 Power Good
The power-good function is activated after soft start has finished. The PGOOD output is an open drain output.
When the output voltage is between 85% and 110% of the target value, internal comparator detect power good
state and the power good signal becomes high. If the output voltage is lower than 80% or greater than 115% of
the target value, the power good signal becomes low.
8.3.7 Overcurrent Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW terminal and GND.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS56X20 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below
the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner.
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the output voltage becomes lower than 60% of the target voltage, the UVP comparator detects
it. Depending on the values of Hiccup Mode bit and UVP Latchoff Mode bit in the Control A and Control B
registers, the device may enter Hiccup Mode or Latchoff Mode or keep running under cycle-by-cycle current
limiting.
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Feature Description (continued)
The TPS56X20 also implements reverse overcurrent protection. When reverse overcurrent protection is
triggered, the high-side MOSFET turns on for the preset on-time and then the low-side MOSFET turns on to
monitor the switch valley current. The high-side MOSFET turns on again if either VFB pin voltage drops below
reference voltage, or the reverse switch current hits the reverse current trip point.
8.3.8 UVLO Protection
Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 terminal. When the VREG5 voltage
is lower than UVLO threshold voltage, the TPS56X20 is shut off. This protection is non-latching.
8.4 Device Functional Modes
8.4.1 Operation at Light Loads
The TPS56x20 works in Auto-Skip Eco-modeTM at light load to boost the efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the where its
ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept same as it
was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller
load current to the level of the nominal output voltage. The transition point to the light load operation IO(LL) current
can be estimated with Equation 2 with 500kHz used as ƒsw.
IOUT(LL) =
(PVIN - VOUT )´ VOUT
1
´
2 ´ LO ´ ƒSW
PVIN
(2)
8.5 Programming
8.5.1 I2C Interface
The TPS56X20 implements a subset of the Phillips I2C specification Ver. 1.1. The TPS56X20 is a Slave-Only (it
never becomes a Master, and so never pulls down the SCL terminal on the I2C bus). An I2C transaction consists
of either writing a data byte to one of the TPS56X20’s internal registers which requires a 3-byte transaction or
reading back one byte from a register which requires a 4-byte transaction. The protocols follow the System
Management Bus (SMBUS) Specification Ver. 2.0 Write Byte and Read Byte protocols. This spec is available on
the Internet for further reading, but the subset implemented in TPS56X20 is described below.
Long-form address modes, multi-byte data transfers and Packet Error Code (PEC) protocols are not supported in
this implementation, though a Check Sum bit unique to the TPS56X20 is implemented and described below. The
SMBUS Send Byte protocol (the 2-byte protocol used in TPS56921) is not implemented on TPS56X20.
The I2C interface terminals are composed of the SDA (Data) and SCL (Clock) terminals, and the A0 and A1
terminals to set up the chip’s address. SDA and SCL are designed to be used with pullup resistors to 3.3V. A0
and A1 are designed to be either grounded (logic LOW) or left open (logic HIGH) and should not tie to a high
voltage.
8.5.2 I2C Protocol
Input voltage – Logic levels for I2C SDA and SCL terminals are not fixed. For the TPS56X20, a logic “0” (LOW)
should be 0V and a logic “1” (HIGH) can be any voltage between 1.8V and 3.3V. Logic HIGH is generated by
external pullup resistors (see next paragraph).
Output voltage – the I2C bus has external pullup resistors, one for SCL and one for SDA. These pull up to a
voltage called VDD which must lie between 1.8V and 3.3V. The outputs are pulled down to their logic LOW levels
by open-drain outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be
selected so that the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is
less than 3.3mA.
Data format – One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data
on the SDA line must be stable during the HIGH period of the SCL clock line. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW.
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Programming (continued)
START and STOP conditions – A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a
START condition. A LOW to HIGH transition on the SDA line while the SCL line is HIGH defines a STOP
condition. START and STOP conditions are always generated by the Master. The bus is considered to be BUSY
after the condition. It is considered to be free again after a minimum of 4.7µS after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated
START are functionally identical.
Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for
an ACK signal put onto the bus by the TPS56X20 pulling down on the bus to acknowledge receipt of the data). In
the following diagrams, shaded blocks indicate SDA data generated by the TPS56X20 being sent to the Master
I2C controller, while white blocks indicate SDA data generated by the Master being received by the TPS56X20.
The Master always generates the SCL signal.
Sending data to the TPS56X20 is accomplished using the following 3-byte sequence, referred to as a Write Byte
transaction as follows:
S
SDA
Chip Address
Wr
A 6 A 5 A 4 A 3 A 2 A1 A0
A
Register Address
A
Data Byte
A
P
0 ACK R7 R6 R5 R4 R3 R2 R1 R0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
Stop Condition
Start Condition
Figure 29. A complete Write Byte transfer, adapted from SMBUS spec
Reading back data from the TPS56X20 is accomplished using the following 4-byte sequence, referred to as a
Read Byte transaction:
S
SDA
Chip Address
Wr
A 6 A 5 A 4 A 3 A 2 A1 A0
A
Register Address
A Sr
0 ACK R7 R6 R5 R4 R3 R2 R1 R0 ACK
Chip Address
A6 A5 A4 A3 A2 A1 A0
Rd
A
Data Byte
A
P
1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
Start Condition
Stop Condition
Repeated Start
Figure 30. A complete Read Byte transfer, adapted from SMBUS spec
On the TPS56X20, the I2C bus is inactive until:
1. Both SDA and SCL have been at a logic high simultaneously to prevent power sequencing issues
2. VREG5 is in regulation.
Control registers should not be written to during the Soft Start time, but can be written before VOUT is enabled or
after the PGOOD terminal or status register go high, indicating that soft start is complete.
Until a VOUT command has been accepted, the TPS56X20’s output voltage will be determined by the external
resistor divider feedback to the VFB terminals, the condition of the EN terminals, and the capacitance on the SS
terminals.
When the TPS56X20 receives a Chip Address code it recognizes to be its own, it will respond by sending an
ACK (pulling down on the SDA bus during the next clock on the SCL bus). If the address is not recognized, the
TPS56X20 assumes that the I2C message is intended for another chip on the bus, and it takes no action. It will
disregard data sent thereafter until the next START is begun.
If, after recognizing its Chip Address, the TPS56X20 receives a valid Register Address, it will send an ACK and
prepare to receive a Data Byte to be sent to that Register.
If a valid Data Byte is then received, it will send an ACK and will set the output voltage to the desired value. If the
byte is deemed invalid, ACK will not be sent and the Master will need to retry by sending a STOP sequence
followed by a new START sequence and an initiating resend of the entire address/data packet. When sending
data to the Output Voltage register, the output voltage will only change upon receipt of a valid data byte.
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Programming (continued)
8.5.3 I2C Chip Address Byte
The 7-bit address of the TPS56X20 can be any number between 34h (0110100) and 37h (0110111). The 5
MSB’s are set internally and the 2 LSB’s are customer-selectable via the A1 and A0 terminals, allowing up to 4
TPS56X20’s to be controlled on the same I2C bus. When the Master is sending the address as an 8-bit value,
the 7-bit address should be sent followed by a trailing 0 to indicate this is a WRITE operation. A0 and A1 must be
floated for logic 1. Do not tie them to external voltage source. The following codes assume this trailing zero.
Table 1. TPS56X20 Address as a Function of A1 and A0 Terminals
A1
A0
Address (binary)
Address (hex)
Ground (0)
Ground (0)
01101000
68h
Ground (0)
Open (1)
01101010
6Ah
Open (1)
Ground (0)
01101100
6Ch
Open (1)
Open (1)
01101110
6Eh
8.6 Register Maps
8.6.1 I2C Register Address Byte
The TPS56X20 contains four customer-accessible registers. Register 0 is the Output Voltage register. Registers
8 and 9 set several operating features for the regulator. The lower 3 bits of Register 9 sets the current limit for
the high-current, etc. Register 24 provides the status of the regulator. The register map is as follows:
Register
Name
VOUT
Addr
(Decimal)
0
Bit 7
Bit 6
Bit 5
Bit 4
Odd Parity
Bit 3
Bit 2
Bit 1
Bit 0
VOUT[6:0]
Control A
8
Internal Mode
Control B
9
Enable
—
OVP
Latchoff
Mode Off
Hiccup
Mode On
UVP
Latchoff
Mode Off
Status
(Read Only)
24
—
TI Only
TI Only
TI Only
PGOOD Delay [1:0]
—
ECO Mode
On
—
TI Only
DAC Settle [1:0]
Current Limit [2:0]
OT Shut
Down
Early OT
Warn
PGOOD
8.6.2 Output Voltage Registers
The lower 7 bits of the Output Voltage Register controls the VOUT of the TPS56X20. These bits are the 7-bit
selector for one of the output voltages.
As previously mentioned, when the IC powers up, the startup and output voltage regulation conditions are set by
the external resistor divider feedback to the VFB terminal, the condition of the EN terminal, and the capacitance
on the SS terminal.
Bringing the EN terminal high (or setting the Enable bit in Control register 9 high) begins a soft-start ramp on the
regulator.
After applying VIN, VREG5 will come into regulation and the I2C interface will active. The user can activate soft
start and VOUT by bring the EN terminal high or programming the Enable bit in Control Register 9.
By default, the part will regulate VOUT using the external feedback resistors connected to the VFB terminal. The
user can then program VOUT by writing any VOUT code. Alternatively, if the EN terminal is low, soft start and
VOUT can be enabled by writing the desired VOUT code and programming the Enable bit to a one.
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Table 2. Ideal VOUT vs VOUT[6:0] Code
Code
Binary
VOUT
Code
Binary
VOUT
Code
Binary
VOUT
Code
Binary
VOUT
0
0000000
0.60
32
0100000
0.92
64
1000000
1.24
96
1100000
1.56
1
0000001
0.61
33
0100001
0.93
65
1000001
1.25
97
1100001
1.57
2
0000010
0.62
34
0100010
0.94
66
1000010
1.26
98
1100010
1.58
3
0000011
0.63
35
0100011
0.95
67
1000011
1.27
99
1100011
1.59
4
0000100
0.64
36
0100100
0.96
68
1000100
1.28
100
1100100
1.60
5
0000101
0.65
37
0100101
0.97
69
1000101
1.29
101
1100101
1.61
6
0000110
0.66
38
0100110
0.98
70
1000110
1.30
102
1100110
1.62
7
0000111
0.67
39
0100111
0.99
71
1000111
1.31
103
1100111
1.63
8
0001000
0.68
40
0101000
1.00
72
1001000
1.32
104
1101000
1.64
9
0001001
0.69
41
0101001
1.01
73
1001001
1.33
105
1101001
1.65
10
0001010
0.70
42
0101010
1.02
74
1001010
1.34
106
1101010
1.66
11
0001011
0.71
43
0101011
1.03
75
1001011
1.35
107
1101011
1.67
12
0001100
0.72
44
0101100
1.04
76
1001100
1.36
108
1101100
1.68
13
0001101
0.73
45
0101101
1.05
77
1001101
1.37
109
1101101
1.69
14
0001110
0.74
46
0101110
1.06
78
1001110
1.38
110
1101110
1.70
15
0001111
0.75
47
0101111
1.07
79
1001111
1.39
111
1101111
1.71
16
0010000
0.76
48
0110000
1.08
80
1010000
1.40
112
1110000
1.72
17
0010001
0.77
49
0110001
1.09
81
1010001
1.41
113
1110001
1.73
18
0010010
0.78
50
0110010
1.10
82
1010010
1.42
114
1110010
1.74
19
0010011
0.79
51
0110011
1.11
83
1010011
1.43
115
1110011
1.75
20
0010100
0.80
52
0110100
1.12
84
1010100
1.44
116
1110100
1.76
21
0010101
0.81
53
0110101
1.13
85
1010101
1.45
117
1110101
1.77
22
0010110
0.82
54
0110110
1.14
86
1010110
1.46
118
1110110
1.78
23
0010111
0.83
55
0110111
1.15
87
1010111
1.47
119
1110111
1.79
24
0011000
0.84
56
0111000
1.16
88
1011000
1.48
120
1111000
1.80
25
0011001
0.85
57
0111001
1.17
89
1011001
1.49
121
1111001
1.81
26
0011010
0.86
58
0111010
1.18
90
1011010
1.50
122
1111010
1.82
27
0011011
0.87
59
0111011
1.19
91
1011011
1.51
123
1111011
1.83
28
0011100
0.88
60
0111100
1.20
92
1011100
1.52
124
1111100
1.84
29
0011101
0.89
61
0111101
1.21
93
1011101
1.53
125
1111101
1.85
30
0011110
0.90
62
0111110
1.22
94
1011110
1.54
126
1111110
1.86
31
0011111
0.91
63
0111111
1.23
95
1011111
1.55
127
1111111
1.87
8.6.3
CheckSum Bit (VOUT Register Only)
The CheckSum bit should be set by the Master controller to be the exclusive-NOR of the D[6:0] bits (odd parity).
This will be used by the TPS56X20 to check that a valid data byte was received. If CheckSum is not equal to the
exclusive-NOR of these bits, the TPS56X20 assumes that an error occurred during the data transmission, and it
will not send an ACK bit, nor will it reset the VOUT to the received code (or, if the Control register, will not reset
the register contents as requested). The Master should try again to send the data. When reading back the VOUT
register, the parity bit is also sent back.
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8.6.4 Control Registers
There are 4 control registers: Registers 0, 8, 9 and 24.
Table 3. Summary of Default Control Bits
CONTROL BIT(s)
DEFAULT
(BINARY)
FUNCTION
VOUT code, 7 bits VOUT[6:0] + odd parity checksum bit at VOUT[7]
VOUT[7:0]
0110010
Writing a valid code to this register also sets Internal Mode.
Sending an invalid code (checksum incorrect) to this register does not change register contents
or set Internal/Enable bits.
Internal Mode
0
(EXTERNAL
mode)
1. If set to 1, the part switches to INTERNAL mode and VOUT register value controls output
voltage.
2. Writing a valid code to the VOUT register sets this Internal Mode bit to 1.
3. The part can be set back to EXTERNAL control mode at any time by writing this bit to 0.
PGOOD Delay [1:0]
11
Part defaults to PGOOD Delay = 26.4µS
Hiccup Mode
1
Part defaults to Hiccup Mode On. If Hiccup Mode is enabled, do not turn on OVP Latchoff
Mode and/or UVP Latchoff Mode.
ECO Mode
0
Part defaults to ECO Mode Off
DAC Settle [1:0]
11
Part defaults to DAC Settle = 25µS
Enable
0
OVP Latchoff Mode
Disable
1
Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff
Mode and/or UVP Latchoff Mode.
UVP Latchoff Mode
Disable
1
Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff
Mode and/or UVP Latchoff Mode.
Part defaults to Disabled.
CurLim[2:0]
This bit can be set to 1 by writing the bit to 1. The external EN terminal being set to 1 overrides
the register value (you cannot disable the part by writing a 0 if the EN terminal is high).
111
Selects default current limit value
Enable: This bit can be used to enable the regulator just like setting the EN terminal high. The EN terminal has
priority (if EN=high, the Enable bit does nothing, the chip is already enabled). This allows the customer to tie EN
to GND externally or leave the EN terminal floating (the terminal is pulled low internally) and subsequently enable
the regulator by I2C software control.
DAC Settle [1:0]: When a new VOUT voltage is selected, this happens by setting an internal DAC to a new
internal VREF voltage. If this happens instantly, the regulator loop will be thrown out of regulation and the
DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. This can cause
VOUT overshoots (or undershoots) or head to high transient input currents. Therefore, an analog filter on the
DAC output causes this internal VREF to change more slowly. The DAC Settle[1:0] bits change the filter time
constant as follows:
DAC Settle [1:0]
Typical Filter Time Constant
00
6 µs
01
10 µs
10
15 µs
11
25 µs
The power-up default value of the DAC Settle[1:0] bits is 11.
Internal Mode: This bit can be interrogated to discover whether the chip is running in EXT Mode (using external
resistor dividers to VFB terminal to set the output voltage) or INT Mode (using codes set in Output Voltage
register to set the output voltage). Further, it can be set by the user to force either Internal or External mode.
Writing a valid value to a VOUT register always sets External to 1 on the corresponding regulator.
In default, the TPS56X20 will start up into external mode and the output voltage is set by VFB with divider
resistors. If starting up into internal VID mode is desired, the input voltage should be applied first, write Internal
Mode bit to "1" the next, then enable the device by EN terminal or EN bit.
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Current Limit [2:0]: Set the low-side valley current limit threshold for the regulator. Power-up default setting is
[111].
TPS56520
TPS56720
TPS56920
TPS56C20
Current Limit [2:0]
Typical Current
Limit
Typical Current
Limit
Typical Current
Limit
Typical Current
Limit
Units
000
1.72
3
3.8
5.08
Amps
001
2.28
3.6
4.76
6.16
Amps
010
2.88
4.58
5.8
7.68
Amps
011
3.44
5.52
6.88
9.12
Amps
100
4.32
6.68
8.52
11.16
Amps
101
5.32
8.24
10.32
13.44
Amps
110
6.4
9.92
12.52
16.24
Amps
111
7.84
12.12
15.16
19.76
Amps
PGOOD Delay [1:0]: Especially for low load currents, large jumps in the I2C-controlled VOUT setting may have a
long settling time compared to the UV/OV thresholds. If this happens, it will cause the PGOOD signal to
temporarily indicate a fault condition. If this is not the desired behavior, it is possible to “blank” the PGOOD being
pulled down for some number of µS according to the table below.
PGOOD Delay
[1:0]
FUNCTION
00
Set delay from PGOOD fault to PGOOD terminal pulldown to 0µS
01
Set delay from PGOOD fault to PGOOD terminal pulldown to 6.6µS
10
Set delay from PGOOD fault to PGOOD terminal pulldown to 13.2µS
11
Set delay from PGOOD fault to PGOOD terminal pulldown to 26.4µS (Default)
On power-up, the delay defaults to 26.4 µS. The user can reset the blanking time using these codes at any time
without affecting any other device behavior.
8.6.5 Latchoff
Latchoff turns the output voltage off in the event of an overvoltage or undervoltage condition. VOUT will not be
enabled again until the EN terminal or EN bit is cycled. By default Latchoff Mode is disabled, but overvoltage
protection (OVP) and undervoltage protection (UVP) Latchoff Modes can be enabled by setting the OVP and
UVP Latchoff Mode Off bits to zero. Power cycling Vin will reset these bits to their default values. If either
Latchoff Mode is enabled, Hiccup Mode On should be disabled.
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9 Applications and Implementation
9.1 Application Information
The devices are synchronous step down DC-DC converters rated at different output currents whose output
voltage can be dynamically scaled by sending commands over an I2C interface. The section below discusses the
design of the external components to complete the power supply design by using a typical application as a
reference
9.2 Typical Application
9.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
3.3 V
U1
R2
1.0kW
R3
1.0kW
1
1
2
SDA
3
SCL
A1 4
A0 5
VIN = PVIN = 4.5-17V
6
7
VIN
8
C1
10µF
C2
10µF
C3
4.7µF
9
10
EN
PWRGD
VFB
SDA
VOUT
SCL
SS
A1
GND
A0
VREG5
VIN
PGOOD
PVIN
VBST
PVIN
SW
PGND
SW
20
19
18
PGND
PGND
C8
2
16
15
C5
2.2µF
14
C6
0.01µF
R6
22kW
13
11
AGND
R5
18.2kW
17
C4
0.1µF
AGND
L1
12
VOUT
SW
1.5µH
21
PGND
R4
10.0kW
TPS56520
TPS56720
TPS56920
PWRPAD
R1
1.0kW
C7
100µF
PGND
PGND
1
DNP R3 for digital EN control
2
Optional
Figure 31. Typical Application Schematic – TPS56520, TPS56720 and TPS56920
9.2.1.1 Design Requirements
To
•
•
•
•
•
24
begin the design process, the user must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
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Table 4. Design Example
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4.5V to 17V
Output voltage
1.1V
Transient response, 3A-9A load step
ΔVOUT = ±5%
Output voltage ripple
25mV
Input ripple voltage
400mA
Output current rating
12A
Operating Frequency
500kHz
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB terminal. It is recommended to
use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ R5 ö
VOUT = 0.6 ´ ç 1+
÷
è R6 ø
(3)
9.2.1.2.1.1 Output Filter Selection
The output filter used with the TPS56X20 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´ COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56X20. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 5.
Table 5. Recommended Component Values
Output Voltage (V)
R5 (kΩ)
R6 (kΩ)
C8 (pF)
L1 (µH)
C7 (µF)
1
14.7
22
DNP
1.0-2.2
44-100
1.1
18.2
22
DNP
1.0-2.2
44-100
1.2
22
22
DNP
1.0-2.2
44-100
1.5
33
22
DNP
1.0-2.2
44-100
1.8
44.2
22
DNP
1.0-2.2
44-100
For higher output voltages additional phase boost can be achieved by adding a feed forward capacitor (C6) in
parallel with R5.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 500 kHz for
fSW.
Use 500 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
VIN(MAX) - VOUT
VOUT
I lP -P =
´
VIN(MAX)
LO ´ ¦ SW
(5)
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I lPEAK = IO +
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I lP -P
2
ILO(RMS) = IO2 +
(6)
1
I lP -P2
12
(7)
The capacitor value and ESR determines the amount of output voltage ripple. The TPS56X20 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 44µF to 100µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(8)
9.2.1.2.2 Input Capacitor Selection
The TPS56X20 requires an input decoupling capacitor and a bulk capacitor depending on the application. A
ceramic capacitor of 20µF or above is recommended for the decoupling capacitors from PVIN to PGND.
Additionally, a 4.7 µF ceramic capacitor from VIN to GND is also recommended. The capacitors voltage rating
needs to be greater than the maximum input voltage.
9.2.1.2.3 Bootstrap Capacitor Selection
The 0.1 µF ceramic capacitors must be connected between the VBST to SW terminals for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
9.2.1.2.4 VREG5 Capacitor Selection
For the TPS56920/720/520, a 2.2 µF ceramic capacitor must be connected between the VREG5 to GND
terminals for proper operation.
9.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
100
100
90
90
80
80
70
VIN = 5 V
Efficiency - %
Efficiency - %
70
60
VIN = 12 V
50
40
40
30
20
20
10
10
0.0
1.0
2.0
3.0
4.0
Output Current - A
Figure 32. TPS56520 Efficiency
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5.0
C029
VIN = 5 V
50
30
0
26
60
VIN = 12 V
0
0.01
0.1
1
Output Current - A
10
C030
Figure 33. TPS56520 Eco-mode™ Efficiency
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0.10
0.40
0.08
Load Regulation - %
Load Regulation - %
0.30
VIN = 12 V
0.06
0.04
0.02
0.00
-0.02
-0.04
VIN = 5 V
-0.06
0.10
0.00
-0.10
VIN = 5 V
-0.20
-0.30
-0.08
-0.10
-0.40
0.0
1.0
2.0
3.0
4.0
Output Current - A
5.0
0.0
2.0
3.0
4.0
5.0
Output Current - A
C032
Figure 35. TPS56520 Load Regulation with Eco-mode™
0.10
100
0.08
IOUT = 10 mA,
Eco-mode = OFF
0.06
90
IOUT = 10 mA,
Eco-mode = ON
80
70
Efficiency - %
0.04
0.02
0.00
±0.02
VIN = 5 V
60
VIN = 12 V
50
40
30
±0.04
IOUT = 5 A
±0.06
20
10
±0.08
0
±0.10
5
8
11
14
Input Voltage - V
17
0.0
0.08
80
0.06
Load Regulation - %
0.10
70
60
VIN = 5 V
VIN = 12 V
30
4.0
5.0
6.0
7.0
C034
VIN = 12 V
0.04
0.02
0.00
-0.02
VIN = 5 V
-0.04
20
-0.06
10
-0.08
0
0.01
3.0
Figure 37. TPS56720 Efficiency
90
40
2.0
Output Current - A
100
50
1.0
C033
Figure 36. TPS56520 Line Regulation
Efficiency - %
1.0
C031
Figure 34. TPS56520 Load Regulation
Line Regulation - %
VIN = 12 V
0.20
-0.10
0.1
1
Output Current - A
Figure 38. TPS56720 Eco-mode™ Efficiency
Copyright © 2013–2017, Texas Instruments Incorporated
10
C035
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Output Current - A
7.0
C036
Figure 39. TPS56720 Load Regulation
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27
TPS56C20, TPS56920, TPS56720, TPS56520
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0.40
0.20
0.30
0.15
VIN = 12 V
0.20
Line Regulation - %
Load Regulation - %
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
0.10
0.00
-0.10
VIN = 5 V
-0.20
-0.30
0.10
0.05
0.00
±0.05
±0.10
IOUT = 7 A
±0.15
-0.40
±0.20
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Output Current - A
7.0
5
8
100
90
90
80
80
Efficiency - %
Efficiency - %
VIN = 12 V
40
40
20
20
10
10
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Output Current - A
VIN = 12 V
0
0.01
9.0
0.1
1
10
Output Current - A
C039
Figure 42. TPS56920 Efficiency
C040
Figure 43. TPS56920 Eco-mode™ Efficiency
0.10
0.40
VIN = 12 V
0.08
0.30
Load Regulation - %
0.06
Load Regulation - %
VIN = 5 V
50
30
1.0
C038
60
30
0.0
17
70
VIN = 5 V
60
50
14
Figure 41. TPS56720 Line Regulation
100
70
11
Input Voltage - V
C037
Figure 40. TPS56720 Load Regulation with Eco-mode™
0.04
0.02
0.00
VIN = 5 V
-0.02
-0.04
-0.06
VIN = 12 V
0.20
0.10
0.00
-0.10
VIN = 5 V
-0.20
-0.30
-0.08
-0.10
-0.40
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Output Current - A
Figure 44. TPS56920 Load Regulation
28
IOUT = 10 mA,
Eco-mode = OFF
IOUT = 10 mA,
Eco-mode = ON
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9.0
C041
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Output Current - A
7.0
8.0
9.0
C042
Figure 45. TPS56520 Load Regulation with Eco-mode™
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520
TPS56C20, TPS56920, TPS56720, TPS56520
www.ti.com
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
0.20
IOUT = 10 mA,
Eco-mode = ON
Line Regulation - %
0.15
IOUT = 10 mA,
Eco-mode = OFF
VOUT = 50 mV/div (ac coupled)
0.10
0.05
0.00
±0.05
±0.10
IOUT = 2 A/div
IOUT = 9 A
±0.15
2.25 A to 6.75 A load step,
slew rate = 500 mA / µsec
±0.20
5
8
11
14
17
Input Voltage - V
C043
Time = 200 µs/div
Figure 46. TPS56920 Line Regulation
Figure 47. TPS56920 Transient Response
IOUT = 9 A
IOUT = 9 A
VIN = 100 mV/div (ac coupled)
VOUT = 20 mV/div (ac coupled)
PH = 5 V/div
PH = 5 V/div
Time = 1 µs/div
Time = 1 µs/div
Figure 48. TPS56920 Input Voltage Ripple
Figure 49. TPS56920 Output Voltage Ripple
VIN = 10 V/div
EN = 5 V/div
VOUT = 1 V/div
PGOOD = 2 V/div
Time = 2 ms/div
Figure 50. TPS56920 Start Up Relative to VIN
Copyright © 2013–2017, Texas Instruments Incorporated
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29
TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
www.ti.com
9.2.3 TPS56C20 12-A Converter
3.3 V
R2
1.0kW
R3
1.0kW
1
1
2
SDA
3
SCL
A1 4
A0 5
VIN = PVIN = 4.5-17V
6
7
VIN
8
C1
10µF
C2
10µF
C3
4.7µF
9
10
PGND
11
AGND
12
R4
10.0kW
U1
PWRGD
TPS56C20
EN
VFB
SDA
VOUT
SCL
SS
A1
GND
A0
VREG5
VIN
PGOOD
PVIN
VBST
PVIN
SW
PGND
SW
PGND
SW
PGND
PGND
PWRPAD
R1
1.0kW
SW
SW
24
23
22
R5
18.2kW
21
C8
2
20
19
C5
3.3µF
18
C6
0.01µF
R6
22kW
17
16
15
14
AGND
C4
0.1µF
L1
13
VOUT
PGND
25
1.5µH
C7
100µF
PGND
PGND
1
DNP R3 for digital EN control
2
Optional
Figure 51. Typical Schematic – TPS56C20
9.2.3.1 Design Requirements
To
•
•
•
•
•
begin the design process, the user must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
9.2.3.2 Design Procedure
Follow the design procedure for the TPS56X20 converter listed above. For the TPS56C20, a 3.3 µF ceramic
capacitor must be connected between the VREG5 to GND terminals for proper operation. Do not load the
VREG5 terminal with any other load. It is recommended to use a ceramic capacitor with a dielectric of X5R or
better.
9.2.3.3 TPS56C20 Application Performance Curves
VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.
30
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www.ti.com
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
100
100
90
90
80
80
70
VIN = 5 V
Efficiency - %
Efficiency - %
70
60
50
VIN = 12 V
40
60
40
30
30
20
20
10
10
0
0.0
2.0
4.0
6.0
8.0
10.0
0.1
1
10
100
Output Current - A
C044
Figure 52. TPS56C20 Efficiency
C045
Figure 53. TPS56C20 Eco-mode™ Efficiency
0.25
0.40
0.20
0.30
VIN = 12 V
Load Regulation - %
0.15
Load Regulation - %
VIN = 12 V
0
0.01
12.0
Output Current - A
VIN = 5 V
50
0.10
0.05
0.00
-0.05
-0.10
-0.15
VIN = 12 V
0.20
0.10
0.00
-0.10
-0.20
VIN = 5 V
VIN = 5 V
-0.30
-0.20
-0.25
-0.40
0.0
2.0
4.0
6.0
8.0
10.0
12.0
Output Current - A
0.0
2.0
4.0
6.0
8.0
10.0
Output Current - A
C046
Figure 54. TPS56C20 Load Regulation
12.0
C047
Figure 55. TPS56C20 Load Regulation with Eco-mode™
0.40
Line Regulation - %
0.30
IOUT = 10 mA,
Eco-mode = ON
0.20
IOUT = 10 mA,
Eco-mode = OFF
0.10
0.00
±0.10
±0.20
IOUT = 12 A
±0.30
±0.40
5
8
11
14
Input Voltage - V
17
C048
Figure 56. TPS56C20 Line Regulation
Copyright © 2013–2017, Texas Instruments Incorporated
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TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
www.ti.com
10 Power Supply Recommendations
The devices are designed to operate from an input supply range between 4.5 V and 17 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS56X20 device, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
1. Keep the input switching current loop as small as possible. And avoid the input switching current through
thermal Pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Kelvin connections should be brought from the output to the feedback terminal of the device.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. Input capacitors should be placed as near as possible to the device.
15. The topside and the bottom side of the PCB should be filled with as much ground plane as possible that has
an uninterrupted heat flow path. The ground plane should be made as large as possible. The PVIN cap
should connect to PGND and the VIN cap should connect to GND.
32
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TPS56C20, TPS56920, TPS56720, TPS56520
www.ti.com
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
11.2 Layout Example
Additional Thermal
Vias
Feedback Resistors
Analog Traces on
the Bottom Layer
EN
VFB
SDA
VOUT
SCL
SS
A1
GND
A0
VREG5
VIN
PGOOD
PVIN
VBST
PVIN
SW
PGND
SW
PGND
SW
PGND
SW
PGND
SW
Soft Start Cap
Exposed Thermal
Pad Area
VIN normally
connected to PVIN
PVIN Input Bypass
Capacitors
AGND
VREG5 Cap
PVIN
SW
Trace on the
Bottom Layer
Power Ground
Output Inductor
Power Ground
Output
Capacitor
VOUT
Figure 57. TPS56X20 Board Layout
Copyright © 2013–2017, Texas Instruments Incorporated
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33
TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For the TPS56C20 Pspice model go to www.ti.com/product/tps56x20.
For the TPS56920 Pspice model go to www.ti.com/product/tps56x20.
For the TPS56720 Pspice model go to www.ti.com/product/tps56x20.
For the TPS56520 Pspice model go to www.ti.com/product/tps56x20.
12.2 Documentation Support
12.2.1 Related Documentation
TPS56X20-614, 12-A, SWIFTTM Regulator Evaluation Module User's Guide, SBAU227
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS56C20
Click here
Click here
Click here
Click here
Click here
TPS56920
Click here
Click here
Click here
Click here
Click here
TPS56720
Click here
Click here
Click here
Click here
Click here
TPS56520
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS56520PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56520
TPS56520PWPR
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56520
TPS56720PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56720
TPS56720PWPR
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56720
TPS56920PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56920
TPS56920PWPR
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56920
TPS56C20PWP
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56C20
TPS56C20PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
56C20
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS56520PWPR
HTSSOP
PWP
20
2000
330.0
16.4
TPS56720PWPR
HTSSOP
PWP
20
2000
330.0
TPS56920PWPR
HTSSOP
PWP
20
2000
330.0
TPS56C20PWPR
HTSSOP
PWP
24
2000
330.0
6.95
7.1
1.6
8.0
16.0
Q1
16.4
6.95
7.1
1.6
8.0
16.0
Q1
16.4
6.95
7.1
1.6
8.0
16.0
Q1
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS56520PWPR
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS56720PWPR
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS56920PWPR
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS56C20PWPR
HTSSOP
PWP
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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