Texas Instruments | TLV757P 1-A, Low IQ, Small Size, Low Dropout Regulator (Rev. A) | Datasheet | Texas Instruments TLV757P 1-A, Low IQ, Small Size, Low Dropout Regulator (Rev. A) Datasheet

Texas Instruments TLV757P 1-A, Low IQ, Small Size, Low Dropout Regulator (Rev. A) Datasheet
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TLV757P
SBVS322A – OCTOBER 2017 – REVISED DECEMBER 2017
TLV757P 1-A, Low IQ, Small Size, Low Dropout Regulator
1 Features
3 Description
•
•
The TLV757P low-dropout regulator (LDO) is an ultrasmall, low quiescent current LDO that sources 1 A
with good line and load transient performance. The
TLV757P is optimized for wide variety of applications
by supporting an input voltage range from 1.45 V to
5.5 V. To minimize cost and solution size, the device
is offered in fixed output voltages ranging from 0.6 V
to 5 V to support the lower core voltages of modern
MCUs. Additionally, the TLV757P has a low IQ with
enable functionality to minimize standby power. This
device features an internal soft-start to lower the
inrush current which provides a controlled voltage to
the load and minimizes the input voltage drop during
start up. When shutdown, the device actively pulls
down the output to quickly discharge the outputs and
ensure a known start-up state.
1
•
•
•
•
•
•
•
•
•
Input Voltage Range: 1.45 V to 5.5 V
Available in Fixed-Output Voltages:
– 0.6 V to 5 V (50-mV Steps)
Low IQ: 25 µA (Typical)
Low Dropout:
– 425 mV (Maximum) at 1 A (3.3 VOUT)
Output Accuracy: 1% (Maximum)
Built-In Soft-Start With Monotonic VOUT Rise
Foldback Current Limit
Active Output Discharge
High PSRR: 45 dB at 100 kHz
Stable With a 1-µF Ceramic Output Capacitor
Packages:
– SOT-23-5 (Preview)
– 2 mm × 2 mm (WSON-6)
2 Applications
•
•
•
•
•
•
•
Set Top Boxes, TV, and Gaming Consoles
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
Tablets and Remote Controls
White Goods and Appliances
Grid Infrastructure and Protection Relays
Camera Modules and Image Sensors
The TLV757P is stable with small ceramic output
capacitors allowing for a small overall solution size. A
precision band-gap and error amplifier provides a
typical accuracy of 1%. All device versions have
integrated thermal shutdown, current limit, and
undervoltage lockout (UVLO). The TLV757P has an
internal foldback current limit that helps to reduce the
thermal dissipation during short circuit events.
Device Information(1)
PART NUMBER
PACKAGE
TLV757P
BODY SIZE (NOM)
SON (6)
2.00 mm × 2.00 mm
SOT-23 (5)
(Preview)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Startup Waveform
7
TLV757P
EN
VIN
VEN
IOUT
6
150
5
125
4
100
3
75
2
50
1
25
COUT
GND
ON
OFF
Copyright © 2017, Texas Instruments Incorporated
0
Output Current (mA)
CIN
175
VOUT
OUT
Voltage (V)
IN
0
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV757P
SBVS322A – OCTOBER 2017 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2017) to Revision A
•
2
Page
Released DRV package to production .................................................................................................................................. 1
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SBVS322A – OCTOBER 2017 – REVISED DECEMBER 2017
5 Pin Configuration and Functions
DBV Package (Preview)
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
DRV Package
6-Pin SON With Exposed Thermal Pad
Top View
OUT
OUT
NC
GND
4
1
6
IN
2 Thermal 5
Pad
NC
3
EN
4
NC
Not to scale
Not to scale
NC- no internal connection
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DBV
DRV
EN
3
4
I
GND
2
3
—
IN
1
6
I
NC
4
2, 5
—
No internal connection
OUT
5
1
O
Regulated output voltage pin. A capacitor with a value of 1 µF or larger is
required from this pin to ground (1). See the Input and Output Capacitor Selection
section for more information.
Thermal pad
—
Pad
—
Connect the thermal pad to a large-area ground plane. The thermal pad is
internally connected to GND.
(1)
Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less
than VLO to place the LDO into shutdown mode.
Ground pin
Input pin. A capacitor with a value of 1 µF or larger is required from this pin to
ground (1). See the Input and Output Capacitor Selection section for more
information.
The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these
capacitors is 50%. Take care to ensure that the effective capacitance at the pin is greater than 0.47 µF.
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SBVS322A – OCTOBER 2017 – REVISED DECEMBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VIN
–0.3
6
V
Enable voltage, VEN
–0.3
Output voltage, VOUT
–0.3
Operating junction temperature range, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
6
V
VIN + 0.3
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or 6 V, whichever is smaller
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Output voltage
VEN
Enable voltage
IOUT
NOM
MAX
1.45
UNIT
5.5
V
0.6
5
V
0
5.5
V
Output current
0
1
A
CIN
Input capacitor
1
COUT
Output capacitor
1
fEN
Enable toggle frequency
TJ
Junction temperature
µF
–40
200
µF
10
kHz
125
°C
6.4 Thermal Information
TLV757
THERMAL METRIC
(1)
DBV (SOT-23)
DRV (SON)
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
231.1
100.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
118.4
108.5
°C/W
RθJB
Junction-to-board thermal resistance
64.4
64.3
°C/W
ψJT
Junction-to-top characterization parameter
28.4
10.4
°C/W
ψJB
Junction-to-board characterization parameter
63.8
64.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
34.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.45 V (whichever is greater), IOUT =
1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage
VOUT
Output voltage
TEST CONDITIONS
–40°C ≤ TJ ≤ 85°C, VOUT ≥ 1 V
Output accuracy
–40°C ≤ TJ ≤ 85°C, 0.6 V ≤ VOUT < 1 V
VOUT ≥ 1 V
0.6 V ≤ VOUT < 1 V
(ΔVOUT)ΔVIN
ΔVOUT/ΔIOU
Line regulation
Load regulation
T
MIN
Ground current
ISHDN
Shutdown current
0.6
5
V
–1%
1%
–10
10
–1.5%
1.5%
–15
0.044
DBV package
0.060
25
VOUT = VOUT - 0.2 V,
VOUT ≤ 1.5 V
ISC
Short circuit current
limit
VOUT = 0 V, VIN = VOUT + VDO(MAX) + 0.25 V
IOUT = 1 A,
–40°C ≤ TJ ≤ +125°C
VOUT = 0.9 x VOUT, 1.5
V < VOUT ≤ 4.5 V
1.2
1.55
1.78
A
755
mA
0.8 V ≤ VOUT < 1 V
1200
1300
mV
1 V ≤ VOUT < 1.2 V
1100
1150
mV
1.2 V ≤ VOUT < 1.5 V
1000
1050
mV
1.5 V ≤ VOUT < 1.8 V
700
800
mV
1.8 V ≤ VOUT < 2.5 V
650
750
mV
2.5 V ≤ VOUT < 3.3 V
500
600
mV
3.3 V ≤ VOUT < 5.0 V
300
425
mV
0.6 V ≤ VOUT < 0.8 V
1450
mV
0.8 V ≤ VOUT < 1 V
1350
mV
1 V ≤ VOUT < 1.2 V
1200
mV
1.2 V ≤ VOUT < 1.5 V
1100
mV
1.5 V ≤ VOUT < 1.8 V
850
mV
1.8 V ≤ VOUT < 2.5 V
800
mV
2.5 V ≤ VOUT < 3.3 V
650
mV
3.3 V ≤ VOUT < 5.0 V
475
mV
f = 1 kHz, VIN = VOUT + 1 V, IOUT = 50 mA
52
f = 100 kHz, , VIN = VOUT + 1 V, IOUT = 50 mA
46
BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 1 A
VUVLO
Undervoltage lockout
VIN rising
Undervoltage lockout
hysteresis
VIN falling
f = 1 MHz, , VIN = VOUT + 1 V, IOUT = 50 mA
(1)
µA
mV
Output noise voltage
VHI
1
1400
Vn
EN pin high voltage
(enabled)
0.1
1350
Power supply rejection
ratio
Startup time
µA
0.6 V ≤ VOUT < 0.8 V
PSRR
tSTR
31
40
VEN ≤ 0.4 V, 1.45 V ≤ VIN ≤ 5.5 V,
–40°C ≤ TJ ≤ +125°C
VIN = VOUT + VDO(MAX) + 0.25 V
HYST
V/A
–40°C ≤ TJ ≤ +125°C
Dropout voltage
mV
mV
33
Output current limit
VUVLO,
15
DRV package
ICL
VDO
mV
2
–40°C ≤ TJ ≤ +85°C
IOUT = 1 A,
–40°C ≤ TJ ≤ +85°C
UNIT
V
VOUT + 0.5 V (1) ≤ VIN ≤ 5.5 V
0.1 mA ≤ IOUT ≤ 1 A, VIN ≥ 2.4
V
MAX
5.5
TJ = 25°C
IGND
TYP
1.45
dB
52
71.5
1.21
1.3
µVRMS
1.44
V
40
mV
550
µs
1
V
VIN = 1.45V for VOUT < 0.9 V
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Electrical Characteristics (continued)
over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.45 V (whichever is greater), IOUT =
1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLO
EN pin low voltage
(enabled)
IEN
Enable pin current
VIN = 5.5 V, EN = 5.5 V
10
nA
RPULLDOWN
Pulldown resistance
VIN = 3.3 V (P version only)
95
Ω
TSD
Thermal shutdown
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
155
°C
6
0.3
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
80
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
80
70
60
50
40
30
20
10
10 mA
50 mA
0
10
100
IOUT
100 mA
500 mA
1k
1A
10k
100k
Frequency (Hz)
1M
70
60
50
40
30
20
VIN = 3.8 V
VIN = 4 V
VIN = 4.3 V
VIN = 5 V
10
0
10
10M
100
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 µF
Figure 1. PSRR vs IOUT
1M
10M
Figure 2. PSRR Vs VIN
10
5
70
2
60
Noise (PV/—Hz)
Power Supply Rejection Ratio (dB)
10k
100k
Frequency (Hz)
VOUT = 3.3 V, COUT = 1 µF, IOUT = 1 A
80
50
40
30
10
100
1
0.5
0.2
0.1
COUT
4.7 PF, 151 PVRMS
10 PF, 150 PVRMS
22 PF, 151 PVRMS
47 PF, 150 PVRMS
100 PF, 148 PVRMS
0.05
COUT
1 PF
10 PF
22 PF
100 PF
20
0
10
0.02
0.01
1k
10k
100k
Frequency (Hz)
1M
0.005
10
10M
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 µF
Figure 3. PSRR Vs COUT
Noise (PV/—Hz)
1
0.5
0.2
0.02
0.01
0.005
10
10k
100k
Frequency (Hz)
1M
10M
Figure 4. Output Spectral Noise Density
2
0.1
1k
10
5
5
0.05
100
VOUT = 3.3 V, IOUT = 1 A, VRMS BW = 10 Hz to 100 kHz
10
Noise (PV/—Hz)
1k
IOUT
10 mA, 158 PVRMS
50 mA, 159 PVRMS
100 mA, 159 PVRMS
500 mA, 153 PVRMS
1 A, 151 PVRMS
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 3.3 V, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
Figure 5. Output Spectral Noise Density
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
VOUT
0.9 V, 53.8 PVRMS
1.2 V, 71.47 PVRMS
3.3 V, 151 PVRMS
5 V, 217 PVRMS
100
1k
10k
100k
Frequency (Hz)
1M
10M
IOUT = 1 A, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
Figure 6. Output Noise vs Frequency and VOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
6
220
3.328
VIN
VOUT
200
Output Noise Voltage (PVRMS)
5
3.32
160
140
120
100
4
3.312
3
3.304
2
3.296
1
3.288
Output Voltage (V)
Input Voltage (V)
180
80
60
0
40
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
0
5
20
Time (ms)
IOUT = 1 A, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
VOUT = 3.3 V, COUT = 1 µF, VIN slew rate = 1 V/µs
Figure 7. Output Noise Voltage vs VOUT
Figure 8. Line Transient
2.2
50
1.6
0
1.4
-50
1.2
-100
1
-150
0.8
-200
0.6
-250
0.4
-300
0.2
-350
0
20
40
60
80
100 120
Time (Ps)
140
160
4
3
2
1
0
200
180
VIN
VOUT
5
Voltage (V)
100
VOUT
2
IOUT
1.8
6
Output Current (A)
AC Coupled Output Voltage (mV)
200
150
3.28
50
40
0
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, IOUT slew rate = 1 A/µs
Figure 9. 3.3-V, 1-mA to 1-A Load Transient
Figure 10. VIN = VEN Power-Up
7
5
175
VOUT
VIN
VOUT
VIN
VEN
IOUT
6
150
5
125
4
100
3
75
2
50
1
25
Voltage (V)
Voltage (V)
4
3
2
1
0
0
0
1
2
3
4
5
6
Time (ms)
7
8
9
10
Output Current (mA)
6
0
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
VIN = 5 V, IOUT = 100 mA, VEN slew rate = 1 V/µs, VOUT = 3.3 V
Figure 11. VIN = VEN Shutdown
8
Figure 12. EN Startup
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
400
-40qC
0qC
25qC
85qC
125qC
0
-40qC
0qC
25qC
350
Dropout Voltage (mV)
Change in Output Voltage (mV)
15
-15
-30
300
250
200
150
100
-45
50
0
-60
0
100
200
300
400 500 600 700
Output Current (mA)
800
0
900 1000
100
Figure 13. Load Regulation vs IOUT
200
300
400 500 600 700
Output Current (mA)
800
900 1000
Figure 14. 3.3-V Dropout Voltage vs IOUT
1
400
-40qC
0qC
25qC
85qC
125qC
350
300
200
150
125qC
0.25
0
-0.25
100
-0.5
50
-0.75
-1
3.5
0
100
25qC
85qC
0.5
250
0
-40qC
0qC
0.75
Accuracy (%)
Dropout Voltage (mV)
85qC
125qC
200
300
400 500 600 700
Output Current (mA)
800
900 1000
3.75
4
4.25
4.5
4.75
Input Voltage (V)
5
5.25
5.5
VOUT = 3.3 V, IOUT = 1 mA
Figure 15. 5.0-V Dropout Voltage vs IOUT
Figure 16. 3.3 V Regulation vs VIN (Line Regulation)
1
-40qC
0qC
0.75
25qC
85qC
125qC
GND Pin Current (PA)
Accuracy (%)
0.5
0.25
0
-0.25
-0.5
-0.75
-1
5
5.1
5.2
5.3
Input Voltage (V)
5.4
5.5
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-40qC
0qC
25qC
85qC
125qC
0
100
200
300
400 500 600 700
Output Current (mA)
800
900 1000
IOUT = 1 mA, VOUT = 5 V
Figure 17. 5.0-V Accuracy vs VIN (Line Regulation)
Figure 18. IGND vs IOUT
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Typical Characteristics (continued)
300
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40qC
0qC
25qC
85qC
125qC
-40qC
0qC
25qC
85qC
125qC
250
Quiescent Current (PA)
GND Pin Current (PA)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
200
150
100
50
0
0
1
2
3
4
Input Voltage (V)
5
6
0
1
VOUT = 3.3 V, IOUT = 1 mA
2
Figure 19. IGND vs VIN
6
Figure 20. IGND vs VIN
180
-40qC
0qC
25qC
85qC
125qC
250
160
Shutdown Current (nA)
300
Shutdown Current (nA)
5
VOUT = 3.3 V, IOUT = 0 mA
350
200
150
100
50
140
120
100
80
60
40
20
0
-40
0
0
1
2
3
4
Input Voltage (V)
5
6
0
20
40
60
80
Temperature (qC)
100
120
140
250
800
750
-40qC
0qC
25qC
85qC
125qC
Enable Current (PA)
200
700
650
600
150
100
50
550
EN Negative
500
-50
-20
Figure 22. ISHDN vs Temperature
Figure 21. ISHDN vs VIN
Enable Threshold (mV)
3
4
Input Voltage (V)
EN Positive
0
-25
0
25
50
Temperature (qC)
75
100
125
0
1
2
3
4
Input Voltage (V)
5
6
VEN = 5.5 V
Figure 23. Enable Threshold vs Temperature
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Figure 24. IEN vs VIN
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
600
1.4
-40qC
0qC
25qC
550
500
Output Voltage (mV)
UVLO Threshold (V)
1.36
1.32
1.28
1.24
450
400
350
300
250
200
150
100
UVLO Negative
1.2
-50
85qC
125qC
50
UVLO Positive
0
-25
0
25
50
Temperature (qC)
75
100
125
0
Figure 25. UVLO Threshold vs Temperature
1
2
3
Output Current (mA)
4
5
Figure 26. IOUT vs VOUT Pulldown Resistor
4
Output Voltage (V)
3.2
2.4
1.6
-40qC
0qC
25qC
85qC
125qC
0.8
0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Output Current (mA)
Figure 27. 3.3-V Foldback Current Limit vs IOUT
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7 Detailed Description
7.1 Overview
The TLV757P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low
quiescent current and delivers excellent line and load transient performance. The TLV757P is optimized for wide
variety of applications by supporting an input voltage range from 1.4 V to 5.5 V. To minimize cost and solution
size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core voltages of
modern microcontrollers (MCUs).
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
is –40°C to +125°C.
7.2 Functional Block Diagram
OUT
IN
Current
Limit
R1
±
+
Thermal
Shutdown
UVLO
120 Ÿ
R2
EN
Bandgap
GND
Logic
(1)
R2 = 550 kΩ, R1 = adjustable.
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO
voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is
connected to ground with a 120-Ω pulldown resistor.
7.3.2 Enable (EN)
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by
forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN.
The device has an internal pull-down that connects a 120-Ω resistor to ground when the device is disabled. The
discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel
with the 120-Ω pulldown resistor. Equation 1 calculates the time constant τ:
120 · RL
t=
· COUT
120 + RL
(1)
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Feature Description (continued)
The EN pin is independent of the input pin, but if the EN pin is driven to a higher voltage than VIN, the current
into the EN pin increases. This effect is illustrated in Figure 24. When the EN voltage is higher than the input
voltage there is an increased current flow into the EN pin. If this increased flow causes problems in the
application, sequence the EN pin after VIN is high, or to tie EN to VIN to prevent this flow increase from
happening. If EN is driven to a higher voltage than VIN, limit the frequency on EN to below 10 kHz.
7.3.3 Internal Foldback Current Limit
The TLV757P has an internal current limit that protects the regulator during fault conditions. The current limit is a
hybrid scheme with brick wall until the output voltage is less than 0.4 × VOUT(NOM). When the voltage drops below
0.4 × VOUT(NOM), a foldback current limit is implemented which scales back the current as the output voltage
approaches GND. When the output shorts, the LDO supplies a typical current of ISC. The output voltage is not
regulated when the device is in current limit. In this condition, the output voltage is the product of the regulated
current and the load resistance. When the device output is shorts, the PMOS pass transistor dissipates power
[(VIN – VOUT) × ISC] until thermal shutdown is triggered and the device turns off. After the device cools down, the
internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles
between current limit and thermal shutdown.
The foldback current-limit circuit limits the current that is allowed through the device to current levels lower than
the minimum current limit at nominal VOUT current limit (ICL) during start up. See Figure 27 for typical current limit
values. If the output is loaded by a constant-current load during start up, or if the output voltage is negative when
the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the
device may not rise to the full output voltage. For constant-current loads, disable the output load until the output
has risen to the nominal voltage.
Excess inductance can cause the current limit to oscillate. Minimize the inductance to keep the current limit from
oscillating during a fault condition.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation which protects the circuit from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to a maximum
of 125°C. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry protects against overload conditions but is not intended to be activated in normal
operation. Continuously running the device into thermal shutdown degrades device reliability.
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7.4 Device Functional Modes
Table 1 lists a comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
(1)
(2)
VIN
EN
IOUT
TJ
Normal (1)
VIN > VOUT(NOM) + VDO
VEN > VHI
IOUT < ICL
TJ < TSD
Dropout (1)
VIN < VOUT(NOM) + VDO
VEN > VHI
—
TJ < TSD
Disabled (2)
VIN < VUVLO
VEN < VLO
—
TJ > TSD
All table conditions must be met.
The device is disabled when any condition is met.
7.4.1 Normal Operation
The device regulates to the nominal output voltage when all of the following conditions are met.
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks
the input voltage. During this mode, the transient performance of the device degrades because the pass device
is in a triode state and no longer controls the output voltage of the LDO. Line or load transients in dropout can
result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible
when the control loop is out of balance. During the normal time required for the device to regain regulation, VIN ≥
VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.
7.4.3 Disabled
The output is shut down by forcing the enable pin below VLO. When disabled, the pass device is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from
the output to ground. The active pulldown is on when sufficient input voltage is provided.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV757P requires an output capacitance of 0.47 μF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in capacitance value and equivalent series
resistance (ESR) over temperature. When selecting a capacitor for a specific application, consider the DC bias
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. As a
general rule, ceramic capacitors must be derated by 50%. For best performance, TI recommends a maximum
output capacitance value of 200 µF.
Place a 1 µF or greater capacitor on the input pin of the LDO. Some input supplies have a high impedance.
Placing a capacitor on the input supply reduces the input impedance. The input capacitor counteracts reactive
input sources and improves transient response and PSRR. If the input supply has a high impedance over a large
range of frequencies, several input capacitors are used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
The TLV757P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales linearly with the output current because the PMOS device
functions like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 14 and Figure 15 for typical dropout values.
8.1.3 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range; see Figure 28.
Use an enable signal to avoid this condition.
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Application Information (continued)
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Voltage
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 28. Startup into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 29 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS)
is pulled all the way down to give the pass device the lowest on-resistance as possible. However, if a line
transient occurs while the device is in dropout, the loop is not in regulation which can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Application Information (continued)
Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
Figure 29. Line Transients From Dropout
8.1.4 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
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Application Information (continued)
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 30 shows one approach of protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 30. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free of other heat-generating devices as possible that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
It is important to minimize power dissipation to achieve greater efficiency. This minimizing process is achieved by
selecting the correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage
differential . The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area should contain an array of plated
vias that conduct heat to inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to
Equation 3.
TJ = TA + θJA × PD
(3)
Unfortunately, this thermal resistance (θJA) is dependent on the heat-spreading capability built into the particular
PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The θJA value is only used as a relative measure of package thermal performance. θJA is the sum of the VQFN
package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB
copper.
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Application Information (continued)
8.1.5.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but offer
practical and relative means of estimating junction temperatures. These psi metrics are independent of the
copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are shown in the table and are used in
accordance with Equation 4.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as shown in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(4)
8.2 Typical Application
IN
OUT
1 …F
DC-DC
Converter
1 …F
TLV757P
EN
Load
GND
ON
Copyright © 2017, Texas Instruments Incorporated
OFF
Figure 31. TLV757P Typical Application
8.2.1 Design Requirements
Table 2 lists the design requirements for this application.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
2.5 V
Output voltage
1.8 V
Input current
700 mA (maximum)
Output load
600-mA DC
Maximum ambient temperature
70°C
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 5 to calculate the current through the input.
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(5)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 6 to calculate the power dissipation. Multiply PD by RθJA and add the
ambient temperature (TA) to calculate the junction temperature (TJ) as Equation 7 shows.
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(6)
(7)
If the (TJ(MAX)) value does not exceed 125°C calculate the maximum ambient temperature as Equation 8 shows.
Equation 9 calculates the maximum ambient temperature with a value of 82.916°C.
TA(MAX) = TJ(MAX) – RθJA × PD
TA(MAX) = 125°C – 100.2 × (2.5 V –1.8 V) × (0.6 A) = 82.916°C
(8)
(9)
8.2.3 Application Curves
1.2
1
2
0.8
1.5
0.6
1
0.4
VIN
VOUT
EN
IIN
0.5
0.2
0
0.5
1
80
60
40
20
IOUT = 600 mA
0
0
Input Current (A)
Voltage (V)
2.5
100
Power Supply Rejection Ratio (dB)
3
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 2.5 V, VOUT = 1.8 V, IOUT = 600 mA
Figure 32. Startup With a 600-mA Load
Figure 33. PSRR (2.5 V to 1.8 V at 600 mA)
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV757P. If the input source is
reactive, consider using multiple input capacitors in parallel with the 1-µF input capacitor to lower the input supply
impedance over frequency.
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10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
10.2 Layout Examples
VOUT
VIN
1
CIN
5
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
Figure 34. Layout Example: DBV Package
VIN
VOUT
COUT
1
6
2
5
3
4
CIN
EN
GND PLANE
Represents via used for
application specific connections
Figure 35. Layout Example: DRV Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1) (2)
PRODUCT
TLV757xx(x)Pyyyz
(1)
(2)
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 50 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV757P family will actively
discharge the output when the device is disabled.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.6 V to 5 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV75709PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1H8F
TLV75709PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HGH
TLV75710PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FEF
TLV75710PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HHH
TLV75712PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FFF
TLV75712PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HIH
TLV75715PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FGF
TLV75715PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HJH
TLV75718PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FHF
TLV75718PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HKH
TLV75719PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1H7F
TLV75719PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HLH
TLV75725PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FIF
TLV75725PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HMH
TLV75728PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FJF
TLV75728PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HNH
TLV75729PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1H9F
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Jun-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV75730PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1GHF
TLV75730PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HOH
TLV75733PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
1FKF
TLV75733PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HPH
TLV75740PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HQH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
B0
(mm)
K0
(mm)
P1
(mm)
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75709PDRVR
WSON
DRV
6
3000
180.0
TLV75710PDBVR
SOT-23
DBV
5
3000
178.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
9.0
3.3
3.2
1.4
4.0
8.0
TLV75710PDBVR
SOT-23
DBV
5
3000
Q3
180.0
8.4
3.2
3.2
1.4
4.0
8.0
TLV75710PDRVR
WSON
DRV
6
Q3
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75712PDBVR
SOT-23
DBV
TLV75712PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
TLV75712PDRVR
WSON
Q3
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75715PDBVR
TLV75715PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75715PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75709PDBVR
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
W
Pin1
(mm) Quadrant
TLV75718PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75718PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75719PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75719PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75719PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75725PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75725PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV75725PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75728PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75728PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75728PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75729PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75729PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75730PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75730PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75730PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75733PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV75733PDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV75733PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV75740PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV75709PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75709PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75710PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75710PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV75710PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75712PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75712PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75712PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75715PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75715PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75715PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75718PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75718PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75719PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75719PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75719PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75725PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75725PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75725PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75728PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75728PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75728PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75729PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75729PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75730PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75730PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75730PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75733PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV75733PDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV75733PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TLV75740PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A
C
B
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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