Texas Instruments | TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator | Datasheet | Texas Instruments TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator Datasheet

Texas Instruments TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator Datasheet
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TPS55160-Q1, TPS55162-Q1, TPS55165-Q1
SLVSD46 – NOVEMBER 2017
TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up
and Step-Down Voltage Regulator
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
2-V to 36-V Input Voltage Range for VOUT = 5 V
5-V or 12-V Fixed Output Voltage (TPS55165-Q1)
Adjustable Output Voltage Options from 5.7 V to
9 V (TPS55160-Q1 and TPS55162-Q1)
Up to 85% Efficiency
1-A Output Current for VOUT = 5 V and VIN ≥ 5.3 V
0.8-A Output Current for VOUT = 5 V and
VIN ≥ 3.8 V
0.4-A Output Current for VOUT = 5 V and
VIN ≥ 2.3 V
Automatic Transition Between Step-Down and
Step-Up Mode
Low-Power Mode for Improved Efficiency at Light
Load Conditions (TPS55160-Q1 and
TPS55165-Q1)
Device Quiescent Current Less than 15 μA in
Low-Power Mode (TPS55160-Q1 and
TPS55165-Q1)
Device Shutdown Current Less than 3 μA
Forced Fixed-Frequency Operation at 2 MHz
Selectable Spread Spectrum (TPS55160-Q1 and
TPS55165-Q1)
Wake-up Through IGN With Power-Latch Function
Smart Power-Good Output With Configurable
Delay Time
Overtemperature Protection and Output
Overvoltage Protection
Available in Easy-to-Use 20-Pin HTSSOP
PowerPAD™ Package
•
Industrial Applications With Fluctuating Input
Voltage
– Solar-to-Battery Charging
– Li-Ion Battery Packs
3 Description
The TPS5516x-Q1 family of devices is a high-voltage
synchronous buck-boost DC-DC converter. The
device provides a stable power-supply output from a
wide varying input-power supply such as an
automotive car battery. The buck-boost overlap
control ensures automatic transition between stepdown and step-up mode with optimal efficiency. The
TPS55165-Q1 output voltage can be set to a fixed
level of 5 V or 12 V. The TPS55160-Q1 and
TPS55162-Q1 devices have a configurable output
voltage ranging from 5.7 V to 9 V that is set by an
external resistive divider.
Output currents can be as high as 1 A for a normal
car battery voltage, and can be maintained at 0.4 A
for lower input voltages, such as those for common
battery-cranking profiles. The buck-boost converter is
based on a fixed-frequency, pulse-width-modulation
(PWM) control circuit using synchronous rectification
to obtain maximum efficiency. The switching
frequency is set to 2 MHz (typical) which allows for
the usage of a small inductor that uses less board
space.
Device Information(1)
PART NUMBER
TPS55162-Q1
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Available for preview.
Simplified Schematic
4.7 µF
0.1 µF
2 Applications
Start-Stop Sensitive Automotive Power
Applications
– Infotainment and Cluster
– Body Electronics and Gateway Modules
BODY SIZE (NOM)
TPS55165-Q1(2)
2 V ” VIN ” 36 V
•
PACKAGE
TPS55160-Q1
10 µF
ON
BST1 L1
VINP
L2
BST2
VOUT
VINL
100 k
IGN_PWRL
OFF
Power
Latch
IGN
LowPower
Mode
PS
PGND
GND
VOUT = 5 V
1 A at VIN t 5.3 V
0.8 A at VIN t 3.8 V
0.4 A at VIN t 2.3 V
0.1 µF
PG
VOUT_SENSE
SS_EN
VOS_FB
22 µF
100 nF
VREG
VREG_Q
PG_DLY
TPS5516x-Q1
RDLY
4.7 µF
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS55160-Q1, TPS55162-Q1, TPS55165-Q1
SLVSD46 – NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
Overvoltage Lockout ................................................
7.17 Switching Characteristics — IGN Wakeup............
7.18 Switching Characteristics — Logic Pins PS,
IGN_PWRL, SS_EN ................................................
7.19 Switching Characteristics – Power Good..............
7.20 Typical Characteristics ..........................................
1
1
1
2
3
3
5
8
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics — External Components .. 6
Electrical Characteristics — Supply Voltage (VINP,
VINL pins) .................................................................. 6
7.7 Electrical Characteristics — Reference Voltage
(VOS_FB Pin) and Output Voltage (VOUT Pin) ........ 7
7.8 Electrical Characteristics — Buck-Boost................... 7
7.9 Electrical Characteristics — Undervoltage and
Overvoltage Lockout .................................................. 9
7.10 Electrical Characteristics — IGN Wakeup .............. 9
7.11 Electrical Characteristics — Logic Pins PS,
IGN_PWRL, SS_EN .................................................. 9
7.12 Electrical Characteristics – Overtemperature
Protection ................................................................. 10
7.13 Electrical Characteristics – Power Good............... 10
7.14 Switching Characteristics — Reference Voltage
(VOS_FB Pin) and Output Voltage (VOUT Pin) ...... 10
7.15 Switching Characteristics — Buck-Boost.............. 11
7.16 Switching Characteristics — Undervoltage and
9
11
12
12
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
7.1
7.2
7.3
7.4
7.5
7.6
11
11
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
16
17
18
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application ................................................. 31
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2017
*
Initial release.
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SLVSD46 – NOVEMBER 2017
5 Description (continued)
A selectable spread-spectrum option (TPS55160-Q1 and TPS55165-Q1) helps reduce radiated electromagnetic
interference (EMI). Internal loop compensation eliminates the need for external compensation components. In
low-power mode (TPS55160-Q1 and TPS55165-Q1), the device achieves a quiescent current of less than 15 µA
which allows an automotive electronic control unit (ECU) to stay in standby mode (for example, listen-to-CAN
mode) while achieving OEM quiescent-current requirements. The low-power mode can be disabled which forces
the converter to operate in full continuous mode at a fixed switching frequency of 2 MHz (typical) for the entire
load-current range. The maximum average current in the inductor is limited to a typical value of 2 A.
The converter can be disabled to minimize battery drain. Furthermore, the device offers a power-good (PG) pin
to indicate when the output rail is less than the specified tolerance. The device also has a power-latch function to
allow an external microcontroller unit (MCU) to keep the output voltage available for as long as needed.
The device is available in a 20-pin HTSSOP PowerPAD package.
6 Pin Configuration and Functions
PWP PowerPAD™ Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
PGND
1
20
L2
L1
2
19
BST2
BST1
3
18
GND
VINP
4
17
VOUT
VINL
5
16
VOUT_SENSE
15
PG
Thermal
IGN
6
PS
7
14
VOS_FB
IGN_PWRL
8
13
GND
SS_EN
9
12
VREG
10
11
VREG_Q
PG_DLY
Pad
Not to scale
Pin Functions
PIN
I/O (1) TYPE (2)
DESCRIPTION
NAME
NO.
PGND
1
—
G
Power-ground pin
L1
2
I
A
Buck power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the L1
and L2 pins.
BST1
3
I
A
Bootstrap node for the buck power stage. Connect a 100-nF capacitor between this pin and the L1
pin.
VINP
4
—
P
Supply-power input voltage. Connect this pin to the input supply line.
VINL
5
—
P
Supply-input voltage for internal biasing. Connect this pin to the input supply line.
IGN
6
I
D
Ignition-enable input signal. The ignition is enabled when this pin is high (1) and is disabled when
this pin is low (0).
PS
7
I
D
Logic-level input signal to enable and disable low-power mode. The power mode is low-power
mode when this pin is high (1) and is normal mode when this pin is low (1).
(1)
(2)
I = Input Pin, O = Output Pin
A = Analog Pin, D = Digital Pin, G = Ground Pin, P = Power Pin
Copyright © 2017, Texas Instruments Incorporated
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Pin Functions (continued)
PIN
NAME
NO.
I/O (1) TYPE (2)
DESCRIPTION
IGN_PWRL
8
I
D
Logic-level IGN power-latch signal. The IGN pin is latched when this pin is high (1) and is not
latched when this pin is low (0).
SS_EN
9
I
D
Configuration pin to enable and disable the spread-Spectrum. The spread-spectrum feature is
enabled when this pin is open and disabled when this pin is low.
PG_DLY
10
I
A
Configuration pin for power-good delay time. Connect this pin to a resistor with a value from 10kΩ
to 100kΩ to configure the PG delay time from 0.5 ms to 40 ms. Connect this pin to ground for the
default PG delay time which is 2 ms (typical).
VREG_Q (3)
11
I
A
Quiet feedback pin for the gate-drive supply of the buck-boost power stages. This pin must be
connected close to the top side of the 4.7-µF (typical) decoupling capacitor at the VREG output pin.
VREG
12
O
A
Gate-drive supply for the buck-boost power stages. Apply a 4.7-µF (typical) decoupling capacitor at
this pin to the power ground. The VREG pin cannot drive external loads in the application.
GND
13
—
G
Analog ground
VOS_FB
14
I
A
For the TPS55160-Q1 and TPS55162-Q1 devices, this pin is used to adjust the VOUT
configuration. Connect this pin to a resistive feedback network with less than 1-MΩ total resistance
between the VOUT pin, FB pin, and GND pin (analog ground).
For the TPS55165-Q1 device, this pin is used to select the output voltage. The output voltage is set
to 5 V when this pin is connected to the GND pin. The output voltage is 12 V when this pin is
connected to the VREG pin.
PG
15
O
D
Output power good pin. This pin is an open-drain pin. The status of the power-good output is good
when this pin is high (1) and has a failure when this pin is low (0)
VOUT_SEN
SE
16
I
A
Sense pin for the buck-boost converter output voltage. This pin must be connected to the VOUT
pin.
VOUT
17
O
A
Buck-boost converter output voltage
GND
18
—
G
Analog ground
BST2
19
I
A
Bootstrap node for the boost power-stage. Connect a typical 100-nF capacitor between this pin and
the L2 pin.
L2
20
I
A
Boost power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the
L1 and L2 pins.
—
—
The thermal pad must be soldered to the power ground to achieve the appropriate power
dissipation through the analog ground plane.
PowerPAD
(3)
4
The VREG_Q pin must be connected to the VREG pin at all times while the device is in operation to prevent possible electrostatic
overstress (EOS) damage to the device.
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SLVSD46 – NOVEMBER 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
M1.1
POS
Protected battery voltage
VINP, VINL
–0.3
40
V
M1.2
Feedback voltage
VOS_FB
–0.3
5.5
V
M1.3
Low-power mode input
PS
-0.3
40
V
M1.4
Low-voltage inputs
IGN_PWRL, SS_EN, PG_DLY
–0.3
5.5
V
M1.5
Ignition enable input
IGN
–7
40
V
M1.6
Buck-boost output voltage
VOUT, VOUT_SENSE
–0.3
20
V
M1.7
Gate-driver supply
VREG, VREG_Q
–0.3
5.5
V
M1.8
Buck switching node voltage
L1
–0.3
40
V
M1.9
Boost switching node voltage
L2
–0.3
20
V
M1.10
Boot-strap overdrive voltage
BST1-L1, BST2-L2
–0.3
5.5
V
M1.11
Power-good output voltage
PG
-0.3
15
V
M1.12
Ground
PGND, GND
–0.3
0.3
V
M2
Junction temperature, TJ
–40
150
°C
M3
Storage temperature, Tstg
–65
175
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted
7.2 ESD Ratings
VALUE
M4
Human-body model (HBM), per AEC Q100-002
M5.1
V(ESD)
Electrostatic
discharge
M5.2
(1)
Charged-device model (CDM), per AEC
Q100-011
(1)
UNIT
±2000
All pins
±500
Corner pins (1, 10, 11, and 20)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
POS
TPS55165-Q1 with VOS_FB pin connected to
GND
R1.1a
R1.1b
Supply voltage at VINP and VINL pins (after
wake-up)
R1.1c
TPS55165-Q1 with VOS_FB pin connected to
VREG
TPS55160-Q1 and TPS55162-Q1
MIN
MAX
UNIT
2
36
V
4
36
V
3.6
36
V
R1.2a
Output voltage at VOUT and VOUT_SENSE pins
0
12
V
R1.2b
Output voltage at PG pin
0
5
V
R1.3
Input voltage on IGN pin
0
36
V
R1.4
Input voltage on logic pins IGN_PWRL, PS and SS_EN
R1.5a
R1.5b
Input voltage on VOS_FB pin
0
5
V
TPS55165-Q1
0
5
V
TPS55160/2-Q1
0
0.8
V
R2.1
Operating free air temperature, TA
–40
125
℃
R2.2
Operating virtual junction temperature, TJ
–40
150
℃
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7.4 Thermal Information
TPS5516x-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
35.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.8
°C/W
RθJB
Junction-to-board thermal resistance
16.8
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
16.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics — External Components
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
AN.1
PARAMETER
TEST CONDITIONS
Value of output ceramic
capacitor
COUT
AN.1a ESR COUT
Value of ESR of output
capacitor, COUT
AN.2
Value of bootstrap ceramic
capacitor
CBST
AN.2a ESR CBST
Value of ESR of bootstrap
ceramic capacitor, CBST
AN3
Value of inductor
L
Value of DCR of inductor
AN.4
Value of supply input ceramic
capacitor
AN.4a ESR CIN
Value of ESR of input capacitor,
CIN
AN.5
Decoupling capacitor on VREG
pin to ground
CVREG
AN.5a ESR CVREG
(1)
TYP
MAX
18
22
47
µF
100
mΩ
0
ESR < 10 mΩ. Connect between BST1 and
L1 with respect to BST2 and L2
nF
3.3
4.7
0
40-V compliant. Connect between VIN and
PGND
8.2
3.9
Value of ESR of input capacitor,
CVREG
10
mΩ
6.2
µH
40
mΩ
10
µF
0
Connect between VREG and PGND
UNIT
100
0
Saturation current > 2.5 A, ESR < 30 mΩ
AN.3a DCR L
CIN
Connect between VOUT and PGND
MIN
4.7
0
100
mΩ
5.6
µF
10
mΩ
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.6 Electrical Characteristics — Supply Voltage (VINP, VINL pins)
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
1.1a
1.1b
VIN
Operating supply input
voltage
1.1c
Applied at VINP and VINL
pins, after device startup
MIN
TYP
MAX
TPS55165-Q1 with
VOS_FB pin connected to
GND
2
14
36
TPS55165-Q1 with
VOS_FB pin connected to
VREG
4
14
36
3.6
14
36
TPS55160/2-Q1
1.2
VIN_startup
Minimum input voltage
for startup
Applied at VINP and VINL pins; TJ = 25°C. This minimum
voltage is required until VOUT > PGTH_UV;
IVOUT < 400 mA, CVOUT = 22 µF
1.3
ISD
VIN Shutdown supply
current
VIN = 12 V, VIGN= 0 V, VPS= 0 V, VIGN_PWRL = 0 V, TJ =
25°C
(1)
6
UNIT
V
5.3
V
V
3
µA
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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Electrical Characteristics — Supply Voltage (VINP, VINL pins) (continued)
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
1.4
PARAMETER
IQ
TEST CONDITIONS
VIN Quiescent supply
current
MIN
TPS55165-Q1:
VIN = VIGN = 12 V, VOUT = 5 V, IOUT = 0 mA, TJ = 25°C
Device in low-power mode, Non-switching
VOS_FB pin connected to GND
TYP
MAX
0
15
UNIT
µA
7.7 Electrical Characteristics — Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT
Pin)
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.784
0.8
0.816
V
4.9
5
5.1
V
VFB_NM_adj
Feedback voltage in normal mode
for adjustable VOUT setting (2)
TPS55160/2-Q1:
Measured at VOS_FB pin
Resistive divider with total resistance < 1
MΩ connected between VOUT, VOS_FB,
and GND pins
2.1b
VFB_NM_5V
Feedback voltage in normal mode
for VOUT in fixed 5-V setting (2)
TPS55165-Q1:
Measured at VOUT_SENSE pin
VOS_FB pin connected to GND; VOUT pin
connected to VOUT_SENSE
2.1c
VFB_NM_12V
Feedback voltage in normal mode
for VOUT in fixed 12-V setting (2)
TPS55165-Q1:
Measured at VOUT_SENSE pin
VOS_FB pin connected to VREG; VOUT
pin connected to VOUT_SENSE
11.76
12
12.24
V
VFB_PS_adj
Feedback voltage in low-power
mode for adjustable VOUT setting (3)
TPS55160/2-Q1:
Measured at VOS_FB pin
Resistive divider with total resistance < 1
MΩ connected between VOUT, VOS_FB,
and GND pins
0.776
0.8
0.824
V
2.2b
VFB_PS_5V
Feedback voltage in low-power
mode for VOUT in 5-V setting (3)
TPS55165-Q1:
Measured at VOUT_SENSE pin
VOS_FB pin connected to GND; VOUT pin
connected to VOUT_SENSE
4.85
5
5.15
V
2.2c
VFB_PS_12V
Feedback voltage in low-power
mode for VOUT in 12-V setting (3)
TPS55165-Q1:
Measured at VOUT_SENSE pin
VOS_FB pin connected to VREG; VOUT
pin connected to VOUT_SENSE
11.64
12
12.36
V
2.3
VOUT_OL
Adjustable output voltage range
TPS55160/2-Q1:
Measured at VOUT_SENSE pin
5.7
9
V
2.6
RpdVOUT
Pulldown discharge resistance at
VOUT
Device in OFF state, INIT state, or
PRE_RAMP state; VIGN = 0 V, VPS = 0 V,
VIGN_PWRL = 0 V
250
850
Ω
2.1a
2.2a
(1)
(2)
(3)
365
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
VPS= 0 V; Average DC value excluding ripple and load transients for VIN and load current ranges as specified in IVOUT. Inclusive DC line
and load regulation, temperature drift, and long term drift.
VPS= 5 V; Average DC value excluding ripple and load transients for VIN and load current ranges as specified in IVOUT. Inclusive DC line
and load regulation, temperature drift, and long term drift.
7.8 Electrical Characteristics — Buck-Boost
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
(1)
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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Electrical Characteristics — Buck-Boost (continued)
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted)(1)
POS
PARAMETER
TEST CONDITIONS
MIN
6 V ≤ VIN; DCR ≤ 40 mΩ
3.1a
Max output current in
normal operation for
VOUT in 5-V setting
TPS55165-Q1 with
VOS_FB pin
connected to GND
TYP
MAX
1
UNIT
A
3.8 V ≤ VIN ≤ 6 V; DCR ≤ 40 mΩ
800
2.3 V ≤ VIN < 3.8 V; DCR ≤ 40 mΩ
400
2 V ≤ VIN < 2.3 V; DCR ≤ 40 mΩ
200
14 V ≤ VIN; DCR ≤ 40 mΩ
800
9.2 V≤ VIN ≤ 14 V; DCR ≤ 40 mΩ
600
5.6 V≤ VIN < 9.2 V; DCR ≤ 40 mΩ
300
4 V ≤ VIN < 5.6 V; DCR ≤ 40 mΩ
150
3.2a
(VOUT + 2V) ≤ VIN; DCR ≤ 40 mΩ
800
3.2b
0.76 * VOUT ≤ VIN ≤ (VOUT + 2V);
DCR ≤ 40 mΩ
600
mA
0.46 * VOUT ≤ VIN < 0.76 * VOUT;
DCR ≤ 40 mΩ
300
mA
3.6 V ≤ VIN < 0.46 * VOUT; DCR ≤
40 mΩ
150
mA
(VOUT + 1V) ≤ VIN; DCR ≤ 40 mΩ
800
0.76 * VOUT ≤ VIN < (VOUT + 1V);
DCR ≤ 40 mΩ
600
3.6 V ≤ VIN < 0.76 * VOUT; DCR ≤
40 mΩ
300
3.1b
3.1c
IOUT_5V
3.1d
3.1e
3.1f
3.1g
IOUT_12V
Max output current in
normal operation for
VOUT in 12-V setting
3.1h
3.2c
IOUT_adj_VoutH
Max output current in
normal operation for
adjustable
configuration, 8V <
VOUT ≤ 9V
TPS55165-Q1 with
VOS_FB pin
connected to
VREG
TPS55160-Q1 and
TPS55162-Q1,
8V < VOUT ≤ 9V
3.2d
3.2e
3.2f
IOUT_adj_VoutL
3.2g
Max output current in
normal operation for
adjustable
configuration, 5.7V ≤
VOUT ≤ 8V
TPS55160-Q1 and
TPS55162-Q1,
5.7V ≤ VOUT ≤ 8V
mA
mA
mA
3.11
IOUT_PS
Max output current in
low-power mode
3.3
Rdson_
On-resistance buckstage high-side (HS)
FET
150
300
mΩ
On-resistance buckstage low-side (LS)
FET
150
300
mΩ
On-resistance booststage HS FET
150
300
mΩ
On-resistance booststage LS FET
150
300
mΩ
3.5
4.5
A
2.8
A
BUCK_HS
3.4
Rdson_
BUCK_LS
3.5
Rdson_
BOOST_HS
3.6
Rdson_
BOOST_LS
50
3.7
ISW_limit
Peak current limit for
HS buck, LS buck, and
LS boost
Device in normal operating mode
3.9
ICoilAvglimit
Average coil current
limit
Device in normal operating mode; L = 4.7 µH
2
3.20a
Transient load step
VTLDSR_5V_100 response for VOUT in
5-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12 V, IOUT = 0.1
A to 0.5 A, TR = TF = 1 µs, COUT = 47 µF
5
3.20b
Transient load step
VTLDSR_5V_500 response for VOUT in
5-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12 V, IOUT = 0.5
A to 1 A, TR = TF = 1 µs, COUT = 47 µF
5
3.21a
VRIPPLE_5V
Output ripple for VOUT
in 5-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to GND; VIN = 12V, IOUT = 1 A,
SS_EN = low
5.5
mVpp
3.21b
VRIPPLE_12V
Output ripple for VOUT
in 12-V setting
TPS55165-Q1: Measured at VOUT_SENSE pin;
VOS_FB pin connected to VREG; VIN = 14V, IOUT = 0.8
A, SS_EN = low
5
mVpp
8
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7.9 Electrical Characteristics — Undervoltage and Overvoltage Lockout
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
4.1a
UVLO
VIN Undervoltage (UV)
lockout threshold
4.1b
VIN voltage decreasing;
Device turned-off when
VIN < UVLO
Device is in normal
operating mode
MIN
UNIT
2
V
TPS55165-Q1 with
VOS_FB pin connected to
VREG
3.6
4
V
1.8
2
V
36
40
V
110%
125%
UVLO
VIN voltage decreasing;
Device turned-off when
VIN < UVLO
Device is in normal
operating mode
4.2
OVLO
VIN Overvoltage (OV)
lockout threshold
VIN voltage increasing; Device stops switching when
VIN > OVLO, and recovers when VIN < OVLO and IGN
=1
Device is in normal operating mode
4.9
VOUT_PROT_OV
VOUT OV protection
Device is in normal operating mode
(1)
MAX
1.8
VIN Undervoltage (UV)
lockout threshold
4.1c
TYP
TPS55165-Q1 with
VOS_FB pin connected to
GND
TPS55160-Q1 and
TPS55162-Q1
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.10 Electrical Characteristics — IGN Wakeup
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
5.1a
PARAMETER
IGNWAKE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IGN wake-up threshold
VIGN voltage increasing to wake-up device
2.5
3.1
3.7
V
VIGN voltage decreasing to power-down
device
1.5
2.1
2.7
V
0.76
1
1.35
V
5.1b
IGNPD
IGN power-down threshold
5.2
IGNHYST
IGN wake-up hysteresis
5.3a
I_IGN36V
IGN pin forward input current
VIGN = 36 V
at 36 V
11
17
30
µA
5.3b
I_IGN12V
IGN pin forward input current
VIGN = 12 V
at 12 V
2.3
3.7
7.1
µA
5.5
I_IGNrev
IGN pin reverse current
370
650
µA
(1)
VIGN = –7 V
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.11 Electrical Characteristics — Logic Pins PS, IGN_PWRL, SS_EN
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
MIN
6.1
VLOGIC_IN_HIGH
Logic input low-to-high
threshold for pins
IGN_PWRL PS, and SS_EN
6.2
VLOGIC_IN_LOW
Logic Input high-to-low
threshold for pins
Device in power-up condition
IGN_PWRL, PS, and SS_EN
6.3
VLOGIC_IN_HYST
Logic input hysteresis for
pins IGN_PWRL, PS, and
SS_EN
6.4
RLOGIC_IN_PD
Pulldown resistance on PS
pin to GND
35
6.5
Ipull-up_SS_EN
Pullup current on SS_EN pin
Ipull-up_IGN_PWRL
Pullup current on
IGN_PWRL pin
6.6
(1)
Device in power-up condition
TYP
MAX
2
Device in power-up condition
UNIT
V
0.74
V
0.39
V
111
kΩ
85
266
µA
1
8
µA
0.15
70
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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7.12 Electrical Characteristics – Overtemperature Protection
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
7.1
TPROT
Overtemperature shutdown
protection threshold
7.2
THYS
Overtemperature shutdown
hysteresis
(1)
TEST CONDITIONS
MIN
TYP
175
MAX
UNIT
210
℃
30
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.13 Electrical Characteristics – Power Good
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
MIN
Deviation from nominal VOUT to assert PG
low, in normal mode
8.1
PGTH_UV
PG threshold undervoltage
8.2
(1)
VPG_LOW
PG output-low voltage
–10%
Deviation from nominal VOUT to assert PG
low, during low power mode to normal mode
transition
Deviation from nominal VOUT to assert PG
low, in low power mode
TYP
MAX
UNIT
–5%
-12%
-20%
-5%
IPGL ≤ 1mA
0.4
V
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.14 Switching Characteristics — Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT
Pin)
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
2.5
(1)
10
tstart_VOUT
PARAMETER
TEST CONDITIONS
VOUT startup time
L = 4.7 µH, COUT = 22 µF; VOUT rising from 10%
to 90% of final value
MIN
TYP
1.5
MAX
UNIT
ms
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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SLVSD46 – NOVEMBER 2017
7.15 Switching Characteristics — Buck-Boost
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.8
tblank_Iswlim
Time until peak current limit is
active
3.11
ƒSW
Switching frequency without
Spread-Spectrum
VIN_max = 27 V
1860 2000
2140
kHz
3.12
ƒSW_SS
Switching frequency with SpreadSpectrum Enabled
VIN_max = 27 V; SS_EN pin not connected to
GND; Device in buck operation
1800 2100
2400
kHz
3.14
ton_Min_Buck
Minimum on time in buck
operation
Device in normal operation mode
55
65
ns
3.15
ton_Max_Boost
Maximum on time in boost
operation
Device in normal operation mode
400
450
ns
3.16
ton_Max_Bst_L
Maximum boost on time in power
save mode
PM
(1)
VIN = 14 V
40
350
70
4
ns
µs
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.16 Switching Characteristics — Undervoltage and Overvoltage Lockout
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
4.3
tdegl_VINUVOV
VIN UV and OV deglitch time
4.8
tdegl_VREGUVOV
VREG UV and OV deglitch time
(1)
TEST CONDITIONS
MIN
TYP
MAX
40
50
60
10
UNIT
µs
µs
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.17 Switching Characteristics — IGN Wakeup
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
5.6
IGN_deg
IGN deglitch filter time
5.7
IGNstartup_time
Time from IGN high till VOUT
crossing 95% of the end-value
(1)
TEST CONDITIONS
MIN
TYP
7.5
MAX
UNIT
22
ms
25
ms
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
7.18 Switching Characteristics — Logic Pins PS, IGN_PWRL, SS_EN
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
256
272
µs
6.7
tDelay_IGN_PWRL
Input Delay time for IGN_PWRL
pin
Delay time betweein the toggling of the
IGN_PWRL pin and the state change of
the signal inside the device
213
6.8a
tDelay_PS_L2H
Input Delay time for PS pin
pulling high
Delay time between pullping the PS high
and the device enters low-power mode
59
136
µs
6.8b
tDelay_PS_H2L
Delay time between releasing the PS pin
Input Delay time for PS pin going
and the device enters normal mode from
low
low-power mode
262
510
µs
(1)
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
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7.19 Switching Characteristics – Power Good
Over operating free air temperature range –40°C ≤ TA ≤ 125°C and maximum junction temperature TJ = 150°C and
recommended operating input supply range (unless otherwise noted) (1)
POS
8.3
PARAMETER
TEST CONDITIONS
PGDeglitch
PG deglitch filter time
PGexttime
PG extension time (rising edge
only)
8.4a
8.4b
8.4c
8.4d
(1)
MIN
TYP
MAX
45
50
55
PG_DLY Shorted to VREG
40
100 kΩ between PG_DLY and GND
30
10 kΩ between PG_DLY and GND
PG_DLY grounded
UNIT
µs
ms
4
ms
0.7
ms
The term VIN refers to the voltage on all supply pins VINP and VINL (unless otherwise noted).
3.5
2.2
3
2.15
Switching Frequency (MHz)
Shutdown Quiescent Current (PA)
7.20 Typical Characteristics
2.5
2
1.5
1
0.5
2.1
2.05
2
1.95
1.9
1.85
0
-50
-25
0
25
50
75
Temperature (qC)
100
125
1.8
-50
150
-25
0
D001
25
50
Temperature (qC)
75
100
125
D002
tps5
VIN = 12 V
Figure 2. Switching Frequency vs Temperature
5.08
5.08
5.06
5.06
Output Voltage (V)
Output Voltage (V)
Figure 1. Shutdown IQ vs Temperature
5.04
5.02
5
VIN = 3.8 V
VIN = 6 V
VIN = 12 V
VIN = 36 V
4.98
5.02
5
IOUT = 0 A
IOUT = 0.3 A
IOUT = 0.5 A
IOUT = 1 A
4.98
4.96
4.96
0
0.2
0.4
0.6
Output Current (A)
0.8
1
D003
Figure 3. 5-V Output Regulation vs Load Current
12
5.04
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0
5
10
15
20
25
Input Voltage (V)
30
35
40
D004
Figure 4. 5-V Output Regulation vs Input Voltage
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12.5
12.5
12.4
12.4
12.3
12.3
12.2
12.2
Output Voltage (V)
Output Voltage (V)
Typical Characteristics (continued)
12.1
12
11.9
11.8
VIN = 4 V
VIN = 5.6 V
VIN = 14 V
VIN = 36 V
11.7
11.6
12.1
12
11.9
11.8
IOUT = 0 A
IOUT = 0.3 A
IOUT = 0.5 A
IOUT = 0.8 A
11.7
11.6
11.5
11.5
0
0.2
0.4
Output Current (A)
0.6
0.8
0
5
D005
Figure 5. 12-V Output Regulation vs Load Current
10
15
20
25
Input Voltage (V)
30
35
40
D006
Figure 6. 12-V Output Regulation vs Input Voltage
L1
L1
VOUT
VOUT
PG_DLY
VIN = 12 V
PG_DLY
VOUT = 5 V
Figure 7. Power-Good Delay When PGDLY Is Grounded
VIN = 12 V
VOUT = 5 V
Figure 8. Power-Good Delay When PGDLY Connects to 100kΩ Resistor
L1
VOUT
L1
VOUT
PG_DLY
IGN
VIN = 12 V
VOUT = 5 V
Figure 9. Power-Good Delay When PGDLY Connects to
VREG
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VIN = 14 V
VOUT = 5 V
IOUT = 0 A
Figure 10. Ignition Shutdown Sequence
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Typical Characteristics (continued)
VOUT
VIN
VOUT
PS
L1
L1
L2
L2
VIN = 12 V
VOUT = 5 V
IOUT = 50 mA
4 V ≤ VIN ≤ 12 V
Figure 11. Low-Power Mode Enabling
VOUT = 5 V
IOUT = 0.5 A
Figure 12. Step-Up to Step-Down Mode Transition
1.2
VIN
Load Current Derating (A)
1
VOUT
L1
L2
0.8
0.6
0.4
0.2
IOUT = 5 V
IOUT = 12 V
0
0
4 V ≤ VIN ≤ 8 V
VOUT = 5 V
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10
15
20
25
Input Voltage (V)
30
35
40
D007
IOUT = 0.5 A
Figure 13. Step-Down to Step-Up Mode Transition
14
5
Figure 14. Load Current Derating vs Input Voltage
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8 Detailed Description
8.1 Overview
The control circuit of the TPS5516x-Q1 buck-boost converter is based on an average current-mode topology.
The control circuit also uses input and output voltage feedforward. Changes of input and output voltage are
monitored and the duty cycle in the modulator is immediately adapted to achieve a fast response to those
changes. The voltage error amplifier gets its feedback input from the VOS_FB pin. The feedback voltage is
compared with the internal reference voltage to generate a stable and accurate output voltage.
The buck-boost converter uses four internal N-channel MOSFETs to maintain synchronous power conversion at
all possible operating conditions. This feature enables the device to keep high efficiency over a wide input
voltage and output power range. To avoid ground shift problems caused by the high currents in the switches,
separate ground pins (GND and PGND) are used. The reference for all control functions are the GND pins. The
power switches are connected to the PGND pins. Both grounds must be connected on the PCB at only one point
which is ideally close to the GND pin. Because of the 4-switch topology, the load is always disconnected from the
input during shutdown of the converter.
To drive the high-side switches of the buck and the boost power stages, the buck-boost converter requires
external boot-strapping ceramic capacitors with low ESR. These bootstrap capacitors are charged by the VREG
supply. The VREG supply requires a low-ESR ceramic capacitor for loop stabilization, and must not be loaded by
the external application. The VREG supply is also used to drive the low-side switches of the buck and boost
power stages. At device start-up, the VREG pin is supplied by the input voltage. When the buck-boost output
voltage is greater than its power-good threshold (the PG pin is high), the VREG pin is supplied by the output
voltage to reduce power dissipation.
The device can be enabled with the IGN pin, and, when enabled, the device has a power-latch function which
can be selected with the IGN_PWRL pin. This function allows an external MCU to keep TPS5516s-Q1 device on
even after the IGN pin goes low.
For the TPS55160-Q1 and TPS55165-Q1 devices, the operation mode of the buck-boost converter can be
selected through the PS pin. When the PS pin is low, the buck-boost operates in normal mode with a constant
fixed switching frequency. When the PS pin is high, the buck-boost operates in low-power mode with pulsefrequency modulation.
The TPS55160-Q1 and TPS55165-Q1 devices also have a frequency spread-spectrum option that can be
enabled or disabled through the SS_EN pin.
The output voltage of the TPS55165-Q1 device is selected as a fixed 5 V or fixed 12 V through the VOS_FB pin.
The TPS55160-Q1 and TPS55162-Q1 devices have an adjustable output voltage from 5.7 V to 9 V through an
external feedback network.
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8.2 Functional Block Diagram
VIN
VINP
VINL
VOUT
BST1
VVREG
Current
Sense
VVREG
VOUT
BST2
L2
L1
Buck-Boost
Overlap Control
VVREG
VVREG
PGND
IGN
IGN_PWRL
VINL
VOUT
VREG
UVLO and
OVLO
Device Type?
VOUT_SENSE
Power Up and
Shutdown Logic
Thermal
Shutdown
PS
SS_EN
+
Low-Power
Mode select
VOS_FB
Device Type?
± FBint
Vref
SpreadSpectrum Select
GND
Output
Voltage
Select
VOUT_SENSE
VINL
Power
Select
VREG
Gate-Driver
Supply
VREG_Q
Power-Good
Comparator
Internal Vref
Reference
PG
Delay
Filter
GND
GND
FBint
TPS55160-Q1
TPS55162-Q1
TPS55165-Q1
PG_DLY
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8.3 Feature Description
8.3.1 Spread-Spectrum Feature
The TPS55160-Q1 and TPS55165-Q1 devices have a spread-spectrum feature to modulate the switching
frequency through a pseudo-random algorithm.
This spread-spectrum feature is enabled and disabled through the SS_EN pin. When the SS_EN pin is
unconnected, the spread-spectrum feature is enabled. The SS_EN pin is internally pulled up with a pullup current
between 100 µA and 200 µA. When the SS_EN pin is connected to ground, the spread-spectrum feature is
disabled.
This feature can only be enabled when the device is in normal mode with step-down operation. This feature
cannot be enabled in low-power mode.
8.3.2 Overcurrent Protection
The buck-boost regulator has two ways of protecting against overcurrent conditions. When the buck-boost is in
regulation (essentially the output voltage is at the target voltage), the average current limit provides the protection
against overcurrent conditions. When the average current limit is activated (essentially the maximum inductor
average current is reached), the output voltage gradually decreases, but the control loop tries to maintain the
target output voltage. So when the overcurrent condition clears before the buck-boost control circuit gets too far
out of regulation, the output voltage gradually reaches its target voltage level again.
The buck-boost regulator limits the peak-overcurrent in the power MOSFETs. When such a peak-overcurrent
event occurs, the buck-boost regulator shuts down and restarts after 5.5 µs. If three peak-overcurrent events
occur, and the time between each of these peak-overcurrent events is less than 10 ╦s, the device goes into the
PRE_RAMP state and a 12-ms time-out is started. The device restarts and goes from the PRE_RAMP state to
the RAMP state after this 12-ms time-out expires and the IGN pin is high.
When the device operates in low-power mode, both the average current limit and the peak-current limit protection
functions are disabled.
8.3.3 Overtemperature Protection
The internal Power-MOSFETs are protected against excess power dissipation with junction overtemperature
protection. In case of a detected overtemperature condition, the TPS55165-Q1 device goes to the PRE_RAMP
state (the buck-boost regulator is switched off and the VREG supply is enabled) and a 12-ms time-out is started
when the overtemperature condition is cleared. The device restarts in the PRE_RAMP state after this 12-ms
time-out expires, the overtemperature condition disappeared, and the IGN pin is high.
When the device operates in low-power mode, this overtemperature protection function is disabled.
8.3.4 Undervoltage Lockout and Minimum Start-Up Voltage
The TPS55165-Q1 device has an undervoltage lockout (UVLO) function. When the device operates in normal
mode (the PS pin is low), this UVLO function puts the device in the OFF state when the input voltage is less than
the UVLO threshold. The device restarts when the IGN pin is high and the input voltage is greater than or equal
to the minimum input voltage for startup, which must be maintained until the output voltage is greater than the
PG undervoltage threshold.
When the device operates in low-power mode, this UVLO function is disabled.
8.3.5 Overvoltage Lockout
The TPS55165-Q1 device has an overvoltage lockout (OVLO) function. When the input voltage is greater than
the OVLO threshold while the device operates in normal mode (the PS pin is low), this OVLO function puts the
device in the PRE_RAMP state (the buck-boost regulator is switched off and the VREG supply is enabled), and a
12-ms time-out starts. The device restarts in the PRE_RAMP state after this 12-ms time-out expires, the input
voltage is less than the OVLO threshold, and the IGN pin is high.
When the device operates in low-power mode, this OVLO function is disabled.
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Feature Description (continued)
8.3.6 VOUT Overvoltage Protection
When the device operates in normal mode (the PS pin is low) and the output voltage is greater than or equal to
the VOUT overvoltage protection, the device goes to the PRE_RAMP state (the buck-boost regulator is switchedoff and the VREG supply is enabled) and a 12-ms time-out starts when the output voltage is less than the VOUT
overvoltage protection. The device restarts in the PRE_RAMP state after this 12-ms time-out expires, the output
voltage is less than the VOUT overvoltage protection, and the IGN pin is high.
When the device operates in low-power mode, this VOUT overvoltage protection function is disabled.
8.3.7 Power-Good Pin
The power-good (PG) pin is a low-side FET open-drain output which is released as soon as the output voltage is
greater than the PG undervoltage threshold (essentially the output voltage is rising) and the extension time
(PGexttime) is expired. The intended usage of this pin is to release the reset of an external MCU. Therefore, the
logic-input signals (IGN_PWRL and PS) are considered to be valid only when the PG pin reaches the high level.
When the output voltage is less than the PG undervoltage threshold (essentially the output voltage is falling) for a
time longer than the PG deglitch filter time, the PG pin is pulled low. When the PG pin is low, the level of the PS
and IGN_PWRL pins is interpreted as low, regardless of the actual level. The device goes to the OFF state if the
IGN pin is low under this condition. For more information on the behavior of the PG pin for rising and falling
output voltage, see Figure 16 through Figure 20.
The PG pin is operational in low-power mode. The PG extension time can be configured by connecting the
PG_DLY pin to the VREG pin, the GND pin, or through an external resistor with a value from 10 kΩ to 100 kΩ to
the GND pin. The extension time is as follows for the listed configurations:
• When the PG_DLY pin is shorted to the VREG pin, the typical PG extension time is 40 ms.
• When the PG_DLY pin is connected to the GND pin, the typical PG extension time is 0.6 ms.
• When the external resistor between the PG_DLY and GND pins has a value of 10 kΩ, the typical PG
extension time is 3 ms.
• When the external resistor between pin the PG_DLY and GND pins has a value of 100 kΩ, the typical PG
extension time is 30 ms.
8.4 Device Functional Modes
8.4.1 State Diagram
Figure 15 shows the state diagram.
18
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PRE_RAMP
we
-Po
Pre
r-Go
ff C
od O
itio
ond
n
‡ 95(* HQDEOHG
‡ %XFN-boost disabled
‡ .HHSV FRXQW RI 5$03 WR
PRE_RAMP
ND
nA D
itio
N
ond s A
p C expire MP
am
A
e-R e-out RE_R times
t Pr
No ms tim P to P rs < 5
12- AM
ccu
no
If R
sitio
ion
tran
ndit
Co
mp
-Ra
Pre
VOUT (normal mode) > VOUT_ABSMAX
RAMP
INIT
‡ 95(* HQDEOHG
‡ 926 SLQ VWDWH VDPSOHG DQG
latched
‡ 66_EN pin state sampled
and latched
‡ %XFN-Boost ramping up
OFF
NPOR
‡ 'HYLFH GLVDEOHG
Not Pre-Power-Good
Off condition AND
VREG > VREG_UV
AND
EEPROM Load
Complete
al
IGN_CLR
Po
o
Off C
nditio
Not Pre-Power-Good
Off Condition AND
Not Pre-Ramp
Condition AND
PG = High
n
Good
ower-
o
Off C
nditio
n
Pre-P
n or
nditio n
io
ff Co
al O p Condit
m
r
No -Ram
Pre
‡ &OHDUV ,*1 VLJQDO
Low-Power Off
Condition
Pre-Power-Good Off Condition: IGN = Low OR VINL < VIN_startup OR VREG > VREG_OV
Normal Off Condition: (IGN = Low AND IGN_PWRL= Low) OR VINL < UVLO OR VREG > VREG_OV
Low-Power Off Condition: IGN = Low AND IGN_PWRL = Low AND PS = Low
Pre-Ramp Condition: VREG < VREG_UV OR Overtemperature Shutdown OR IOUT > ISW_limit OR VINL > OVLO OR VOUT (normal mode) > VOUT_PROT_OV
Valid IGN_PWRL: IGN_PWRL= High AND PG = High AND PG pin is not pulled down
Valid PS: PS = High AND PG = High AND PG pin is not pulled down
(IGN = High or Valid IGN_PWRL)
AND Not Valid PS
Pre-
ood
wer-G
NORMAL MODE
‡ 95(* HQDEOHG
‡ %XFN-boost enabled in
normal mode
(IGN = High or Valid IGN_PWRL)
AND Valid PS
w
ay
s
Not Pre-Power-Good
off condition
‡ /RDGLQJ ((3520
‡ %XFN-boost disabled
‡ 95(* HQDEOHG
LOW-POWER MODE
‡ 95(* HQDEOHG
‡ %XFN-boost enabled in lowpower mode
Note:
•
The 12-ms time-out from the PRE_RAMP state to the RAMP state starts only when all conditions for going to the RAMP state are satisfied. As soon as one of these
conditions is violated, the 12-ms time-out is reset.
•
The oscillator is turned off in low-power mode. The oscillator is turned back on upon detecting a negative edge on the PS pin, or a negative edge on the PG pin
which requires the device to go out of low-power mode and enter normal mode again.
Figure 15. State Diagram
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8.4.2 Modes of Operation
The operational mode of the buck-boost converter is selected through the PS pin. When the PS pin is low, the
buck-boost operates in normal mode with a constant fixed switching frequency. When the PS pin is high, the
buck-boost operates in low-power mode with pulse-frequency modulation.
8.4.2.1 Normal Mode
To regulate the output voltage at all possible input voltage conditions, the buck-boost converter automatically
switches from step-down operation to boost operation and back as required by the configuration. The regulator
always uses one active switch, one rectifying switch, one always-on switch, and one always-off switch.
Therefore, the regulator operates as a step-down converter (buck) when the input voltage is higher than the
output voltage, and as a boost converter when the input voltage is lower than the output voltage. In normal
mode, no mode of operation is available in which all four switches are permanently switching. Controlling the
switches in this way allows the converter to maintain high efficiency at the most important point of operation;
when the input voltage is close to the output voltage. The RMS current through the switches and the inductor is
kept at a minimum to minimize switching and conduction losses. For the remaining two switches, one is kept
permanently on and the other is kept permanently off which causes no switching losses.
In normal mode, the converter operates in full continuous mode at a fixed switching frequency of 2 MHz (typical)
for the entire load-current range, even with no load at the output. No pulse-skipping should occur for supply
voltages from 2 V to 27 V.
8.4.2.2 Low-Power Mode
When the buck-boost converter is in low-power mode, the output voltage is monitored with a comparator with its
threshold at the regulation target voltage. When the buck-boost regulator goes to low-power mode, the converter
temporary stops operating and the output voltage drops. The slope of the output voltage depends on the load
and output capacitance. As the output voltage decreases to less than the regulation target voltage, the device
ramps up the output voltage again by giving one or several pulses until the output voltage exceeds the regulation
target voltage. In low-power mode, the buck-boost operates in 4-switch mode, which allows regulation at the
target output voltage regardless of whether the input voltage is greater than or less than the target output voltage
value.
After the device enters low-power mode, the internal oscillator is turned off. As a result of the oscillator being
turned off, all signal deglitching functions are disabled while the device is in low-power mode. These functions
include the VIN and VREG OV and UV signal deglitch functions, and the IGN input signal deglitch function.
20
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8.4.3 Power-Up and Power-Down Sequences
Figure 16 shows the power-up and power-down sequence without the usage of the IGN_PWRL pin.
IGN
Deglitch time
7.5 ms (min) to 22 ms (max)
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN_PWRL
PS
tDelay_PS_L2H
tDelay_PS_H2L
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
VOUTTstart
2 ms (typ)
PG
PGexttime
2 ms (typ)
PGdeglitch
PGdeglitch
Load
EEPROM
Operation Mode
OFF
A.
INIT
RAMP
NORMAL
MODE
LOW-POWER
MODE
NORMAL MODE
OFF
The actual ramp-down time of the output voltage depends on external load conditions.
Figure 16. Power-Up and Power-Down Sequence With Normal Mode and Low-Power Mode, Without
Usage of IGN_PWRL
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Figure 17 shows the power-up and power-down sequence with usage of the IGN_PWRL pin.
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN
tDelay_IGN_PWRL
IGN_PWRL
tDelay_PS_L2H
PS
tDelay_IGN_PWRL
tDelay_PS_H2L
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
PGexttime
VOUTTstart 2 ms (typ)
2 ms (typ)
PG
PGdeglitch
PGdeglitch
Load
EEPROM
Operation Mode
OFF
A.
INIT
RAMP
NORMAL MODE
LOW-POWER
MODE
NORMAL MODE
OFF
The actual ramp-down time of the output voltage depends on external load conditions.
Figure 17. Power-Up and Power-Down Sequence With Normal Mode and Low-Power Mode, With Usage
of IGN_PWRL
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Figure 18 shows a power-up and power-down sequence in low-Power mode with the IGN pin low. Figure 18
shows that after the device is powered on in the OFF state, the device is in low-power mode when the PS pin is
high regardless of what was applied on the IGN and IGN_PWRL input pins.
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN
tDelay_IGN_PWRL
IGN_PWRL
tDelay_IGN_PWRL
tDelay_PS_H2L
tDelay_PS_L2H
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
VOUTTstart
2 ms (typ)
PG
PGexttime
2 ms (typ)
PGdeglitch
PGdeglitch
Operation Mode
OFF
A.
Load
EEPROM
INIT
RAMP
NORMAL MODE
LOW-POWER
MODE
OFF
The actual ramp-down time of the output voltage depends on external load conditions.
Figure 18. Power-Up and Power-Down Sequence With Low-Power Mode When IGN and IGN_PWRLare
low (Essentially When the ECU is in Sleep or Standby mode)
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Figure 19 shows that when the device starts in the OFF state, the buck-boost converter always enters normal
mode first, even when the PS pin was previously set high. The device can only enter low-power mode when the
PG output pin is set high. Figure 19 also shows that the device does not start-up as long as the IGN pin is low.
IGN
Deglitch time
7.5 ms (min) to 22 ms (max)
tDelay_IGN_PWRL
IGN_PWRL
tDelay_IGN_PWRL
tDelay_PS_L2H
PS
tDelay_PS_H2L
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
VOUTTstart
2 ms (typ)
PG
PGexttime
2 ms (typ)
PGdeglitch
PGdeglitch
Operation Mode
Load
EEPROM
OFF
A.
Note:
INIT
RAMP
NORMAL
MODE
LOW-POWER MODE
OFF
The actual ramp-down time of the output voltage depends on external load conditions.
The buck-boost converter always enters normal mode first after ramp up before it can enter low-power mode.
Figure 19. Power-Up Behavior With PS Pin Previously Set High
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Figure 20 shows that the device only can start-up in the OFF state when the IGN pin is high. Setting the
IGN_PWRL pin before the IGN pin is high does not start-up the device. Figure 20 also shows that the
IGN_PWRL signal is only valid after the PG pin is high and the PGDeglitch time has elapsed.
Deglitch time
7.5 ms (min) to 22 ms (max)
IGN
tDelay_IGN_PWRL
IGN_PWRL
tDelay_IGN_PWRL
PS
VREG
VREG = 4.5 V (typ)
VREG_UV level
(minimum 3.7 V)
VOUT
5V
VOUT_PG level
(4.55 to 4.75 V)
See Note A
VOUTTstart
2 ms (typ)
PG
PGexttime
2 ms (typ)
PGdeglitch
PGdeglitch
Operation Mode
Load
EEPROM
OFF
A.
Note:
INIT
RAMP
NORMAL MODE
OFF
The actual ramp-down time of the output voltage depends on external load conditions.
The device does not start-up until the IGN pin is high. The IGN power-latch is only be set after the PG pin is high.
Figure 20. Power-Up Behavior With IGN_PWRL Set High Prior to High IGN
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8.4.4 Soft-Start Feature
On power up, the device has a soft-start feature which ramps the output of the regulator at a steady slew rate.
The soft-start ramp time is 0.5 ms by default. When the device pulls the PG pin low because of a VOUT
undervoltage condition while the device is in normal mode, the device stays in normal mode and tries to get to
the VOUT level again without soft-start slew-ramp control.
8.4.5 Pulldown Resistor on VOUT
When the buck-boost regulator is disabled (in the OFF state, INIT state, and PRE_RAMP state), an internal
active pulldown circuit (specified as RpdVOUT in the Electrical Characteristics — Reference Voltage (VOS_FB Pin)
and Output Voltage (VOUT Pin) table) pulls down the VOUT pin.
8.4.6 Output Voltage Selection
The configuration of the output voltage is selectable through the VOS_FB pin.
The fixed output voltage of the TPS55165-Q1 device is 5 V when the VOS_FB pin is connected to ground and is
12 V when the VOS_FB pin is connected to the VREG pin. For the TPS55165-Q1 device in the 5-V configuration
(VOS_FB pin connected to ground), the UVLO threshold is set to less than 2 V. When the TPS55165-Q1 device
is in the 12-V configuration (VOS_FB pin connected to the VREG pin), the UVLO threshold is set to less than 3.6
V. For the TPS55162-Q1 device, the UVLO threshold is also set to less than 3.6 V.
For the adjustable output voltage of the TPS55160-Q1 and TPS55162-Q1 devices, connect the VOS_FB pin to
the external feedback network. The total resistance of this external feedback network must be less than 1 MΩ
(essentially, this value must be similar to or less than the implemented total resistance of the implemented
internal feedback network for the 12 V setting).
26
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS5516x-Q1 family of devices is a high-voltage synchronous buck-boost DC-DC converter with all four
power MOSFETs integrated. Each device in the device family can produce a well-regulated output voltage from a
widely-varying input voltage source such as an automotive car battery. If the input voltage is higher than the
output voltage, the TPS5516x-Q1 device operates in step-down mode. If the input voltage is lower than the
output, the device operates in step-up mode. If the input voltage is equal or close to the output voltage, the
device operates between the step-down and step-up mode. The buck-boost overlap control ensures automatic
and smooth transition between step-down and step-up (This is ok. Step-up and step-down modes were
mentioned in the first page of the spec)modes with optimal efficiency. The output voltage of the TPS55165-Q1
device can be set to a fixed level of 5 V or 12 V. The output voltage of the TPS55160-Q1 and TPS55162-Q1
devices is programmable from 5.7 V to 9 V.
9.1.1 Application Circuits for Output Voltage Configurations
Figure 21 and Figure 22 show the application diagrams for the adjustable output configuration.
4.7 µH
0.1 µF
2 V ” VIN ” 36 V
0.1 µF
BST1 L1
L2
VINP
BST2
5.7 V ” VOUT ” 9 V
VOUT
10 µF
22 µF
VOUT_SENSE
VINL
100 k
R1
100 nF
ON
IGN_PWRL
OFF
PG
VOS_FB
Power
Latch
IGN
LowPower
Mode
R2
ON
SS_EN
PS
OFF
VREG
VREG_Q
PGND
GND
PG_DLY
TPS55160-Q1
4.7 µF
RDLY
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Figure 21. TPS55160-Q1 Application Diagram for Adjustable Output Voltage
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Application Information (continued)
4.7 µH
0.1 µF
2 V ” VIN ” 36 V
0.1 µF
BST1 L1
L2
VINP
BST2
5.7 V ” VOUT ” 9 V
VOUT
10 µF
VOUT_SENSE
VINL
22 µF
100 k
R1
100 nF
ON
IGN_PWRL
OFF
PG
VOS_FB
Power
Latch
IGN
R2
VREG
VREG_Q
PGND
GND
PG_DLY
TPS55162-Q1
4.7 µF
RDLY
Copyright © 2017, Texas Instruments Incorporated
Figure 22. TPS55162-Q1 Application Diagram for Adjustable Output Voltage
Use Equation 1 to calculate the output voltage.
R1 R2
VOUT
u VFB
R2
where
•
28
VFB is 0.8 V (see Electrical Characteristics — Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT
Pin)).
(1)
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Application Information (continued)
Figure 23 shows the TPS55165-Q1 device in the 5-V configuration.
4.7 µH
0.1 µF
2 V ” VIN ” 36 V
0.1 µF
BST1 L1
L2
VINP
VOUT = 5 V
1 A at VIN t 5.3 V
0.8 A at VIN t 3.8 V
0.4 A at VIN t 2.3 V
BST2
VOUT
10 µF
22 µF
VINL
100 k
PG
ON
IGN_PWRL
VOUT_SENSE
OFF
SS_EN
Power
Latch
IGN
100 nF
ON
OFF
VOS_FB
LowPower
Mode
PS
VREG
VREG_Q
PGND
GND
PG_DLY
TPS55165-Q1
4.7 µF
RDLY
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Figure 23. TPS55165-Q1 Application Diagram for 5-V Voltage
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Application Information (continued)
Figure 24 shows the TPS55165-Q1 device in the 12-V configuration.
4.7 µH
0.1 µF
0.1 µF
5-V Supply
2 V ” VIN ” 36 V
BST1 L1
L2
BST2
100 k
VINP
10 µF
PG
VINL
VOUT = 12 V
VOUT
22 µF
ON
IGN_PWRL
VOUT_SENSE
OFF
SS_EN
Power
Latch
IGN
LowPower
Mode
PS
VOS_FB
PGND
VREG
VREG_Q
100 nF
ON
OFF
GND
PG_DLY
TPS55165-Q1
4.7 µF
RDLY
Copyright © 2017, Texas Instruments Incorporated
Figure 24. TPS55165-Q1 Application Diagram for 12-V Voltage
CAUTION
For TPS55165-Q1 in 12-V configuration (VOS_FB is shorted to VREG), the PG pin
must be tied to an external 5-V supply through a pullup resistor. Tying the PG pin to a
supply greater than 5.5 V could damage the device in the unlikely event of a shortage
between the PG pin and the adjacent VOS_FB pin, which is tied to the VREG pin in
the 12-V output configuration. The absolute-maximum voltage rating of the VREG pin
is 5.5 V.
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9.2 Typical Application
The TPS5516x-Q1 family of devices requires a minimum number of external components to implement a buckboost converter. Figure 25 shows the typical schematic for the TPS55165-Q1 device in the 5-V configuration.
L
CBST1
0.1 µF
2 V ” VIN ” 36 V
CIN
20 µF
CINP
0.1 µF
CBST2
0.1 µF
BST1 L1
L2
VINP
VOUT = 5 V
1 A at VIN t 5.3 V
0.8 A at VIN t 3.8 V
0.4 A at VIN t 2.3 V
BST2
VOUT
COUT
22 µF
RPG
100 k
VINL
CINL
0.47 µF
PG
VOUT_SENSE
ON
CVOSN
0.1 µF
IGN_PWRL
OFF
Power
Latch
Low
Power
Mode
ON
SS_EN
IGN
OFF
VOS_FB
PS
VREG
VREG_Q
PGND
GND
PG_DLY
TPS55165-Q1
RDLY
CVREG
4.7 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 25. TPS55165-Q1 Buck-Boost Converter for Fixed 5-V Output
9.2.1 Design Requirements
Table 1 lists the design requirements for Figure 25.
Table 1. Design Requirements
PARAMETER
VALUE
VIN_MIN
The least input voltage after startup.
The IOUT_MAX load current deratings listed in this table apply for VIN < 5.3 V.
VIN_startup
The minimum input voltage required for startup.
VIN_MAX
The greatest input voltage after startup.
36 V
VOUT
The output voltage.
5V
> 5.3 V
The maximum output current at VIN ≥ 5.3 V
IOUT_MAX
2V
1A
The maximum output current at 3.8 V ≤ VIN < 5.3 V
0.8 A
The maximum output current at 2.3 V ≤ VIN < 3.8 V
0.4 A
9.2.2 Detailed Design Procedure
9.2.2.1 Power-Circuit Selections: CIN, L, COUT
The TPS5516x-Q1 family of devices integrates not only the power switches but also the loop compensation
network as well as many other control circuits which reduces the number of required external components. For
the internal loop compensation to be effective, the selection of the external power circuits (power inductor and
capacitor) must be confined. TI strongly recommends users selecting the component values as follows: 3.3-µH to
6.2-µH power inductor, 18-µF to 47-µF output capacitor, and 8.2-µF or greater input capacitor. Because the
TPS5516x-Q1 device switches at about 2 MHz, a shielded inductor and X5R-type or X7R-type ceramic
capacitors should be used for the power circuit.
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Considering the component tolerance, the following power component values were selected for this design
example:
• CIN = 20 µF
• COUT = 22 µF
• L = 4.7 µH
For the input capacitor (CIN), the voltage rating should be greater than the maximum input voltage (VIN_MAX).
Therefore, two, 10-µF X7R capacitors rated for 50 V were selected for this design example. Adding a small, highfrequency decoupling ceramic capacitor (CVINP with a value of 100 nF typical) in parallel with the input capacitor
is recommended to better filter out the switching noises at the VINP pin. Adding another decoupling ceramic
capacitor (CVINL with a value of 470 nF typical) is also recommended for the VINL pin.
The output capacitor (COUT), receives a voltage of 5 V. Considering some voltage-rating margin, two 10-µF X7R
capacitors rater for 10 V or greater and one, 2.2-µF X7R-type capacitor rated for 10 V or greater in parallel were
selected for the output capacitor. Adding a small, high-frequency decoupling ceramic capacitor (CVOSN with a
value of 100 nF typical) in parallel with the output capacitor is recommended to better filter out the switching
noises at the VOUT_SENSE pin.
The power inductor (L) should be a shielded type, and it should not saturate during operation. The inductor
should also be able to support the power dissipation under the maximum load. Use the calculations in the
following sections to find the required current capabilities for the inductor.
9.2.2.1.1 Inductor Current in Step-Down Mode
Use Equation 2 to calculate inductor peak-ripple current in the step-down, or buck, mode (Ipk_buck).
1 VOUT 1 Dbuck
Ipk _ buck
u
u
2
L
fS
where
•
•
•
•
Dbuck
VOUT is the output voltage.
L is the value of the inductor.
Dbuck is the duty cycle (refer to Equation 3).
fS is the switching frequency.
(2)
VOUT
VIN
(3)
The maximum peak-ripple current of the inductor (Ipk) occurs when the duty cycle is at the minimum value,
specifically when the input voltage (VIN) is at the maximum value which yields the value shown in Equation 4.
5V
Dbuck
0.139
36 V
(4)
Substitute the values for fS, L, and Dbuck, in Equation 2 to find the peak-ripple current as shown in Equation 5.
1
5V
1 0.139
Ipk _ buck
u
u
0.458 A
2 4.7 PH 2 MHz
(5)
The power dissipations can be determined by the RMS current of the inductor. Use Equation 6 to calculate the
RMS current of the inductor in buck mode (Irms_buck).
Irms _ buck
2
IOUT
1
u Ipk _ buck 2
3
1 A2
1
u 0.458 A2
3
1.1 A
(6)
Use Equation 7 to calculate the approximate power dissipation of the inductor in buck-mode (Ploss_L_buck).
2
Irms
_ buck u Rdc
(7)
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Ploss _ L _ buck
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9.2.2.1.2 Inductor Current in Step-Up Mode
Use Equation 8 to calculate the inductor peak-ripple current in the step-up, or boost, mode (Ipk_boost).
1 VIN Dboost
Ipk _ boost
u
u
2 L
fsw
where
•
Dboost
Dboost is the duty cycle in boost mode (refer to Equation 9).
(8)
VOUT VIN
VVOUT
(9)
In general, the maximum peak-ripple current occurs at 50% duty cycle. In this example, because of the power
derating versus the input voltage, a few calculations can find that the maximum RMS current occurs when the
input voltage is approximately 3.8 V, of which the load current is 0.8 A, according to Table 1. Equation 10 and
Equation 11 show the peak-ripple current under this condition.
5 V 3.8 V
Dboost
0.240
5V
(10)
1 3.8 V 0.240
Ipk _ boost
u
u
0.049 A
2 4.7 PH 2 MHz
(11)
The power dissipations can be determined by the RMS current of the inductor. Use Equation 12 to calculate the
RMS current of the inductor in buck mode (Irms_boost).
Irms _ boost
§ IOUT ·
¨
¸
© 1 Dboost ¹
2
1
u Ipk _ boost 2
3
§ 0.8 A ·
¨ 1 0.24 ¸
©
¹
2
1
u 0.049 A 2
3
1.053 A
(12)
Use Equation 13 to calculate the approximate power dissipation of the inductor in boost-mode (Ploss_L_boost).
Ploss _ L _ boost
2
Irms
_ boost u R dc
(13)
9.2.2.1.3 Inductor Current in Buck-Boost Overlap Mode
When input voltage is very close to the output voltage, the device operates in buck-boost overlap mode, and the
L1 and L2 pins are switched alternatively in consecutive cycles. The small voltage difference between the input
and output voltage leads to a small amount of ripple current through the inductor. Therefore, the total inductor
current is essentially the load current with small ripples superimposed onto it, and the RMS current is
approximately the same as the load current, which is 1 A.
Ploss _ L _ buckboost
Io2 u Rdc
(14)
9.2.2.1.4 Inductor Peak Current
Because the TPS5516x-Q1 device has internal peak current limit (ISW_limit) of 4.5 A (maximum), this current
should be considered when selecting the power inductor. Select the inductor of the saturation current (ISAT) with
a minimum value of 4.5 A so that the inductor never gets saturated. TI recommends using a shielded inductor.
9.2.2.1.5
Inductor Peak Current
For this design example, select an AEC-Q200 Grade 0, shielded inductor with the following characteristics:
• Is a surface-mount device (SMD)
• Has an inductance of 4.7 µH
• Supports a saturation current (ISAT) of 4.8 A
• Is rated for an RMS current (Irms) of 1.5 A or larger
• Is rated for a DC load (Rdc) of 0.04 Ω or smaller
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9.2.2.2 Control-Circuit Selections
9.2.2.2.1 Bootstrap Capacitors
The bootstrap capacitors (CBST1 and CBST2) supply the internal high-side MOSFET driver. TI recommends using
a 0.1-µF, X7R-type ceramic capacitor rated for 15 V or larger for the bootstrap capacitors.
9.2.2.2.2 VOUT-Sense Bypass Capacitor
To improve noise immunity, connect a 0.1-µF, X7R-type ceramic capacitor rated for 25 V or greater to the VOUT
pin.
9.2.2.2.3 VREG Bypass Capacitor
The VREG supplies the internal control circuit as well as the drivers for the integrated low-side driver. To improve
noise immunity and stabilize the internal VREG regulator, TI recommends connecting a 4.7-µF, X7R-type
ceramic capacitor rated for 25 V or greater between the VREG and GND pins.
9.2.2.2.4 PG Pullup Resistor and Delay Time
The power-good indicator pin (PG) is an open-drain output pin. The PG pin requires an external pullup resistor to
flag the power-good status. For this design example, select a 100-kΩ resistor to pull up the PG pin from the
output rail.
The PG_DLY pin sets the delay time for the PG status to flip. Follow the instructions listed in the Power-Good
Pin to program the delay.
9.2.3 Application Curves
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
36-V Supply Voltage
18-V Supply Voltage
12-V Supply Voltage
5-V Supply Voltage
3-V Supply Voltage
20%
10%
0%
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Load Current (A)
0.8
0.9
1
Figure 26. Efficiency vs Load
VIN = 12 V
IOUT step change from 0.25 A to 0.75 A
Figure 28. Step Load Response
34
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VIN = 12 V
IOUT = 1 A
Figure 27. Start-Up Procedure
IOUT = 0.5 A
VIN transient rom 12 V to 4 V
Figure 29. Battery-Voltage Cranking Response
Copyright © 2017, Texas Instruments Incorporated
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SLVSD46 – NOVEMBER 2017
10 Power Supply Recommendations
The TPS5516x-Q1 family of devices is a power-management device. The power supply for the device is any DCvoltage source within the specified input range. The supply should also be capable of supplying sufficient current
based on the maximum inductor current in boost-mode operation. When connecting to the power supply and
load, try to use short and solid wires. Twisting the pair of wires for the input and output helps minimize the line
impedance and avoid adversary interference with the circuit operation.
11 Layout
11.1 Layout Guidelines
The layout of the printed-circuit board (PCB) is critical to achieve low EMI and stable power-supply operation as
well as optimal efficiency. Make the high frequency current loops as small as possible, and follow these
guidelines of good layout practices;
• The TPS5516x-Q1 family of devices is a high-frequency switching converter. Because the four switch
MOSFETs are integrated, the device should be located at the center of the DC-DC power stage. Separate the
power ground and analog ground such that the control circuit can be connected to the relatively quieter
analog ground without being contaminated by the noisy power ground. Use the PGND pin, GND pin, and the
device PowerPAD as the single-point connection between the analog and power grounds.
• Identify the high-frequency switched AC-current loops. In step-down mode, the AC current loop is along the
path of the input capacitor (CIN), L1 pin, internal buck-switch leg, and PGND pin, and closes at the input
capacitor. In step-up mode, the AC current loop is along the path of the output capacitor (COUT), L2 pin,
internal boost-switch leg, and PGND pin, and closes at the output capacitor. These two AC-current loops are
both involved in buck-boost overlap mode.
• Optimize component placement and orientation before routing any traces. Place the input and output filter
capacitors, the device, and the power inductor close together such that the AC-current loops are short, direct,
and the spatial areas enclosed by the loops are minimized. Make the power flow in a straight path rather than
a zigzag path on the board.
• Place the high frequency decoupling ceramic capacitors for the input and output as close as possible to the
device with the main input and output ceramic capacitors placed next to the high-frequency capacitors. This
placement helps confine the high switching noises within a very small area around the device.
• Place the VREG decoupling capacitor close to the VREG pin because it serves as the supply to the internal
low-side MOSFETs drivers. Because the VREG pin receives power from the output rail, the ground lead of
the VREG decoupling capacitor should connect directly to the COUT ground to improve device noise immunity.
NOTE
The VREG_Q pin must always connect to the VREG pin. Both pins should have a Kelvin
connection to the decoupling capacitor.
•
•
•
•
•
Place the bootstrap capacitors (CBST1 and CBST2) close to the device with short and direct traces to connect to
the corresponding device pins becuase these capacitors serve as the supplies to the internal high-side
MOSFETs drivers
Place the VOUT_SENSE decoupling capacitor (CVOSN) close to the device. Give the placement of this
capacitor priority over the main output capacitors.
For TPS55160-Q1 or TPS55162-Q1, place the sense-resistor divider for the output voltage close to the
device.
Use eight to nine via holes with a 0.3 mm diameter in the device PowerPAD to help dissipate heat through
the layers of the ground plane. Additional vias holes around the device PowerPAD can further enhance heat
dissipation.
Use at least ten via holes with a 0.3 mm diameter around the input and output capacitors that are connected
to ground-plane layers to minimize the PCB impedance for power current flows.
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11.2 Layout Example
Figure 30. Example Circuit Layout
36
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SLVSD46 – NOVEMBER 2017
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
TPS55160-Q1 PSpice Transient Model
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, TPS5516xQ1-EVM Evaluation Module for 1-A Single- Inductor Buck-Boost-Converter user's
guide
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS55160-Q1
Click here
Click here
Click here
Click here
Click here
TPS55162-Q1
Click here
Click here
Click here
Click here
Click here
TPS55165-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS55160QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55160
TPS55160QPWPTQ1
ACTIVE
HTSSOP
PWP
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55160
TPS55162QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55162
TPS55162QPWPTQ1
ACTIVE
HTSSOP
PWP
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55162
TPS55165QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55165
TPS55165QPWPTQ1
ACTIVE
HTSSOP
PWP
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS55165
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS55160QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
7.1
1.6
8.0
16.0
Q1
TPS55160QPWPTQ1
HTSSOP
PWP
20
250
180.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS55162QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS55162QPWPTQ1
HTSSOP
PWP
20
250
180.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS55165QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TPS55165QPWPTQ1
HTSSOP
PWP
20
250
180.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS55160QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS55160QPWPTQ1
HTSSOP
PWP
20
250
213.0
191.0
55.0
TPS55162QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS55162QPWPTQ1
HTSSOP
PWP
20
250
213.0
191.0
55.0
TPS55165QPWPRQ1
HTSSOP
PWP
20
2000
350.0
350.0
43.0
TPS55165QPWPTQ1
HTSSOP
PWP
20
250
213.0
191.0
55.0
Pack Materials-Page 2
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