Texas Instruments | TPS25927x 4.5-V to 18-V eFuse with Blocking FET Control (Rev. E) | Datasheet | Texas Instruments TPS25927x 4.5-V to 18-V eFuse with Blocking FET Control (Rev. E) Datasheet

Texas Instruments TPS25927x 4.5-V to 18-V eFuse with Blocking FET Control (Rev. E) Datasheet
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TPS259270, TPS259271
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TPS25927x 4.5-V to 18-V eFuse with Blocking FET Control
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TPS25927x family of eFuses is a highly
integrated circuit protection and power management
solution in a tiny package. The devices use few
external components and provide multiple protection
modes. They are a robust defense against overloads,
shorts circuits, excessive inrush current, and reverse
current.
1
•
•
4.5-V to 18-V Protection
Integrated 28-mΩ Pass MOSFET
Absolute Maximum Voltage of 20 V
1-A to 5-A Adjustable ILIMIT
±8% ILIMIT Accuracy at 3.7A
Reverse Current Blocking Support
Programmable OUT Slew Rate, UVLO
Built-in Thermal Shutdown
UL 2367 Recognized – File No. E339631*
– *RILIM ≤ 130 kΩ (5 A maximum)
Safe During Single Point Failure Test (UL60950)
Small Foot Print – 10L (3 mm x 3 mm) VSON
2 Applications
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•
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HDD and SSD Drives
Set Top Boxes
Servers / AUX Supplies
Fan Control
PCI/PCIe Cards
Adapter Powered Devices
PART NUMBER
TPS259270
TPS259271
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Transient: Output Short Circuit
OUT
VIN
Many systems, such as SSDs, must not allow holdup
capacitance energy to dump back through the FET
body diode onto a drooping or shorted input bus. The
BFET pin is for such systems. An external NFET can
be connected “Back to Back (B2B)” with the
TPS25927x output and the gate driven by BFET to
prevent current flow from load to source.
Device Information(1)
Application Schematic
VIN
Current limit level can be set with a single external
resistor. Applications with particular voltage ramp
requirements can set dV/dT pin with a single
capacitor to ensure proper output ramp rates.
OUT
28m:
R1
COUT
R2
CdVdT
EN/UVLO
BFET
dV/dT
ILIM
GND
RLIM
TPS25927x
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS259270, TPS259271
SLVSCU8E – AUGUST 2015 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9
Power Supply Recommendations...................... 22
9.1 Transient Protection ................................................ 22
9.2 Output Short-Circuit Measurements ....................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Revision D (January 2017) to Revision E
•
Page
Deleted Over Voltage from the Function Block Diagram ...................................................................................................... 1
Changes from Revision C (September 2017) to Revision D
•
Page
Changed status of TPS259270 from Preview to Active in the Table 1 .................................................................................. 3
Changes from Revision B (September 2016) to Revision C
•
Page
Added Transient junction temperature to Absolute Maximum Ratings table ......................................................................... 4
Changes from Revision A (August 2015) to Revision B
•
Page
Added section:Controlled Power Down using TPS25927x ................................................................................................. 20
Changes from Original (August 2015) to Revision A
•
2
Page
Changed from Product Preview to Production Data............................................................................................................... 1
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Product Folder Links: TPS259270 TPS259271
TPS259270, TPS259271
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SLVSCU8E – AUGUST 2015 – REVISED NOVEMBER 2017
Table 1. Device Comparison Table
PART NUMBER
UV
OV CLAMP
FAULT RESPONSE
STATUS
TPS259271
4.3 V
—
Auto-retry
Active
TPS259270
4.3 V
—
Latched
Active
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
dV/dT 1
EN/UVLO
VIN
VIN
GND
VIN 5
10 ILIM
BFET
OUT
OUT
6 OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
9
O
Connect this pin to the gate of a blocking NFET. See the Feature Description
section. This pin can be left floating if it is not used
1
O
Connect a capacitor from this pin to GND to control the ramp rate of OUT at
device turnon
2
I
GND
Thermal
Pad
—
GND
ILIM
10
O
A resistor from this pin to GND sets the overload and short circuit limit
OUT
6-8
O
Output of the device
VIN
3-5
I
Input supply voltage
BFET
dV/dT
EN/UVL
O
This is a dual function control pin. When used as an ENABLE pin and pulled
down, it shuts off the internal pass MOSFET and pulls BFET to GND. When
pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via
external resistor divider
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Product Folder Links: TPS259270 TPS259271
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
VIN
(1) (2)
Supply voltage (1)
VIN (10 ms Transient)
OUT
MAX
20
–0.3
V
–1.2
V
–0.3
7
EN/UVLO
–0.3
7
–0.3
7
Voltage
BFET
Tstg
(1)
(2)
V
VIN + 0.3
ILIM
dV/dT
UNIT
22
Output voltage
OUT (Transient < 1 µs)
MIN
–0.3
V
–0.3
30
Transient junction temperature
–65
TSHDN
°C
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
6.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
BFET
dV/dT, EN/UVLO
Input voltage
ILIM
IOUT
Continuous output current
ILIM
Resistance
OUT
dV/dT
External capacitance
TYP
MAX
UNIT
4.5
18 (1)
0
VIN+6
0
6
0
3
0
5
A
V
10
100
162
kΩ
0.1
1
1000
µF
1
1000
nF
TJ
Operating junction temperature
–40
25
125
°C
TA
Operating Ambient temperature
–40
25
85
°C
(1)
4
Maximum voltage (including input transients) at VIN pin must not exceed absolute maximum rating as specified in the Absolute
Maximum Ratings table.
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SLVSCU8E – AUGUST 2015 – REVISED NOVEMBER 2017
6.4 Thermal Information (1)
over operating free-air temperature range (unless otherwise noted)
TPS25927x
THERMAL METRIC
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJCtop
Junction-to-case (top) thermal resistance
45.9
°C/W
53
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
21.2
°C/W
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
21.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
5.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.3
4.45
V
0.42
0.55
mA
0.13
0.225
mA
V
VIN (INPUT SUPPLY)
VUVR
UVLO threshold, rising
VUVhyst
UVLO hysteresis (1)
IQON
IQOFF
4.15
5%
Enabled: EN/UVLO = 2 V
Supply current
0.3
EN/UVLO = 0 V
EN/UVLO (ENABLE/UVLO INPUT)
VENR
EN threshold voltage, rising
1.37
1.4
1.44
VENF
EN threshold voltage, falling
1.32
1.35
1.39
V
IEN
EN Input leakage current
–100
0
100
nA
0 V ≤ VEN ≤ 5 V
dV/dT (OUTPUT RAMP CONTROL)
IdVdT
dV/dT charging current (1)
VdVdT = 0 V
RdVdT_disch
dV/dT discharging resistance
EN/UVLO = 0 V, IdVdT = 10 mA sinking
VdVdTmax
dV/dT Max capacitor voltage (1)
GAINdVdT
dV/dT to OUT gain (1)
220
50
73
nA
100
Ω
5.5
V
ΔVdVdT
4.85
V/V
10
µA
RILIM = 10 kΩ, VVIN – OUT = 1 V
1.02
ILIM (CURRENT LIMIT PROGRAMMING)
ILIM bias current (1)
IILIM
IOL
Overload current limit (2)
RILIM = 45.3 kΩ, VVIN – OUT = 1 V
1.79
2.10
2.42
RILIM = 100 kΩ, VVIN – OUT = 1 V
3.46
3.75
4.03
RILIM = 150 kΩ, VVIN – OUT = 1 V
4.5
5.1
5.7
A
IOL-R-Short
RILIM = 0 Ω, shorted resistor current limit (single point failure
test: UL60950) (1)
0.84
A
IOL-R-Open
RILIM = OPEN, open resistor current limit (single point failure
test: UL60950) (1)
0.73
A
RILIM = 10 kΩ, VVIN – OUT = 12 V
Short-circuit current limit (2)
ISCL
1.66
1.98
2.37
RILIM = 100 kΩ, VVIN – OUT = 12 V
2.90
3.32
3.85
RILIM = 150 kΩ, VVIN – OUT = 12 V
3.7
4.5
5.5
RATIOFASTRIP
Fast-trip comparator level w.r.t.
overload current limit (1)
IFASTRIP : IOL
VOpenILIM
ILIM open resistor detect
threshold (1)
VILIM Rising, RILIM = OPEN
(1)
(2)
1
RILIM = 45.3 kΩ, VVIN – OUT = 12 V
A
160%
3.1
V
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
21
28
37
39
48
UNIT
OUT (PASS FET OUTPUT)
RDS(on)
TJ = 25°C
FET ON resistance
IOUT-OFF-LKG
IOUT-OFF-SINK
TJ = 125°C
OUT Bias current in off state
VEN/UVLO = 0 V, VOUT = 0 V (sourcing)
–5
0
1.2
VEN/UVLO = 0 V, VOUT = 300 mV (sinking)
10
15
20
mΩ
µA
BFET (BLOCKING FET GATE DRIVER)
BFET charging current (1)
IBFET
VBFETmax
BFET clamp voltage (1)
RBFETdisch
BFET discharging resistance to
GND
VBFET = VOUT
VEN/UVLO = 0 V, IBFET = 100 mA
15
2
µA
VVIN +
6.4
V
26
36
Ω
TSD (THERMAL SHUT DOWN)
TSHDN
TSD threshold, rising (1)
TSHDNhyst
TSD hysteresis (1)
Thermal fault: latched or auto-retry
150
°C
10
°C
TPS259270
Latched
TPS259271
Auto-retry
6.6 Timing Requirements
PARAMETER
Turnon delay (1)
TON
tOFFdly
Turnoff delay
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at
OUT
220
µs
EN↓ to BFET↓, CBFET = 0
0.4
µs
dV/dT (OUTPUT RAMP CONTROL)
tdVdT
Output ramp time
EN/UVLO → H to OUT = 11.7 V, CdVdT = 0
EN/UVLO → H to OUT = 11.7 V, CdVdT = 1 nF (1)
0.7
1
12
1.3
ms
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly
Fast-trip comparator delay (1)
IOUT > IFASTRIP to IOUT = 0 (Switch off)
300
EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF
4.2
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF
42
EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF
0.4
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF
1.4
TPS259271 only
100
ns
BFET (BLOCKING FET GATE DRIVER)
tBFET-ON
BFET turnon duration (1)
tBFET-OFF
BFET Turnoff duration (1)
ms
µs
Thermal Shutdown (TSD)
tTSDdly
(1)
6
Retry delay after TSD recovery,
TJ < [TSHDN – 10°C] (1)
µs
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.7 Typical Characteristics
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
4.35
0.25
0.2
4.25
IQ-OFF (mA)
Input UVLO (Rising, Falling) (V)
4.3
4.2
4.15
0.15
0.1
4.1
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
0.05
4.05
4
0
-50
0
50
100
150
Temperature (ƒC)
0
5
Figure 1. Input UVLO vs Temperature
15
20
C002
Figure 2. IQ-OFF vs VIN
250
0.6
0.5
230
0.4
TON (Ps)
IVIN-ON (mA)
10
VIN (V)
C001
0.3
0.2
125 °C
85 °C
25 °C
-40 °C
0.1
0
0
5
10
15
VIN (V)
210
190
170
20
150
-50
C003
0
50
100
150
Temperature (oC)
Figure 3. IVIN-ON vs VIN
Figure 4. TON vs Temperature
230
150
225
TdVdT (ms)
IdVdT (nA)
100
220
215
50
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
210
205
0
-50
0
50
100
Temperature (ƒC)
150
0
2
C010
Figure 5. IdVdT vs Temperature
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4
6
8
CdVdT (nF)
10
C013
Figure 6. TdVdT vs CdVdT
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
1.41
100
1.39
10
Rising
1.38
IEN (nA)
VEN-VIH VEN-VIL (V)
1.4
Falling
1.37
125qC
85qC
25qC
-40qC
1
1.36
1.35
1.34
-50
0
50
100
0.1
150
0
o
Temperature ( C)
2
3
4
5
VEN (V)
Figure 7. VEN-VIH, VEN-VIL vs Temperature
D016
Figure 8. IEN (Leakage Current) vs VEN
45
2.2
40
2
1.8
35
IVOUT (A)
RDSON (m:)
1
30
1.6
1.4
125qC
85qC
25qC
-40qC
25
1.2
20
-50
0
50
100
1
150
0
Temperature (oC)
0.5
1
VVIN-OUT (V)
1.5
2
D029
RILIM = 45.3 kΩ
Figure 9. RDSON vs Temperature
Figure 10. IVOUT vs VVIN-OUT
6
1
5
-1
-2
IVOUT (A)
IOL, ISC (% Normalized)
0
IOL-45.3k
ISC-45.3k
-3
4
3
-4
125qC
85qC
25qC
-40qC
2
-5
-6
-50
0
50
100
150
1
0
0.5
Temperature (oC)
RILIM = 45.3 kΩ
1.5
2
D027
RILIM = 150 kΩ
Figure 11. IOL, ISC vs Temperature
8
1
VVIN-OUT (V)
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Figure 12. IVOUT vs VVIN-OUT
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
2
4
3.5
-2
-4
3
IVOUT (A)
IOL, ISC (% Normalized)
0
-6
IOL-150k
ISC-150k
-8
-10
2.5
2
125qC
85qC
25qC
-40qC
-12
1.5
-14
-16
-50
0
50
Temperature
100
1
150
0
0.5
(oC)
RILIM = 150 kΩ
1
VVIN-OUT (V)
1.5
2
D028
RILIM = 100 kΩ
Figure 13. IOL, ISC vs Temperature
Figure 14. IVOUT vs VVIN-OUT
2
0.95
0.9
-2
IOL-R-SHORT (A)
IOL, ISC (% Normalized)
0
-4
IOL-100k
ISC-100k
-6
0.85
-8
0.8
-10
-12
-50
0
50
Temperature
100
0.75
-50
150
0
(oC)
RILIM = 100 kΩ
50
Temperature (oC)
100
150
D001
RILIM = 0 Ω
Figure 15. IOL, ISC vs Temperature
Figure 16. IOL-R-Short vs Temperature
4
0.8
Overload Current Limit (A)
IOL-R-OPEN (A)
3.5
0.75
0.7
3
2.5
2
1.5
1
0.5
0.65
-50
0
0
50
Temperature (oC)
100
150
0
20
D001
40
60
80
RILIM Resistor (k:)
100
120
D001
RILIM = OPEN
Figure 17. IOL-R-Open vs Temperature
Figure 18. Overload Current Limit vs RILIM Resistor
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Typical Characteristics (continued)
Accuracy (Process, Voltage, Temperature) (%)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
ILIM Open Detect Threshold (V)
3.1
3.09
3.08
3.07
3.06
3.05
-50
0
50
Temperature
100
150
35
30
25
20
15
10
5
0
1
1.5
2
(oC)
2.5
3
3.5
4
Overload Current Limit (A)
4.5
5
5.5
D001
Figure 20. Accuracy vs Overload Current Limit
Figure 19. VOpenILIM vs Temperature
Thermal Shutdown Time (ms)
10000
C1
C2
EN
VIN
1000
100
C2
C2
10
1
C3
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
0.1
0.1
VOUT
I_IN
C4
1
10
Power Dissipation (W)
100
D001
TPS25927x, CdVdT = OPEN, COUT = 4.7 μF
Figure 21. Thermal Shutdown Time vs Power Dissipation
Figure 22. Transient: Output Ramp
EN
C1
C2
EN
C1
C2
VIN
VOUT
C2
C2
C3
VOUT
C3
I_OUT
I_IN
C4
C4
TPS25927x, VIN = 18 V, CdVdT = OPEN, COUT = 10 μF
Figure 23. Transient: Output Ramp
10
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Figure 24. Transient: Turnoff Delay
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
VIN
EN
C1
C2
VOUT
VOUT
C1
C2
BFET
BFET
C3
C3
C2
C2
EN ↓
VIN ↓
Figure 25. Turnoff Delay to BFET
Figure 26. Turnoff Delay to BFET
Figure 27. Transient: Output Short Circuit
Figure 28. Short Circuit (Zoom): Fast-Trip Comparator
EN
EN
VIN
C1
C2
C1
C2
VIN
VOUT
C2
C2
C3
C3
I_IN
C4
C4
VOUT
I_IN
TPS259271
TPS259271
Figure 29. Transient: Recovery from Short Circuit-Over
Current
Figure 30. Transient: Wake Up to Short Circuit
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
EN
C1
C2
VIN
VOUT
C2
C3
I_IN
C4
TPS259271
ILOAD Stepped from 50% to 120%, Back to 50%
Figure 31. Transient: Overload Current Limit
Figure 32. Transient: Thermal Fault Auto-Retry
TPS259270, VIN = 5 V
Figure 33. Transient: Thermal Fault Latched
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7 Detailed Description
7.1 Overview
The TPS25927x is an e-fuse with integrated power switch that is used to manage current, voltage and start-up
voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds
the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables
the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and allow current to
flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has
the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current, ensuring that the
adjustable overload current limit IOL is not exceeded. The device also has built-in thermal sensor. In the event
device temperature (TJ) exceeds TSHDN, typically 150°C, the thermal shutdown circuitry shuts down the internal
MOSFET thereby disconnecting the load from the supply. In TPS259270, the output remains disconnected
(MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then high). The
TPS259271 device remains off during a cooling period until device temperature falls below TSHDN – 10°C, after
which it attempts to restart. This ON and OFF cycle continues until fault is cleared.
7.2 Functional Block Diagram
VIN
3,
4,
5
+
UVLO
4.3 V
4.08 V
EN/
UVLO
2 mA
EN
1.4 V
1.35 V
SWEN
Thermal
Shutdown
6V
OUT
28 mW
Charge
Pump
+
2
Current
Sense
6,
7,
8
9
BFET
10
ILIM
SWEN
GATE
CONTROL
22 W
TSD
6V
VIN
220 nA
10 mA
+
ILIMIT
dV/dT
4.8x
1
+
+
70 pF
GND
EP
80 W
SWEN
Fast Trip
Comp
1.6*ILIMIT
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7.3 Feature Description
7.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
7.3.2 VIN
Input voltage to the TPS25927x. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 18 V for
TPS25927x. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device is going to be in over-voltage protection (OVP) mode, limiting
the output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN – VOVC) × IOUT, which can
potentially heat up the device and cause thermal shutdown.
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Feature Description (continued)
7.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate
at start-up is shown in Equation 1:
dVOUT IdVdT ´ GAINdVdT
=
dt
CdVdT + CINT
where
•
•
•
IdVdT = 220 nA (Typical)
CINT = 70 pF (Typical)
GAINdVdT = 4.85
dVOUT
= Desired output slew rate
dT
(1)
The total ramp time (TdVdT) for 0 to VIN can be calculated using Equation 2:
TdVdT = 106 ´ VIN ´ (CdVdT + 70 pF )
(2)
For details on how to select an appropriate charging time/rate, refer to the applications section Setting Output
Voltage Ramp Time (TdVdT).
7.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either input UVLO (VUVR) event or EN/UVLO (see
Table 2). BFET can source charging current of 2 µA (typical) and sink (discharge) current from the gate of the
external FET via a 26-Ω internal discharge resistor to initiate fast turnoff, typically <1 µs. Due to 2-µA charging
current, it is recommended to use >10 MΩ impedance when probing the BFET node.
Table 2. BFET
EN/UVLO > VENR
VIN>VUVR
BFET MODE
H
H
Charge
X
L
Discharge
L
X
Discharge
7.3.5 EN/UVLO
As an input pin, it controls both the ON and OFF state of the internal MOSFET and that of the external blocking
FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low
on this pin turns off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS259270 by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turnoff of the BFET driver, thereby stopping the flow of reverse current. For applications
where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO to GND.
7.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit). as shown in
Equation 3:
(
)
(3)
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IOL = 0.7 + 3 ´ 10-5 ´ RILIM
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When power dissipation in the internal MOSFET [PD = (VVIN – VOUT) × IOUT] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature. See Figure 34.
0
Foldback (ISC - IOL)/IOL (%)
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
Power (W)
40
50
60
Figure 34. Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS25927x
incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed overload current limit (IFASTRIP = 1.6 × IOL). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see Figure 35 and
Figure 36).
Figure 35. Fast-Trip Current
Figure 36. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
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7.4 Device Functional Modes
The TPS25927x is a hot-swap controller with integrated power switch that is used to manage current, voltage
and start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When
VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on
this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if connected) via
the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected) starts conducting
and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF), the internal
MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to OUT. User
also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and
GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current, ensuring
that the adjustable overload current limit IOL is not exceeded. This keeps the output device safe from harmful
current transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds
TSHDN , typically 150°C, the thermal shutdown circuitry shuts down the internal MOSFET thereby disconnecting
the load from the supply. In the TPS259270, the output remains disconnected (MOSFET open) until power to
device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259271 device remains off during
a cooling period until device temperature falls below TSHDN – 10°C, after which it attempts to restart. This ON and
OFF cycle continues until fault is cleared.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA25927x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This
section presents a simplified discussion of the design process.
8.2 Typical Application
8.2.1 Simple 2.1-A eFuse Protection for Set Top Boxes
VIN = 4.5 to 18 V
IN
*
CVIN
0.1µF
R1
1MO
VOUT, IOUT < 1.7A
OUT
COUT
1µF
28mO
EN/UVLO
**
BFET
R2
dVdT
GND
ILIM
TPS25927x
RILIM
45.3kO
**Optional & only needed for external UVLO
*Optional & only for noise suppression
Figure 37. Typical Application Schematic: Simple e-Fuse for STBs
8.2.1.1 Design Requirements
Table 3 shows the design parameters for this application.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range, VIN
12 V
Undervoltage lockout set point, V(UV)
Default: VUVR = 4.3 V
Load at start-up, RL(SU)
8Ω
Current limit, IOL = IILIM
2.1 A
Load capacitance, COUT
1 µF
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Typical Application (continued)
Table 3. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Maximum ambient temperature, TA
85°C
8.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25927x.
8.2.1.2.1 Step by Step Design Procedure
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
8.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4:
I
- 0.7
RILIM = ILIM
3 x 10-5
(4)
For IOL = IILIM = 2.1 A, from Equation 4, RILIM = 45.3 kΩ, choose closest standard value resistor with 1%
tolerance.
8.2.1.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5:
R + R2
V(UV) = 1
´ VENR
R2
(5)
Where VENR = 1.4 V is enable voltage rising threshold.
Since R1 and R2 leak the current from input supply (VIN), these resistors must be selected based on the
acceptable leakage current from input power supply (VIN). The current drawn by R1 and R2 from the power
supply {IR12 = VIN/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6:
V(PFAIL) = 0.96 x VUVR
(6)
Where VUVR is 4.3 V, Power fail threshold set is : 4.1 V.
8.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:
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8.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS25927x, the inrush current is determined using Equation 7:
I(INRUSH) = C(OUT) x
V(IN)
TdVdT
(7)
Power dissipation during start-up is given by Equation 8:
PD(INRUSH) = 0.5 x V(IN) x I(INRUSH)
(8)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
8.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
When load draws current during the turnon sequence, there is additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given
by Equation 9:
V 2(IN)
æ 1ö
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU)
(9)
Total power dissipated in the device during startup is given by Equation 10:
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(10)
Total current during start-up is given by Equation 11:
I(STARTUP) = I(INRUSH) + IL (t)
(11)
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by
Equation 12:
é
æ
öù
ç
ê
÷÷÷ú
çç I
ê
ú
÷
ç
ê IOL
(INRUSH) ÷÷ú
÷ú
- 1 + LNççç
TdVdT(Current-Limited) = COUT x RL(SU) x ê
÷
÷
V
ç
êI
(IN) ÷÷ú
ç
ê (INRUSH)
÷÷ú
çççIOL - R
ê
÷øú
L(SU)
è
ë
û
(12)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 38.
Thermal Shutdown Time (ms)
10000
1000
100
10
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1
0.1
0.1
1
10
Power Dissipation (W)
100
D001
Figure 38. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2 we
get Equation 13:
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TdVdT = 106 x 12 x (0 + 70 pF ) = 840 ms
(13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by
Equation 14:
I(INRUSH) = 1 mF x
12
= 15 mA
840 ms
(14)
The inrush power dissipation is calculated, using Equation 8 as shown in Equation 15:
PD(INRUSH) = 0.5 x 12 x 15 m = 90 mW
(15)
For 90 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 38 at TA =
85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any
load on output.
Considering the start-up with load 8 Ω, the additional power dissipation, when load is present during start-up is
calculated, using Equation 9 we get Equation 16:
PD(LOAD) =
12 x 12
=3W
6 ´ 8
(16)
The total device power dissipation during start-up is given by Equation 17:
PD(STARTUP) = 3 + 90 m = 3.09 W
(17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 3.09 W is more than 100 ms. So
it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 8 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.
8.2.1.2.5 Support Component Selection—CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.
8.2.1.3 Application Curves
Figure 39. Output Ramp without Load on Output
Figure 40. Output Ramp with 4-Ω Load at Start-Up
8.2.2 Controlled Power Down using TPS25927x
When the device is disabled, the output voltage is left floating and power down profile is entirely dictated by the
load. In some applications, this can lead to undesired activity as the load is not powered down to a defined state.
Controlled output discharge can ensure the load is turned off completely and not in an undefined operational
state. The BFET pin in TPS25927x family of eFuses facilitates Quick Output Discharge (QOD) function as
illustrated in Figure 41 . When the device is/gets disabled, the BFET pin pulls low which enables the external PMOSFET Q1 for discharge feature to function. The output voltage discharge rate is dictated by the output
capacitor COUT, the discharge resistance RDCHG and the load.
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OUT
VIN
VIN
C*IN
VOUT
28m:
R1
RDCHG
EN/UVLO
BFET
Q1
ZXM61P03F
dVdT
R2
COUT
ILIM
GND
CdVdT
TPS25927x
RILIM
*Optional & only for noise suppression
Figure 41. Circuit Implementation with Quick Output Discharge Function
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9 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
9.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 18:
VSPIKE(Absolute) = V(IN) + I(LOAD) x
L(IN)
C(IN)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(18)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 42.
VIN
IN
*
CVIN
0.1µF
R1
VOUT
OUT
28mO
COUT
EN/UVLO
*
R2
dVdT
*
BFET
CdVdT
GND
*Optional components for
transient suppression
ILIM
TPS25927x
RILIM
Figure 42. Circuit Implementation with Optional Protection Components
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9.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 43 for a PCB layout example.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
Locate all support components: RILIM, CdVdT and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the RILIM and CdVdT components to the device must be as short as possible to reduce parasitic effects on the
current limit and soft start timing. These traces must not have any coupling to switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
10.2 Layout Example
Top layer
Bottom layer signal ground plane
Via to signal ground plane
dV/dT
1
10 ILIM
EN/UVLO
2
9
BFET
VIN
3
8
OUT
VIN
4
7
OUT
5
6
VIN
OUT
Ground Bottom
layer
VIN
VOUT
*
*
VIN
High Frequency
Bypass Capacitor
Power Ground
* Optional: Needed only to suppress the transients caused by inductive load switching
Figure 43. Layout Example
24
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: TPS259270 TPS259271
TPS259270, TPS259271
www.ti.com
SLVSCU8E – AUGUST 2015 – REVISED NOVEMBER 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For the TPS259270 PSpice Transient Model, see SLVMB88
For the TPS259271 PSpice Transient Model, see SLVMB91
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
TPS2592xx Design Calculator
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS259270
Click here
Click here
Click here
Click here
Click here
TPS259271
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: TPS259270 TPS259271
Submit Documentation Feedback
25
TPS259270, TPS259271
SLVSCU8E – AUGUST 2015 – REVISED NOVEMBER 2017
www.ti.com
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: TPS259270 TPS259271
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS259270DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259270
TPS259270DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259270
TPS259271DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259271
TPS259271DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259271
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS259270DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259270DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259270DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259270DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259271DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259271DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259271DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS259271DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS259270DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS259270DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS259270DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS259270DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS259271DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS259271DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS259271DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS259271DRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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