Texas Instruments | UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller (Rev. D) | Datasheet | Texas Instruments UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller (Rev. D) Datasheet

Texas Instruments UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller (Rev. D) Datasheet
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UCC28019A
SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The UCC28019A 8-pin active Power Factor
Correction (PFC) controller uses the boost topology
operating in Continuous Conduction Mode (CCM).
The controller is suitable for systems in the 100 W to
>2 kW range over a wide-range universal ac line
input. Start-up current during undervoltage lockout is
less than 200 μA. The user can control low power
standby mode by pulling the VSENSE pin below
0.77 V.
1
8-Pin Solution Reduces External Components
Wide-Range Universal AC Input Voltage
Fixed 65-kHz Operating Frequency
Maximum Duty Cycle of 98% (typ.)
Output Over/Undervoltage Protection
Input Brown-Out Protection
Cycle-by-Cycle Peak Current Limiting
Open Loop Detection
Low-Power User-Controlled Standby Mode
2 Applications
•
•
•
•
•
CCM Boost Power Factor Correction Power
Converters in the 100 W to >2 kW Range
Digital TV
Home Electronics
White Goods and Industrial Electronics
Server and Desktop Power Supplies
Low-distortion wave shaping of the input current
using average current mode control is achieved
without input line sensing, reducing the external
component count. Simple external networks allow for
flexible compensation of the current and voltage
control loops. The switching frequency is internally
fixed and trimmed to better than ±5% accuracy at
25°C. Fast 1.5-A peak gate current drives the
external switch.
Numerous system-level protection features include
peak current limit, soft over-current, open-loop
detection,
input
brown-out,
and
output
over/undervoltage. Soft-start limits boost current
during start-up. A trimmed internal reference provides
accurate protection thresholds and a regulation setpoint. An internal clamp limits the gate drive voltage
to 12.5 V.
Device Information(1)
PART NUMBER
UCC28019A
PACKAGE
BODY SIZE (NOM)
SOIC (8)
3.91 mm × 4.9 mm
PDIP (8)
6.35 mm × 9.81 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VOUT
EMI Filter
LINE
INPUT
–
Bridge
Rectifier
+
1
GND
GATE
8
2
ICOMP
VCC
7
3
ISENSE
VSENSE
6
4
VINS
VCOMP
5
Auxilary
Supply
Rload
UCC28019A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28019A
SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
11
12
19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 21
9
Power Supply Recommendations...................... 40
9.1 Bias Supply ............................................................. 40
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
Changes from Revision C (August 2015) to Revision D
Page
•
Changed VCOMP and ICOMP MAX value from 7 V to 7.5 V. ............................................................................................... 4
•
Added VCOMP and ICOMP note. ......................................................................................................................................... 4
Changes from Revision B (April 2009) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
D, P Package
8-Pin SOIC, 8-Pin PDIP
Top View
GATE
8
2 ICOMP
VCC
7
3 ISENSE
VSENSE 6
VINS
VCOMP 5
1 GND
4
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
SOIC,
PDIP
GND
1
—
Ground: device ground reference.
ICOMP
2
O
Current loop compensation: Transconductance current amplifier output. A capacitor connected to
GND provides compensation and averaging of the current sense signal in the current control loop.
The controller is disabled if the voltage on ICOMP is less than 0.6 V.
I
Inductor current sense: Input for the voltage across the external current sense resistor, which
represents the instantaneous current through the PFC boost inductor. This voltage is averaged by the
current amplifier to eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the
average inductor current. Cycle-by-cycle Peak Current Limit (PCL) immediately shuts off the GATE
drive if the peak-limit voltage is exceeded. An internal 1.5-μA current source pulls ISENSE above 0.1
V to shut down PFC operation if this pin becomes open-circuited. Use a 220-Ω resistor between this
pin and the current sense resistor to limit inrush-surge currents into this pin.
I
Input ac voltage sense: A filtered resistor-divider network connects from this pin to the rectified-mains
node. Input Brown-Out Protection (IBOP) detects when the system ac-input voltage is above a userdefined normal operating level, or below a user-defined “brown-out” level. At startup the controller is
disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft start. The controller is
also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not resume until
both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft start.
O
Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor
network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC,
VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP
is charged until the VSENSE voltage reaches 99% of its nominal regulation level. When Enhanced
Dynamic Response (EDR) is engaged, a higher transconductance is applied to VCOMP to reduce the
charge time for faster transient response. Soft Start is programmed by the capacitance on this pin.
The EDR higher transconductance is inhibited during Soft Start.
I
Output voltage sense: An external resistor-divider network connected from this pin to the PFC output
voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small
capacitor from this pin to GND filters high-frequency noise. Standby mode disables the controller and
discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8 V. An
internal 100-nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin
disconnection. Output Over-Voltage Protection (OVP) disables the GATE output when VSENSE
exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the
output voltage to its normal regulation level when a system line or load step causes VSENSE to fall
below 95% of the reference voltage.
ISENSE
VINS
VCOMP
VSENSE
3
4
5
6
VCC
7
GATE
8
Device supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until
VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off
(UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 μF minimum value should be
connected from VCC to GND as close to the device as possible for high frequency filtering of the
VCC voltage.
O
Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A
sink and 1.5-A source capability. Output voltage is typically clamped at 12.5 V.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range unless otherwise noted. Unless noted, all voltages are with respect to GND.
Currents are positive into and negative out of the specified terminal.
MIN
MAX
UNIT
VCC, GATE
–0.3
22
V
VINS, VSENSE,
–0.3
7
V
VCOMP, ICOMP (2)
–0.3
7.5
V
ISENSE
–24
7
V
Input current range
VSENSE, ISENSE
–1
1
mA
Lead temperature, TSOL
Soldering, 10s
Input voltage range
Junction temperature, TJ
(1)
(2)
300
°C
Operating
–55
150
°C
Storage
–65
150
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
The VCOMP and ICOMP pin can go to 7.5 V ±6% due to internal drive circuitry. Absolute maximum rating is 7 V when an external bias
is applied to the pin, with the source current limited below 50 µA.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC input voltage from a low-impedance source
Operating junction temperature, TJ
MAX
UNIT
VCCOFF + 1 V
21
V
-40
125
°C
6.4 Thermal Information
UCC28019A
THERMAL METRIC (1)
P (PDIP)
D (SOIC)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
52.8
113.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
61.5
°C/W
RθJB
Junction-to-board thermal resistance
30.0
53.2
°C/W
ψJT
Junction-to-top characterization parameter
19.5
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.9
52.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Unless otherwise noted, VCC=15 VDC, 0.1 μF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VCC Bias Supply
ICCPRESTART
ICC pre-start current
VCC = VCCON – 0.1 V
25
100
200
μA
ICCSTBY
ICC standby current
VSENSE = 0.5 V
1
2.2
2.9
mA
ICCON_load
ICC operating current
VSENSE = 4.5 V, CGATE = 4.7 nF
4
7.5
10
mA
Under Voltage Lockout (UVLO)
VCCON
VCC turn on threshold
10
10.5
11
V
VCCOFF
VCC turn off threshold
9
9.5
10
V
0.8
1
1.2
V
UVLO hysteresis
Oscillator
TA = 25°C
fSW
Switching frequency
61.7
65
68.3
kHz
-25°C ≤ TA ≤ 125°C
59
65
71
kHz
-40°C ≤ TA ≤ 125°C
57
71
kHz
PWM
DMIN
Minimum duty cycle
VCOMP = 0 V, VSENSE = 5 V,
ICOMP = 6.4 V
DMAX
Maximum duty cycle
VSENSE = 4.95 V
tOFF(min)
Minimum off time
VSENSE = 3 V, ICOMP = 1 V
0%
94%
98%
99.3%
100
250
600
ns
-0.66
-0.73
-0.79
V
-1
-1.08
-1.15
V
-2.1
-4.0
μA
System Protection
VSOC
ISENSE threshold, Soft Over Current
(SOC)
VPCL
ISENSE threshold, Peak Current Limit
(PCL)
IISOP
ISENSE bias current, ISENSE Open-Pin
Protection (ISOP)
ISENSE = 0 V
VISOP
ISENSE threshold, ISENSE Open-Pin
Protection (ISOP)
ISENSE = open pin
VOLP
VSENSE threshold, Open Loop
Protection (OLP)
ICOMP = 1 V, ISENSE = -0.1 V,
VCOMP = 1 V
Open Loop Protection (OLP) Internal
pull-down current
VSENSE = 0.5 V
0.082
0.77
V
0.82
0.86
V
100
250
nA
4.63
4.75
4.87
V
5.12
5.25
5.38
V
VUVD
VSENSE threshold, output UnderVoltage Detection (UVD) (1)
VOVP
VSENSE threshold, output Over-Voltage
Protection (OVP)
VINSBROWNOUT
Input Brown-Out Detection (IBOP)
high-to-low threshold
0.76
0.82
0.88
V
VINSENABLE_th
Input Brown-Out Detection (IBOP)
low-to-high threshold
1.4
1.5
1.6
V
IVINS_0V
VINS bias current
0
±0.1
μA
_th
ISENSE = -0.1 V
VINS = 0 V
ICOMP threshold, external overload
protection
(1)
0.6
V
Not production tested. Characterized by design.
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Electrical Characteristics (continued)
Unless otherwise noted, VCC=15 VDC, 0.1 μF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.75
0.95
1.15
mS
Current Loop
gmi
Transconductance gain
TA = 25°C
Output linear range (1)
±50
3.7
4
μA
ICOMP voltage during OLP
VSENSE = 0.5 V
4.3
V
VREF
Reference voltage
-40°C ≤ TA ≤ 125°C
gmv
Transconductance gain without EDR
gmv-EDR
Transconductance gain under EDR
VSENSE = 4.65 V
Maximum sink current under normal
operation
VSENSE = 6 V, VCOMP = 4 V
Source current under soft start
VSENSE = 4 V, VCOMP = 2.5 V
Maximum source current under EDR
operation
VSENSE = 4 V, VCOMP = 2.5 V
-300
μA
VSENSE = 4 V, VCOMP = 4 V
-170
μA
Voltage Loop
4.9
5
5.1
V
-31.5
-42
-52.5
μS
-440
Enhanced dynamic response VSENSE
low threshold, falling (1)
μS
21
30
38
μA
-21
-30
-38
μA
4.63
4.75
4.87
V
20
100
250
nA
0
0.2
0.4
VSENSE input bias current
VSENSE = 5 V
VCOMP voltage during OLP
VSENSE = 0.5 V, IVCOMP = 0.5 mA
VCOMP rapid discharge current
VCOMP = 3 V, VCC = 0 V
0.77
VPRECHARGE
VCOMP precharge voltage
IVCOMP = -100 μA, VSENSE = 5 V
1.76
IPRECHARGE
VCOMP precharge current
VCOMP = 1.0 V
VSENSE threshold, end of soft start
Initial start up
GATE current, peak, sinking (1)
GATE current, peak, sourcing (1)
GATE rise time
CGATE = 4.7 nF, GATE = 2 V to 8 V
8
40
GATE fall time
CGATE = 4.7 nF, GATE = 8 V to 2 V
8
GATE low voltage, no load
I GATE = 0 A
GATE low voltage, sinking
I GATE = 20 mA
GATE low voltage, sourcing
I GATE = -20 mA
V
mA
V
-1
mA
4.95
V
CGATE = 4.7 nF
2
A
CGATE = 4.7 nF
-1.5
GATE Driver
GATE low voltage, sinking, device OFF
GATE high voltage
6
A
60
ns
25
40
ns
0
0.05
V
0.3
0.8
V
-0.3
-0.8
V
VCC = 5 V, IGATE = 5 mA
0.2
0.75
1.2
V
VCC = 5 V, IGATE = 20 mA
0.2
0.9
1.5
V
VCC = 20 V, CGATE = 4.7 nF
11.0
12.5
14.0
V
VCC = 11 V, CGATE = 4.7 nF
9.5
10.5
11.0
V
VCC = VCCOFF + 0.2 V, CGATE =
4.7 nF
8.0
9.4
10.2
V
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6.6 Typical Characteristics
Unless otherwise noted, VCC = 15 VDC, 0.1 μF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
4.0
12.0
TJ = 25°C
VSENSE = VINS = 3V
No Gate Load
11.0
VCC Turn ON
ICC - Supply Current - mA
VCC(on)/VCC(off) - UVLO Threshold - V
3.5
10.0
VCC Turn OFF
9.0
3.0
2.5
2.0
ICC Turn OFF
ICC Turn ON
1.5
1.0
0.5
8.0
0
-60
-35
15
-10
40
65
90
115
140
0
5
TJ - Temperature - °C
20
Figure 2. Supply Current vs Bias Supply Voltage
Figure 1. UVLO Thrasholds vs Temperature
10
0.5
9
VCC = 15V
7
ICC(start) - Supply Current - mA
8
ICC - Supply Current - mA
15
10
VCC - Bias Supply Voltage - V
Operating, GATE Load = 4.7 nF
6
5
4
3
Standby
2
VCC = UVLO - 0.1 V
0.4
0.3
0.2
Pre-Start
0.1
1
0
0
-60
-35
-10
15
40
65
90
115
140
-60
-35
-10
TJ - Temperature - °C
Figure 3. Supply Current vs Temperature
115
140
Figure 4. Supply Current vs Temperature
75
75
VCC = 15V
73
73
71
fSW - Switching Frequency - kHz
fSW - Switching Frequency - kHz
15
40
65
90
TJ - Temperature - °C
69
67
Switching Frequency
65
63
61
59
71
69
67
63
61
59
57
55
55
-35
-10
15
40
65
90
115
Switching Frequency
65
57
-60
TJ = 25°C
140
10
TJ - Temperature - °C
12
14
16
18
20
VCC - Bias Supply Voltage - V
Figure 5. Oscillator Frequency vs Temperature
Figure 6. Oscillator Frequency vs Bias Supply Voltage
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Typical Characteristics (continued)
Unless otherwise noted, VCC = 15 VDC, 0.1 μF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
2.0
50
1.8
48
VCC = 15V
1.6
46
1.4
Gain, No EDR
44
1.2
gmv - Gain - µA/V
gmi - Gain - mA/V
VCC = 15V
Gain
1.0
0.8
42
40
38
0.6
36
0.4
34
0.2
32
0
30
-60
-35
-10
15
40
65
90
115
140
-60
-35
-10
TJ - Temperature - °C
15
40
65
90
115
140
TJ - Temperature - °C
Figure 7. Current Averaging Amplifier Transconductance vs
Temperature
Figure 8. Voltage Error Amplifier Transconductance vs
Temperature
0
5.50
VCC = 15V
VCC = 15V
-0.1
VSOC - ISENSE Threshold - V
VREF - Reference Voltage - V
-0.2
5.25
Reference Voltage
5.00
4.75
-0.3
-0.4
-0.5
-0.6
Soft Over-Current Protection (SOC)
-0.7
-0.8
-0.9
-1.0
4.50
-60
-35
-10
15
40
65
90
TJ - Temperature - °C
115
140
-60
Figure 9. Reference Voltage vs Temperature
-10
15
40
65
90
TJ - Temperature - °C
115
140
Figure 10. ISENSE Threshold vs Temperature
2.0
5.50
VCC = 15V
1.8
VOLP – VSENSE Threshold - V
VOVP / VUVD- VSENSE Threshold - V
-35
5.25
Over-Voltage Protection (VOVP)
5.00
4.75
VCC = 15V
1.6
1.4
1.2
1.0
Open Loop Protection
0.8
0.6
0.4
Under-Voltage Protection (VUVD)
0.2
4.50
0
-60
-35
-10
15
40
65
90
TJ - Temperature - °C
115
140
Figure 11. VSENSE Threshold vs Temperature
8
-60
-35
-10
15
40
65
90
TJ - Temperature - °C
115
140
Figure 12. VSENSE Threshold vs Temperature
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Typical Characteristics (continued)
2.0
600
1.8
1.6
500
VINS Enable (VINSENABLE_TH)
1.4
450
1.2
1.0
0.8
0.6
400
350
300
0.4
200
0.2
105
0
100
-35
-10
15
40
65
90
TJ - Temperature - °C
115
tOFF(min)
250
Input Brown-Out Protection (VINSBROWNOUT_TH)
-60
-60
140
-35
-10
15
40
65
90
115
140
TJ - Temperature - °C
Figure 13. VINS Threshold vs Temperature
Figure 14. Minimum Off Time vs Temperature
50
50
VCC = 15V
CGATE = 4.7 nF
VGATE = 2V-8V
45
40
40
35
35
30
30
25
TJ = 25°C,
CGATE = 4.7 nF
VGATE = 2V-8V
45
t - Time - ns
t - Time - ns
VSENSE = 3 V
ICOMP = 1 V
550
VCC = 15V
t - Time - ns
VINSENABLE_TH / VINSBROUWNOUT_TH – VINS Threshold - V
Unless otherwise noted, VCC = 15 VDC, 0.1 μF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
Fall Time
20
Rise Time
25
20
Fall Time
15
15
Rise Time
10
10
5
5
0
0
-60
-35
-10
15
40
65
90
115
140
10
12
TJ - Temperature - °C
14
16
18
20
VCC - Bias Supply Voltage - V
Figure 16. Gate Drive Switching vs Bias Supply Voltage
Figure 15. Gate Drive Switching vs Temperature
2.0
VCC = 5V
ICC = 20mA
1.8
VGATE – Gate Low Voltage - V
1.6
1.4
1.2
VGATE
1.0
0.8
0.6
0.4
0.2
0
-60
-35
-10
15
40
65
90
115
140
TJ - Temperature - °C
Figure 17. Gate Low Voltage With Device Off vs Temperature
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7 Detailed Description
7.1 Overview
The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a
fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate
as an active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz,
ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum are
below the EN55022 conducted-band 150 kHz measurement limit.
Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typical
world-wide 85-265VAC mains input range from zero to full output load.
Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the
sinusoidal input voltage under continuous inductor current conditions. Under light load conditions, depending on
the boost inductor value, the inductor current may go discontinuous but still meet Class-D requirements of
EN61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by
generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal
gain parameters for maintaining a low-distortion steady-state input current wave-shape.
10
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7.2 Functional Block Diagram
EMI Filter
LBST
LINE
INPUT
–
Bridge
Rectifier
RVINS1
QBST
CIN
+
RFB1
COUT
ICOMP Protection
UCC28019A Block Diagram
2
Current
Amplifier
FAULT
CICOMP
VCC
PWM
Comparator
KPC(s)
+
Gate Driver
gmi
S
Q
R
Q
+
4V
Fault
IBOP
PWM
RAMP
M2
GAIN
M1, K1
UVLO
Min Off Time
Fault
Logic
OLP
65kHz
Oscillator
PCL
OVP
Clock
M2
8
S
Q
R
Q
UVLO
7
+
40k
40k
Peak Current Limit (PCL)
300ns
Leading Edge
Blanking
VPCL
1.08V
CISENSEfilter
ISENSE
Open-pin
Protection
+
Q
S
Q
R
+
VCC
CVCC
VCCOFF
9.5V
1
GND
-1x
+
Soft Over Current (SOC)
SOC
VSOC 0.73V
S
Q
R
Q
VINENABLE_th 1.5V
Voltage Error
Amplifier
+
OLP/STANDBY
0.82V
+
100nA
+
5V
gmv
IBOP
5V
VINBROWNOUT_th 0.82V
UNDERVOLTAGE
4.75V
OLP/STANDBY
+
CVINS
+
EDR
Input Brown-Out Protection
(IBOP)
4
OVERVOLTAGE
5.25V
OVP
+
20k
VCCON
10.5V
UVLO
+
ISOP
VINS
Auxiliary
Supply
Pre-Drive and
Clamp Circuit
SOC
3
GATE
VCOMP
M1
RISENSEfilter
ISENSE
RLOAD
RFB2
10k
ISOP
ICOMP
VOUT
RGATE
RVINS2
RSENSE
0.6V
DBST
+
6
gmv Enhancement
+
END OF SS
CVSENSE
END OF
SOFT-START
4.95V
5
UVLO
Rapid Discharge
when
VCC < VCCOFF
VPRECHARGE
Q
FAULT
VCOMP
RCV
EDR
SS
VSENSE
Q
S
END OF SS
R
FAULT
CCV2
FAULT
CCV1
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7.3 Feature Description
7.3.1 Soft-Start
Soft Start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a
function of time. VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO,
IBOP, and OLP (Open-Loop Protection)/STANDBY. Once the fault condition is released, an initial pre-charge
source rapidly charges VCOMP to about 1.9 V. After that point, a constant 30 μA of current is sourced into the
compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85%
of its final value. At this point, the sourcing current decreases until the output voltage reaches 99% of its final
rated voltage. The Soft-Start time is controlled by the voltage error amplifier compensation capacitor values
selected, and is user programmable based on desired loop crossover frequency. Once the output voltage
exceeds 99% of rated voltage, the pre-charge source is discountinued and EDR is no longer inhibited.
Soft-Start
+
VCOMP
5V
gmv
VSENSE
FAULT
ISS = -30uA
for VSENSE < 4.25V
during Soft-Start
VCOMP
FAULT
END OF SS
(LATCHED)
+
VPRECHARGE
source for
rapid pre-charge
of VCOMP prior
to Soft-Start
Figure 18. Soft Start
12
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Feature Description (continued)
7.3.2 System Protection
System-level protection features help keep the converter within safe operating limits.
7.3.2.1 VCC Undervoltage Lockout (UVLO)
During startup, Under-Voltage Lockout (UVLO) keeps the device in the off state until VCC rises above the 10.5-V
enable threshold, VCCON. With a typical 1 V of hysteresis on UVLO to increase noise immunity, the device turns
off when VCC drops to the 9.5-V disable threshold, VCCOFF.
UVLO
VCC
Auxilary Supply
+
VCC ON 10.5V
S
Q
R
Q
C DECOUPLE
UVLO
GND
+
VCCOFF 9.5V
Figure 19. UVLO
If, during a brief ac-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT
circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP
capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current
surge should the ac-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically,
these capacitors can be discharged to less than 1.2 V within 150 ms of loss of VCC.
7.3.2.2 Input Brown-Out Protection (IBOP)
The sensed line-voltage input, VINS, provides a means for the designer to set the desired mains RMS voltage
level at which the PFC pre-regulator should start-up, VACturnon, as well as the desired mains RMS level at which it
should shut down, VACturnoff. This prevents unwanted sustained system operation at or below a brown-out
voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived
directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC
UVLO turn-off.
R VINS1
VINS
20k
Input Brown-Out Protection (IBOP)
Rectified AC Line
+
CIN
R VINS2
S
Q
R
Q
VINENABLE_th 1.5V
CVINS
IBOP
5V
VINBROWNOUT_th 0.8V
+
Figure 20. Input Brown-Out Protection
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Feature Description (continued)
Input line voltage is sensed directly from the rectified ac mains voltage through a resistor-divider filter network
providing a scaled and filtered value at the VINS input. IBOP will put the device into standby mode when VINS
falls (high to low) below 0.8 V, VINSBROWNOUT_th. The device comes out of standby when VINS rises (low to high)
above 1.5 V, VINSENABLE_th. Bias current sourced from VINS, IVINS_0V, is less than 0.1 μA. With a bias current this
low, there is little concern for any set-point error caused by this current flowing through the sensing network. The
highest praticable value resistance for this network should be chosen to minimize power dissipation, especially in
applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise
pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used
and its voltage rating, RVINS1 should be implemented with multiple resistors in series to reduce voltage stresses.
First, select RVINS1 based on choosing the highest reasonable resistance value available for typical applications.
Then select RVINS2 based on this value:
RVINS 2 = RVINS 1
VINS ENABLE _ th
2VACturnon - VINS ENABLE _ th
(1)
Power dissipated in the resistor network is:
PVINS =
VIN ( RMS )2
RVINS 1 + RVINS 2
(2)
The filter capacitor, CVINS, has two functions. First, to attenuate the voltage ripple to levels between the enable
and brown-out threshold to prevent ripple on VINS from falsely triggering IBOP when the converter is operating
at low line. Second, CVINS delays the brown-out protection operation for a desired number of line-half-cycle
periods while still having a good response to an actual brown-out event.
The capacitor is chosen so that it will discharge to the VINSBROWNOUT_th level after a delay of N number of line ½cycles to accommodate ac-line dropout ride-through requirements.
CVINS =
-tdischrg
æ
ç
VINS BROWNOUT _ th
RVINS 2 ln ç
RVINS 2
ç 0.9V
AC min
ç
RVINS 1 + RVINS 2
è
ö
÷
÷
÷
÷
ø
(3)
Where,
tdischrg =
1
N
2 f LINE
(4)
and VACmin is the lowest normal operating rms input voltage.
14
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Feature Description (continued)
7.3.2.3 Output Overvoltage Protection (OVP)
VOUT(OVP) is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold
(5-V reference voltage + 5%), VOVP. The normal control loop is bypassed and the GATE output is disabled until
VSENSE falls below 5.25 V. VOUT(OVP) is 420 V in a system with a 400-V rated output, for example.
7.3.2.4 Open Loop Protection/Standby (OLP/Standby)
If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE
input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To
prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage,
causing VSENSE to fall below 0.8 V, the device is put in standby, a state where the PWM switching is halted and
the device is still on but draws standby current below 2.9 mA. This shutdown feature also gives the designer the
option of pulling VSENSE low with an external switch.
7.3.2.5 ISENSE Open-Pin Protection (ISOP)
If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then
it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an
internal pull-up source drives ISENSE above 0.1 V so that a detector forces a state where the PWM switching is
halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature avoids continual
operation in OVP and severely distorted input current.
7.3.2.6 Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
During normal operation, small perturbations on the PFC output voltage rarely exceed 5% deviation and the
normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the
output voltage drop exceeds -5%, an output under-voltage is detected (UVD) and Enhanced Dynamic Response
(EDR) acts to speed up the slow response of the low-bandwidth voltage loop. During EDR, the transconductance
of the voltage error amplifier is increased approximately 16 times to speed charging of the voltage-loop
compensation capacitors to the level required for regulation. EDR is removed when VSENSE > 4.75 V. The EDR
feature is not activated until soft start is completed.
Over and Under Voltage Protection
Open Loop Protection / Standby
Soft-Start Complete
Output Voltage
R FB1
Standby
VSENSE
R FB2
Optional
OVERVOLTAGE
5.25V
UNDERVOLTAGE
4.75V
+
OVP
+
UVD
SOFT-START COMPLETE 4.95V
END OF SS
+
OPEN LOOP
PROTECTION/STANDBY 0.82V
+
OLP/STANDBY
Figure 21. OVP, UVD, OLP/ Standby, Soft Start Complete
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Feature Description (continued)
OVP 105% VREF
100% VREF
EDR 95% VREF
Feedback
Voltage
OLP/SS 16% VREF
Protection
State
OLP
Soft-Start
(No EDR
to 99% VREF)
Run
OVP
(No Gate Output)
Run
UVD
(EDR on)
OLP
Figure 22. Soft Start and Protection States
7.3.2.7 Over-Current Protection
Inductor current is sensed by RISENSE, a low value resistor in the return path of input rectifier. The other side of
the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is
always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to
the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against
an overload on the output and Peak Current Limit (PCL) protects against inductor saturation.
Soft Over Current (SOC)
LINE
INPUT
VSOC
0.73V
ISENSE Open-Pin
Protection (ISOP)
–
+
VOUT
I ISOP
1.5µA
SOC
+
VISOP
0.1V
RISENSE
ISOP
+
ISENSE
RISENSEfilter
C ISENSEfilter
VPCL
1.08V
(Optional)
+
300 ns
Leading Edge
Blanking
PCL
+
-1x
Peak Current Limit (PCL)
Figure 23. Soft Over Current/ Peak Current Limit
7.3.2.8 Soft Over Current (SOC)
Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE
reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty
cycle.
16
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Feature Description (continued)
7.3.2.9 Peak Current Limit (PCL)
Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE
reaches -1.08 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked
to improve noise immunity against false triggering.
7.3.2.10 Current Sense Resistor, RISENSE
The current sense resistor, RISENSE, is sized using the minimum threshold value of Soft Over Current (SOC),
VSOC(min) = 0.66 V. To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle,
the resistor is sized for an overload current of 10% more than the peak inductor current,
RISENSE £
VSOC(min)
1.1I L _ PEAK (max)
(5)
Since RISENSE sees the average input current, worst-case power dissipation occurs at input low-line when input
current is at its maximum. Power dissipated by the sense resistor is given by:
PRISENSE = ( I IN _ RMS (max) )2 RISENSE
(6)
Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor
reaches the PCL threshold, VPCL. The absolute maximum peak current, IPCL, is given by:
I PCL =
VPCL
RISENSE
(7)
7.3.3 Gate Driver
The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET
gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to
12.5 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the Off state. An
external gate drive resistor, RGATE, can be used to limit the rise and fall times and dampen ringing caused by
parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of the resistor
depends upon the parasitic elements associated with the layout and other considerations. A 10-kΩ resistor close
to the gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and helps protect
against inadvertent dv/dt-triggered turn-on.
VCC
UVLO
Gate Driver
FAULT
Fault
Logic
OLP
VCC
From
PWM
Latch
Rectified
AC
L BOOST
DBOOST
VOUT
QBOOST
IBOP
GATE
COUT
RGATE
PCL
OVP
CLOCK
S
Q
R
Q
10k
Pre-Drive and
Clamp Circuit
GND
Figure 24. Gate Driver
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Feature Description (continued)
7.3.4 Current Loop
The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator
(PWM) stage, the external boost inductor stage and the external current sensing resistor.
7.3.5 ISENSE and ICOMP Functions
The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The
internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The
voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the
ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is
determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-line
voltage range.
ICOMP is connected to 4V internally whenever the device is in a Fault or Standby condition.
7.3.6 Pulse Width Modulator
The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output
signal which is High whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined
by a non-linear function of the internal VCOMP voltage.
PWM cycle
VICOMP
VRAMP =
F(VVCOMP)
PWM
tOFF
tON
t
Figure 25. PWM Generation
The PWM output signal always starts Low at the beginning of the cycle, triggered by the internal clock. The
output stays Low for a minimum off-time, tOFF_min, after which the ramp rises linearly to intersect the ICOMP
voltage. The ramp-ICOMP intersection determines tOFF, and hence DOFF. Since DOFF = VIN/VOUT by the boosttopology equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor
current, it follows that the control loop forces the inductor current to follow the input voltage wave-shape to
maintain boost regulation. Therefore, the average input current is also sinusoidal in wave-shape.
7.3.7 Control Logic
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various
protection functions incorporated into the device. The GATE output duty-cycle may be as high as 99%, but will
always have a minimum off-time tOFF_min. Normal duty-cycle operation can be interrupted directly by OVP and
PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and
further inhibit output until the SS operation can begin.
7.3.8 Voltage Loop
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing
stage, the voltage error amplifier stage, and the non-linear gain generation.
18
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Feature Description (continued)
7.3.9 Output Sensing
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control
loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference
voltage.
Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable
resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves
to filter the signal in a high-noise environment. This filter time constant should generally be less than 100 μs.
7.3.10 Voltage Error Amplifier
The transconductance error amplifier (gmv) generates an output current proportional to the difference between the
voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges
the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system
operating conditions. Proper selection of the compensation network components leads to a stable PFC preregulator over the entire ac-line range and 0-100% load range. The total capacitance also determines the rate-ofrise of the VCOMP voltage at soft start, as discussed earlier.
The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge the
compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays
complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias
voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large
capacitor could be left with substantial voltage on it, negating the benefit of a subsequent soft start. The
UCC28019A incorporates a parallel discharge path which operates without VCC bias, to further discharge the
compensation network after VCC is removed.
When output voltage perturbations greater than ±5% appear at the VSENSE input, the amplifier moves out of
linear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSE
returns within ±5% of regulation. On an under-voltage, the UVD function invokes EDR which immediately
increases the voltage error amplifier transconductance to about 440 μS. This higher gain facilitates faster
charging of the compensation capacitors to the new operating level.
7.3.11 Non-Linear Gain Generation
The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is
buffered internally and is then subject to modification by the SOC function, as discussed earlier.
Together the current gain and the PWM slope adjust to the different system operating conditions (set by the acline voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor input
current wave-shape following that of the input voltage.
7.4 Device Functional Modes
This device has no functional modes.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a
fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate
as an active PFC pre-regulator. The operating switching frequency is fixed at 65 kHz.
The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85VAC to 265-VAC mains input range from zero to full output load. The usable system load ranges from 100 W to
few kW.
Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the
sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on
the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC
61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating
a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain
parameters for maintaining a low-distortion, steady-state, input-current wave shape.
20
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8.2 Typical Application
+
+
Figure 26 illustrates the design process and component selection for a continuous conduction mode power factor
correction boost converter utilizing the UCC28019A. The target design is a universal input, 350-W PFC designed
for an ATX supply application. This design process is directly tied to the UCC28019A Design Calculator
(SLUC117) spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas
Instruments website.
Figure 26. Design Example Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Design goal parameters for a continuous conduction mode power factor correction boost converter utilizing the
UCC28019A.
Table 1. Design Goal Parameters
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
115
265
VAC
Input characteristics
VIN
Input voltage
85
fLINE
Input frequency
47
Brown out voltage
63
Hz
VAC(on), IOUT = 0.9 A
75
VAC
VAC(off), IOUT = 0.9 A
65
VAC
Output characteristics
VOUT
Output voltage
85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63
Hz
0 A ≤ IOUT ≤ 0.9 A
380
390
402
VDC
VRIPPLE(SW High frequency output
voltage ripple
)
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
3.9
VPP
VIN = 230 VAC , fLINE = 50 Hz, IOUT = 0.9 A
3.9
VPP
VRIPPLE(f_LI Line frequency output
voltage ripple
NE)
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
19.5
VPP
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A
19.5
VPP
0.9
A
350
W
85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63
Hz
IOUT
Output load current
POUT
Output power
VOUT(OVP)
Output over voltage
protection
410
V
VOUT(UVP)
Output under voltage
protection
370
V
Control loop characteristics
fSW
Switching frequency
TJ = 25°C
f(CO)
Control loop bandwidth
VIN = 162 VDC, IOUT = 0.45 A
14
Hz
Phase margin
VIN = 162 VDC, IOUT = 0.45 A
70
degrees
PF
Power factor
VIN = 115 VAC, IOUT = 0.9 A
THD
Total harmonic distortion
η
Full load efficiency
TAMB
Ambient temperature
22
61.7
65
68.3
0.98
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
4.3%
10%
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A
6.6%
10%
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
0.95
50
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8.2.2 Detailed Design Procedure
8.2.2.1 Current Calculations
First, determine the maximum average output current, IOUT(max):
I OUT (max) =
I OUT (max) =
POUT (max)
VOUT
(8)
350 W
@ 0 .9 A
390 V
(9)
The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the
efficiency and power factor initial assumptions:
I
I
IN _ RMS (max)
IN _ RMS (max)
=
=
POUT (max)
hVIN (min) PF
(10)
350W
= 4.52 A
0.92 ´ 85V ´ 0.99
(11)
Based upon the calculated RMS value, the maximum peak input current, IIN_PEAK(max), and the maximum average
input current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.
I IN _ PEAK (max) = 2 I IN _ RMS (max)
(12)
I IN _ PEAK (max) = 2 ´ 4.52 A = 6.39 A
I IN _ AVG(max) =
I IN _ AVG(max) =
(13)
2 I IN _ PEAK (max)
p
(14)
2 ´ 6.39 A
= 4.07 A
p
(15)
8.2.2.2 Bridge Rectifier
Assuming a forward voltage drop, VF_BRIDGE, of 0.95 V across the rectifier diodes, BR1, the power loss in the
input bridge, PBRIDGE, can be calculated:
PBRIDGE = 2VF _ BRIDGE I IN _ AVG(max)
(16)
PBRIDGE = 2 ´ 0.95V ´ 4.07 A = 7.73W
(17)
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8.2.2.3 Input Capacitor
Note that the UCC28019A is a continuous conduction mode controller and as such the inductor ripple current
should be sized accordingly. High inductor ripple current has an impact on the CCM/DCM boundary and results
in higher light-load THD, and also affects the choices for RSENSE and CICOMP values. Allowing an inductor ripple
current, IRIPPLE, of 20% and a high frequency ripple voltage factor, ΔVRIPPLE_IN, of 6%, the minimum input
capacitor value, CIN, is calculated by first determining the input ripple current, IRIPPLE, and the input ripple voltage,
VIN_RIPPLE(max):
I
RIPPLE
= DI RIPPLE I IN _ PEAK (max)
(18)
DI RIPPLE = 0.2
I
RIPPLE
(19)
= 0.2 ´ 6.39 A = 1.28 A
(20)
VIN _ RIPPLE(max) = DVRIPPLE _ INVIN _ RECTIFIED(min)
DVRIPPLE _ IN = 0.06
(22)
VIN _ RECTIFIED = 2VIN
V IN _ RECTIFIED (min) =
(21)
(23)
2 ´ 85V = 120 .2V
VIN _ RIPPLE(max) = 0.06 ´120.2V = 7.21V
(24)
(25)
The value for the input x-capacitor can now be calculated:
CIN =
CIN =
I RIPPLE
8 f SW VIN _ RIPPLE(max)
(26)
1.28 A
= 0.341m F
8 ´ 65kHz ´ 7.21V
(27)
A 0.33 μF, 275 VAC ex-2 film capacitor was selected for CIN.
24
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8.2.2.4 Boost Inductor
The boost inductor, LBST, is selected after determining the maximum inductor peak current, IL_PEAK(max):
I L _ PEAK (max) = I IN _ PEAK (max) +
I L _ PEAK (max) = 6.39 A +
I RIPPLE
2
(28)
1.28 A
= 7.03 A
2
(29)
The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5:
LBST (min) ³
LBST (min) ³
VOUT D( 1 - D )
f SW ( typ ) I RIPPLE
(30)
390V ´ 0.5( 1 - 0.5 )
³ 1.17 mH
65kHz ´1.28 A
(31)
The actual value of the boost inductor that will be used is 1.25 mH.
The maximum duty cycle, DUTY(max), can be calculated and will occur at the minimum input voltage:
DUTY(max) =
VOUT - VIN _ RECTIFIED(min)
VOUT
(32)
VIN _ RECTIFIED(min) = 2 ´ 85V = 120V
DUTY(max) =
(33)
390V - 120V
= 0.692
390V
(34)
8.2.2.5 Boost Diode
The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery
charge, QRR, of the diode. This design uses a silicon-carbide diode. Although somewhat more expensive, it
essentially eliminates the reverse recovery losses because QRR is equal to 0nC.
PDIODE = VF _125C I OUT (max) + 0.5 f SW ( typ )VOUT QRR
(35)
VF _125C = 1.5V
(36)
QRR = 0nC
(37)
PDIODE = 1.5V ´ 0.897 A + 0.5 ´ 65kHz ´ 390V ´ 0nC = 1.35W
(38)
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8.2.2.6 Switching Element
The conduction losses of the switch are estimated using the RDS(on) of the FET at 125°C , found in the FET data
sheet, and the calculated drain to source RMS current, IDS_RMS:
2
PCOND = I DS
_ RMS RDSon( 125C )
(39)
RDSon( 125C ) = 0.35W
I DS _ RMS =
I DS _ RMS =
(40)
POUT (max)
2-
16VIN _ RECTIFIED(min)
VIN _ RECTIFIED(min)
350W
120V
2-
3p VOUT
(41)
16 ´120V
= 3.54 A
3p ´ 390V
(42)
PCOND = 3.54 A2 ´ 0.35W = 4.38W
(43)
The switching losses are estimated using the rise time, (tr), and fall time, (tf), of the gate, and the output
capacitance losses.
For the selected device:
t r = 5 . 0 ns ,t f = 4 . 5 ns
(44)
COSS = 780 pF
(45)
PSW = f SW ( typ ) ( 0 .5 VOUT I IN - PEAK (max) (t r + t f )+ 0 .5C OSS V
2
OUT
)
(46)
PSW = 65kHz( 0.5 ´ 390V ´ 6.39 A (5n + 4.5ns ) + 0.5 ´ 780 pF ´ 390V ) = 4.626W
2
(47)
Total FET losses:
PCOND + PSW = 4.38W + 4.626W = 9.007W
26
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8.2.2.7 Sense Resistor
To accommodate the gain of the internal non-linear power limit, RSENSE is sized such that it will trigger the soft
over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, VSOC, of
ISENSE.
RSENSE =
RSENSE =
VSOC
I L _ PEAK (max) ´1.25
(49)
0.66V
= 0.075W
7.03 A ´1.25
(50)
Using a parallel combination of available standard value resistors, the sense resistor is chosen.
RSENSE = 0.067W
(51)
The power dissipated across the sense resistor, PRsense, must be calculated:
2
PRsense = I IN
_ RMS (max) RSENSE
(52)
2
PRsense = ( 4.52 A ) ´ 0.067W = 1.37W
(53)
The peak current limit, PCL, protection feature will be triggered when current through the sense resistor results in
the voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL
threshold is used:
I PCL =
I PCL =
VPCL
RSENSE
(54)
1.15V
= 17.16 A
0.067W
(55)
To protect the device from inrush current, a standard 220-Ω resistor, RISENSE, is placed in series with the ISENSE
pin. A 1000-pF capacitor, CISENSE, is placed close to the device to improve noise immunity on the ISENSE pin.
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8.2.2.8 Output Capacitor
The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream
converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle,
tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:
COUT (min) ³
COUT (min) ³
2
OUT
V
2 POUT t HOLDUP
2
- VOUT
_ HOLDUP(min)
(56)
2 ´ 350W ´ 21.28ms
³ 240 m F
390V 2 - 300V 2
(57)
It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 μF.
Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that
the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the
controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current
of the output capacitor are calculated:
VOUT _ RIPPLE( pp ) < 0.05VOUT
(58)
VOUT _ RIPPLE( pp ) < 0.05 ´ 390V < 19.5VPP
VOUT _ RIPPLE( pp ) =
VOUT _ RIPPLE( pp ) =
(59)
I OUT
p ( 2 f LINE(min) )COUT
(60)
0 .9 A
= 11.26V
p ( 2 ´ 47 Hz ) ´ 270 m F
(61)
The required ripple current rating at twice the line frequency is equal to:
I Cout _ 2 fline =
I Cout _ 2 fline =
I OUT (max)
2
(62)
0 .9 A
= 0.635 A
2
(63)
There will also be a high frequency ripple current through the output capacitor:
I Cout _ HF = I OUT (max)
I Cout _ HF = 0.9 A
16VOUT
3p VIN _ RECTIFIED(min)
- 1 .5
16 ´ 390V
- 1 .5 = 1 .8 A
3p ´120V
(64)
(65)
The total ripple current in the output capacitor is the combination of both and the output capacitor must be
selected accordingly:
28
I
Cout _ RMS ( total )
2
2
= I Cout
_ 2 fline + I Cout _ HF
I
Cout _ RMS ( total )
= 0.635 A2 + 1.8 A2 = 1.9 A
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8.2.2.9 Output Voltage Set Point
For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 MΩ
for the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum
allowable voltage across each. Using the internal 5-V reference, VREF, select the bottom divider resistor, RFB2, to
meet the output voltage design goals.
RFB 2 =
RFB 2 =
VREF RFB1
VOUT - VREF
(68)
5V ´1M W
= 13.04k W
390V - 5V
(69)
Using 13 kΩ for RFB2 results in a nominal output voltage set point of 391 V.
The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:
æ R + RFB 2 ö
VOUT ( OVP ) = VSENSEOVP ç FB1
÷
RFB 2
è
ø
(70)
æ 1M W + 13k W ö
VOUT ( OVP ) = 5.25V ´ ç
÷ = 410.7V
13k W
è
ø
(71)
The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal setpoint:
æ R + RFB 2 ö
VOUT ( UVD ) = VSENSEUVD ç FB1
÷
RFB 2
è
ø
(72)
æ 1M W + 13k W ö
VOUT ( UVD ) = 4 .75V ´ ç
÷ = 371 .6V
13k W
è
ø
(73)
A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that
the RC time constant is less than 0.1 ms so as not to significantly reduce the control response time to output
voltage deviations. With careful layout, the noise on this design is minimal, so an RC time constant of 0.01 ms
was all that was needed:
CVSENSE =
CVSENSE =
0.01ms
RFB 2
(74)
0.01ms
= 769 pF
13k W
(75)
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8.2.2.10 Loop Compensation
The selection of compensation components, for both the current loop and the voltage loop, is made easier by
using the UCC28019A Design Calculator spreadsheet that can be found in the Tools section of the UCC28019A
product folder on the Texas Instruments website. The current loop is compensated first by determining the
product of the internal loop variables, M1M2, using the internal controller constants K1 and KFQ:
M 1M 2 =
K FQ =
K FQ =
2
I OUT (max)VOUT
RSENSE K1
h 2VIN2 _ RMS K FQ
(76)
1
f SW ( typ )
(77)
1
= 15.385m s
65kHz
(78)
K1 = 7
M 1M 2 =
(79)
0.9 A ´ 391V 2 ´ 0.067W ´ 7
V
= 0.374
2
2
0.92 ´115V ´15.385m s
ms
(80)
The VCOMP operating point is found on Figure 27. The Design Calculator spreadsheet enables the user to
iteratively select the appropriate VCOMP value.
M1M2
vs
VCOMP
2.0
1.8
1.6
1.4
M1M2
1.2
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
VCOMP - V
Figure 27. M1M2 vs. VCOMP
30
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For the given M1M2 of 0.374 V/μs, the VCOMP is approximately equal to 4, as shown in Figure 27.
The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp
slope, are calculated using the following conditions:
The M1 current loop gain factor:
• if : 0 < VCOMP < 2
then : M 1 = 0 . 064
•
(81)
if : 2 ≤ VCOMP < 3
then : M 1 = 0.139 ´ VCOMP - 0.214
•
(82)
if : 3 ≤ VCOMP < 5.5
then : M 1 = 0 . 279 ´ V C O M P - 0 . 632
•
(83)
if : 5.5 ≤ VCOMP < 7
then : M 1 = 0.903
(84)
In this example:
VCOMP = 4
M 1 = 0.279 ´ 4 - 0.632 = 0.484
(85)
The M2 PWM ramp slope:
• if : 0 < VCOMP < 1.5
then : M 2 = 0
•
V
ms
(86)
if : 1.5 ≤ VCOMP < 5.6
then : M 2 = 0.1223 ´ (VCOMP - 1.5 )2
•
V
ms
(87)
if : 5.6 ≤ VCOMP < 7
then : M 2 = 2.056
V
ms
(88)
In this example:
VCOMP = 4
M 2 = 0.1223 ´ ( 4 - 1.5 )2
V
V
= 0.764
ms
ms
(89)
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Verify that the product of the individual gain factors is approximately equal to the M1M2 factor determined above,
if not, reselect VCOMP and recalculate M1M2.
M 1 ´ M 2 = 0.484 ´ 0.764
0.37
V
V
= 0.37
ms
ms
(90)
V
V
@ M 1M 2 = 0.372
ms
ms
(91)
The non-linear gain variable, M3, can now be calculated:
• if : 0 < VCOMP < 3
then : M 3 = 0.0510 ´ VCOMP 2 - 0.1543 ´ VCOMP - 0.1167
•
(92)
if : 3 ≤ VCOMP < 7
then : M 3 = 0.1026 ´ VCOMP 2 - 0.3596 ´ VCOMP + 0.3085
(93)
In this example:
VCOMP = 4
M 3 = 0.1026 ´ 42 - 0.3596 ´ 4 + 0.3085 = 0.512
(94)
The frequency of the current averaging pole, fIAVG, is chosen to be at 9.5 kHz. The required capacitor on ICOMP,
CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:
CICOMP =
CICOMP =
g mi M 1
K1 2p f IAVG
(95)
0.95mS ´ 0.484
= 1100 pF
7 ´ 2 ´ p ´ 9.5kHz
(96)
Using a 1200 pF capacitor for CICOMP results in a current averaging pole frequency of 8.7 kHz:
f IAVG =
f
32
IAVG
=
g mi M 1
K1 2p CICOMP
(97)
0.95mS ´ 0.484
= 8.7 kHz
7 ´ 2 ´ p ´1200 pF
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The transfer function of the current loop can be plotted:
GCL ( f ) =
K1 RSENSEVOUT
´
K FQ M 1M 2 LBST
1
s( f )2 K1CICOMP
s( f ) +
g mi M 1
(99)
GCLdB ( f ) = 20 log ( GCL ( f ) )
(100)
CURRENT AVERAGING CIRCUIT
-80
100
80
60
-100
Phase
40
-120
0
qGCL(f)
GCLdB(f)
20
Gain
-140
-20
-40
-160
-60
-80
-180
-100
10
100
3
1*10
4
1*10
5
1*10
6
1*10
f - Hz
Figure 28. Bode Plot of the Current Averaging Circuit.
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The open loop of the voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and
the gain from the pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator
to power stage pole, fPWM_PS. The plotted result is shown in Figure 29.
GFB =
GFB =
RFB 2
RFB1 + RFB 2
(101)
13k W
= 0.013
1M W + 13k W
(102)
1
f PWM _ PS =
2p
f PWM _ PS =
3
K1 RSENSEVOUT
COUT
2
K FQ M 1M 2VIN ( typ )
(103)
1
= 1.581Hz
7 ´ 0.067W ´ 391V 3 ´ 270 m F
2p
V
15.385m s ´ 0.484 ´ 0.764 ´115V 2
ms
(104)
M 3VOUT
M 1M 2 ´1m s
GPWM _ PS ( f ) =
s( f )
1+
2p f PWM _ PS
(105)
GVL ( f ) = GFB GPWM _ PS ( f )
(106)
GVLdB ( f ) = 20 log ( GVL ( f ) )
(107)
OPEN LOOP VOLTAGE TRANSFER
FUNCTION
0
20
-20
0
-40
qGVL(f)
GVLdB(f)
Gain
Phase
-20
-60
-40
-80
-100
-60
0.01
0.1
1
10
100
1*103
1*104
f - Hz
Figure 29. Bode Plot of the Open Loop Voltage Transfer Function
34
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The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20
Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired
to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.
f ZERO =
1
2p RVCOMP CVCOMP
(108)
1
f POLE =
2p
RVCOMP CVCOMP CVCOMP _ P
CVCOMP + CVCOMP _ P
(109)
é
ê
ê
1 + s( f )RVCOMP CVCOMP
GEA ( f ) = gmv ê
é
æ RVCOMP CVCOMP CVCOMP _ P
ê
1
C
C
s(
f
)
s(
f
)
+
+
ê
ç
(
)
VCOMP _ P
ê VCOMP
ç CVCOMP + CVCOMP _ P
êë
è
ë
ù
ú
ú
ú
öù ú
÷÷ ú ú
ø úû û
fV = 10 Hz
(110)
(111)
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From Figure 29, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10
Hz is approximately 0.667 dB. Estimating that the parallel capacitor, CVCOMP_P, is much smaller than the series
capacitor, CVCOMP, the unity gain will be at fV, and the zero will be at fPWM_PS, the series compensation capacitor
is determined:
gmv
CVCOMP =
10
fV
f PWM _ PS
GVLdB ( f )
20
´ 2p fV
(112)
10 Hz
= 0.667 dB 1.581Hz = 3.92 m F
10 20 ´ 2 ´ p ´10 Hz
42 m S ´
CVCOMP
(113)
A 3.3-μF capacitor is used for CVCOMP.
RVCOMP =
RVCOMP =
1
2p f ZERO CVCOMP
(114)
1
= 30.51k W
2 ´ p ´1.581Hz ´ 3.3m F
(115)
A 33.2-kΩ resistor is used for RVCOMP.
CVCOMP _ P =
CVCOMP _ P =
36
CVCOMP
2p f POLE RVCOMP CVCOMP - 1
3 .3 m F
= 0 .258 m F
2 ´ p ´ 20 Hz ´ 33 .2 k W ´ 3 .3 m F - 1
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A 0.22-μF capacitor is used for CVCOMP_P.
The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 30.
GVL _ total ( f ) = GFB ( f )GPWM _ PS ( f )GEA ( f )
(
GVL _ totaldB ( f ) = 20 log GVL _ total ( f )
(118)
)
(119)
100
100
50
80
60
0
Gain
qGVL_total(f)
GVL_totaldB(f)
CLOSED LOOP VOLTAGE TRANSFER
FUNCTION
40
-50
Phase
-100
20
-150
0
0.01
0.1
1
10
100
1*103
1*104
f - Hz
Figure 30. Closed Loop Voltage Bode Plot
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8.2.2.11 Brown Out Protection
Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low
bias current into VINS means the value of RVINS1 could be hundreds of megaOhms. For practical purposes, a
value less than 10 MΩ is usually chosen. Assuming approximately 150 times the input bias current through the
resistor dividers will result in an RVINS1 that is less than 10 MΩ , so as to not contribute excessive noise, and still
maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the
user programmable minimum voltage, VAC(off), and turn on when the input rises above VAC(on).
IVINS = 150 ´ IVINS _ 0V
(120)
IVINS = 150 ´ 0.1m A = 15m A
(121)
VAC( on ) = 75V
(122)
V AC ( off ) = 65V
RVINS 1 =
RVINS 1 =
(123)
2 ´ VAC( on ) - VF _ BRIDGE - VINS ENABLE _ th(max)
IVINS
(124)
2 ´ 75V - 0.95V - 1.6V
= 6.9 M W
15m A
(125)
A 6.5-M resistance is chosen.
RVINS 2 =
RVINS 2 =
38
VINS ENABLE _ th(max)´R VINS 1
2 ´ VAC( on ) - VINS ENABLE _ th(max) - VF _ BRIDGE
1.6V ´ 6.5M W
= 100k W
2 ´ 75V - 1.6V - 0.95V
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(126)
(127)
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Product Folder Links: UCC28019A
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The capacitor on VINS, CVINS, is selected so that it's discharge time is greater than the output capacitor hold up
time. COUT was chosen to meet one-cycle hold-up time so CVINS will be chosen to meet 2.5 half-line cycles.
tCVINS _ dischrg =
tCVINS _ dischrg =
CVINS =
C
VINS
=
N HALF _ CYCLES
2 ´ f LINE (min)
(128)
2 .5
= 25 .6 ms
2 ´ 47 Hz
(129)
-tCVINS _ dischrg
é
ù
ê
ú
VINS BROWNOUT _ th(min)
ê
ú
RVINS 2 ´ ln
ê
ú
æ
ö
RVINS 2
ê 0.9 ´ VIN _ RMS (min) ´ ç
÷ú
êë
è RVINS 1 + RVINS 2 ø úû
-25.6ms
é
ù
ê
ú
0.76V
ú
100k W ´ ln ê
100k W
öú
ê 0.9 ´ 85V ´ æ
ç
÷
êë
è 6.5M W + 100k W ø úû
(130)
= 0.63m F
(131)
8.2.3 Application Curves
1
20
IOUT 85 VAC
IOUT 115 VAC
IOUT 230 VAC
IOUT 265 VAC
0.95
18
Total Harmonic Distortion (THD)
0.9
Power Factor
85 VAC, 50 Hz
115 VAC, 50 Hz
230 VAC, 50 Hz
265 VAC, 50 Hz
0.85
0.8
0.75
0.7
16
14
12
10
8
6
0.65
4
0.6
2
0
0.1
0.2
0.3
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
0
0.1
D001
Figure 31. Power Factor vs. Load Current
0.2
0.3
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
D001
Figure 32. Total Harmonic Distortion vs. Load Current
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SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
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9 Power Supply Recommendations
9.1 Bias Supply
The UCC28019A operates from an external bias supply. It is recommended that the device be powered from a
regulated auxiliary supply.
NOTE
This device is not intended to be used from a bootstrap bias supply. A bootstrap bias
supply is fed from the input high voltage through a resistor with sufficient capacitance on
VCC to hold up the voltage on VCC until current can be supplied from a bias winding on
the boost inductor. For that reason, the minimal hysteresis on VCC would require an
unreasonable value of hold-up capacitance.
During normal operation, when the output is regulated, current drawn by the device includes the nominal run
current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take
switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor of 0.1
μF minimum value from VCC to GND with short, wide traces is recommended.
VCC
VCC(ON) 10.5V
VCC(OFF) 9.5V
ICC
ICC(ON)
ICC(stby) <2.9mA
ICC(start) <200µA
Controller
State
PWM
State
UVLO
Soft-Start
Run
Fault/Standby
OFF
Ramp
Regulated
OFF
SoftStart
Run
Ramp Regulated
UVLO
OFF
Figure 33. Device Supply States
The device bias operates in several states. During startup, VCC Under-Voltage Lock-Out (UVLO) sets the
minimum operational dc input voltage of the controller. There are two UVLO thresholds. When the UVLO turn-on
threshold is exceeded, the PFC controller turns ON. If the VCC voltage falls below the UVLO turn-off threshold,
the PFC controller turns off. During UVLO, current drawn by the device is minimal. After the device turns on, Soft
Start (SS) is initiated and the boost inductor current is ramped up in a controlled manner to reduce the stress on
the external components and avoids output voltage overshoot. During Soft Start and after the output is in
regulation, the device draws its normal run current. If any of several fault conditions is encountered or if the
device is put in Standby with an external signal, the device draws a reduced standby current.
40
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SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
10 Layout
10.1 Layout Guidelines
As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the
integrity of the ground return. The pin out of the UCC28019A is ideally suited for separating the high di/dt
induced noise on the power ground from the low current quiet signal ground required for adequate noise
immunity. A star point ground connection at the GND pin of the device can be achieved with a simple cut out in
the ground plane of the printed circuit board. As shown in Figure 34, the capacitors on ISENSE, VINS, VCOMP,
and VSENSE must all be returned directly to the quiet portion of the ground plane, indicated by Signal GND, and
not the high current return path of the converter, shown as the Power GND. Because the example circuit in
Figure 34 uses surface mount components, the ICOMP capacitor, C10, has its own dedicated return to the GND
pin.
Table 2. Layout Components
REFERENCE DESIGNATOR
FUNCTION
U1
UCC28019A
Q1
Main switch
R1
RGATE
R5
Pull-down resistor on GATE
C13, C14
VCC bypass capacitors
C10
ICOMP compensation, CICOMP
R6
Inrush current limiting resistor, RISENSE
C11
ISENSE filter, CISENSE
R12, R13, R14
RFB1 on VSENSE
R18
RFB2 on VSENSE
C16
CVSENSE
R16, C17, C15
VCOMP compensation components, RVCOMP, CVCOMP, CVCOMP_P
C12, R17
CVINS, RVINS2 on VINS
D2
Boost diode
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Layout Guidelines (continued)
10.2 Layout Example
Power
GND
Cut out in
ground plane
GND
ICOMP
GATE
VCC
ISENSE
VSENSE
VINS
VCOMP
Signal
GND
Figure 34. Recommended Layout for the UCC28019A
42
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SLUS828D – DECEMBER 2008 – REVISED OCTOBER 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Related Products
The following parts have characteristics similar to the UCC28019A and may be of interest.
Table 3. Related Products
DEVICE
DESCRIPTION
UCC28019
8-Pin CCM PFC Controller
UCC3817/18
Full-Feature PFC Controller
UC2853A
8-Pin CCM PFC Controller
11.2 Documentation Support
11.2.1 Related Documentation
These references, additional design tools, and links to additional references, including design software and
models may be found on the web at www.power.ti.com under Technical Documents.
1. Design Spreadsheet, UCC28019A Design Calculator, SLUC117
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
44
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC28019AD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
28019A
UCC28019ADR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
28019A
UCC28019AP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
28019A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28019ADR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28019ADR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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