Texas Instruments | TLV431x-Q1 Low-Voltage Adjustable Precision Shunt Regulator (Rev. A) | Datasheet | Texas Instruments TLV431x-Q1 Low-Voltage Adjustable Precision Shunt Regulator (Rev. A) Datasheet

Texas Instruments TLV431x-Q1 Low-Voltage Adjustable Precision Shunt Regulator (Rev. A) Datasheet
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TLV431A-Q1, TLV431B-Q1
SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
TLV431x-Q1 Low-Voltage Adjustable Precision Shunt Regulator
1 Features
3 Description
•
•
The TLV431 device is a low-voltage 3-terminal
adjustable voltage reference with specified thermal
stability over applicable industrial and commercial
temperature ranges. Output voltage can be set to
1.24V on stand alone mode or any value between
VREF (1.24 V) and 6 V with two external resistors (see
Figure 23). These devices operate from a lower
voltage (1.24 V) than the widely used TL431 and
TL1431 shunt-regulator references.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: -40°C to 125°C
Ambient Operating Temperature Range
Low-Voltage Operation, VREF = 1.24 V
Adjustable Output Voltage, VO = VREF to 6 V
Reference Voltage Tolerances at 25°C
– 0.5% for TLV431B
– 1% for TLV431A
Typical Temperature Drift
– 11 mV (–40°C to 125°C)
Low Operational Cathode Current, 80 µA Typ
0.25-Ω Typical Output Impedance
See TLVH431 and TLVH432 for:
– Wider VKA (1.24 V to 18 V) and IK (80 mA)
– Multiple Pinouts for SOT-23-3 and SOT-89
Packages
Device Information(1)
PART NUMBER
TLV431x-Q1
2 Applications
•
•
•
•
•
When used with an optocoupler, the TLV431 device
is an ideal voltage reference in isolated feedback
circuits for 3-V to 3.3-V switching-mode power
supplies. These devices have a typical output
impedance of 0.25 Ω. Active output circuitry provides
a very sharp turn-on characteristic, making them
excellent replacements for low-voltage Zener diodes
in many applications, including on-board regulation
and adjustable power supplies.
Adjustable Voltage and Current Referencing
Secondary Side Regulation in Flyback SMPSs
Zener Replacement
Voltage Monitoring
Comparator with Integrated Reference
PACKAGE (PIN)
BODY SIZE (NOM)
SOT-23 (3)
2.90 mm x 1.30 mm
SOT-23 (5)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VO
Input
IK
VREF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV431A-Q1, TLV431B-Q1
SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics for TLV431A-Q1 ...............
Electrical Characteristics for TLV431B-Q1 ...............
Typical Characteristics ..............................................
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
9
Applications and Implementation ...................... 18
9.1 Application Information............................................ 18
9.2 Typical Applications ................................................ 19
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Original (December 2008) to Revision A
Page
•
Added Automotive AEC-Q100 feature ................................................................................................................................... 1
•
Added New typical curves ................................................................................................................................................... 15
2
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SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
DBZ (SOT-23-3) PACKAGE
(TOP VIEW)
DBV (SOT-23-5) PACKAGE
(TOP VIEW)
NC 1
w 2
CATHODE 3
ANODE
5
REF
1
CATHODE
2
3
REF
4
ANODE
NCíNo internal connection
w For TLV431A: NC í No internal connection
w For TLV431B: Pin 2 is attached to Substrate and
must be connected to ANODE or left open.
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
DBZ
DBV
CATHODE
2
3
I/O
REF
1
4
I
Threshold relative to common anode
ANODE
3
5
O
Common pin, normally connected to ground
NC
—
1
I
No Internal Connection
*
—
2
I
Substrate Connection
Shunt Current/Voltage input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VKA
Cathode voltage (2)
IK
Continuous cathode current range
Iref
Reference current range
MAX
V
–20
20
mA
–0.05
3
mA
150
°C
150
°C
Operating virtual junction temperature
Tstg
(1)
(2)
Storage temperature range
UNIT
7
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the anode terminal, unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Thermal Information
TLV431x
THERMAL METRIC
(1)
DBV
DBZ
5 PINS
3 PINS
RθJA
Junction-to-ambient thermal resistance
206
206
RθJC(top)
Junction-to-case (top) thermal resistance
131
76
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VKA
Cathode voltage
VREF
6
V
IK
Cathode current
0.1
15
mA
TA
Operating free-air temperature range
–40
125
°C
4
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TLV431x-Q1
UNIT
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SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
6.5 Electrical Characteristics for TLV431A-Q1
at 25°C free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
1.228
1.24
1.252
TA = full range (1)
(see Figure 22)
1.209
VREF
Reference voltage
VKA = VREF,
IK = 10 mA
VREF(dev)
VREF deviation over full
temperature range (2)
VKA = VREF, IK = 10 mA (1)
(see Figure 22)
Ratio of VREF change in cathode
voltage change
Iref
Reference terminal current
Iref(dev)
Iref deviation over full temperature IK = 10 mA, R1 = 10 kΩ,
range (2)
R2 = open (1) (see Figure 23)
IK(min)
Minimum cathode current for
regulation
VKA = VREF (see Figure 22)
IK(off)
Off-state cathode current
VREF = 0, VKA = 6 V (see Figure 24)
DVREF
DVKA
|zKA|
(1)
(2)
Dynamic impedance
(3)
TLV431AQ
UNIT
V
1.271
11
31
VKA = VREF to 6 V, IK = 10 mA
(see Figure 23)
–1.5
–2.7
mV/V
IK = 10 mA, R1 = 10 kΩ,
R2 = open
(see Figure 23)
0.15
0.5
µA
0.15
0.5
µA
55
100
µA
0.001
0.1
µA
0.25
0.4
Ω
VKA = VREF, f ≤ 1 kHz, IK = 0.1 mA to 15 mA
(see Figure 22)
mV
Full temperature range is –40°C to 125°C for TLV431x-Q1.
The deviation parameters VREF(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage, αVREF, is defined as:
VREF(dev )
æ
ö
6
ç
÷ ´ 10
=
°
V
T
25
C
(
)
ppm
æ
ö = è REF A
ø
aVREF ç
÷
DTA
è °C ø
where ΔTA is the rated operating free-air temperature range of the device.
αVREF can be positive or negative, depending on whether minimum VREF or maximum VREF, respectively, occurs at the lower
temperature.
(3)
DVKA
The dynamic impedance is defined as zka =
DIK
spacer
When the device is operating with two external resistors (see Figure 23), the total dynamic impedance of the circuit is defined as:
z ka
¢=
DV
DI
»
z ka
æ
è
´ ç1 +
R1 ö
÷
R2 ø
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6.6 Electrical Characteristics for TLV431B-Q1
at 25°C free-air temperature (unless otherwise noted)
PARAMETER
TLV431BQ
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
1.234
1.24
1.246
TA = full range (1)
(see Figure 22)
1.221
VREF
Reference voltage
VKA = VREF,
IK = 10 mA
VREF(dev)
VREF deviation over full temperature
range (2)
VKA = VREF , IK = 10 mA (1)
(see Figure 22)
Ratio of VREF change in cathode
voltage change
VKA = VREF to 6 V, IK = 10 mA
(see Figure 23)
Iref
Reference terminal current
Iref(dev)
UNIT
V
1.265
11
31
–1.5
–2.7
mV/V
IK = 10 mA, R1 = 10 kΩ,
R2 = open
(see Figure 23)
0.1
0.5
µA
Iref deviation over full temperature
range (2)
IK = 10 mA, R1 = 10 kΩ,
R2 = open
(see Figure 23)
0.15
0.5
µA
IK(min)
Minimum cathode current for
regulation
VKA = VREF (see Figure 22)
55
100
µA
IK(off)
Off-state cathode current
VREF = 0, VKA = 6 V (see Figure 24)
0.001
0.1
µA
Dynamic impedance (3)
VKA = VREF, f ≤ 1 kHz, IK = 0.1 mA to 15 mA
(see Figure 22)
0.25
0.4
Ω
DVREF
DVKA
|zKA|
(1)
(2)
mV
Full temperature range is –40°C to 125°C for TLV431x-Q1.
The deviation parameters VREF(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage, αVREF, is defined as:
VREF(dev )
æ
ö
6
ç
÷ ´ 10
=
°
V
T
25
C
(
)
ppm
æ
ö = è REF A
ø
aVREF ç
÷
DTA
è °C ø
where ΔTA is the rated operating free-air temperature range of the device.
αVREF can be positive or negative, depending on whether minimum VREF or maximum VREF, respectively, occurs at the lower
temperature.
(3)
DVKA
The dynamic impedance is defined as zka =
DIK
spacer
When the device is operating with two external resistors (see Figure 23), the total dynamic impedance of the circuit is defined as:
z ka
6
¢=
DV
DI
»
z ka
æ
è
´ ç1 +
R1 ö
÷
R2 ø
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6.7 Typical Characteristics
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
250
1.254
IK = 10 mA
R1 = 10 kΩ
R2 = Open
IK = 10 mA
I ref − Reference Input Current − nA
V ref − Reference Voltage − V
1.252
1.250
1.248
1.246
1.244
1.242
1.240
1.238
− 50
− 25
0
25
50
75
100
125
200
150
100
50
− 50
150
− 25
TJ − Junction Temperature − °C
150
Figure 2. Reference Current vs
Free- air Temperature (TLV431A)
Figure 1. Reference Voltage vs
Junction Temperature
15
250
VKA = VREF
TA = 25°C
IK = 10 mA
R1 = 10 kΩ
R2 = Open
230
210
10
I K − Cathode Current − mA
I ref − Reference Input Current − nA
0
25
50
75 100 125
TJ − Junction Temperature − °C
190
170
150
130
110
90
5
0
−5
−10
70
50
−50
−25
0
25
50
75
100
125
−15
−1
150
TJ − Junction Temperature − °C
250
200
1.5
VKA = VREF
TA = 25°C
150
I K − Cathode Current − µ A
Ik(min)
0
0.5
1
VKA − Cathode Voltage − V
Figure 4. Cathode Current vs
Cathode Voltage
Figure 3. Reference Input Current vs
Junction Temperature (for TLV431B)
120
115
110
105
100
95
90
85
80
75
70
65
60
55
-40
−0.5
100
50
0
−50
− 100
− 150
− 200
-20
0
20
40
60
80
Temperature (qC)
100
120
140
Figure 5. Minimum Cathode Current (µA) vs Temperature
− 250
−1
− 0.5
0
0.5
1
VKA − Cathode Voltage − V
1.5
Figure 6. Cathode Current vs
Cathode Voltage
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
3000
VKA = 5 V
VREF = 0
I K(off) − Off-State Cathode Current − nA
I K(off) − Off-State Cathode Current − nA
40
30
20
10
0
− 50
−25
0
25
50
75
100
125
VKA = 6 V
VREF = 0
2500
2000
1500
1000
500
0
−50
150
−25
0
Figure 7. Off-State Cathode Current vs
Junction Temperature for TLV431A
∆V ref/ ∆V KA − Ratio of Delta Reference Voltage
to Delta Cathode Voltage − mV/V
∆V ref/ ∆V KA − Ratio of Delta Reference Voltage
to Delta Cathode Voltage − mV/V
75
100
125
150
0.0
0
− 0.1
− 0.2
− 0.3
− 0.4
− 0.5
− 0.6
− 0.8
− 50
50
Figure 8. Off-State Cathode Current vs
Junction Temperature for TLV431B
0
− 0.7
25
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
IK = 10 mA
∆VKA = VREF to 6 V
− 25
0
25
50
75
100
125
150
−0.1
IK = 10 mA
∆VKA = VREF to 6 V
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1
−1.0
−50
−25
TJ − Junction Temperature − °C
0
25
50
75
100
125
150
TJ − Junction Temperature − °C
Figure 9. Ratio of Delta Reference Voltage to
Delta Cathode Voltage vs
Junction Temperature for TLV431A
Figure 10. Ratio of Delta Reference Voltage to
Delta Cathode Voltage vs
Junction Temperature (for TLV431B)
0.025
V ref − %
Percentage Change in Vref
IK = 1 mA
% Change (avg)
−0.025
% Change (3δ )
−0.05
−0.075
−0.1
% Change (−3δ)
−0.125
0
10
20
30
40
50
60
Operating Life at 55°C − kh‡
‡
Extrapolated from life-test data taken at 125°C; the activation energy assumed is 0.7 eV.
Figure 11. Percentage Change in VREF vs
Operating Life at 55°C
8
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
Vn − Equivalent Input Noise Voltage − nV/ Hz
3V
VKA = VREF
IK = 1 mA
TA = 25°C
1 kΩ
300
+
470 µF
750 Ω
2200 µF
+
250
TLV431
or
TLV431A
or
TLV431B
200
TLE2027
+
_
TP
820 Ω
160 kΩ
160 Ω
TEST CIRCUIT FOR EQUIVALENT INPUT NOISE VOLTAGE
150
10
100
1k
10k
100k
f − Frequency − Hz
Figure 12. Equivalent Input Noise Voltage
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
EQUIVALENT INPUT NOISE VOLTAGE
OVER A 10-s PERIOD
Vn − Equivalent Input Noise Voltage − µ V
10
f = 0.1 Hz to 10 Hz
IK = 1 mA
TA = 25°C
8
6
4
2
0
−2
−4
−6
−8
−10
0
2
4
6
8
10
t − Time − s
3V
1 kΩ
+
470 µF
750 Ω
0.47 µF
2200 µF
+
820 Ω
TLV431
or
TLV431A
or
TLV431B
TLE2027
10 kΩ
+
_
160 kΩ
TLE2027
+
_
10 kΩ
2.2 µF
+
1 µF
TP
CRO 1 MΩ
33 kΩ
16 Ω
0.1 µF
33 kΩ
TEST CIRCUIT FOR 0.1-Hz TO 10-Hz EQUIVALENT NOISE VOLTAGE
Figure 13. Equivalent Noise Voltage
over a 10s Period
10
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Typical Characteristics (continued)
80
0°
IK = 10 mA
TA = 25°C
70
36°
60
72°
50
108°
40
144°
30
180°
Phase Shift
A V − Small-Signal Voltage Gain/Phase Margin − dB
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
SMALL-SIGNAL VOLTAGE GAIN/PHASE MARGIN
vs
FREQUENCY µF
Output
IK
6.8 kΩ
180 Ω
10
5V
4.3 kΩ
20
10
GND
0
−10
−20
100
TEST CIRCUIT FOR VOLTAGE GAIN
AND PHASE MARGIN
1k
10k
100k
1M
f − Frequency − Hz
Figure 14. Voltage Gain and Phase Margin
REFERENCE IMPEDANCE
vs
FREQUENCY
100
|z ka | − Reference Impedance − Ω
IK = 0.1 mA to 15 mA
TA = 25°C
100 Ω
Output
10
IK
100 Ω
1
−
+
GND
0.1
TEST CIRCUIT FOR REFERENCE IMPEDANCE
0.01
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 15. Reference Impedance vs Frequency
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
PULSE RESPONSE 1
3.5
3
Input and Output Voltage − V
R = 18 kΩ
TA = 25°C
Input
18 kΩ
Output
2.5
Ik
2
1.5
Pulse
Generator
f = 100 kHz
Output
50 Ω
1
GND
0.5
0
TEST CIRCUIT FOR PULSE RESPONSE 1
− 0.5
0
1
2
3
4
5
6
7
8
t − Time − µs
Figure 16. Pulse Response 1
PULSE RESPONSE 2
3.5
3
Input and Output Voltage − V
R = 1.8 kΩ
TA = 25°C
Input
1.8 kΩ
Output
2.5
IK
2
1.5
Pulse
Generator
f = 100 kHz
Output
50 Ω
1
GND
0.5
0
TEST CIRCUIT FOR PULSE RESPONSE 2
−0.5
0
1
2
3
4
5
6
7
8
t − Time − µs
Figure 17. Pulse Response 2
12
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
STABILITYBOUNDARYCONDITION Á
150 Ÿ
(for TLV431A-Q1)
IK
TA = 25°C
+
IK = 15 mA Max
CL
IK íCathode CurrentímA
Stable
Vbat
í
VKA =V REF
12
Stable
TEST CIRCUIT FOR VKA =VREF
150 Ÿ
VKA = 2 V
IK
+
R1 = 10 kŸ
CL
í
R2
3
Vbat
VKA = 3 V
TEST CIRCUIT FOR V
KA
= 2 V, 3 V
CL í Load Capacitance í µF
‡
The areas under the curves represent conditions that may cause the device to oscillate. For VKA = 2-V and 3-V curves, R2 and Vbat were
adjusted to establish the initial VKA and IK conditions with CL = 0. Vbat and CL then were adjusted to determine the ranges of stability.
Figure 18. Stability Boundary Conditions
IK
Figure 19. Phase Margin vs Capacitive Load VKA = VREF (1.25 V), TA= 25°C (For TLV431B-Q1)
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Typical Characteristics (continued)
Operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions
table are not implied.
IK
Figure 20. Phase Margin vs Capacitive Load VKA = 2.50 V, TA= 25°C (For TLV431B-Q1)
IK
Figure 21. Phase Margin vs Capacitive Load VKA = 5.00 V, TA= 25°C (For TLV431B-Q1)
14
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7 Parameter Measurement Information
VO
Input
IK
VREF
Figure 22. Test Circuit for VKA = VREF, VO = VKA = VREF
xxx
xxx
xxx
Input
VO
IK
R1
R2
Iref
VREF
Figure 23. Test Circuit for VKA > VREF, VO = VKA = VREF × (1 + R1/R2) + Iref × R1
xxx
xxx
xxx
Input
VO
IK(off)
Figure 24. Test Circuit for IK(off)
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8 Detailed Description
8.1 Overview
TLV431 is a low power counterpart to TL431, having lower reference voltage (1.24 V vs 2.5 V) for lower voltage
adjustability and lower minimum cathode current (Ik(min)=100 µA vs 1 mA). Like TL431, the TLV431 is used in
conjunction with it's key components to behave as a single voltage reference, error amplifier, voltage clamp or
comparator with integrated reference.
TLV431 can be operated and adjusted to cathode voltages from 1.24V to 6V, making this part optimum for a
wide range of end equipments in industrial, auto, telecom & computing. In order for this device to behave as a
shunt regulator or error amplifier, > 100 µA (Imin(max)) must be supplied in to the cathode pin. Under this
condition, feedback can be applied from the Cathode and Ref pins to create a replica of the internal reference
voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5%, and 1%. These
reference options are denoted by B (0.5%) and A (1.0%) after the TLV431x-Q1.
The TLV431x-Q1 devices are characterized for operation from –40°C to 125°C.
8.2 Functional Block Diagram
CATHODE
+
REF
_
Vref
ANODE
8.3 Feature Description
TLV431 consists of an internal reference and amplifier that outputs a sink current base on the difference between
the reference pin and the virtual internal pin. The sink current is produced by an internal darlington pair.
When operated with enough voltage headroom (≥ 1.24 V) and cathode current (Ika), TLV431 forces the
reference pin to 1.24 V. However, the reference pin can not be left floating, as it needs Iref ≥ 0.5 µA (please see
the Functional Block Diagram). This is because the reference pin is driven into an npn, which needs base current
in order operate properly.
When feedback is applied from the Cathode and Reference pins, TLV431 behaves as a Zener diode, regulating
to a constant voltage dependent on current being supplied into the cathode. This is due to the internal amplifier
and reference entering the proper operating regions. The same amount of current needed in the above feedback
situation must be applied to this device in open loop, servo or error amplifying implementations in order for it to
be in the proper linear region giving TLV431 enough gain.
Unlike many linear regulators, TLV431 is internally compensated to be stable without an output capacitor
between the cathode and anode. However, if it is desired to use an output capacitor Figure 18 can be used as a
guide to assist in choosing the correct capacitor to maintain stability.
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8.4 Device Functional Modes
8.4.1 Open Loop (Comparator)
When the cathode/output voltage or current of TLV431 is not being fed back to the reference/input pin in any
form, this device is operating in open loop. With proper cathode current (Ika) applied to this device, TLV431 will
have the characteristics shown in Figure 6. With such high gain in this configuration, TLV431 is typically used as
a comparator. With the reference integrated makes TLV431 the preferred choice when users are trying to
monitor a certain level of a single signal.
8.4.2 Closed Loop
When the cathode/output voltage or current of TLV431 is being fed back to the reference/input pin in any form,
this device is operating in closed loop. The majority of applications involving TLV431 use it in this manner to
regulate a fixed voltage or current. The feedback enables this device to behave as an error amplifier, computing
a portion of the output voltage and adjusting it to maintain the desired regulation. This is done by relating the
output voltage back to the reference pin in a manner to make it equal to the internal reference voltage, which can
be accomplished via resistive or direct feedback.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 25 shows the TLV431A, or TLV431B used in a 3.3-V isolated flyback supply. Output voltage VO can be as
low as reference voltage VREF (1.24 V ± 1%). The output of the regulator, plus the forward voltage drop of the
optocoupler LED (1.24 + 1.4 = 2.64 V), determine the minimum voltage that can be regulated in an isolated
supply configuration. Regulated voltage as low as 2.7 Vdc is possible in the topology shown in Figure 25.
The 431 family of devices are prevalent in these applications, being designers go to choice for secondary side
regulation. Due to this prevalence, this section will further go on to explain operation and design in both states of
TLV431 that this application will see, open loop (Comparator + Vref) & closed loop (Shunt Regulator).
Further information about system stability and using a TLV431 device for compensation can be found in the
application note Compensation Design With TL431 for UCC28600, SLUA671.
~
VI
120 V
−
+
P
~
VO
3.3 V
P
P
Gate Drive
VCC
Controller
VFB
TLV431
or
TLV431A
or
TLV431B
Current
Sense
GND
P
P
P
P
Figure 25. Flyback With Isolation Using TLV431, TLV431A, or TLV431B
as Voltage Reference and Error Amplifier
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9.2 Typical Applications
9.2.1 Comparator with Integrated Reference (Open Loop)
Vsup
Rsup
Vout
CATHODE
R1
RIN
VIN
REF
VL
+
R2
1.24 V
ANODE
Figure 26. Comparator Application Schematic
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage Range
0 V to 5 V
Input Resistance
10 kΩ
Supply Voltage
5V
Cathode Current (Ik)
500 µA
Output Voltage Level
~1 V - Vsup
Logic Input Thresholds VIH/VIL
VL
9.2.1.2 Detailed Design Procedure
When using TLV431 as a comparator with reference, determine the following:
• Input voltage range
• Reference voltage accuracy
• Output logic input high and low level thresholds
• Current source resistance
9.2.1.2.1 Basic Operation
In the configuration shown in Figure 26 TLV431 will behave as a comparator, comparing the Vref pin voltage to
the internal virtual reference voltage. When provided a proper cathode current (Ik), TLV431 will have enough
open loop gain to provide a quick response. With the TLV431's min Operating Current maximum (Imin) being 55
uA to 100 uA over temperature, operation below that could result in low gain, leading to a slow response.
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9.2.1.2.2 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage will be within the range of 1.24V ±(0.5% or 1.0% ) depending on which version is being used.
The more overdrive voltage provided, the faster the TLV431 will respond. This can be seen in figures Figure 27
and Figure 28, where it displays the output responses to various input voltages.
For applications where TLV431 is being used as a comparator, it is best to set the trip point to greater than the
positive expected error (i.e. +1.0% for the A version). For fast response, setting the trip point to > 10% of the
internal Vref should suffice.
For minimal voltage drop or difference from Vin to the ref pin, it is recommended to use an input resistor < 10 kΩ
to provide Iref.
9.2.1.2.3 Output Voltage and Logic Input Level
In order for TLV431 to properly be used as a comparator, the logic output must be readable by the recieving
logic device. This is accomplished by knowing the input high and low level threshold voltage levels, typically
denoted by VIH & VIL.
As seen in Figure 27, TLV431's output low level voltage in open-loop/comparator mode is ~1 V, which is
sufficient for some 3.3V supplied logic. However, would not work for 2.5 V and 1.8 V supplied logic. In order to
accommodate this a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible
to the receiving low voltage logic device.
TLV431's output high voltage is approximately Vsup due to TLV431 being open-collector. If Vsup is much higher
than the receiving logic's maximum input voltage tolerance, the output must be attenuated to accommodate the
outgoing logic's reliability.
When using a resistive divider on the output, be sure to make the sum of the resistive divider (R1 & R2 in
Figure 26) is much greater than Rsup in order to not interfere with TLV431's ability to pull close to Vsup when
turning off.
9.2.1.2.3.1 Input Resistance
TLV431 requires an input resistance in this application in order to source the reference current (Iref) needed from
this device to be in the proper operating regions while turning on. The actual voltage seen at the ref pin will be
Vref=Vin-Iref*Rin. Since Iref can be as high as 0.5 µA it is recommended to use a resistance small enough that will
mitigate the error that Iref creates from Vin.
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-0.4
10
Vin~1.24V (+/-5%)
Vo(Vin=1.18V)
Vo(Vin=1.24V)
Vo(Vin=1.30V)
9
7
6
5
4
3
2
1
0
-1
-0.2
0
0.2
0.4
Time (ms)
0.6
-2
-0.4
0.8
Submit Documentation Feedback
-0.2
0
D001
Figure 27. Output Response with Small Overdrive Voltages
20
Vo(Vin=5.0V)
Vin=5.0V
8
Voltage (V)
Voltage (V)
9.2.1.3 Application Curves
0.2
0.4
Time (ms)
0.6
0.8
D001
Figure 28. Output Response with Large Overdrive Voltage
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SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
9.2.2 Shunt Regulator/Reference
VSUP
RSUP
VO = ( 1 +
R1
0.1%
CATHODE
REF
Vr ef
R1
) Vref
R2
R2
0.1%
TL431
ANODE
CL
Figure 29. Shunt Regulator Schematic
9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Reference Initial Accuracy
1.0%
Supply Voltage
6V
Cathode Current (Ik)
1 mA
Output Voltage Level
1.24 V - 6 V
Load Capacitance
100 nF
Feedback Resistor Values and Accuracy (R1 & R2)
10 kΩ
9.2.2.2 Detailed Design Procedure
When using TLV431 as a Shunt Regulator, determine the following:
• Input voltage range
• Temperature range
• Total accuracy
• Cathode current
• Reference initial accuracy
• Output capacitance
9.2.2.2.1
Programming Output/Cathode Voltage
In order to program the cathode voltage to a regulated voltage a resistive bridge must be shunted between the
cathode and anode pins with the mid point tied to the reference pin. This can be seen in Figure 29, with R1 & R2
being the resistive bridge. The cathode/output voltage in the shunt regulator configuration can be approximated
by the equation shown in Figure 29. The cathode voltage can be more accuratel determined by taking in to
account the cathode current:
VO=(1+R1/R2)*Vref–Iref*R1
In order for this equation to be valid, TLV431 must be fully biased so that it has enough open loop gain to
mitigate any gain error. This can be done by meeting the Imin spec denoted in Recommended Operating
Conditions table.
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9.2.2.2.2 Total Accuracy
When programming the output above unity gain (Vka=Vref), TLV431 is susceptible to other errors that may effect
the overall accuracy beyond Vref. These errors include:
•
•
•
•
R1 and R2 accuracies
VI(dev) - Change in reference voltage over temperature
ΔVref / ΔVKA - Change in reference voltage to the change in cathode voltage
|zKA| - Dynamic impedance, causing a change in cathode voltage with cathode current
Worst case cathode voltage can be determined taking all of the variables in to account. Application note
SLVA445 assists designers in setting the shunt voltage to achieve optimum accuracy for this device.
9.2.2.2.3 Stability
Though TLV431 is stable with no capacitive load, the device that receives the shunt regulator's output voltage
could present a capacitive load that is within the TLV431 region of stability, shown in Figure 18. Also, designers
may use capacitive loads to improve the transient response or for power supply decoupling.
Voltage (V)
9.2.2.3 Application Curves
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
Vsup
Vka=Vref
R1=10k: & R2=10k:
0
1
2
3
4
5
Time (Ps)
6
7
8
9
D001
Figure 30. TLV431 Start-Up Response
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SLVS905A – DECEMBER 2008 – REVISED OCTOBER 2017
10 Power Supply Recommendations
When using TLV431 as a Linear Regulator to supply a load, designers will typically use a bypass capacitor on
the output/cathode pin. When doing this, be sure that the capacitance is within the stability criteria shown in
Figure 18.
In order to not exceed the maximum cathode current, be sure that the supply voltage is current limited. Also, be
sure to limit the current being driven into the Ref pin, as not to exceed it's absolute maximum rating.
For applications shunting high currents, pay attention to the cathode and anode trace lengths, adjusting the width
of the traces to have the proper current density.
11 Layout
11.1 Layout Guidelines
Place decoupling capacitors as close to the device as possible. Use appropriate widths for traces when shunting
high currents to avoid excessive voltage drops.
11.2 Layout Example
DBZ
(TOP VIEW)
Rref
Vin
REF
1
Rsup
Vsup
ANODE
3
CATHODE
2
GND
CL
GND
Figure 31. DBZ Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV431A-Q1
Click here
Click here
Click here
Click here
Click here
TLV431B-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV431AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VONQ
TLV431BQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOMQ
TLV431BQDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOQQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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19-Oct-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV431A-Q1, TLV431B-Q1 :
• Catalog: TLV431A, TLV431B
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TLV431AQDBVRQ1
SOT-23
DBV
5
3000
179.0
8.4
TLV431BQDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
3.2
TLV431BQDBZRQ1
SOT-23
DBZ
3
3000
180.0
8.4
3.15
Pack Materials-Page 1
3.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
3.2
1.4
4.0
8.0
Q3
2.95
1.22
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV431AQDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
TLV431BQDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
TLV431BQDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
Pack Materials-Page 2
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
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EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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