Texas Instruments | TPS79901-EP 200-mA, Low-Quiescent Current, Ultra-Low-Noise, High-PSRR Low-Dropout Linear Regulator (Rev. A) | Datasheet | Texas Instruments TPS79901-EP 200-mA, Low-Quiescent Current, Ultra-Low-Noise, High-PSRR Low-Dropout Linear Regulator (Rev. A) Datasheet

Texas Instruments TPS79901-EP 200-mA, Low-Quiescent Current, Ultra-Low-Noise, High-PSRR Low-Dropout Linear Regulator (Rev. A) Datasheet
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TPS79901-EP
SBVS330A – SEPTEMBER 2017 – REVISED OCTOBER 2017
TPS79901-EP 200-mA, Low-Quiescent Current, Ultra-Low-Noise, High-PSRR
Low-Dropout Linear Regulator
1 Features
2 Applications
•
•
•
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•
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•
1
•
•
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•
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200-mA Low-Dropout Regulator With EN
Multiple Output Voltage Versions Available:
– Adjustable Outputs from 1.2 V to 6.5 V
Inrush Current Protection with EN Toggle
Low IQ: 40 μA
High PSRR:
– 66 dB at 1 kHz
– 51 dB at 10 kHz
Stable with a Low-ESR, 2-μF Typical Output
Capacitance
Excellent Load and Line Transient Response
2% Overall Accuracy (Load, Line, and
Temperature)
Very Low Dropout: 100 mV
Package: 6-Pin SON
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
Base Stations
Smart Phones
EPOS
Wearable Electronics
VCOs, RF
Wireless LAN, Bluetooth®
3 Description
The TPS79901 family of low-dropout (LDO), lowpower linear regulators offers excellent ac
performance with very low ground current. High
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
response are provided while consuming a very low
40-μA (typical) ground current.
The TPS79901 is stable with ceramic capacitors and
uses an advanced BiCMOS fabrication process to
yield a dropout voltage of typically 100 mV at a
200-mA output. The TPS79901 uses a precision
voltage reference and feedback loop to achieve an
overall accuracy of 2% over all load, line, process,
and temperature variations. The TPS79901 features
inrush current protection when the EN toggle is used
to start the device, immediately clamping the current.
The TPS79901 is fully specified over the temperature
range of TJ = –55°C to +125°C, and offered in a lowprofile, ideal for wireless handsets and WLAN cards.
Device Information(1)
PART NUMBER
TPS79901-EP
PACKAGE
SON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Circuit
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT =
OUT
TPS79901
EN
GND
(R1 + R2)
R2
´ 1.193
VOUT
R1
FB
CFB
2.2 mF
Ceramic
R2
VEN
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS79901-EP
SBVS330A – SEPTEMBER 2017 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
8.3 Do's and Don'ts ....................................................... 16
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2017) to Revision A
Page
•
Changed content in Features section..................................................................................................................................... 1
•
Changed content in Description section ................................................................................................................................. 1
•
Deleted NR from the Pin Functions table ............................................................................................................................... 3
•
Changed HBM value from ±2000 : to ±1500 in the ESD Ratings section.............................................................................. 4
•
Deleted errant part numbers from the Electrical Characteristics section ............................................................................... 5
•
Deleted errant part numbers from the Typical Characteristics section .................................................................................. 7
2
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SBVS330A – SEPTEMBER 2017 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
DRV Package
6-Pin SON With Exposed Thermal Pad
Top View
OUT
1
FB
2
GND 3
6
GND
IN
5
N/C
4
EN
Pin Functions
PIN
NAME
IN
NO.
I/O
DESCRIPTION
6
I
3, Pad
—
EN
4
I
Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
FB
2
I
Adjustable voltage version only. Feedback; this pin is the input to the control loop error amplifier and
sets the output voltage of the device.
OUT
1
O
Output of the regulator. To assure stability, a small ceramic capacitor (total typical capacitance ≥ 2
μF) is required from this pin to ground.
N/C
5
—
Not internally connected. This pin must either be left open or tied to GND.
GND
Input supply.
Ground. The pad must be tied to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage (2)
Current
Temperature
(1)
(2)
MIN
MAX
IN
–0.3
7
EN
–0.3
VIN + 0.3
OUT
–0.3
VIN + 0.3
OUT
Internally limited
Operating virtual junction, TJ
–55
150
Storage temperature range, Tstg
–55
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage (1)
2.7
6.5
V
IOUT
Output current
0.5
200
mA
TJ
Operating junction temperature
–55
125
°C
(1)
Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
6.4 Thermal Information
TPS799
THERMAL METRIC (1)
DRV (SON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
74.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.8
°C/W
RθJB
Junction-to-board thermal resistance
145.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
54.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
at TJ = –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
VFB
Internal reference
VOUT
Output voltage range
TEST CONDITIONS
1.169
VFB
Output accuracy, nominal
TJ = 25°C
–1%
Output accuracy (1)
over VIN, IOUT, temperature
VOUT + 0.3 V ≤ VIN ≤ 6.5 V
500 μA ≤ IOUT ≤ 200 mA
–2%
(1)
VOUT(NOM) + 0.3 V ≤ VIN ≤ 6.5 V
Line regulation
ΔVO(ΔIO)
Load regulation
500 μA ≤ IOUT ≤ 200 mA
VDO
Dropout voltage (2)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 200 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
IGND
Ground pin current
500 μA ≤ IOUT ≤ 200 mA
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4 V, 2.7 V ≤ VIN ≤ 6.5 V
IFB
Feedback pin current
Vn
Power-supply rejection ratio
VIN = 3.85 V,
VOUT = 2.85 V,
CNR = 0.01 μF,
IOUT = 100 mA
Output noise voltage
BW = 10 Hz to 100 kHz,
VOUT = 2.85 V
Start-up time
VOUT = 2.85 V,
RL = 14 Ω,
COUT = 2.2 μF
VEN(LO)
Enable low (shutdown)
IEN(HI)
Enable pin current, enabled
VEN = VIN = 6.5 V
UVLO
Undervoltage lockout
VIN rising
UVLO hysteresis
VIN falling
(1)
(2)
MAX
UNIT
6.5
V
1.217
V
6.5 – VDO
V
1%
±1%
2%
0.02
%/V
0.002
%/mA
VOUT(nom) ≤ 3.3 V
100
175
VOUT(nom) ≥ 3.3 V
90
160
400
600
mA
40
60
μA
0.15
1
μA
0.5
µA
220
f = 100 Hz
70
f = 1 kHz
66
f = 10 kHz
51
f = 100 kHz
38
CNR = 0.01 μF
μVRMS
94 × VOUT
CNR = 0.001 μF
45
CNR = 0.047 μF
45
CNR = 0.01 μF
50
mV
dB
10.5 × VOUT
CNR = none
CNR = none
Enable high (enabled)
Thermal shutdown temperature
1.193
–0.5
VEN(HI)
Tsd
TYP
2.7
ΔVO(ΔVI)
PSRR
MIN
μs
50
1.2
VIN
0
1.90
V
0.4
V
0.03
1
μA
2.20
2.65
V
70
Shutdown, temperature increasing
165
Reset, temperature decreasing
145
mV
°C
Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
VDO is not measured for VOUT(nom) < 2.8 V because minimum VIN = 2.7 V.
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1000000
Electromigration Fail Mode
Estimated Life (hrs)
100000
10000
1000
100
80
90
100
110
120
Continuous Junction Temperature TJ (qC)
130
140
D008
(1)
See data sheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
Enhanced plastic product disclaimer applies.
Figure 1. TPS79901-EP Derating Chart
6
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6.6 Typical Characteristics
at TJ= –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
1
TJ = 55qC
TJ = 40qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
-5
0.8
0.6
Change in VOUT (%)
Change in VOUT (mV)
0
-10
0.4
0.2
0
-0.2
-0.4
TJ = 55qC
TJ = 40qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
-0.6
-0.8
-15
0
50
100
IOUT (mA)
150
-1
2.5
200
3.5
Figure 2. Load Regulation
6.5
7.5
D002
Figure 3. Line Regulation
140
IOUT = 200mA
IOUT = 100mA
IOUT = 1mA
1.5
TJ = 55qC
TJ = 40qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
120
1
100
0.5
VDO (mV)
Change in VOUT (%)
5.5
VIN (V)
2
0
-0.5
80
60
40
-1
20
-1.5
-2
-55 -40 -25 -10
0
5
20
35 50
TJ (qC)
65
80
0
95 110 125
Figure 4. Output Voltage vs Junction Temperature
100
IOUT (mA)
150
200
D004
Figure 5. Dropout Voltage vs Output Current
110
IOUT = 200mA
IOUT = 100mA
IOUT = 1mA
180
160
100
90
80
120
70
VDO (mV)
140
100
80
60
50
60
40
40
30
20
20
0
10
-20
-55 -40 -25 -10
50
D003
200
VOD (mV)
4.5
D001
0
5
20
35 50
TJ (qC)
65
80
95 110 125
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
D005
VIN (V)
IOUT = 200 mA
Figure 6. Dropout Voltage vs Junction Temperature
Figure 7. Dropout vs Input Voltage
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Typical Characteristics (continued)
at TJ= –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
60
60
50
50
IOUT = 200 mA
40
IOUT = 500 mA
IGND (PA)
IGND (mA)
40
30
20
30
20
10
VIN = 2.7 V
VIN = 3.2 V
VIN = 5 V
10
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
-55 -40 -25 -10
7.0
5
VIN (V)
20
35 50
TJ (qC)
65
80
95 110 125
D006
VOUT = 2.85 V
Figure 9. Ground Pin Current vs Junction Temperature
Figure 8. Ground Pin Current vs Input Voltage
90
600
500
VIN = 3.2 V
VIN = 6.5 V
I OUT = 1mA
70
PSRR (dB)
400
IGND (nA)
I OUT = 100mA
80
300
60
IOUT = 200mA
50
40
30
200
20
100
10
0
-55 -40 -25 -10
0
5
20
35 50
TJ (qC)
65
80
10
95 110 125
1k
D007
100k
VIN – VOUT = 1 V
CNR = 0.01 µF
1M
10M
VOUT = 2.85 V
COUT = 2.2 µF
Figure 11. Power-Supply Ripple Rejection vs Frequency
90
90
IOUT = 100mA
80
IOUT = 1mA
80
70
60
60
PSRR (dB)
70
50
40
30
IOUT = 1mA
50
40
IOUT = 200mA
30
20
20
IOUT = 200mA
10
IOUT = 100mA
10
0
0
10
100
1k
10k
100k
1M
10M
10
100
1k
Frequency (Hz)
VIN – VOUT = 0.5 V
CNR = 0.01 µF
10k
100k
1M
10M
Frequency (Hz)
VOUT = 2.85 V
COUT = 2.2 µF
Figure 12. Power-Supply Ripple Rejection vs Frequency
8
10k
Frequency (Hz)
Figure 10. Ground Pin Current (Disabled) vs Junction
Temperature
PSRR (dB)
100
VIN – VOUT = 0.25 V
CNR = 0.01 µF
VOUT = 2.85 V
COUT = 2.2 µF
Figure 13. Power-Supply Ripple Rejection vs Frequency
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Typical Characteristics (continued)
at TJ= –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
90
90
80
80
IOUT = 1mA
60
PSRR (dB)
PSRR (dB)
IOUT = 1mA
70
70
IOUT = 200mA
50
40
60
50
40
30
30
20
20
10
10
IOUT = 200mA
0
0
10
100
1k
10k
100k
1M
10
10M
100
1k
VIN – VOUT = 1 V
CNR = 0.01 µF
VOUT = 2.85 V
COUT = 10 µF
VIN – VOUT = 0.25 V
CNR = 0.01 µF
1M
10M
VOUT = 2.85 V
COUT = 10 µF
Figure 14. Power-Supply Ripple Rejection vs Frequency
Figure 15. Power-Supply Ripple Rejection vs Frequency
90
80
80
1MHz
0.1kHz
1kHz
70
IOUT = 1mA
60
60
PSRR (dB)
PSRR (dB)
100k
90
70
50
40
30
20
100
1k
40
100kHz
10kHz
30
10
0
10
50
20
IOUT = 200mA
10
10k
100k
1M
0
0.0
10M
0.5
1.0
Frequency (Hz)
VIN – VOUT = 1 V
COUT = 10 µF
1.5
2.0
3.0
2.5
3.5
4.0
VIN - VOUT (V)
VOUT = 2.85 V
IOUT = 1 mA
COUT = 2.2 µF
CNR = 0.01 µF
Figure 16. Power-Supply Ripple Rejection vs Frequency
Figure 17. Power-Supply Ripple Rejection vs VIN – VOUT
90
90
0.1kHz
80
80
1kHz
70
0.1kHz
1kHz
70
60
60
10kHz
PSRR (dB)
PSRR (dB)
10k
Frequency (Hz)
Frequency (Hz)
50
40
30
100kHz
1MHz
20
10kHz
50
40
30
10
100kHz
1MHz
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.0
0.5
1.0
VIN - VOUT (V)
IOUT = 100 mA
COUT = 2.2 µF
1.5
2.0
2.5
3.0
3.5
4.0
VIN - VOUT (V)
CNR = 0.01 µF
Figure 18. Power-Supply Ripple Rejection vs VIN – VOUT
IOUT = 200 mA
COUT = 2.2 µF
CNR = 0.01 µF
Figure 19. Power-Supply Ripple Rejection vs VIN – VOUT
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Typical Characteristics (continued)
at TJ= –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
35
200
180
30
Total Noise (mVrms)
Total Noise (mVrms)
160
140
120
100
80
60
25
20
15
10
40
5
20
0
0
0.01
0.1
1
10
0
5
10
VOUT = 2.85 V
COUT = 2.2 µF
15
20
25
COUT (mF)
CNR (nF)
IOUT = 1 mA
VOUT = 2.85 V
CNR = 0.01 µF
Figure 20. Total Noise vs CNR
IOUT = 1 mA
Figure 21. Total Noise vs COUT
COUT = 2.2mF
100mV/div
VOUT
COUT = 10mF
20mV/div
VOUT
COUT = 10mF
100mV/div
20mV/div
C OUT = 2.2mF
150mA
VOUT
dVIN
4.15V
= 1V/ms
100mA/div
1mA
dt
IOUT
3.15V
1V/div
VOUT
VIN
20ms/div
20ms/div
VOUT = 2.85 V
VIN = 3.35 V
IOUT = 150 mA
Figure 23. Load Transient Response
Figure 22. Line Transient Response
RLOAD = 19W
COUT = 2.2mF
VOUT = 2.85 V
RLOAD = 19 W
COUT = 2.2 mF
VOUT
VOUT
RLOAD = 19 W
COUT = 10 mF
RLOAD = 19W
COUT = 10mF
1V/div
1V/div
3.85V
VIN
0V
4V/div
VEN
5V/div
10ms/div
VEN = VIN
10ms/div
VOUT = 2.85 V
VIN = 3.85 V
Figure 24. Turn-On Response
10
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VOUT = 2.85 V
Figure 25. Enable Response
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Typical Characteristics (continued)
at TJ= –55°C to +125°C, VIN = VOUT(nom) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR =
0.01 μF, and VOUT = 3 V (unless otherwise noted). Typical values are at TJ = 25°C.
7
6
VIN
5
Volts
4
3
VOUT
2
1
0
-1
50ms/div
VOUT = 2.85 V
RL = 19 Ω
Figure 26. Power-Up and Power-Down
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7 Detailed Description
7.1 Overview
The TPS79901 low-dropout (LDO) regulator combines the high performance required of many RF and precision
analog applications with ultra-low-current consumption. High PSRR is provided by a high-gain, high-bandwidth
error loop with good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is provided to
bypass noise generated by the band-gap reference and to improve PSRR, while a quick-start circuit quickly
charges this capacitor at start-up. The combination of high performance and low ground current also make these
devices an excellent choice for portable applications. All versions have thermal and overcurrent protection, and
are fully specified from –55°C to +125°C.
The TPS79901 also features inrush current protection with an EN toggle start-up, and overshoot detection at the
output. When the EN toggle is used to start the device, current limit protection is immediately activated,
restricting the inrush current to the device. If voltage at the output overshoots 5% from the nominal value, a
pulldown resistor reduces the voltage to normal operating conditions, as shown in the Functional Block Diagram.
7.2 Functional Block Diagram
IN
OUT
400W
3.3MW
Current
Limit
Thermal
Shutdown
EN
Overshoot
Detect
UVLO
1.193V
Bandgap
FB
500k
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Adjustable-Voltage Versions
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS79901 internal current limit helps protect the regulator during fault conditions. In current limit mode, the
output sources a fixed amount of current that is largely independent of the output voltage. For reliable operation,
do not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS79901 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited; therefore, if extended reverse voltage operation is
anticipated, external limiting may be required.
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
12
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Feature Description (continued)
7.3.3 Start Up
The TPS79901 uses a start-up circuit to quickly charge the noise reduction capacitor, CNR, if present (see the
Functional Block Diagram). This circuit allows for the combination of very low output noise and fast start-up
times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are
appropriate for this configuration.
Note that for fastest start-up, apply VIN first, and then drive the enable pin (EN) high. If EN is tied to IN, start-up is
somewhat slower. The start-up switch is closed for approximately 135 μs. To ensure that CNR is fully charged
during start-up, use a 0.01-μF or smaller capacitor.
7.3.4 Undervoltage Lockout (UVLO)
The TPS79901 use an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating
properly. The UVLO circuit has a deglitch feature so that undershoot transients are typically ignored on the input
if these transients are less than 50 μs in duration.
7.4 Device Functional Modes
Driving EN over 1.2-V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode,
thus reducing the operating current to 150 nA, nominal.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS79901 LDO regulator provides high PSRR while maintaining ultra-low-current consumption. The device
also features inrush current protection and overshoot detection at the output.
8.2 Typical Applications
Figure 28 shows the basic circuit connections.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT =
OUT
TPS79901
EN
GND
(R1 + R2)
R2
´ 1.193
VOUT
R1
CFB
FB
2.2 mF
Ceramic
R2
VEN
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Typical Application Circuit for Adjustable Voltage Version
8.2.1 Design Requirements
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND terminal current, and power the load.
14
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Typical Applications (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1-μF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is located several inches from the
power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure
stability.
The TPS79901 is designed to be stable with standard ceramic capacitors with values of 2.2 μF or greater. X5Rand X7R-type capacitors are best because they have minimal variation in value and ESR over temperature.
Maximum ESR must be less than 1 Ω.
8.2.2.2 Output Noise
In most LDOs, the band gap is the dominant noise source. If a noise-reduction capacitor (CNR) is used with the
TPS79901, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output
resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF noise
reduction capacitor. To further optimize noise, equivalent series resistance of the output capacitor can be set to
approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing total output noise
by up to 10%.
Noise can be referred to the feedback point; with CNR = 0.01 μF total noise is approximately given by Equation 1:
10.5mVRMS
VN =
x VOUT
V
(1)
8.2.2.3 Dropout Voltage
The TPS79901 uses a PMOS pass transistor to achieve a low-dropout voltage. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and rDS(on) of the PMOS pass
element is the input-to-output resistance. Because the PMOS device behaves like a resistor in dropout, VDO
approximately scales with the output current.
As with any linear regulator, PSRR degrades as (VIN – VOUT) approaches dropout. This effect is illustrated in
Figure 11 through Figure 19 in the Typical Characteristics section.
8.2.2.4 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude, but
increases the duration of the transient response. The transient response of the TPS799 is enhanced by an active
pulldown device that engages when the output overshoots by approximately 5% or more when the device is
enabled. When enabled, the pulldown device behaves like a 350-Ω resistor to ground.
8.2.2.5 Minimum Load
The TPS79901 is stable with no output load. To meet the specified accuracy, a minimum load of 500 μA is
required. With loads less than 500 μA at junction temperatures near 125°C, the output can drift up enough to
cause the output pulldown device to turn on. The output pulldown device limits voltage drift to 5% typically;
however, ground current can increase by approximately 50 μA. In typical applications, the junction cannot reach
high temperatures at light loads because there is no noticeable dissipated power. The specified ground current is
then valid at no load in most applications.
8.2.2.6 Feedback Capacitor Requirements
The feedback capacitor, CFB, shown in Figure 28 is required for stability. For a parallel combination of R1 and R2
equal to 250 kΩ, any value from 3 pF to 1 nF can be used. Values below 5 pF should be used to ensure fast
startup; values above 47 pF can be used to implement an output voltage soft-start. Larger value capacitors also
improve noise slightly. The TPS79901 is stable in unity-gain configuration (OUT tied to FB) without CFB.
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Typical Applications (continued)
8.2.3 Application Curve
100
IOUT = 1 mA
IOUT = 100 mA
IOUT = 250 mA
90
80
PSRR (dB)
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
G001
COUT = 2.2 µF
CNR = 0.01 µF
Figure 29. Power-Supply Rejection Ratio vs Frequency
8.3 Do's and Don'ts
Do place at least one 2.2-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input
of the regulator.
Do not exceed the absolute maximum ratings.
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 2.7 V and 6.5 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
is well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help
improve the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), design the board with
separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device.
In addition, connect the bypass capacitor directly to the GND pin of the device.
10.1.2 Thermal Information
10.1.2.1 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C the output circuitry is again enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage resulting from
overheating.
16
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Layout Guidelines (continued)
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection triggers at least
35°C above the maximum expected ambient condition of a particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS799 is designed to protect against overload conditions. This circuitry is
not intended to replace proper heatsinking. Continuously running the device into thermal shutdown degrades
device reliability.
10.1.2.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the head from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal
Information table near the front of this data sheet. Using heavier copper increases the effectiveness in removing
heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink
effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the
output current times the voltage drop across the output pass element, as shown in Equation 2:
P D + ǒVIN*V OUTǓ @ I OUT
(2)
10.1.2.3 Package Mounting
Solder pad footprint recommendations for the TPS799 are available from the TI's website at www.ti.com.
10.2 Layout Example
VI
VO
TPS799
CIN
COUT
EN
GND
CNR
Represents via used for
application specific connections.
Figure 30. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS799.
This EVM, the TPS799 evaluation module, can be requested at the Texas Instruments web site through the
product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS799 is available through the product folders under
simulation models.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Application report: Using New Thermal Metrics, SBVA025.
• Application report: IC Package Thermal Metrics, SPRA953
• TPS799xxEVM-105 User's Guide, SLVU130
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS79901MDRVTEP
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
17L
V62/17614-01XE
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
17L
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS79901MDRVTEP
Package Package Pins
Type Drawing
WSON
DRV
6
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
179.0
8.4
Pack Materials-Page 1
2.2
B0
(mm)
K0
(mm)
P1
(mm)
2.2
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS79901MDRVTEP
WSON
DRV
6
250
203.0
203.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A B
C
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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