Texas Instruments | TPS65311-Q1 High-Voltage Power-Management IC for Automotive Applications (Rev. C) | Datasheet | Texas Instruments TPS65311-Q1 High-Voltage Power-Management IC for Automotive Applications (Rev. C) Datasheet

Texas Instruments TPS65311-Q1 High-Voltage Power-Management IC for Automotive Applications (Rev. C) Datasheet
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TPS65311-Q1
SLVSCA6C – OCTOBER 2013 – REVISED OCTOBER 2017
TPS65311-Q1 High-Voltage Power-Management IC for Automotive Applications
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level H1B
– Device CDM ESD Classification Level C4B
Input Voltage Range: 4 V to 40 V, Transients up
to 60 V; 80 V When Using External PMOS-FET
Single-Output Synchronous-Buck Controller
– Peak Gate-Drive Current 0.6 A
– 490-kHz Fixed Switching Frequency
– Pseudo Random Frequency-Hopping Spread
Spectrum or Triangular Mode
Dual-Synchronous Buck Converter
– Designed for Output Currents up to 2 A
– Out of Phase Switching
– Switching Frequency: 2.45 MHz
Adjustable 350-mA Linear Regulator
Adjustable Asynchronous-Boost Converter
– 1-A Integrated Switch
– Switching Frequency: 2.45 MHz
Soft-Start Feature for All Regulator Outputs
Independent Voltage Monitoring
Undervoltage (UV) Detection and Overvoltage
(OV) Protection
Short Circuit, Overcurrent, and Thermal Protection
on all supply output rails
Serial-Peripheral Interface (SPI) for Control and
Diagnostic
Integrated Window Watchdog (WD)
Reference Voltage Output
High-Side (HS) Driver for Use with External
PMOS-FET for driving an LED
Input for External Temperature Sensor for
Shutdown at TA < –40°C
Thermally Enhanced Packages With Exposed
Thermal Pad
– 56-Pin VQFN (RVJ) or 56-Pin VQFNP (RWE)
Multi-Rail DC Power Distribution Systems
Safety-Relevant Automotive Applications
– Advanced Driver Assistance Systems
3 Description
The TPS65311-Q1 device is a power-management IC
(PMIC), meeting the requirements of digital-signalprocessor (DSP) controlled-automotive systems (for
example, advanced driver-assistance systems). With
the integration of commonly used supply rails and
features, the TPS65311-Q1 device significantly
reduces board space and system costs.
The device is capable of providing stable output
voltages to the application, including a typical 5-V
CAN-supply, from a varying input power supply (such
as an automotive car battery) from 4 V to 40 V. The
device includes one synchronous buck controller as a
pre-regulator that offers flexible output power to the
application. For post-regulation, the device includes
two synchronous buck and one asynchronous boost
converter, working at a switching frequency of 2.45
MHz to allow for a smaller inductor which requires
less board space. The two buck converters also offer
internal loop compensation which eliminates the need
for external compensation components. Furthermore,
the device includes a low-noise linear regulator.
Device Information(1)
DEVICE NAME
TPS65311-Q1
PACKAGE
BODY SIZE
VQFN (56)
8.00 mm × 8.00 mm
VQFNP (56)
8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VBAT
VBuck1
VBuck1
VBoost
TPS65311-Q1
VBuck1
VBuck3
VBuck1
VBuck2
VLDO
Logic I/O
(SPI, Watchdog, Reset)
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65311-Q1
SLVSCA6C – OCTOBER 2013 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
4
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics........................................... 9
Timing Requirements .............................................. 13
Switching Characteristics ........................................ 15
Typical Characteristics ............................................ 16
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 30
8.5 Programming........................................................... 34
8.6 Register Map........................................................... 35
9
Application and Implementation ........................ 41
9.1 Application Information............................................ 41
9.2 Typical Applications ................................................ 41
10 Power Supply Recommendations ..................... 51
11 Layout................................................................... 53
11.1 Layout Guidelines ................................................. 53
11.2 Layout Example .................................................... 54
12 Device and Documentation Support ................. 55
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2014) to Revision C
Page
•
Added the VQFNP (RWE) package option to the data sheet ............................................................................................... 1
•
Added pin descriptions for the S1 and S2 pins in the Pin Functions table ............................................................................ 5
•
Deleted the lead temperature (soldering, 10 sec), 260°C parameter from the Absolute Maximum Ratings table ................ 8
•
Changed the Handling Ratings table to ESD Ratings and moved storage temperature back to the Absolute
Maximum Ratings table .......................................................................................................................................................... 8
•
Changed all the thermal values for the RWE package in the Thermal Information table ...................................................... 8
•
Added the Receiving Notification of Documentation Updates and Community Resources sections................................... 55
Changes from Revision A (October 2013) to Revision B
Page
•
Changed CDM ESD Classification Level from C3B to C4B in the Features list and ESD ratings ........................................ 1
•
Added device number to document title ................................................................................................................................. 1
•
Added Device Information table to first page and Table of Contents to second page. Moved Revision History to
second page also ................................................................................................................................................................... 1
•
Added two new paragraphs following the first paragraph in the Description section ............................................................ 1
•
Deleted simplified block diagram from first page and added new schematic image ............................................................. 1
•
Moved the pin diagram and function table to before the electrical specifications and change it to the Pin
Configurations and Functions section ................................................................................................................................... 4
•
Added the word range to the Absolute Maximum Ratings ..................................................................................................... 7
•
Moved the electrical specifications tables into the Specifications section ............................................................................. 7
•
Moved the ESD ratings and storage temperature out of the Absolute Maximum Ratings table and into the Handling
Ratings table. Also added the ESD HBM and CDM notes..................................................................................................... 8
•
Changed both max values for TJ from 125 to 150 in the RECOMMEND OPERATING CONDITIONS table........................ 8
•
Lowered all thermal values in the Thermal Information table ................................................................................................ 8
•
Changed condition statement of ELECTRICAL CHARACTERISTICS table from TJ(max) = 125°C to TJ(max) = 150°C ........... 9
2
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SLVSCA6C – OCTOBER 2013 – REVISED OCTOBER 2017
•
Added test condition for IOUT = 350 mA, TJ = 150°C to the VDropout parameter in the ELECTRICAL
CHARACTERISTICS table ................................................................................................................................................... 10
•
Changed the min value for the VHSSC_HY parameter from 1.5 to 1 and deleted the typ (2.5) and max (3.5) values ............ 10
•
Moved all timing specifications from the Electrical Characteristics table into the Timing Requirements table and
added figure references to the timing diagram..................................................................................................................... 13
•
Changed the max value for the tVSSENSE_BLK parameter from 20 to 35 ................................................................................. 13
•
Changed the MAX value for the WD filter time parameter from 0.5 µs to 1.2 µs in the Timing Requirements table ......... 14
•
Changed the min value for the tGL-BLK parameter from 10 to 5 ............................................................................................. 14
•
Moved all switching characteristics out of the Electrical Characteristics and into the new Switching Characteristics
table ..................................................................................................................................................................................... 15
•
Moved all but the first paragraph of the Description into the new Overview section in the Detailed Description section.... 19
•
Moved the block diagram into the Detailed Description section .......................................................................................... 20
•
Deleted the Operating Modes table and Normal Mode PWM Operation section title for Buck Controller (BUCK1)............ 21
•
Changed the resistor name for the resistor next to C1 from R1 to R3 and added R1 and R2 to the Detailed Block
Diagram of Buck 1 Controller image .................................................................................................................................... 21
•
Moved the component selection portion of the Synchronous Buck Converters BUCK2 and BUCK3 section into the
Typical Applications section ................................................................................................................................................ 22
•
Moved the component selection portion of the BOOST Converter section into the Typical Applications section .............. 22
•
Changed the voltage value that EXTSUP is connected to from 4.6 to 4.8 in the Gate Driver Supply section ................... 23
•
Moved the SPI section into a Programming section ........................................................................................................... 34
•
Added the Design Parameters tables for each of the Typical Application sections ............................................................. 42
•
Added the Adjusting the Output Voltage for the BUCK1 Controller section to the Buck Controller (BUCK1)
application section ................................................................................................................................................................ 42
•
Moved the component selection portion of the Buck Controller (BUCK1) section into the Typical Applications section ... 42
•
Changed R1 to R3 in the Compensation of the Buck Controller section ............................................................................. 43
•
Added the Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter to the Detailed Design Procedure in
the Synchronous Buck Converters BUCK2 and BUCK3 section ......................................................................................... 45
•
Changed the inductance, capacitance and FLC values from 3.3 µH, 20 µF, and 12.9 kHz to 1.5 µH, 39 µF, and 13.7
kHz (respectively) in the For example: section of the Compensation of the BOOST Converter section ............................. 49
•
Added the Linear Regulator application section .................................................................................................................. 50
•
Added the Device and Documentation Support and Mechanical, Packaging, and Orderable Information sections.
The Device and Documentation Support now includes the electrostatic discharge caution, trademark information,
and a link to the TI Glossary................................................................................................................................................. 55
Changes from Original (October 2013) to Revision A
Page
•
Changed document status from Product Preview to Production Data ................................................................................... 1
•
Deleted both min values (–44°C and –55°C) for TJ in the RECOMMENDED OPERATING CONDITIONS table................. 8
•
Changed both max values for TJ from 150°C to 125°C in the RECOMMENDED OPERATING CONDITIONS table........... 8
•
Changed condition statement of ELECTRICAL CHARACTERISTICS table from TJ temperature range to TJ(max) = 125°C . 9
•
Changed one test condition for the VDroupout parameter in the ELECTRICAL CHARACTERISTICS table from TJ =
150°C to TJ = 125°C ............................................................................................................................................................. 10
•
Deleted the TJ temperature range from SHUTDOWN COMPARATOR subheader row in the ELECTRICAL
CHARACTERISTICS table ................................................................................................................................................... 11
•
Changed one test condition for the IVT_leak parameter in the ELECTRICAL CHARACTERISTICS table from TJ =
–20°C to 150°C to TJ = –20°C to 125°C............................................................................................................................... 11
•
Changed the TJ temperature range to TJ(max) = 125°C for the INTERNAL VOLTAGE REGULATORS subheader row
in the ELECTRICAL CHARACTERISTICS table.................................................................................................................. 12
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5 Description (continued)
To help support system safety, the device includes voltage monitoring on all supply rails and a window-watchdog
to monitor the MCU and DSP. Other features include a high-side driver which drives a warning-lamp LED, a
reference voltage which is used as ADC reference in the MCU, DSP, and a shutdown comparator which, in
combination with external NTC-resistor, switches off the device at too-low ambient temperature.
6 Pin Configuration and Functions
GND
DVDD
VT
VREF
VSENSE4
LDO_OUT
VSUP4
HSPWM
VIO
SDO
SCK
SDI
CSN
WD
56
55
54
53
52
51
50
49
48
47
46
45
44
43
56-Pin VQFN and VQFNP
RVJ and RWE Package With Exposed Thermal Pad
Top View
VSSENSE
1
42
BOOT3
VIN
2
41
VSUP3
GPFET
3
40
PH3
VINPROT
4
39
PGND3
HSCTRL
5
38
VMON3
HSSENSE
6
37
COMP3
WAKE
7
36
VSENSE3
Thermal
Pad
24
25
26
27
28
VBOOST
VT_REF
PRESN
RESN
IRQ
BOOT2
23
VSUP2
29
PH5
30
14
22
13
21
GL
PGND1
PGND5
PH2
VSENSE5
31
20
12
COMP5
PH1
19
PGND2
18
VMON2
32
COMP1
33
11
VSENSE1
10
GU
17
BOOT1
16
COMP2
S2
VSENSE2
34
VMON1
35
9
15
8
VREG
S1
EXTSUP
Not to scale
Pin Functions
PIN
TYPE (1)
PULLUP OR
PULLDOWN
10
I
—
The capacitor on this pin acts as the voltage supply for the BUCK1 high-side MOSFET gate-drive
circuitry.
BOOT2
29
I
—
The capacitor on this pin acts as the voltage supply for the BUCK2 high-side MOSFET gate drive
circuitry.
BOOT3
42
I
—
The capacitor on this pin act as the voltage supply for the BUCK3 high-side MOSFET gate drive
circuitry.
COMP1
18
O
—
Error amplifier output for the switching controller. External compensation network is connected to this
pin.
COMP2
34
I
—
Compensation selection for the BUCK2 switching converter
COMP3
37
I
—
Compensation selection for the BUCK3 switching converter.
COMP5
20
O
—
Error amplifier output for the boost switching controller. External compensation network is connected
to this pin.
CSN
44
I
Pullup
NAME
NO.
BOOT1
(1)
4
DESCRIPTION
SPI – Chip select
Description of pin type: I = Input; O = Output; OD = Open-drain output
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Pin Functions (continued)
PIN
TYPE (1)
PULLUP OR
PULLDOWN
55
O
—
Internal DVDD output for decoupling
8
I
—
Optional LV input for gate driver supply
GL
13
O
—
Gate driver – low-side FET
GND
56
O
—
Analog GND, digital GND and substrate connection
GPFET
3
O
—
Gate driver external protection PMOS FET.
GU
11
O
—
Gate driver – high-side FET
HSCTRL
5
O
—
High-side gate driver output
HSPWM
49
I
Pulldown
High side and LED PWM input
HSSENSE
6
I
—
Sense input high side and LED
IRQ
28
OD
—
Low battery interrupt output in operating mode
LDO_OUT
51
O
—
Linear regulated output (connect a low ESR ceramic output capacitor to this pin)
PGND1
14
O
—
Ground for low-side FET driver
PGND2
32
O
—
Power ground of synchronous converter BUCK2
PGND3
39
O
—
Power ground of synchronous converter BUCK3
PGND5
22
O
—
Power ground boost converter
PH1
12
O
—
Switching node - BUCK1 (floating ground for high-side FET driver)
PH2
31
O
—
Switching node BUCK2
PH3
40
O
—
Switching node BUCK3
PH5
23
O
—
Switching node boost
PRESN
26
OD
—
Peripherals reset
RESN
27
OD
—
System reset
S1
15
I
—
Differential current sense input for BUCK1
S2
16
I
Pulldown
Differential current sense input for BUCK1, pulldown only active in RAMP and ACTIVE state
SCK
46
I
Pulldown
SPI – Clock
SDI
45
I
Pulldown
SPI – Master out, slave in
SDO
47
O
—
SPI – Master in, slave out - push-pull output supplied by VIO
VBOOST
24
I
—
Booster output voltage
VIN
2
I
—
Unprotected supply input for the base functionality and band-gap 1. Supplied blocks are: RESET, WD,
wake, SPI, temp sensing, voltage monitoring and the logic block.
VINPROT
4
I
—
Main input supply (gate drivers and bandgap2)
VIO
48
I
—
Supply input for the digital interface to the MCU. Voltage on this input is monitored. If VIO falls below
UV threshold a reset is generated and the part enters error mode.
VMON1
17
I
—
Input for the independent voltage monitor at BUCK1
VMON2
33
I
—
Input for the independent voltage monitor at BUCK2
VMON3
38
I
—
Input for the independent voltage monitor at BUCK3
VREF
53
O
—
Accurate reference voltage output for peripherals on the system (for example, ADC)
VREG
9
O
—
Internal regulator for gate driver supply (decoupling) and VREF
VSENSE1
19
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
VSENSE2
35
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
VSENSE3
36
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
VSENSE4
52
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
VSENSE5
21
I
—
Input for externally sensed voltage of the boost output using a resistor divider network from their
respective output line to ground.
VSSENSE
1
I
—
Input to monitor the battery line for undervoltage conditions. UV is indicated by the IRQ pin.
VSUP2
30
I
—
Input voltage supply for switch mode regulator BUCK2
VSUP3
41
I
—
Input voltage supply for switch mode regulator BUCK3
VSUP4
50
I
—
Input voltage supply for linear regulator LDO
NAME
NO.
DVDD
EXTSUP
DESCRIPTION
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
PULLUP OR
PULLDOWN
DESCRIPTION
VT
54
I
—
Input for the comparator with shutdown functionality. This input can be used to sense an external NTC
resistor to shutdown the IC in case the ambient temperature is too high or too low. Tie to GND if not
in use.
VT_REF
25
O
—
Shutdown comparator reference output. Internally connected to DVDD, current-limited. When not in
use can be connected to DVDD or left open.
WAKE
7
I
Pulldown
Wake up input
WD
43
I
Pulldown
Watchdog input. WD is the trigger input coming from the MCU.
6
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply inputs
Buck controller
MIN
MAX
VIN
–0.3
80
VINPROT
–0.3
60
VSUP2, 3 (BUCK2 and 3)
–0.3
20
VSUP4 (Linear Regulator)
–0.3
20
VBOOST
–0.3
20
EXTSUP
–0.3
13
VIO
–0.3
5.5
PH1
–1
–2 for 100 ns
60
VSENSE1
–0.3
20
COMP1
–0.3
20
GU-PH1, GL-PGND1, BOOT1-PH1
–0.3
8
S1, S2
–0.3
20
S1-S2
–2
2
BOOT1
–0.3
68
VMON1
–0.3
20
–1
20
BOOT2, BOOT3
(2)
–1
–2 for 10 ns
20 (2)
VSENSE2, VSENSE3
–0.3
20
COMP2, COMP3
–0.3
20
VMON2, VMON3
–0.3
20
BOOTx – PHx
–0.3
8
LDO_OUT
–0.3
8
VSENSE4
–0.3
20
VSENSE5
–0.3
20
PH5
–0.3
20
COMP5
–0.3
20
CSN, SCK, SDO, SDI, WD, HSPWM
–0.3
5.5
RESN, PRESN, IRQ
–0.3
20
WAKE
–1 (3)
60
GPFET
–0.3
80
VIN – GPFET
–0.3
20
–1 (3)
60
Transients up to 80 V (4)
VT
–0.3
5.5
VT_REF
–0.3
20
PH2, PH3
Buck controller
Linear regulator
Boost converter
Digital interface
Wake input
Protection FET
Battery sense input
Temperature sense
(1)
(2)
(3)
(4)
VSSENSE
UNIT
V
V
V
V
V
V
V
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum 3.5 A
Imax = 100 mA
Internally clamped to 60-V, 20-kΩ external resistor required, current into pin limited to 1 mA.
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Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)
Reference voltage
High-side and LED driver
MIN
MAX
UNIT
VREF
–0.3
5.5
V
HSSENSE
–0.3
60
HSCTRL
–0.3
60
20
V
VINPROT-HSSENSE, VINPROT-HSCTRL
–0.3
Driver supply decoupling
VREG
–0.3
8
V
Supply decoupling
DVDD
–0.3
3.6
V
Junction temperature range, TJ
–55
150
Operating temperature range, TA
–55
125
Storage temperature, Tstg
–55
165
Temperature ratings
°C
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic
discharge
V(ESD)
(1)
Charged-device model (CDM), per AEC
Q100-011
UNIT
±1000
VT pin
±150
Corner pins (1, 14, 15, 28, 29, 42, 43,
and 56)
±750
All other pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX
Supply voltage at VIN, VINPROT, VSSENSE
TA
Operating free air temperature
TJ
Operating virtual junction
temperature
4.8
40
All electrical characteristics in specification
–40
125
Shutdown comparator and internal voltage regulators in
specification
–55
125
All electrical characteristics in specification
150
Shutdown comparator and internal voltage regulators in
specification
150
UNIT
V
°C
°C
7.4 Thermal Information
TPS65311-Q1
THERMAL METRIC (1)
RWE (VQFNP)
RVJ (VQFN)
UNIT
56 PINS
56 PINS
RθJA
Junction-to-ambient thermal resistance
22.1
22.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
9.6
9.8
°C/W
RθJB
Junction-to-board thermal resistance
6.2
6.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
0.1
°C/W
ψJB
Junction-to-board characterization parameter
6.2
6.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.4
0.7
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE-CURRENT CONSUMPTION
VIN
Device operating range
VPOR
Power-on reset threshold
VPOR_hyst
Power-on reset hysteresis on VIN
Buck regulator operating range, Voltage on VIN and
VINPROT pins
4
50
Falling VIN
3.5
3.6
3.8
Rising VIN
3.9
4.2
4.3
0.47
0.6
V
V
0.73
V
44
μA
60
μA
ILPM0
LPM0 current consumption (1) (2)
All off, wake active, VIN = 13 V
Total current into VSSENSE, VIN and VINPROT
ILPM0
LPM0 current (commercial vehicle
application) consumption (3) (2)
All off, wake active, VIN = 24.5 V
Total current into VSSENSE, VIN and VINPROT
IACTIVE1
ACTIVE total current
consumption (1) (4)
BUCK1 = on, VIN = 13 V, EXTSUP = 0 V,
Qg of BUCK1 FETs = 15 nC.
Total current into VSSENSE, VIN and VINPROT
32
mA
IACTIVE123
ACTIVE total current
consumption (1) (4)
BUCK1/2/3 = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC.
Total current into VSSENSE, VIN and VINPROT
40
mA
IACTIVE1235
ACTIVE current consumption (1) (4)
BUCK1/2/3, LDO, BOOST, high-side switch = on,
VIN = 13 V, Qg of BUCK1 FETs = 15 nC.
EXTSUP = 5 V from BOOST
Total current into VSSENSE, VIN and VINPROT
31
mA
IACTIVE1235_noEXT ACTIVE current consumption (1) (4)
BUCK1/2/3, LDO, BOOST, high-side switch = on,
VIN = 13 V, Qg of BUCK1 FETs = 15 nC,
EXTSUP = open
Total current into VSENSE, VIN and VINPROT
53
mA
BUCK CONTROLLER (BUCK1)
VBUCK1
Adjustable output voltage range
VSense1_NRM
Internal reference voltage in
operating mode
VS1-2
VS1-2 for forward OC in CCM
VSENSE1 pin, load = 0 mA,
Internal REF = 0.8 V
Maximum sense voltage VSENSE1 = 0.75 V (low
duty cycle)
Minimum sense voltage VSENSE 1 = 1 V (negative
current limit)
ACS
Current sense voltage gain
∆VCOMP1 / ∆ (VS1 - VS2)
IGpeak
Gate driver peak current
VREG = 5.8 V
RDSON_DRIVER
Source and sink driver
IG current for external MOSFET = 200 mA,
VREG = 5.8 V, VBOOT1-PH1 = 5.8 V
VDIO1
Bootstrap diode forward voltage
IBOOT1 = –200 mA, VREG-BOOT1
3
11
–1%
1%
60
75
90
–65
–37.5
–23
8
12
V
mV
4
0.6
5
0.8
V/V
A
10
Ω
1.1
V
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER
gmEA
Forward transconductance
AEA
Error amplifier DC gain
COMP1/2/3/5 = 0.8 V; source/sink = 5 µA,
Test in feedback loop
0.9
mS
60
dB
SYNCHRONOUS BUCK CONVERTER BUCK2 AND BUCK3 (BUCK2/3)
VSUP2/3
Supply voltage
3
11
V
0.8
5.5
V
VBUCK2/3
Regulated output voltage range
Iload = 0…2 A
VSUPx = VBUCK2/3 + Iload × 0.2 Ω
RDSON-HS
RDSON high-side switch
VBOOTx –PHx = 5.8 V
0.20
Ω
RDSON-LS
RDSON low-side switch
VREG = 5.8 V
0.20
Ω
IHS-Limit
High-side switch current-limit
Static current limit test.
In application L > 1 µH at
IHS-Limit and ILS-Limit to limit dI / dt
2.5
2.9
3.3
A
ILS-Limit
Low-side switch current-limit
Static current limit test.
In application L > 1 µH at
IHS-Limit and ILS-Limit to limit dI / dt
2
2.5
3
A
(1)
(2)
(3)
(4)
TA = 25°C
Quiescent Current Specification does not include the current flow through the external feedback resistor divider. Quiescent Current is
non-switching current, measured with no load on the output with VBAT = 13 V.
TA = 130°C
Total current consumption measured on EVM includes switching losses.
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Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
VSUPLkg
VSUP leakage current
VSUP = 10 V for high side, controller disabled,
TJ = 100°C
VSense2/3
Feedback voltage
With respect to the 800-mV internal reference
COMP2/3HTH
COMP2/3 Input threshold low
COMP2/3LTH
COMP2/3 Input threshold high
RTIEOFF
COMP2/3 internal tie-off
BUCK2/3 enabled. Resistor to VREG and GND,
each
Bootstrap diode forward voltage
IBOOT1 = –200 mA, VREG-BOOT2, VREG-BOOT3
COMP23
VDIO2 3
TYP
MAX
1
2
UNIT
µA
–1%
1%
0.9
1.5
V
VREG – 1.2
VREG –
0.3
V
100
130
kΩ
1.1
1.2
V
70
BOOST CONVERTER
VBoost
Boost adjustable output voltage
range
Using 3.3-V input voltage, Ieak_switch ≤ 1 A
4.5
15
V
VBoost
Boost adjustable output voltage
range
Using 3.3-V input voltage Iloadmax = 20 mA,
Ipeak_switch = 0.3 A
15
18.5
V
RDS-ON_BOOST
Internal switch on-resistance
VREG = 5.8 V
0.5
Ω
VSense5
Feedback voltage
With respect to the 800-mV internal reference
ICLBOOST
Internal switch current-limit
0.3
–1%
1%
1
1.5
A
LINEAR REGULATOR LDO
VSUP4
Device operating range for LDO
Recommended operating range
VLDO
Regulated output range
IOUT = 1 mA to 350 mA
VRefLDO
DC output voltage tolerance at
VSENSE4
Vstep1
VSense4
VDropout
3
7
V
0.8
5.25
V
VSENSE4 = 0.8 V (regulated at internal ref)
VSUP4 = 3 V to 7 V, IOUT = 1 mA to 350 mA
–2%
2%
Load step 1
VSENSE4 = 0.8 V (regulated at internal ref)
IOUT = 1 mA to 101 mA,
CLDO = 6 to 50 µF, trise = 1 µs
–2%
2%
Feedback voltage
With respect to the 800-mV internal reference
–1%
Drop out voltage
1%
IOUT = 350 mA, TJ = 25°C
127
143
IOUT = 350 mA, TJ = 125°C
156
180
IOUT = 350 mA, TJ = 150°C
275
335
IOUT
Output current
VOUT in regulation
ILDO-CL
Output current limit
VOUT = 0 V, VSUP4 = 3 V to 7 V
PSRRLDO
Power supply ripple rejection
Vripple = 0.5 VPP, IOUT = 300 mA,
CLDO = 10 µF
mV
–350
–1
mA
–1000
–400
mA
Freq = 100 Hz
60
Freq = 4 kHz
50
Freq = 150 kHz
25
dB
LDOns10-100
Output noise 10 Hz – 100 Hz
10-µF output capacitance, VLDO = 2.5 V
20
µV/√(Hz)
LDOns100-1k
Output noise 100 Hz – 10 kHz
10-µF output capacitance, VLDO = 2.5 V
6
µV/√(Hz)
Output capacitor
Ceramic capacitor with ESR range, CLDO_ESR = 0 to
100 mΩ
6
50
µF
370
430
mV
60
V
CLDO
LED AND HIGH-SIDE SWITCH CONTROL
VHSSENSE
Current sense voltage
VINPROT – HSSENSE, high-side switch in current
limit
VCMHSSENSE
Common mode range for current
sensing
See VINPROT
VHSOL_TH
VINPROT – HSSENSE open load
threshold
VHSOL_HY
Open load hysteresis
VHS
VINPROT – HSSENSE load short
detection threshold
SC
VHSSC_HY
VINPROT – HSSENSE short
circuit hysteresis
VHSCTRLOFF
Voltage at HSCTRL when OFF
VGS
Clamp voltage between
HSSENSE – HSCTRL
10
400
4
Ramping negative
5
20
35
Ramping positive
26
38
50
10
18
28
Ramping positive
88%
92.5%
96%
VHSSENSE
87
90
93
% of
VHSSENSE
Ramping negative from load short condition
VINPROT
– 0.5
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% of
VHSSENSE
1
6.1
mV
7.7
VINPROT
V
8.5
V
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Product Folder Links: TPS65311-Q1
TPS65311-Q1
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SLVSCA6C – OCTOBER 2013 – REVISED OCTOBER 2017
Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 150°C, unless otherwise noted
PARAMETER
VOS_HS
Overshoot during turn-on
ICL_HSCTRL
HSCTRL current-limit
RPU_HSCTRL
RPU_HSCTRL-
Internal pullup resistors
TEST CONDITIONS
MIN
TYP
VOS_HS = VINPROT - HSSENSE
MAX
UNIT
400
mV
mA
2
4.1
5
Between VINPROT and HSCTRL
70
100
130
Between HSCTRL and HSSENSE
70
100
130
kΩ
HSSENSE
VI_high
High level input voltage
HSPWM, VIO = 3.3 V
VI_low
Low level input voltage
HSPWM, VIO = 3.3 V
VI_hys
Input voltage hysteresis
HSPWM, VIO = 3.3 V
RSENSE
External sense resistor
Design info, no device parameter
CGS
External MOSFET gate source
capacitance
CGD
External MOSFET gate drain
capacitance
2
V
0.8
V
150
500
mV
1.5
50
Ω
100
2000
pF
500
pF
REFERENCE VOLTAGE
VREF
Reference voltage
VREF-tol
Reference voltage tolerance
IREFCL
CVREF
REFns10-100
Output noise 10 Hz–100 Hz
2.2 µF output capacitance, IVREF = 5 mA
REFns100-1k
Output noise 100 Hz–10 kHz
2.2 µF output capacitance, IVREF = 5 mA
VREF_OK
3.3
V
–1%
1%
Reference voltage current-limit
10
25
Capacitive load
0.6
5
µF
20
µV/√(Hz)
6
µV/√(Hz)
Reference voltage OK threshold
IVREF = 5 mA
Threshold, VREF falling
mA
2.91
3.07
3.12
V
Hysteresis
14
70
140
mV
IVT_REF = 20 µA. Measured as drop voltage with
respect to VDVDD
10
17
500
IVT_REF = 600 µA. Measured as drop voltage with
respect to VDVDD. No VT_REF short-circuit
detection.
200
420
1100
VT_REF = 0
0.6
1
1.4
mA
Threshold, VT_REF falling. Measured as drop
voltage with respect to VDVDD
0.9
1.2
1.8
V
SHUTDOWN COMPARATOR
VT_REF
Shutdown comparator reference
voltage
IVT_REFCL
Shutdown comparator reference
current limit
VVT_REF
VT_REF short circuit detection
SH
mV
Hysteresis
130
mV
VTTH-H
Input voltage threshold on VT,
rising edge triggers shutdown
This feature is specified by design to work down to
–55°C.
0.48
0.50
0.52
VT_REF
VTTH-L
Input voltage threshold on VT,
falling voltage enables device
operation
This feature is specified by design to work down to
–55°C.
0.46
0.48
0.52
VT_REF
VTTOL
Threshold variation
VTTH-H – VT_REF / 2, VTTH-L – VT_REF / 2
–20
20
IVT_leak
Leakage current
TJ: –20°C to 125°C
–400
–50
TJ: –55°C to –20°C
–200
–50
VT_REFOV
VT_REF overvoltage threshold
Threshold, VT_REF rising. Measured as drop
voltage with respect to VDVDD
0.42
Hysteresis
0.9
1.2
100
mV
nA
V
mV
WAKE INPUT
VWAKE_ON
Voltage threshold to enable device
WAKE pin is a level sensitive input
3.3
3.7
V
VBAT UNDERVOLTAGE WARNING
VSSENSETH_L
VSSENSE falling threshold low
SPI selectable, default after reset
4.3
4.7
V
VSSENSETH_H
VSSENSE falling threshold high
SPI selectable
6.2
6.8
V
VSSENSE-HY
VSSENSE hysteresis
IVSLEAK
Leakage current at VSSENSE
LPM0 mode, VSSENSE 55 V
1
µA
IVSLEAK60
Leakage current at VSSENSE
LPM0 mode, VSSENSE 60 V
IVSLEAK80
Leakage current at VSSENSE
LPM0 mode, VSSENSE 80 V
0.2
5
V
100
µA
25
mA
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Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 150°C, unless otherwise noted
PARAMETER
RVSSENSE
Internal resistance from VSSENSE
to GND
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSSENSE = 14 V, disabled in LPM0 mode
0.7
1
1.3
MΩ
VIN OVERVOLTAGE PROTECTION
VOVTH_H
VIN overvoltage shutdown
threshold 1 (rising edge)
Selectable with SPI
50
60
V
VOVTH_L
VIN overvoltage shutdown
threshold 2 (rising edge)
Selectable with SPI, default after reset
36
38
V
VOVHY
VIN overvoltage hysteresis
Threshold 1
0.2
1.7
3
Threshold 2 - default after reset
1.5
2
2.5
V
WINDOW WATCHDOG
VI_high
High level input voltage
WD, VIO = 3.3 V
VI_low
Low level input voltage
WD, VIO = 3.3 V
VI_hys
Input voltage hysteresis
WD, VIO = 3.3 V
2
V
0.8
V
150
500
mV
RESET AND IRQ BLOCK
VRESL
Low level output voltage at RESN,
PRESN and IRQ
VIN ≥ 3 V, IxRESN = 2.5 mA
0
0.4
V
VRESL
Low level output voltage at RESN
and PRESN
VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA
0
0.4
V
IRESLeak
Leakage current at RESN, PRESN
and IRQ
Vtest = 5.5 V
1
µA
NRES
Number of consecutive reset
events for transfer to LPM0
7
EXTERNAL PROTECTION
VCLAMP
Gate to source clamp voltage
VIN - GPFET, 100 µA
14
20
V
IGPFET
Gate turn on current
VIN = 14 V, GPFET = 2 V
15
25
µA
RDSONGFET
Gate driver strength
VIN = 14 V, turn off
25
Ω
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
TSDTH
Thermal shutdown
TSDHY
Hysteresis
TOTTH
Overtemperature flag
TOTHY
Hysteresis
Junction temperature
160
Overtemperature flag is implemented as local temp
sensors and expected to trigger before the thermal
shutdown
150
175
°C
20
°C
165
°C
20
°C
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
VMONTH_L
Voltage monitor reference
REF = 0.8 V – falling edge
90%
92%
94%
VMONTH_H
Voltage monitor reference
REF = 0.8 V – rising edge
106%
108%
110%
VMON_HY
Voltage monitor hysteresis
VVIOMON_TH
Undervoltage monitoring at VIO –
falling edge
VVIOMON_HY
UV_VIO hysteresis
2%
3
3.13
0.05
V
V
GND LOSS
VGLTH-low
GND loss threshold low
GND to PGNDx
–0.31
–0.25
–0.19
V
VGLTH-high
GND loss threshold high
GND to PGNDx
0.19
0.25
0.31
V
INTERNAL VOLTAGE REGULATORS
VREG
Internal regulated supply
IVREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V
and EXTSUP = 6.3 V to 12 V
5.5
5.8
6.1
V
VEXTSUP-TH
Switch over voltage
IVREG = 0 mA to 50 mA and EXTSUP ramping
positive, ACTIVE mode
4.4
4.6
4.8
V
VEXTSUP-HY
Switch over hysteresis
100
200
300
mV
200
mV
VREGDROP
IREG_CL
IREG_EXTSUP_CL
CVREG
12
Drop out voltage on VREG
Current limit on VREG
IVREG = 50 mA,
EXTSUP = 5 V / VINPROT = 5 V and
EXTSUP = 0 V / VINPROT = 4 V
EXTSUP = 0 V, VREG = 0 V
–250
–50
mA
EXTSUP ≥ 4.8 V, VREG = 0 V
–250
–50
mA
3.3
µF
Capacitive load
1.2
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SLVSCA6C – OCTOBER 2013 – REVISED OCTOBER 2017
Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 150°C, unless otherwise noted
PARAMETER
MIN
TYP
MAX
VREG rising
TEST CONDITIONS
3.8
4
4.2
V
Hysteresis
350
420
490
mV
3.15
3.3
3.45
V
VREG-OK
VREG undervoltage threshold
VDVDD
Internal regulated low voltage
supply
VDVDD UV
DVDD undervoltage threshold
DVDD falling
VDVDD OV
DVDD overvoltage threshold
DVDD rising
VI_high
High level input voltage
CSN, SCK, SDI; VIO = 3.3 V
VI_low
Low level input voltage
CSN, SCK, SDI; VIO = 3.3 V
VI_hys
Input voltage hysteresis
CSN, SCK, SDI; VIO = 3.3 V
VO_high
SDO output high voltage
VIO = 3.3 V ISDO = 1 mA
VO_low
SDO output low voltage
VIO = 3.3 V ISDO = 1 mA
CSDO
SDO capacitance
UNIT
2.1
V
3.8
V
SPI
2
V
150
0.8
V
500
mV
3
V
0.2
V
50
pF
GLOBAL PARAMETERS
RPU
Internal pullup resistor at CSN pin
70
100
130
kΩ
RPD
Internal pulldown resistor at pins:
HSPWM , SDI, SCK, WD, S2 (5)
70
100
130
kΩ
RPD-WAKE
Internal pulldown resistor at WAKE
pin
140
200
260
kΩ
ILKG
Input pullup current at pins:
- VSENSE1–5
- VMON1–3
–200
–100
–50
nA
(5)
VTEST = 0.8 V
RAMP and ACTIVE only
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
BUCK CONTROLLER (BUCK1)
tOCBUCK1_BLK
RSTN and ERROR mode transition, when over current detected for > tOCBUCK1_BLK
1
ms
LED AND HIGH-SIDE SWITCH CONTROL
tHSOL_BLK
Open load blanking time
tHSS
Net time in current limit to disable driver
tS
CL
HS
70
100
140
µs
4
5
6
ms
Current-limit sampling interval
100
Time from rising HSPWM till high-side
switch in current limitation, ±5% settling
tON
fHS_IN
30
µs
60
µs
100
500
Hz
10
20
µs
Time from rising HSPWM till high-side
switch till voltage-clamp between
HSSENSE – HSCTRL active (within VGS
limits)
Turnon time
HSPWM input frequency
Design information, no device parameter
µs
30
REFERENCE VOLTAGE
TREF_OK
Reference voltage OK deglitch time
SHUTDOWN COMPARATOR
TVT_REF_FLT
VT_REF fault deglitch time
Overvoltage or short condition on VT_REF
10
20
µs
Min. pulse width at WAKE to enable device
VWAKE = 4 V to suppress short spikes at
WAKE pin
10
20
µs
VVSENSE < VSSENSETH_xx → IRQ asserted
10
35
µs
WAKE INPUT
tWAKE
VBAT UNDERVOLTAGE WARNING
tVSSENSE_BLK
Blanking time
VIN OVERVOLTAGE PROTECTION
tOFF BLK-H
OV delay time
VIN > VOVTH_H → GPFET off
tOFF BLK-L
OV blanking time
VIN > VOVTH_L → GPFET off
1
10
µs
20
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Timing Requirements (continued)
MIN
TYP
MAX
UNIT
230
300
370
ms
18
20
22
19.8
22
24.2
WINDOW WATCHDOG
ttimeout
Timeout
tWD
Watchdog window time
tWD_FAIL
Closed window time
tWD_BLK
WD filter time
TESTSTART, TESTSTOP, VTCHECK ,
and RAMP mode:
Starts after entering each mode.
ACTIVE mode:
WD timeout starts with rising edge of
RESN
Spread spectrum disabled
Spread spectrum enable
ms
tWD / 4
1.2
µs
2.2
ms
20
µs
RESET AND IRQ BLOCK
tRESNHOLD
RESN hold time
tIRQHOLD
IRQ hold time
tDR IRQ PRESN
Rising edge delay of IRQ to rising edge of PRESN
2
µs
tDF
Falling edge delay of RESN to PRESN / IRQ
2
µs
RESN_PRESN
1.8
After VVSENSE < VSSENSETH for tVSSENSE_BLK
2
10
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
tSD-BLK
Blanking time before thermal shutdown
10
20
µs
tOT_BLK
Blanking time before thermal over temperature
10
20
µs
10
20
µs
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
tVMON_BLK
Blanking time between UV/OV condition to RESN low
UV/OV: BUCK1/2/3 UV: VIO
tVMONTHL_BLK
Blanking time between undervoltage condition to
ERROR mode transition or corresponding SPI bit
BUCK1/2/3 → ERROR mode LDO or
BOOST → SPI bit set or turn off
tVMONTHL_BLK1
Blanking time between undervoltage condition to
ERROR mode transition
VIO only
10
20
µs
tVMONTHH_BLK1
Blanking time between overvoltage condition to
ERROR mode transition
BUCK1/2/3 → ERROR mode VIO has no
OV protection
10
20
µs
tVMONTHH_BLK2
Blanking time LDO and BOOST overvoltage condition
to corresponding SPI bit or ERROR mode
LDO or BOOST (ACTIVE mode) → SPI bit
set or turn off LDO (VTCHECK or RAMP
mode) → ERROR mode
20
40
µs
5
20
µs
1
ms
GND LOSS
tGL-BLK
Blanking time between GND loss condition and transition to ERROR state
POWER-UP SEQUENCING
tSTART1
Soft start time of BOOST
From start till exceeding VMONTH_L +
VMON_HY Level
0.7
2.7
ms
tSTART2
Soft start time of BUCK1/2/3 and LDO
From start till exceeding VMONTH_L +
VMON_HY Level
0.5
2
ms
tSTART
Startup DVDD regulator
From start till exceeding VMONTH_L +
VMON_HY Level
3
ms
tSEQ2
Sequencing time from start of BUCK1 to BUCK2 and
BOOST
Internal SSDONE_BUCK1 signal
3
ms
tWAKE-RES
Startup time from entering TESTSTART to RESN high
GPFET = IRFR6215
tSEQ1
Sequencing time from start of BOOST to BUCK3
Internal SSDONE_BOOST signal
14
ms
1
4
ms
10
20
µs
INTERNAL VOLTAGE REGULATORS
tDVDD
Blanking time from DVDD overvoltage condition to shutdown mode transition
OV
SPI INTERFACE
tSPI
SCK period
tSCKL
SCK low time
tSCKH
SCK high time
tFSIV
Time between falling edge of CSN and SDO output
valid (FSI bit)
Falling SDO < 0.8 V; Rising SDO > 2 V,
See Figure 1
80
ns
tSDOV
Time between rising edge of SCK and SDO data valid
Falling SDO < 0.8 V; Rising SDO > 2 V,
See Figure 1
55
ns
tSDIS
Setup time of SDI before falling edge of SCK
See Figure 1
tSDOH
Hold time of SDO after rising edge of SCK
tHCS
Hold time of CSN after last falling edge of SCK
tSDOtri
Delay between rising edge of CSN and SDO 3-state
14
See Figure 1
See Figure 1
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240
ns
100
ns
100
ns
20
ns
5
ns
50
ns
80
ns
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Timing Requirements (continued)
MIN
tmin2SPI
Minimum time between two SPI commands
TYP
MAX
UNIT
10
µs
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK CONTROLLER (BUCK1)
fSWBUCK1
Switching frequency
fOSC / 10
High-side minimum on time
DC
Duty cycle
tDEAD_BUCK1
Shoot-through delay, blanking time
100
Maximum duty cycle
ns
98.75%
25
ns
SYNCHRONOUS BUCK CONVERTER BUCK2/3
fSWLBuck2/3
Buck switching frequency
fOSC / 2
High-side minimum on time
DCBUCK2/3
Duty cycle
tDEAD_BUCK2/3
Shoot-through delay
50
Maximum duty cycle
ns
99.8%
20
ns
BOOST CONVERTER
fSWLBOOST
Boost switching frequency
DCBOOST
Maximum internal MOSFET duty cycle
at fSWLBOOST
fOSC / 2
75%
GLOBAL PARAMETERS
fOSC
Internal oscillator used for Buck or
Boost switching frequency
4.6
fspread
Spread spectrum frequency range
0.8 × fOSC
4.9
5.2
MHz
fOSC
CSN
TSPI
tHcs
SCK
tFSIV
SDO
tSDOV
FSI
tSCKL
Bit15
tSDIS
SDI
tSCKH
tSDOtri
Bit14
Bit0
tSDIH
Bit15
Bit14
Bit0
Figure 1. SPI Timing
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7.8 Typical Characteristics
All parameters are measured on a TI EVM, unless otherwise specified.
7.8.1 BUCK 1 Characteristics
Figure 2. Reduction of Current-Limit vs Duty Cycle
7.8.2 BUCK 2 and BUCK3 Characteristics
810
VSUP2 = 5 V, 25°C
806
802
VSUP2 = 3.8 V, -40°C
802
800
798
796
VSENSE3 (mV)
VSUP2 = 3.8 V, 140°C
804
VSENSE2 (mV)
VSUP3 = 3.8 V, 25°C
VSUP3 = 3.3 V, 25°C
VSUP3 = 5 V, 25°C
VSUP3 = 3.8 V, 140°C
VSUP3 = 3.8 V, -40°C
804
VSUP2 = 3.8 V, 25°C
808
800
798
796
794
794
792
792
790
790
0
0.5
1
1.5
2
0
0.5
Load Current (A)
1.5
2
Load Current (A)
Figure 3. Load Regulation BUCK2 = 3.3 V
EXTSUP Pin Open
16
1
Figure 4. Load Regulation BUCK3 = 1.2 V
EXTSUP Pin Open
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BUCK 2 and BUCK3 Characteristics (continued)
805
805
804
25°C
804
803
-40°C
803
25°C
-40°C
140°C
140°C
802
VSENSE3 (mV)
VSENSE2 (mV)
802
801
800
799
801
800
799
798
798
797
797
796
796
795
795
2
4
6
8
10
12
2
4
6
8
10
12
VSUP2 (V)
VSUP3 (V)
Figure 5. Open-Load Line Regulation BUCK2 = 3.3 V
EXTSUP Pin Open
Figure 6. Open-Load Line Regulation BUCK3 = 1.2 V
EXTSUP Pin Open
10
6
9
5.5
5
8
4.5
7
I_VSUP3 (mA)
I_VSUP2 (mA)
4
6
5
4
3.5
3
2.5
2
3
25°C
25°C
1.5
-40°C
2
-40°C
0.5
140°C
125°C
1
0
0
3
5
7
9
11
2
4
6
8
10
12
VSUP2 (V)
VSUP3 (V)
Figure 7. Open-Load Supply Current BUCK2 = 3.3 V
EXTSUP Pin Open
Figure 8. Open-Load Supply Current BUCK3 = 1.2 V
EXTSUP Pin Open
801
802
800.5
801.5
801
800
VSENSE3 (mV)
VSENSE2 (mV)
1
799.5
799
800.5
800
799.5
798.5
VSUP2 = 3.8 V, NO LOAD
799
VSUP3 = 3.8 V, NO LOAD
798
-50
-30
-10
10
30
50
70
90
110
130
150
798.5
-50
Temperature (°Celcius)
-30
-10
10
30
50
70
90
110
130
150
Temperature (°Celcius)
Figure 9. BUCK2 = 3.3-V VSENSE2 vs Temperature
EXTSUP Pin Open
Figure 10. BUCK3 = 1.2-V VSENSE3 vs Temperature
EXTSUP Pin Open
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0.81
0.81
0.805
0.805
VSENSE5 (V)
VSENSE5 (V)
7.8.3 BOOST Characteristics
0.8
0.795
0.8
0.795
0.79
0.79
3
3.2
3.4
3.6
3.8
4
0
0.1
0.2
VSUP5 (V)
0.3
0.4
0.5
Load Current (A)
Figure 11. Open-Load Line Regulation BOOST = 5 V, AT
25°C, EXTSUP Pin Open, BOOST Supply Input = 3.8 V
Figure 12. Load Regulation BOOST = 5 V AT 25°C
EXTSUP Pin Open, BOOST Supply Input = 3.8 V
805
804
803
VSENSE5 (mV)
802
801
800
799
798
797
796
795
-50
0
50
100
150
Temperature (°Celcius)
Figure 13. BOOST = 5-V VSENSE5 vs Temperature
EXTSUP Pin Open, Input Supply = 3.8-V, 0.4-A Load
7.8.4 LDO Noise Characteristics
(2 × 3.3-µF output capacitance, LDO output = 2.5 V, VSUP4 = 3.8 V)
10
9
Noise [LDO ON]
8
Noise [LDO OFF]
(Noisefloor)
NOISE (µV / ÖHz)
7
6
5
4
3
2
1
0
10
100
1000
10000
Frequency (Hz)
Figure 14. LDO Noise Density
18
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8 Detailed Description
8.1 Overview
The device includes one high-voltage buck controller for pre-regulation combined with a two-buck and one-boost
converter for post regulation. A further integrated low-dropout (LDO) regulator rounds up the power-supply
concept and offers a flexible system design with five independent-voltage rails. The device offers a low power
state (LPM0 with all rails off) to reduce current consumption in case the system is constantly connected to the
battery line. All outputs are protected against overload and over temperature.
An external PMOS protection feature makes the device capable of sustaining voltage transients up to 80 V. This
external PMOS is also used in safety-critical applications to protect the system in case one of the rails shows a
malfunction (undervoltage, overvoltage, or overcurrent).
Internal soft-start ensures controlled startup for all supplies. Each power-supply output has an adjustable output
voltage based on the external resistor-network settings.
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8.2 Functional Block Diagram
IRQ
VBUCK1
VIO
EXTSUP
VINPROT
GND
VIN
DVDD
UV
Warning
GPFET
VINPROT
VSSENSE
VBAT
OV
Protection
DVDD
+ POR
UV
Monitoring
VEXTSUP-TH
5.8V
Bandgap1
Bandgap2
VREG
VREG
BOOT1
RESN
PRESN
WD
WAKE
RESET
/
Window
Watchdog
Digital
Logic
GU
PH1
Wake Up
circuit
GL
PGND1
CSN
SDI
+
VREF
Bandgap3
DVDD
VT_REF
Short
Protection
VT
COMP1
SMPS Current Mode
Control
SDO
SPI
Sync. Buck Controller
BUCK1
(current mode)
SCK
S1
VBUCK1
S2
VSENSE1
VMON1
Voltage
Monitoring
Sync. Buck Converter
BUCK2
(low voltage)
VSUP2
VBUCK1
BOOT2
+
GND
-
VINPROT
LT
VBuck2
PH2
Shutdown
Comparator
COMP2
SMPS Voltage
Mode Control
GND
HSSENSE
HSCTRL
LED Driver
HSPWM
PGND2
VSENSE2
VMON2
Voltage
Monitoring
VBUCK1
COMP5
Sync. Buck Converter
BUCK3
(low voltage)
Booster
LDO
VSUP3
VBUCK1
BOOT3
(Low voltage)
PH5
VBuck3
VSENSE5
COMP3
+
-
PGND3
VSENSE3
VMON3
Voltage
Monitoring
VLDO
VBUCK1
VSENSE4
Voltage
Monitoring
VSUP4
Voltage
Monitoring
LDO_OUT
VBooster
SMPS
Voltage
Mode
Control
SMPS Voltage
Mode Control
PGND5
VBOOST
PH3
Charge
Pump
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Figure 15. Detailed Block Diagram
20
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8.3 Feature Description
8.3.1 Buck Controller (BUCK1)
The main buck controller operates using constant frequency peak current mode control. The output voltage is
programmable with external resistors.
The switching frequency is set to a fixed value of fSWBUCK1. Peak current-mode control regulates the peak current
through the inductor such that the output voltage VBUCK1 is maintained to its set value. Current mode control
allows superior line-transient response. The error between the feedback voltage VSENSE1 and the internal
reference produces an error signal at the output of the error amplifier (COMP1) which serves as target for the
peak inductor current. At S1–S2, the current through the inductor is sensed as a differential voltage and
compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at
VSENSE1, which causes COMP1 to rise or fall respectively, thus increasing or decreasing the current through
the inductor until the average current matches the load. In this way the output voltage VBUCK1 is maintained in
regulation.
Sense Resistor
VINPROT
L
RS
GU
HS
DCR Sensing
L
PWM
Logic
RL
PH
Gate
Drivers
VBUCK1
GL
LS
RDCR
CDCR
Current
Comparator
S1
VS1-S2,INT
VSLOPE
Current
Sensing
VS1-S2, EXT
S2
Slope
Compensation
gm
Error
Amp
Current Loop
(Inner Loop)
R1
VSENSE1
C2
R2
COMP1
R3
C1
Voltage Loop (Outer Loop)
Figure 16. Detailed Block Diagram of Buck 1 Controller
The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the
inductor current reaches its peak value as set by the voltage loop. Once the high external FET is turned OFF,
and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the
next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth period the duty
cycle is limited to 95% in order to charge the bootstrap capacitor at BOOT1. This allows a maximum duty cycle
of 98.75%.
The maximum value of COMP1 is clamped so that the maximum current through the inductor is limited to a
specified value. The BUCK1 controller output voltage is monitored by a central independent voltage-monitoring
circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition, BUCK1
is thermally protected with a dedicated temperature sensor.
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Feature Description (continued)
8.3.2 Synchronous Buck Converters BUCK2 and BUCK3
Both regulators are synchronous converters operating with a fixed switching frequency ƒsw = 2.45 MHz. For each
buck converter, the output voltage is programmable with external resistors. The synchronous operation mode
improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216-degree
shift to BUCK3 to minimize input current ripple.
Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground. In
case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when its
current reaches IHS-Limit and the low-side FET is turned on until the end of the given cycle. When the current limit
is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is forced
low for sixteen cycles to prevent uncontrolled current build-up. In case the low-side current limit of ILS-Limit is
reached, for example, because of an output short to the VSUP2 and VSUP23 pins, the low-side FET is turned off
until the end of the cycle. If this is detected shortly after the high-low PWM transition (immediately after the lowside overcurrent comparator blanking time), both FETs are turned off for sixteen cycles.
The output voltages of the BUCK2 and BUCK3 regulators are monitored by a central independent voltagemonitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In
addition BUCK2 and BUCK3 are thermally protected with a dedicated temperature sensor.
8.3.3 BOOST Converter
The BOOST converter is an asynchronous converter operating with a fixed switching frequency ƒsw = 2.45 MHz.
It switches in phase with BUCK1. At low load, the boost regulator switches to pulse skipping.
The output voltage is programmable with external resistors.
The internal low-side switch can handle maximum 1-A current, and is protected with a current limit. In case of an
overcurrent, the integrated cycle-by-cycle current limit turns off the low-side FET when its current reaches
ICLBOOST until the end of the given cycle. When the current limit is reached in the beginning of the cycle for five
consecutive cycles, the PWM is forced low for sixteen cycles to prevent uncontrolled current build-up.
The BOOST converter output voltage is monitored by a central independent voltage-monitoring circuit, which has
an independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE5 or VSENSE5 >
VMONTH_H, the output is switched off and the BOOST_FAIL bit in the SPI PWR_STAT register is set. The BOOST
can be reactivated by setting BOOST_EN bit in the PWR_CONFIG register.
In addition, the BOOST converter is thermally protected with a dedicated temperature sensor. If TJ > TOTTH, the
BOOST converter is switched off and bit OT_BOOST in PWR_STAT register is set. Reactivation of the booster is
only possible if the OT_BOOST bit is 0, and the booster enable bit in the PWR_CONFIG register is set to 1.
8.3.4 Frequency-Hopping Spread Spectrum
The TPS65311-Q1 features a frequency-hopping pseudo-random spectrum or triangular spreading architecture.
The pseudo-random implementation uses a linear feedback shift register that changes the frequency of the
internal oscillator based on a digital code. The shift register is designed in such a way that the frequency shifts
only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies. The triangular
function uses an up-down counter. Whenever spread spectrum is enabled (SPI command), the internal oscillator
frequency is varied from one BUCK1 cycle to the next within a band of 0.8 x fOSC ... fOSC from a total of 16
different frequencies. This means that BUCK3 and BOOST also step through 16 frequencies. The internal
oscillator can also change its frequency during the period of BUCK2, yielding a total of 31 frequencies for
BUCK2.
8.3.5 Linear Regulator LDO
The LDO is a low drop out regulator with an adjustable output voltage through an external resistive divider
network. The output has an internal current-limit protection in case of an output overload or short circuit to
ground. In addition, the output is protected against overtemperature. If TJ > TOTTH, the LDO is switched off and bit
OT_LDO in PWR_STAT register is set. Reactivation of the LDO is only possible through the SPI by setting the
LDO enable bit in the PWR_CONFIG register to 1 if the OT_LDO bit is 0.
22
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Feature Description (continued)
The LDO output voltage is monitored by a central independent voltage-monitoring circuit, which has an
independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE4 or VSENSE4 >
VMONTH_H, the output is switched off and the LDO_FAIL bit in the SPI PWR_STAT register is set. The LDO can
be reactivated through the SPI by setting the LDO_EN bit in the PWR_CONFIG register. In case of overvoltage
in VTCHECK and RAMP mode, the GPFET is turned off and the device changes to ERROR mode.
8.3.6 Gate Driver Supply
The gate drivers of the BUCK1 controller, BUCK2 and BUCK3 converters and the BOOST converter are supplied
from an internal linear regulator. The internal linear regulator output (5.8-V typical) is available at the VREG pin
and must be decoupled using a typical 2.2-μF ceramic capacitor. This pin has an internal current-limit protection
and must not be used to power any other circuits.
The VREG linear regulator is powered from VINPROT by default when the EXTSUP voltage is less than 4.6 V
(typical).
If the VINPROT is expected to go to high levels, there can be excessive power dissipation in this regulator when
using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin,
which can be connected to a supply less than VINPROT but high enough to provide the gate drive. When
EXTSUP is connected to a voltage greater than 4.8 V, the linear regulator automatically switches to EXTSUP as
its input to provide this advantage. This automatic switch-over to EXTSUP can only happen once the TPS65311Q1 device reaches ACTIVE mode. Efficiency improvements are possible when one of the switching regulator
rails from the TPS65311-Q1, or any other voltage available in the system is used to power EXTSUP. The
maximum voltage that must be applied to EXTSUP is 12 V.
8.3.7 RESET
RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in Table 1 are
valid. RESN active (low) is extended for tRESNHOLD after a reset is triggered. RESN is the main processor reset
and also asserts PRESN as a slave signal.
PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at the
WD pin).
RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and
power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages
the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and
PRESN are asserted, even if VIN falls below VPOR or the device is in SHUTDOWN mode.
Loss of LPM clock
Thermal Shutdown
RESN
WD_RESET
POR
Loss of GND
Mono
Flop
•1
Voltage Monitor Buck1-3 fail
Voltage Monitor VIO fail
•1
PRESN
RESET
Over Temperature BUCK1-3, VREG
Over Voltage LDO
S
WD Trigger
Q
R
Over-Current BUCK1
Figure 17. RESET Functionality
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Feature Description (continued)
Table 1. Reset Conditions
RESET CONDITION
CONSEQUENCE FOR DEVICE
POR, Loss of LPM Clock, and Thermal Shutdown
The device reinitializes all registers with their default values. Error counter
is cleared.
Voltage Monitor BUCK 1-3
Input voltage at VMON1-3 pin out-of-bounds:
VVMON1-3 < VMONTH_L or VVMON1-3 > VMONTH_H
Over Voltage LDO
Vsense4 > VMONTH_H
Voltage Monitor VIO
Input voltage at VIO pin out-of-bounds: VVIO < VVIOMON TH
Loss of GND
Open at PGNDx or GND pin
OT BUCK1, BUCK2, BUCK3, VREG
Overtemperature on BUCK1–3 or VREG
WD_RESET
Watchdog window violation
Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by
one. After a reset is consecutively triggered NRES times, the device transfers to the LPM0 state, and the EC is
reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can be
put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated again
by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device in
case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal
shutdown or a loss of LPM clock. Once the device is locked, a voltage below VPOR at VIN pin or a thermal
shutdown condition are the only ways to unlock the device.
8.3.8 Soft Start
The output voltage slopes of BUCK, BOOST and LDO regulators are limited during ramp-up (defined by tSTARTx).
During this period the target output voltage slowly settles to its final value, starting from 0 V. In consequence,
regulators that offer low-side transistors (BUCK1, BUCK2 and BUCK3) actively discharge their output rails to the
momentary ramp-value if previously charged to a higher value.
8.3.9 Power-on Reset Flag
The POR flag in the SYS_STAT SPI register is set:
• When VIN is below the VPOR threshold
• System is in thermal shutdown
• Over or undervoltage on DVDD
• Loss of low power clock
8.3.10 WAKE Pin
Only when the device is in LPM0 mode, it can be activated by a positive voltage on the WAKE pin with a
minimum pulse width tWAKE. A valid wake condition is latched. Normal deactivation of the device can only occur
through the SPI Interface by sending an SPI command to enter LMP0. Once in LMP0, the device stays in LPM0
when the WAKE pin is low, or restarts to TESTSTART when the WAKE pin is high.
The WAKE pin has an internal pulldown resistance RPD-WAKE, and the voltage on the pin is not allowed to exceed
60 V. A higher voltage compliance level in the application can be achieved by applying an external series resistor
between the WAKE pin and the external wake-up signal.
The device cannot be re-enabled by toggling the WAKE pin when the device is in LOCKED state (by SPI
command).
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PowerOn
Reset
VIN > VPOR
(EC==0)
VT>VTTH-H (if enabled)
VT_ref_ok = µ1¶
AND VT<VTTH-L
AND vreg_ok = µ1¶
AND SMPS clock O.K.
VTCHECK
no OV (BUCK1, LDO)
RAMP
Independent voltage monitors
(IVM)
OV (BUCK1, LDO)
OR OV (BUCK2,
BUCK3 if enabled)
AND TJ < TOTTH
Timeout**
AND WAKE
terminal low
INIT
TESTSTOP
CRC=O.K.
AND EE ready
AND Vreg_ok = 0
READY****
UV and OV
Timeout**
AND WAKE
terminal low
Independent voltage
monitors
and VIO
Timeout**
AND WAKE
terminal low
OR TJ > TOTTH
(BUCK1-3,VREG)
OR vreg_ok = µ0¶
OR VT_ref_ok = µ0¶
OR no SMPS clock
OR BUCK1 OC
OR GND LOSS
(EC++)
OV (BUCK1, LDO)
OR Tj > TOTTH
(BUCK1-3,VREG)
OR GND LOSS
(EC++)
Voltage Monitors < VMONTHL
AND TJ < TOTTH
TESTSTART
ERROR
EC=NRES (ECm0, EC_OFm )
Timeout**
AND WAKE
terminal low
WD Reset
(EC++)
VT>VTTH-H
(if enabled)
Wake
(WAKE
terminal high)
EC=NRES
(ECm0, EC_OFm )
OR SPI LPM0 CMD
(EC--)
ACTIVE
All RESET events*** (w/o WD)
OR vreg_ok = µ0¶
OR vref_ok = µ0¶
OR VT_REF_ok = µ0¶
OR no SMPS clock
(EC++)
LPM0
SPI LOCK CMD
LOCKED
TJ >TSDTH OR VIN < VPOR
OR DVDD UV/OV
OR loss of low power clock
* GPFET is turned on in VTCHECK, RAMP, ACTIVE and if
VIN<VINOV
** TIMEOUT counter is reset with every state transition
SHUTDOWN
Generation of
POR
*** RESET EVENTS : WD, GROUND LOSS, VOLTAGE
MONITOR BUCK1, MONITOR BUCK2-3(if enabled), Over
Voltage LDO (if enabled), VOLTAGE MONITOR VIO,
OVERTEMPERATURE BUCK1-3 OR VREG, BUCK1
OVERCURRENT
**** READY = VREF_OK and not BUCK1_UV and Power Up
Sequence completed
Figure 18. Operating Mode Transitions
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8.3.11 IRQ Pin
The IRQ pin has two different functions. In OPERATING mode, the pin is forced low when the voltage on the
battery line is below the VSSENSETHx threshold. The IRQ pin is low as long as PRESN is low. If PRESN goes high
and the battery line is already below the VSSENSETHx threshold, the IRQ pin is forced high for tVSSENSE_BLK.
8.3.12 VBAT Undervoltage Warning
•
•
•
•
Low battery condition on VSSENSE asserts IRQ output (interrupt for µC, open drain output)
Sense input can be directly connected to VBAT through the resistor
Detection threshold for undervoltage warning can be selected through the SPI.
An integrated filter time avoids false reaction due to spikes on the VBAT line.
8.3.13 VIN Over or Undervoltage Protection
•
•
•
•
•
Undervoltage is monitored on the VIN line, for POR generation.
Two VIN overvoltage shutdown thresholds (VOVTH) can be selected through the SPI. After POR, the lower
threshold is enabled.
During LPM0, only the POR condition is monitored.
An integrated filter time avoids false reaction due to spikes on the VIN line.
In case of overvoltage, the external PMOS is switched off to protect the device. The BUCK1 controller is not
switched off and it continues to run until the undervoltage on VREG or BUCK1 output is detected.
VINPROT
VBAT
VSSENSE
VIN
GPFET
IRQ
UV
Internal Supply
PWR_CMD
Bit0
LV_THRES
OV
=
LOCKED
ERROR
=
LPM0
•1
INIT
TESTSTART
TESTSTOP
DVDD
+ POR
Figure 19. Overvoltage or Undervoltage Detection Circuitry
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8.3.14 External Protection
The external PMOS switch is disabled if:
• The device detects VIN overvoltage
• The device is in ERROR, LOCKED, POR, INIT, TESTSTART, TESTSTOP or LPM0 mode
VSSENSE
1k
NOTE
Depending on the application, the external PMOS may be omitted as long as
VBAT < 40 V
VIN
PCH
GPFET
PCH
VINPROT
20µA
50 ± 60V
GND
Figure 20. PMOS Control Circuitry
8.3.15 Overtemperature Detection and Shutdown
There are two levels of thermal protection for the device.
Overtemperature is monitored locally on each regulator.
OT for BUCK1, BUCK2, and BUCK3 If a thermal monitor on the buck rails reaches a threshold higher than
TOTTH, the device enters ERROR mode. Leaving ERROR mode is only possible if the temperature
is below TOTTH–TOTHY.
OT for BOOST and LDO If the temperature monitor of the boost or the LDO reaches the TOTTH threshold, the
corresponding regulator is switched off.
Overtemperature Shutdown is monitored on a central die position. In case the TSDTH is reached, the device
enters shutdown mode. It leaves shutdown when the TSD sensor is below TSDTH – TSDHY. This
event internally generates a POR.
8.3.16 Independent Voltage Monitoring
The device contains independent voltage-monitoring circuits for BUCK1–3, LDO, VIO and BOOST. The
reference voltage for the voltage monitoring unit is derived from an independent bandgap. BUCKs 1–3 use
separate input pins for monitoring. The monitoring circuit is implemented as a window comparator with an upper
and lower threshold.
If there is a violation of the upper (only LDO [RAMP, VTCHECK], or BUCK1–3) or lower threshold (only
BUCK1–3, or VIO), the device enters ERROR mode, RESN and PRESN are asserted low, the external PMOS
(main system switch) is switched off, and the EC is incremented.
In TESTSTART mode, a self-test of the independent voltage monitors is performed.
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In case any of the supply rails for BUCK2, BUCK3, LDO or BOOST are not used in the application, the
respective VMON2 and VMON3 or VSENSE4 and VSENSE5 pin of the unused supply must be connected to
VMON1. Alternatively, the VSENSE4 pin can also be connected directly to ground in case the LDO is not used.
8.3.17 GND Loss Detection
All power grounds PGNDx are monitored. If the voltage difference to GND exceeds VGLTH-low or VGLTH-high, the
device enters ERROR mode. RESN and PRESN are asserted low, the external PMOS (main system switch) is
switched off, and the EC is incremented.
8.3.18 Reference Voltage
The device includes a precise voltage reference output to supply a system ADC. If this reference voltage is used
in the application, a decoupling capacitor between 0.6 and 5 µF must be used. If this reference voltage is not
used in the application, this decoupling capacitor can be left out. The VREF output is enabled in RAMP state.
The output is protected against a short to GND.
8.3.19 Shutdown Comparator
An auxiliary, short circuit protected output supplied from DVDD is provided at the VT_REF pin. This output is
used as a reference for an external resistive divider to the VT pin. In case a voltage > VTTH is detected on the
VT pin, the main switch (external PMOS driven by GPFET) is switched off. This functionality can be used to
monitor over and under temperature (using a NTC resistor) to avoid operation below or above device
specifications.
If the voltage at VT_REF falls below VVT_REF SH while the shutdown comparator is enabled, an ERROR transition
occurs. The shutdown comparator is enabled in VTCHECK state, and can be turned off by SPI. Disabling the
comparator saves power by also disabling the VT_REF output.
8.3.20 LED and High-Side Switch Control
This module controls an external PMOS in current-limited high-side switch.
The current levels can be adjusted with an external sense resistor. Enable and disable is done with the HS_EN
bit. The switch is controlled by the HSPWM input pin. Driving HSPWM high turns on the external FET.
The device offers an open load diagnostic indicated by the HS_OL flag in the SPI register PWR_STAT. Open
load is also indicated in case the voltage on VINPROT–VSSENSE does not drop below the threshold when PWM
is low (self-test).
A counter monitors the overcurrent condition to detect the risk of overheating. While HSPWM = high and HS_EN
= high the counter is incremented during overcurrent conditions, and decremented if the current is below the
overcurrent threshold at a sampling interval of tS HS (see Figure 22). When reaching a net current limit time of tHSS
CL, the driver is turned off and the HS_EN bit is cleared. This feature can be disabled by SPI bit HS_CLDIS.
When HS_EN is cleared, the counter is reset.
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VINPROT
VINPROT
HSPWM
VHSSENSE
VHSOL_TH
OL
HSSENSE
VHS_SC
HSCTRL
SC
ECU
Connector
Figure 21. High-Side Control Circuit
VHSPWM
PWM
VVINPROT - VHSSENSE
VHSSENSE
VHS_SC
countermax ) WHSS_CL
HS_EN
HS_CLDIS
Figure 22. HS Overcurrent Counter
NOTE
In case the LED or high-side switch control is not used in the application, HSSENSE must
be connected to VINPROT.
8.3.21 Window Watchdog
The WD is used to detect a malfunction of the MCU and DSP. Description:
• Timeout trigger mode with long timing starts on the rising edge at RESN
• Window trigger mode with fixed timing after the first and each subsequent rising edge at the WD pin
• Watchdog is triggered by rising edge at the WD pin
A watchdog reset happens by:
• A trigger pulse outside the WD trigger open window
• No trigger pulse during window time
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After the RESN pin is released (rising edge) the DSP and MCU must trigger the WD by a rising edge on the WD
pin within a fixed time ttimeout. With this first trigger, the window watchdog functionality is released.
Start of tWD time with a
rising edge of WD
VWD
WD Trigger fail
WD Trigger open window
tWD_FAIL_min
t
tWD_FAIL_max
tWD1_min
tWD_min
tWD_max
Figure 23. WD Window Description
8.3.22 Timeout in Start-Up Modes
A timer is used to limit the time during which the device can stay in each of the start-up modes: TESTSTART,
TESTSTOP, VTCHECK and RAMP. If the device enters one of these start-up modes and VIN or VT is not in a
proper range, the part enters LPM0 after ttimeout is elapsed and the WAKE pin is low.
8.4 Device Functional Modes
8.4.1 Operating Modes
8.4.1.1 INIT
Coming from a power-on reset the device enters INIT mode. The configuration data from the EEPROM is loaded
in this mode. If the checksum is valid and the internal VREG monitor is indicating an undervoltage condition (selftest VREG comparator), the device enters TESTSTART.
8.4.1.2 TESTSTART
TESTSTART mode is entered:
• After the INIT state (coming from power on)
• After detecting that VT > VTTH-H
• After ERROR mode and the fail condition is gone
• After a wake command in LPM0
In this mode the OV and UV comparators of BUCK1, BUCK2, BUCK3, BOOST, LDO and VIO are tested. The
test is implemented in such a way that during this mode all comparators have to deliver a 1 (fail condition). If this
is the case the device enters TESTSTOP mode.
If this is not the case, the device stays in TESTSTART. If the WAKE pin is low, the device enters LPM0 after
ttimeout. If the pin WAKE is high, the part stays in TESTSTART.
8.4.1.3 TESTSTOP
In this mode the OV and UV comparators are switched to normal operation. It is expected that only the UV
comparators give a fail signal. In case there is an OV condition on any rail or one of the rails has an
overtemperature the device stays in TESTSTOP. If the WAKE pin is low the device enters LPM0 mode after
ttimeout. If the WAKE pin is high, the part stays in TESTSTOP. If there is no overvoltage and overtemperature
detected, the part enters VTCHECK mode.
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Device Functional Modes (continued)
8.4.1.4 VTCHECK
VTCHECK mode is used to:
1. Switch on external GPFET in case VIN < VOVTH_L
2. Turn on VREG regulator and VT_REF
3. Check if voltage on pin VT < VTTH-L
4. Check if SMPS clock is running correctly
5. Check if VREG,VT_REF exceed the minimum voltage
If all checks are valid the part enters the RAMP state. In case the device is indicating a malfunction and the
WAKE pin is low, the device enters LPM0 after ttimeout to reduce current consumption.
In case the voltage monitors detect an overvoltage condition on BUCK1, BUCK2, BUCK3, or LDO, a loss of GND
or an overtemperature condition on BUCK1, BUCK2, BUCK3, or VREG the device enters ERROR mode and the
error counter is increased.
8.4.1.5 RAMP
In this mode the device runs through the power-up sequencing of the SMPS rails (see Figure 24).
8.4.1.5.1 Power-Up Sequencing
After the power-up sequence (see Figure 24), all blocks are fully functional. BUCK1 starts first. After tSEQ2
elapses and BUCK1 is above the undervoltage threshold, BUCK2 and BOOST start. BUCK3 and VREF start one
tSEQ1 after BUCK2. After the release of RESN pin, the µC can enable the LDO per SPI by setting bit 4 LDO_EN
in PWR_CONFIG register to 1 (per default, this LDO_EN is set to 0 after each reset to the µC).
In case any of the following conditions occurduring power-up sequencing, the device enters ERROR mode and
the error counter (EC) is increased:
• Overtemperature on BUCK1, BUCK2, BUCK3 or VREG
• Overvoltage on BUCK1, BUCK2, BUCK3 or LDO
• Overcurrent on BUCK1
• SMPS clock fail
• VT_REF and VREG undervoltage
• Loss of GND
In case VT > VTTH-H, the device transitions to TESTSTART.
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Device Functional Modes (continued)
WakeUp event through WAKE terminal
VPOR
VIN
tSTART
VINPROT
VREG-OK / VVT_REF_SH
VREG/
VT_REF
VMONTH_L + VMON_HY
BUCK1
BUCK1 > VMONTH_L + VMON_HY AND tSEQ2 elapsed before BUCK2 and BOOST are enabled
tSTART2
VMONTH_L + VMON_HY
tSEQ2
BOOSTER
tSTART1
VMONTH_L + VMON_HY
BUCK2
tSTART2
VREF_OK
VREF
VMONTH_L + VMON_HY
BUCK3
LDO enabled through SPI by PC
tSEQ1
tSTART2
VMONTH_L + VMON_HY
LDO
tSTART2
tRESNHOLD
RESN
tWAKE-RES
WD
PRESN
Only when device
is in ACTIVE state
In case of permanent supply with the device in LPM0 mode, the start point of VREG-VT_REF is with the rising
edge of WAKE. In case of non-permanent supply, the rising edge of the VSSENSE and VIN terminals initiates
the start-up sequence
Figure 24. Power-up Sequencing
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Device Functional Modes (continued)
After the power-up sequence is completed (except LDO) without detecting an error condition, the device enters
ACTIVE mode.
8.4.1.5.2 Power-Down Sequencing
There is no dedicated power-down sequencing. All rails are switched off at the same time. The external FETs of
BUCK1 are switched off and the outputs of BUCK2, BUCK3, BOOST (PHx) and the LDO are switched in a highimpedance state.
8.4.1.6 ACTIVE
This is the normal operating mode of the device. Transitions to other modes:
→ ERROR
The device is forced to go to ERROR in case of:
• Any RESET event (without watchdog reset)
• VREG, VREF, or VT_REF below undervoltage threshold
• SMPS clock fail
During the transition to ERROR mode the EC is incremented.
→ LOCKED
In case a dedicated SPI command (SPI_LOCK_CMD) is issued.
→ TESTSTART
The device moves to TESTSTART after detecting that VT < VTTH-L.
→ LPM0
The device can be forced to enter LPM0 with a SPI LPM0 command. During this transition the EC is
decremented.
If the EC reaches the NRES value, the device transitions to LPM0 mode and EC is cleared. Depending on the
state of the WAKE pin, the device remains in LMP0 (WAKE pin low) or restart to TESTSTART (WAKE pin high).
To indicate the device entered LPM0 after EC reached NRES value, a status bit EC_OF (error counter overflow,
SYS_STAT bit 3) is set. The EC_OF bit is cleared on read access to the SYS_STAT register.
A watchdog reset in ACTIVE mode only increases the EC, but it does not change the device mode.
8.4.1.7 ERROR
In this mode all power stages and the GPFET are switched off. The devices leave ERROR mode and enter
TESTSTART if:
• All rails indicate an undervoltage condition
• No GND loss is detected
• No overtemperature condition is detected
When the EC reaches the NRES value, the device transitions to LPM0 and the EC is cleared. To indicate the
device entered LPM0 after EC reached NRES, a status bit EC_OF (error counter overflow, SYS_STAT bit 3) is
set. The EC_OF bit is cleared on read access to the SYS_STAT register.
8.4.1.8 LOCKED
Entering this mode disables the device. The only way to leave this mode is through a power-on reset, thermal
shutdown, or the loss of an LPM clock.
8.4.1.9 LPM0
Low-power mode 0 is used to reduce the quiescent current of the system when no functionality is needed. In this
mode the GPFET and all power rails except for DVDD are switched off.
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Device Functional Modes (continued)
In case a voltage > VWAKE_ON longer than tWAKE is detected on the WAKE pin, the part switches to TESTSTART
mode.
8.4.1.10 SHUTDOWN
The device enters and stays in this mode, as long as TJ > TSDTH - TSDHY or VIN < VPOR or DVDD under or
overvoltage, or loss of low power clock is detected. Leaving this mode and entering INIT mode generates an
internal POR.
8.5 Programming
8.5.1 SPI
The SPI provides a communication channel between the TPS65311-Q1 and a controller. The TPS65311-Q1 is
always the slave. The controller is always the master. The SPI master selects the TPS65311-Q1 by setting CSN
(chip select) to low. SDI (slave in) is the data input, SDO (slave out) is the data output, and SCK (serial clock
input) is the SPI clock provided by the master. If chip select is not active (high), the data output SDO is high
impedance. Each communication consist of 16 bits.
1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])
1 bit R/W; read = 0 and write = 1
6 bits CMD identifier
8 bits data
Bit15
Bit14
Parity
R/W
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
CMD_ID5 CMD_ID4 CMD_ID3 CMD_ID2 CMD_ID1 CMD_ID0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 25. SPI Bit-Frame
Each command is valid if:
• A valid CMD_ID is sent
• The parity bit (odd) is correct
• Exactly 16 SPI clocks are counted between falling and rising edge of CSN
The response to each master command is given in the following SPI cycle. The response address is the CMD_ID
of the previous sent message and the corresponding data byte. The response data is latched with the previous
cycle such that a response to a write command is the status of the register before the write access. (Same
response as a read access.) The response to an invalid command is the original command with the correct parity
bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication (CMD_ID = 0x03).
Write access to a read-only register is not reported as an SPI error and is treated as a read access. The initial
answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.
8.5.1.1 FSI Bit
The slave transmits an FSI bit between the falling edge of CSN and the rising edge of SCK. If the SDO line is
high during this time, a failure occurred in the system and the MCU must use the PWR_STAT to get the root
cause. A low level of SDO indicates normal operation of the device.
The FSI bit is set when: PWR_STAT ! = 0x00, or (SYS_STAT and 0x98) ! = 0x00, or SPI_STAT ! = 0x00. The
FSI is cleared when all status flags are cleared.
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8.6 Register Map
CMD_ID
NAME
0x00
NOP
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x03
SPI_SCK_FAIL
0x11
LPM0_CMD
SCK[2]
SCK[1]
SCK[0]
0x12
LOCK_CMD
0x21
PWR_STAT
BUCK_FAIL
VREG_FAIL
OT_BUCK
OT_LDO
0x22
SYS_STAT
WD
POR
TestMode
SMPCLK_FAIL
OT_BOOST
LDO_FAIL
BOOST_FAIL
HS_OL
EC_OF
EC2
EC1
0x23
SPI_STAT
EC0
CLOCK_FAIL
CMD_ID FAIL
PARITY FAIL
0x24
COMP_STAT
0x29
Serial Nr 1
BUCK3-0
BUCK2-1
BUCK2-0
0x2A
Serial Nr 2
Bit [15:8]
0x2B
Serial Nr 3
Bit [23:16]
0x2C
Serial Nr 4
Bit [31:24]
0x2D
Serial Nr 5
Bit [39:32]
0x2E
Serial Nr 6
0x2F
DEV_REV
0x31
PWR_CONFIG
0x32
DEV_CONFIG
0x33
CLOCK_CONFIG
0x00
1
0
0
SCK_OF
SCK[3]
0xAA
0x55
BUCK3-1
Bit [7:0]
Bit [47:40]
Major3
F_EN
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
HL_CLDIS
VT_EN
RSV
RSV
SS_EN
SS_MODE
F4
F3
F2
F1
F0
8.6.1 Register Description
NOP 0x00
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
SPI_SCK_FAIL 0x03
Default after
RESET
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
0
0
0
0
0
Read
1
0
0
SCK_OF
SCK[3]
SCK[2]
SCK[1]
SCK[0]
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
BIT NAME
BIT NO.
SCK_OF
4
DESCRIPTION
Between a falling and a rising edge of CSN, the number of SCK was greater than 16.
0:
1:
Number of SCK cycles was > 16
Comment: This flag is cleared after its content is transmitted to the master.
BIT NAME
SCK[3:0]
BIT NO.
DESCRIPTION
3:0
The number of rising edges on SCK between a falling and a rising edge of CSN minus 1. Saturates at 0xF if
16 or more edges are received.
Comment: This flag is cleared after its content is transmitted to the master.
LPM0_CMD 0x11
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Write
0xAA
This command is used to send the device into LPM0 mode.
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LOCK_CMD 0x12
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Write
0x55
Sending a lock command (0x55) brings the device into LOCK mode. Only a POR brings the device out of this state.
PWR_STAT 0x21
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
OT_BUCK
OT_LDO
OT_BOOST
LDO_FAIL
BOOST_FAIL
HS_OL
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Default after
POR
Read
BUCK_FAIL VREG_FAIL
Write
d.c.
BIT NAME
BIT NO.
BUCK_FAIL
7
d.c.
DESCRIPTION
BUCK power fail flag
0:
1:
Power stages shutdown detected caused by OC BUCK1, UV, OV, loss of GND (BOOST + all bucks)
BUCK_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
Internal voltage regulator too low
VREG_FAIL
6
0:
1:
VREG fail
VREG_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.
BIT NAME
BIT NO.
OT_BUCK
5
DESCRIPTION
BUCK1-3 overtemperature flag
0:
1:
IC power stages shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
LDO overtemperature flag
OT_LDO
4
0:
1:
LDO shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.
BIT NAME
BIT NO.
OT_BOOST
3
DESCRIPTION
Boost overtemperature flag
0:
1:
BOOST shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
LDO under or overvoltage flag
LDO_FAIL
2
0:
1:
LDO out of regulation
LDO_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag is transmitted to the master.
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BIT NAME
BIT NO.
DESCRIPTION
Booster under or overvoltage flag or loss of GND
BOOST_FAIL
1
0:
1:
Booster out of regulation
BOOST_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag was transmitted to the master.
BIT NAME
BIT NO.
HS_OL
0
DESCRIPTION
High-side switch open load condition
0:
1:
Open load at high side
Bit indicates current OL condition of high side (no flag)
SYS_STAT 0x22
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
1
Read
WD
POR
Testmode
SMPCLK_FAIL
0
EC2
EC1
EC0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Default after
POR
BIT NAME
BIT
NO.
WD
7
DESCRIPTION
Watchdog reset flag
0:
1:
Last reset caused by watchdog
Comment: This flag is cleared after its content is transmitted to the master.
BIT NAME
BIT
NO.
POR
6
DESCRIPTION
Power-on reset flag
0:
1:
Last reset caused by a POR condition
Comment: This flag is cleared after its content is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
If this bit is set, the device entered test mode
Testmode
5
0:
1:
Device in Testmode
Comment: This flag is cleared after its content is transmitted to the master and the device left the test mode.
BIT NAME
BIT NO.
DESCRIPTION
If this bit is set, the clock of the switch mode power supplies is too low.
SMPCLK_
FAIL
4
0:
Clock OK
1:
Clock fail
Comment: This flag is cleared after its content is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
Actual error flag counter
EC [2:0]
0-2
0:
-
1:
-
*Error Counter is only deleted with a POR
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SPI_STAT 0x23
Bit7
Bit6
Bit5
Bit4
Bit3
Default after RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
CLOCK_FAIL
CMD_ID FAIL
PARITY FAIL
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
BIT NAME
BIT NO.
CLOCK_FAIL
2
Bit2
Bit1
Bit0
DESCRIPTION
Between a falling and a rising edge of CSN, the number of SCK does not equal 16
0:
1:
Wrong SCK
Comment: This flag is cleared after its content is transmitted to the master.
BIT NAME
BIT NO.
DESCRIPTION
Last received CMD_ID in a reserved area
CMD_ID FAIL
1
0:
1:
Wrong CMD_ID
Comment: This flag is cleared after its content is transmitted to the master and is not set if the number of SCK cycles is incorrect.
BIT NAME
BIT
NO.
PARITY_FAIL
0
DESCRIPTION
Last received command has a parity bit failure
0:
1:
Parity bit error
Comment: This flag is cleared after its content is transmitted to the master and is not set if the number of SCK cycles is incorrect.
COMP_STAT 0x24
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default after
RESET
0
0
0
0
0
1
1
0
Read
0
0
0
0
BUCK3-1
BUCK3-0
BUCK2-1
BUCK2-0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Register to read back the actual BUCK2/3 compensation settings on COMP2/3. 0x1 ≥ 0 V 0 x 2 ≥ VREG 0 x 3 ≥ open
DEV_REV 0x2F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
Major3
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
Read
Major3
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Hard coded device revision can be read from this register
PWR_CONFIG 0x31
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Default after RESET
0
1
1
0
1
0
0
Bit0
0
Read
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
Write
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
This register contains all power rail enable bits.
38
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BIT NAME
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BIT NO.
DESCRIPTION
BUCK2 enable flag
BUCK2_EN
6
0:
1:
Enable BUCK2
After reset, BUCK2 is enabled
BIT NAME
BIT NO.
DESCRIPTION
BUCK3 enable flag
BUCK3_EN
5
0:
1:
Enable BUCK3
After reset, BUCK3 is enabled
BIT NAME
BIT NO.
LDO_EN
4
DESCRIPTION
LDO enable flag
0:
1:
LDO enabled
After reset, LDO is disabled
BIT NAME
BIT NO.
DESCRIPTION
BOOST enable
BOOST_EN
3
0:
1:
BOOST enabled
After reset, BOOST is enabled
BIT NAME
BIT
NO.
HS_EN
2
DESCRIPTION
LED and high-side switch enable
0:
High side disabled
1:
High side enabled
After reset, high side is disabled
BIT NAME
BIT
NO.
GPFET_OV_HIGH
1
DESCRIPTION
Protection FET overvoltage shutdown
0:
Protection FET switches off at VIN > VOVTH-L
1:
Protection FET switches off at VIN > VOVTH-H
After reset, the lower VIN protection threshold is enabled
BIT NAME
BIT NO.
DESCRIPTION
VSSENSE IRQ low voltage interrupt threshold select
IRQ_THRES
0
0:
Low threshold selected (VSSENSETH_L)
1:
High threshold selected (VSSENSETH_H)
After reset, the lower VBAT monitoring threshold is enabled
DEV_CONFIG 0x32
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Default after RESET
0
0
0
0
0
1
1
Bit0
0
Read
0
0
0
0
0
VT_EN
RSV
RSV
Write
d.c.
d.c.
d.c.
d.c.
d.c.
VT_EN
1
0
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BIT NAME
www.ti.com
BIT NO.
DESCRIPTION
LED and high-side switch current limit counter disable bit
HS_CLDIS
3
BIT NAME
0:
LED and high-side switch current limit counter enabled
1:
LED and high-side switch current limit counter disabled
BIT NO.
DESCRIPTION
VT enable bit
VT_EN
2
0:
VT monitor disabled
1:
VT monitor enabled
The VT monitor cannot be turned on after it was turned off. Turn on only happens during power up in the VTCHECK state.
BIT NAME
BIT NO.
DESCRIPTION
Voltage reference enable bit
RSV
1
BIT NAME
0:
not recommended setting
1:
default setting
BIT NO.
DESCRIPTION
Reserved - keep this bit at 1
RSV
0
0:
default setting
1:
not recommended setting
CLOCK_CONFIG 0x33
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
1
0
0
0
0
Read
F_EN
SS_EN
SS_MODE
F4
F3
F2
F1
F0
Write
F_EN
SS_EN
SS_MODE
F4
F3
F2
F1
F0
Default after
RESET
BIT NAME
BIT NO.
DESCRIPTION
Frequency tuning enable register
F_EN
BIT NAME
7
0:
Off – Setting of Bit4…Bit0 are not effective, setting of Bit6 and Bit5 become effective
1:
On – Setting of Bit4…Bit0 become effective, setting of Bit6 and Bit5 are not effective
BIT NO.
DESCRIPTION
Spread spectrum mode enable
SS_EN
6
0:
Spread spectrum option for all switching regulators disabled
1:
Spread spectrum option for all switching regulators enabled (only when F_EN = 0)
When enabled, the switching frequency of BUCK1/2/3 and BOOST is modulated between 0.8×fosc and fosc
BIT NAME
BIT NO.
SS_MODE
5
DESCRIPTION
Spread spectrum mode select (effective only when F_EN = 0)
BIT NAME
F4, F3, F2, F1,
F0
0:
Pseudo random
1:
Triangular
BIT
NO.
4-0
DESCRIPTION
Frequency tuning register (effective only when F_EN = 1)
0x10 is default value, trim range is 25% for 0x00 setting to –20% for 0x1F setting. Frequency tuning influences the switching frequency of
BUCK1/2/3 and BOOST as well as the watchdog timing.
40
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65311-Q1 device is a multi-rail power supply including one buck controller, two buck converters, one
boost converter and one linear regulator (LDO). The buck controller is typically used to convert a higher car
battery voltage to a lower DC voltage which is then used as pre-regulated input supply for the buck converters,
boost converter, and the linear regulator. Use the following design procedure and application example to select
component values for the TPS65311-Q1 device.
9.2 Typical Applications
9.2.1 Buck Controller (BUCK1)
4 V to 40 V
VBAT (typ. 12 V)
D1
2.2 µF
0.1 µF
BOOT1 10
Q2
C3
GU 11
2.2 µF
8
9
VREG
VINPROT
EXTSUP
4
3
GPFET
2
VIN
VSSENSE
1
0.1 µF
10 k
VINPROT
PH1 12
PGND1 14
33 pF
22 m
50 k
16 k
VSENSE1 19
VMON1 17
VBUCK1
VBUCK1
100 µF
C1
C2
50 k
S2 16
R3
16 k
S1 15
1.2 nF
R2
18 24 k
R1
COMP1
0.1 µF
TPS65311-Q1
10 µH
Q3
GL 13
3.3 V,
2.3 A max
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Figure 26. Buck Controller Schematic
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Typical Applications (continued)
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
Output voltage (VBUCK1)
3.3 V
Maximum output current (Imax_peak_coil)
2.3 A
Load Step ΔIOUT
1A
Output current ripple IL_ripple
500 mA
Output voltage ripple
3 mV
Allowed voltage step on output ΔVOUT
0.198 (or 6%)
Switching frequency (fSWBUCK1)
490 kHz
Bandwidth (FBW)
≈ 60 kHz
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
A resistor divider from the output node to the VSENSE1 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with 16 kΩ for the R1 resistor and use Equation 1 to calculate R2 (see
Figure 26).
R1 ´ (VBUCK1 - 0.8 V)
R2 =
0.8 V
(1)
Therefore, for the value of VBUCK1 to equal to 3.3 V, the value of R2 must be 50 kΩ.
For voltage monitoring of the BUCK1 output voltage, placing an additional resistive divider with the exact same
values from the output node to the VMON1 pin is recommended for safety reasons (see Figure 26). If no safety
standard must be fulfilled in the application, the VMON1 pin can be directly connected to VSENSE1 pin without
the need for this additional resistive divider.
9.2.1.2.2 Output Inductor, Sense Resistor, and Capacitor Selection for the BUCK1 Controller
An external resistor senses the current through the inductor. The current sense resistor pins (S1 and S2) are fed
into an internal differential amplifier which supports the range of VBUCK1 voltages. The sense resistor RS must
be chosen so that the maximum forward peak current in the inductor generates a voltage of 75 mV across the
sense pins. This specified typical value is for low duty cycles only. At typical duty-cycle conditions around 28%
(assuming 3.3-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and
mismatches. The typical characteristics (see Figure 2) provide a guide for using the correct current-limit sense
voltage.
60 mV
RS =
I max_ peak
(2)
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
at all conditions. In order to specify optimal performance of this circuit, the following condition must be satisfied in
the choice of inductor and sense resistor:
L = 410 ´ Rs
where
•
•
L = inductor in µH
Rs = sense resistor in Ω
(3)
The current sense pins S1 and S2 are high impedance pins with low leakage across the entire VBUCK1 range.
This allows DCR current sensing (see Figure 16) using the DC resistance of the inductor for better efficiency.
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For selecting the output capacitance and its ESR resistance, the following set of equations can be used:
2 ´ DIOUT
COUT >
ƒSW ´ DVOUT
COUT >
RESR <
IL _ ripple
1
´
8 ´ ƒSW Vo _ ripple
Vo _ ripple
IL _ ripple
where
•
•
•
•
•
ƒsw is the 490-kHz switching frequency
ΔIOUT is the worst-case load step from the application
ΔVOUT is the allowed voltage step on the output
Vo_ripple is the allowed output voltage ripple
IL_ripple is the ripple current in the coil
(4)
9.2.1.2.3 Compensation of the Buck Controller
The main buck controller requires external type 2 compensation on pin COMP1 for normal mode operation. The
components can be calculated as follows.
1. Select a value for the bandwidth, FBW, to be between fSWBUCK1 / 6 (faster response) and fSWBUCK1 / 10 (more
conservative)
2. Use Equation 5 to select a value for R3 (see Figure 16).
2p ´ FBW ´ VOUT1 ´ COUT1
R3 =
gm ´ K CFB ´ VrefBUCK
where
•
•
•
•
COUT1 is the load capacitance of BUCK1
gm is the error amplifier transconductance
KCFB = 0.125 / Rs
VrefBUCK is the internal reference voltage
(5)
3. Use Equation 6 to select a value for C1 (in series with R3, see Figure 16) to set the zero frequency close to
FBW / 10.
10
C1 =
2p ´ R3 ´ FBW
(6)
4. Use Equation 7 to select a value for C2 (parallel with R3, C1, see Figure 16) to set the second pole below
fSWBUCK1 / 2
1
C2 =
2p ´ R3 ´ FBW ´ 3
(7)
For example:
fSWBUCK1 = 490 kHz, VrefBUCK = 0.8 V, FBW = 60 kHz
VOUT1 = 3.3 V, COUT1 = 100 µF, Rs = 22 mΩ
Selected values: R3 = 24 kΩ, C1 = 1.2 nF, C2 = 33 pF
Resulting in FBW: 58 kHz
Resulting in zero frequency: 5.5 kHz
Resulting in second pole frequency: 201 kHz
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components.
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9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
The BUCK1 controller requires a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The bootstrap
capacitor is located between the PH1 pin and the BOOT1 pin (see Figure 26). The bootstrap capacitor must be a
high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
9.2.1.3 BUCK 1 Application Curve
100
90
80
Efficiency (%)
70
60
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
50
40
30
20
10
=
=
=
=
=
=
=
=
=
=
=
5V
8.1 V
10 V
14 V
18 V
22 V
26 V
30 V
34 V
36 V
37 V
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Load Current (A)
2.1
2.4
2.7
D001
Figure 27. Efficiency Results of Buck1
9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
TPS65311-Q1
VBUCK1
30
10 µF
41
10 µF
COMP3
PGND3
VSENSE3
VMON3
3.3 V
42
40
37
1.2 µH
VBuck3
1.8 V, 2 A max
39
33 µF
PH3
62 µF
33
0.1 µF
BOOT3
0.8 k
35
VBUCK1
VSUP3
1.6 k
32
2k
VMON2
34
1.6 k
VSENSE2
1.2 V, 2 A max
0.8 k
PGND2
VBuck2
1.6 k
COMP2
31
1 µH
2k
PH2
29
0.1 µF
BOOT2
3.3 V
1.6 k
VSUP2
36
38
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Figure 28. Synchronous Buck Converter Schematic
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9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Output voltage (VBUCK2/3)
1.2 V
1.8 V
Maximum output current (Imax_peak)
2A
Output current ripple ΔIL_PP
300 mA
Switching frequency (fSWBUCK2/3)
2.45 MHz
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
A resistor divider from the output node to the VSENSE2 to ground respectively between the VSENSE3 to ground
pin sets the output voltage (see Figure 28). TI recommends using 1% tolerance or better divider resistors. Start
by selecting 1.6 kΩ for the value of the Rx resistor between the VSENSE2 to ground respectively between the
VSENSE3 to ground pin VSENSE3 pin and use Equation 8 to calculate the value for the Ry resistor between
BUCK2 and BUCK3 output and the VSENSE2 to ground respectively between the VSENSE3 to ground pin.
R ´ (VBUCK2/3 - 0.8 V)
Ry = x
0.8 V
(8)
Therefore, for VBUCK2 to equal to 1.2 V, the value of Ry must be 0.8 kΩ. For VBUCK3 to equal to 1.8 V, the value of
Ry must be 2 kΩ.
For voltage monitoring of the BUCK2 and BUCK3 output voltage, placing an additional resistive divider with exact
same values from the output node to the VMON2 and VMON3 pins is recommended for safety reasons (see
Figure 28). If no safety standard must be fulfilled in the application, the VMON2 and VMON3 pins can be directly
connected to VSENSE2 and VSENSE3 pins without the need for this additional resistive divider.
9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
´ (VIN - VOUT )
V
L = OUT
DIL _ PP ´ VIN ´ fsw
(9)
For example:
VIN = 3.3 V (from BUCK1)
VOUT = 1.2 V
ΔIL_PP = 300 mA
fsw = 2.45 MHz
→ L ≈ 1 μH
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9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
The regulators operate in forced continuous mode, and have internal frequency compensation. The frequency
response can be adjusted to the selected LC filter by setting the COMP2 and COMP3 pin low, high, or floating.
After selecting the output inductor value as previously described, the output capacitor must be chosen so that the
L × COUT × VBUCK2/3 product is equal to or less than one of the three values, as listed in Table 4.
Table 4. Compensation Settings
COMP 2/3
L × COUT × VBUCK2/3
EXAMPLE COMPONENTS
=0V
80 µF × µH × V
30 µF × 2.2 µH × 1.2 V
= OPEN
160 µF × µH × V
50 µF × 1.8 µH × 1.8 V
= VREG
320 µF × µH × V
150 µF × 2.2 µH × 1.2 V
Larger output capacitors can be used if a feed-forward capacitor is placed across the upper resistance, Ry, of the
feedback divider. This works effectively for output voltages > 2 V. With an RC product greater than 10 µs, the
effective VBUCK2/3 at higher frequencies can be assumed as 0.8 V, thus allowing an output capacitor increase by
a factor equal to the ratio of the output voltage to 0.8 V.
9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
The BUCK2 and BUCK3 converters require a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The
bootstrap capacitor is located between the PH2 pin and the BOOT2 pin and between the PH3 pin and the
BOOT3 pin (see Figure 28). The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade
dielectric for temperature stability.
9.2.2.3 BUCK2 and BUCK3 Application Curves
100
90
0.8
90
0.9
80
0.8
70
0.7
60
0.6
0.7
0.5
50
EFF VSUP2 = 3.8 V
40
0.4
EFF VSUP2 = 5 V
0.3
LOSS VSUP2 = 3.8 V
30
Efficiency (%)
0.6
60
Power Loss (W)
70
0.5
50
EFF VSUP3 = 3.8 V
EFF VSUP3 = 3.3 V
40
0.4
Power Loss (W)
0.9
80
Efficiency (%)
1
100
EFF VSUP3 = 5 V
0.3
30
LOSS VSUP3 = 3.8 V
LOSS VSUP2 = 5 V
0.2
20
20
0.2
LOSS VSUP3 = 3.3 V
LOSS VSUP3 = 5 V
0.1
10
0
0.001
0
0.01
0.1
1
10
0
0.001
L = 1 μH
C = 20 μF
EXTSUP Pin Open
Figure 29. Efficiency of Buck2, Measured Buck2 Output
Power With Respect to VSUP2 Input Power
46
0
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Buck2 = 3.3 V at 25°C
COMP2 Pin to Ground
0.1
10
Buck3 = 1.2 V at 25°C
EXTSUP Pin Open
L = 1.2 μH
C = 30 μF
COMP3 Pin to Ground
Figure 30. Efficiency of Buck3, Measured Buck3 Output
Power With Respect to VSUP3 Input Power
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100
100
95
Peak Efficiency (%)
Peak Efficiency (%)
95
90
90
85
85
80
75
80
-50
0
50
100
-50
150
0
50
L = 1 μH
COMP2 Pin to Ground
0.5-A LOAD
C = 20 μF
VSUP2 = 3.8 V
EXTSUP Pin Open
L = 1.2 μH
C = 30 μF
EXTSUP Pin Open
COMP3 Pin to Ground
Figure 31. Buck2 = 3.3-V Efficiency at 0.5 A Versus
Temperature, Measured Buck2 Output Power With
Respect to VSUP2 Input Power
150
100
100
95
95
90
85
VSUP3 = 3.8 V
1-A LOAD
Figure 32. Buck3 = 1.2-V Efficiency at 1 A Versus
Temperature, Measured Buck3 Output Power With
Respect to VSUP3 Input Power
Peak Efficiency (%)
Peak Efficiency (%)
100
Temperature (°C)
Temperature (°C)
90
85
80
80
-50
0
50
100
150
-50
Temperature (°C)
L = 1 μH
COMP2 Pin to Ground
C = 20 μF
0
50
100
150
Temperature (°C)
VSUP2 = 3.8 V
EXTSUP Pin Open
Figure 33. Buck2 = 3.3-V Peak Efficiency Versus
Temperature, Measured Buck2 Output Power With
Respect to VSUP2 Input Power
L = 1.2 μH
EXTSUP Pin Open
C = 30 μF
VSUP3 = 3.8 V
COMP3 Pin to Ground
Figure 34. Buck3 = 1.2-V Peak Efficiency Versus
Temperature, Measured Buck3 Output Power With
Respect to VSUP3 Input Power
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9.2.3 BOOST Converter
TPS65311-Q1
VBUCK1
5.6 nF
3.3 V
1.5 µH
10 µF
20
COMP5
2.2 k
23
22
D2
24
VBOOST
8.4 k
21
PGND5
VBOOST
VSENSE5
1.6 k
39 µF
5 V,
600 mA max
PH5
Copyright © 2017, Texas Instruments Incorporated
Figure 35. BOOST Converter Schematic
9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 5.
Table 5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Output voltage (VBOOST)
5V
Peak coil current (Ipeak_coil)
1A
Maximum output current IOUT
≈ 600 mA
Output current ripple ΔIL_PP
300 mA
Switching frequency (fSWBOOST)
2.45 MHz
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
A resistor divider from the output node to the VSENSE5 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with a value of 1.6 kΩ for the Rx resistor and use Equation 10 to
calculate Ry (see Figure 35).
R ´ (VBOOST - 0.8 V)
Ry = x
0.8 V
(10)
Therefore, for the value of VBOOST to equal to 5 V, the value of Ry must be 8.4 kΩ.
9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
V ´ (VOUT - VIN )
L = IN
DIL _ PP ´ VOUT ´ fsw
(11)
For example:
VIN = 3.3 V (from BUCK1)
VOUT = 5 V
48
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ΔIL_PP = 300 mA (30% of 1-A peak current)
ƒsw = 2.45 MHz
→ L ≈ 1.5 μH
The capacitor value COUT must be selected such that the L-C double-pole frequency FLC is in the range of
10 kHz–15 kHz. The FLC is given by Equation 12:
VIN
FLC =
2 ´ p ´ VOUT ´ L ´ COUT
(12)
The right half-plane zero FRHPZ, as given in Equation 13, must be > 200 kHz:
FRHPZ =
2
VIN
> 200 kHz
2 ´ p L ´ IOUT ´ VOUT
where
•
IOUT represents the load current
(13)
If the condition FRHPZ > 200 kHz is not satisfied, L and therefore COUT have to be recalculated.
9.2.3.2.3 Compensation of the BOOST Converter
The BOOST converter requires an external R-C network for compensation (see Figure 15, COMP5). The
components can be calculated using Equation 14 and Equation 15:
æF ö
R = 120 ´ VIN ´ ç BW ÷
è FLC ø
1
C=
2 ´ p ´ R ´ FLC
2
(14)
where
•
•
FBW represents the bandwidth of the regulation loop, and must be set to 30 kHz
FLC represents the L-C double-pole frequency, as mentioned previously
(15)
For example:
VIN = 3.3 V (from BUCK1)
VOUT = 5 V
L = 1.5 μH
C = 39 μF
→ FLC = 13.7 kHz
FBW = 30 kHz
→ R ≈ 2.2 kΩ
→ C ≈ 5.6 nF
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components.
9.2.3.2.4 Output Diode for the BOOST Converter
The BOOST converter requires an external output diode between the PH5 pin and VBOOST pin (see Figure 35,
component D2). The selected diode must have a reverse voltage rating equal to or greater than the VBOOST
output voltage. The peak current rating of the diode must be greater than the maximum inductor current. The
diode must also have a low forward voltage in order to reduce the power losses. Therefore, Schottky diodes are
typically a good choice for the catch diode.
Also, select a diode with an appropriate power rating, because the diode conducts the output current during the
off-time of the internal power switch.
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9.2.3.3 BOOST Converter Application Curves
100
100
250
90
80
200
150
Efficiency
50
Power Loss
100
40
30
Power Loss (mW)
Efficiency (%)
60
Peak Efficiency (%)
95
70
90
85
50
20
10
0
0.001
0
0.01
0.1
80
1
-50
0
Load Current (A)
50
100
150
Temperature (°C)
BOOST Supply Input = 3.8 V
EXTSUP Pin Open
BOOST Supply Input = 3.8 V
Figure 36. Efficiency BOOST = 5 V at 25°C, Measured
BOOST Output Power with respect to Supply Input Power
EXTSUP Pin Open
Figure 37. BOOST = 5-V Peak Efficiency Versus
Temperature, Measured BOOST Output Power with
respect to Supply Input Power
9.2.4 Linear Regulator
51
52
50
VSUP4
VSENSE4
LDO_OUT
TPS65311-Q1
1 µF
1.74 k:
VLDO_OUT
10 µF
820 :
VBUCK1
3.3 V
2.5 V, max 350 mA
Copyright © 2017, Texas Instruments Incorporated
Figure 38. Linear Regulator Schematic
9.2.4.1 Design Requirements
For this design example, use the parameters listed in Table 6.
Table 6. Design Parameters
50
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Output voltage (VLDO_OUT)
2.5 V
Maximum output current (IOUT)
350 mA
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9.2.4.2 Detailed Design Procedure
9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
A resistor divider from the output node to the VSENSE4 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. In order to get the minimum required load current of 1 mA for the linear
regulator, start with a value of 820 Ω for the Rx resistor and use Equation 16 to calculate Ry (see Figure 38).
R x ´ (VLDO _ OUT - 0.8 V)
Ry =
0.8 V
(16)
Therefore, for the value of VLDO_OUT to equal to 2.5 V, the value of Ry must be 1.74 kΩ.
9.2.4.2.2 Output Capacitance for the Linear Regulator
The linear regulator requires and external output capacitance with a value between 6 µF and 50 µF.
9.2.4.3 Linear Regulator Application Curve
10
9
Noise [LDO ON]
8
Noise [LDO OFF]
(Noisefloor)
NOISE (µV / ÖHz)
7
6
5
4
3
2
1
0
10
100
1000
10000
Frequency (Hz)
Figure 39. LDO Noise Density
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 40 V (see Figure 40 for
reference). This input supply must be well regulated. In case the supply voltage in the application is likely to
exceed 40 V, the external PMOS protection device as explained in External Protection must be applied between
VIN and VINPROT pins. Furthermore, if the supply voltage in the application is likely to reach negative voltage
(for example, reverse battery), a forward diode must be placed between the VSSENSE and VIN pins. A ceramic
bypass capacitor with a value of 100 μF (typical) is recommended to be placed close to the VINPROT pin. For
the VIN pin, a small ceramic capacitor of typical 1 µF is recommended. Also place 1-µF (typical) bypass
capacitors to the DVDD and VREF pins, and 100-nF (typical) bypass capacitors to VIO pin. Furthermore, the
VREG pin requires a bypass capacitor of 2.2 µF (typical).
The BUCK1 output voltage is the recommended input supply for the BUCK2, BUCK3, and BOOST regulators.
Place local, 10-µF (typical) bypass capacitors at the VSUP2 and VSUP3 pins and at the supply input of the
BOOST in front of the BOOST-inductor. Also place a local, 1-µF (typical) bypass capacitor at the VSUP4 pin.
The EXTSUP pin can be used to improve efficiency. For the EXTSUP pin to improve efficiency, a voltage of
more than 4.8 V is required in order to have VREG regulator supplied from EXTSUP pin. If the EXSUP pin is not
used, the VINPROT pin supplies the VREG regulator. The EXTSUP pin requires a 100-nF (typical) bypass
capacitor.
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VINPROT
2.2 µF
9
COMP1
18
24 k
SCK
R3
SDO
C2
1.2 nF
C1
47
S1
15
S2
16
VSENSE1
19
VMON1
17
VSUP2
30
BOOT2
29
PH2
31
HSCTRL
COMP2
34
HSPWM
PGND2
32
VSENSE2
35
VMON2
33
COMP5
VSUP3
41
23
PH5
BOOT3
42
22
PGND5
PH3
40
COMP3
37
SDI
VREF
1 µF
54
VT
TPS65311-Q1
VBUCK1
6
5
49
HSSENSE
VBUCK1
0.1 µF
VINPROT
33 µF
38
1.8 V, 2 A maximum
2k
36
VMON3
VBuck3
1.6 k
39
1.2 µH
2k
PGND3
VSENSE3
0.1 µF
10 µF
LDO_OUT
56 GND
50
51
VSENSE5
VSENSE4
21
52
VBOOST
1.6 k
39 µF
8.4 k
24
VSUP4
D2
1.6 k
1.5 µH
10 µF
VBUCK1
2.2 k
VBOOST
5 V,
600 mA max
VBuck2
1.2 V, 2 A maximum
5.6 nF
20
1 µH
62 µF
VT_REF
3.3 V, 2.3 A maximum
10 µF
25
VBUCK1
0.8 k
53
33 pF
0.1 µF
45
100 µF
CSN
1.6 k
46
10 µH
14
2.2 µF
PGND1
50 k
WAKE
0.8 k
44
Q3
16 k
13
22 m
GL
WD
10 k
50 k
12
PRESN
16 k
PH1
RESN
26
Q2
C3
11
R2
GU
R1
10
0.1 µF
VREG
BOOT1
27
43
8
VINPROT 4
3
GPFET
2
VIN
VIO
DVDD
48
10 k
10 k
0.1 µF
VBUCK1
VSSENSE 1
IRQ
10 k
28
55
1 µF
0.1 µF
Q1
1.6 k
D1
4 V to 40 V (typ. 12 V)
EXTSUP
VBAT
www.ti.com
1 µF
VLDO_OUT
2.5 V, maximum 350 mA
10 µF
820
VBUCK1
1.74 k
Copyright © 2017, Texas Instruments Incorporated
Figure 40. Typical Application Schematic
52
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11 Layout
11.1 Layout Guidelines
11.1.1 Buck Controller
•
•
•
•
•
•
Connect a local decoupling capacitor between the drain of Q3 and the source of Q2. The length of this trace
loop should be short.
The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitor for noise near the S1-S2 pins.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
Connect the boot-strap capacitance between the PH1 and BOOT1 pins, and keep the length of these trace
loops as short as possible.
Connect the compensation network between the COMP1 pin and GND pin (IC signal ground).
Connect a local decoupling capacitor between the VREG and PGDN1 pin, and between the EXTSUP and
PGND1 pin. The length of this trace loop should be short.
11.1.2 Buck Converter
•
•
•
•
Connect a local decoupling capacitor between VSUP2 and PGND2 respectively VSUP3 and PGND3 pins.
The length of this trace loop should be short.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
Connect the boot-strap capacitance between the PH2 and BOOT2 respectively PH3 and BOOT3 pins, and
keep the length of this trace loop as short as possible.
If COMP2 and/or COMP3 are chosen to be connected to ground, use the signal ground trace connected to
GND pin for this.
11.1.3 Boost Converter
•
•
•
The path formed from the input capacitor to the inductor and the PH5 pin should have short trace length. The
same applies for the trace from the inductor to Schottky diode D2 to the output capacitor and the VBOOST
pin. Connect the negative pin of the input capacitor and the PGND5 pin together with short trace lengths.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
Connect the compensation network between the COMP5 pin and GND pin (IC signal ground).
11.1.4 Linear Regulator
•
•
Connect a local decoupling capacitor between VSUP4 and GND (IC signal ground) pins. The length of this
trace loop should be short.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
11.1.5 Other Considerations
•
•
Short PGNDx and GND to the thermal pad.
Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the
compensation-network ground, voltage-sense feedback ground, and local biasing bypass capacitor ground
networks to this star ground.
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WD
CSN
SDI
SCK
VIO
SDO
HSPWM
VSUP4
LDO_OUT
VT_REF
VSENSE4
VT
VREF
GND
Analog Signal Ground trace
Sense resistors LDO
DVDD
Input supply voltage
Analog Signal Ground trace
LDO output
voltage
11.2 Layout Example
VSSENSE
BOOT3
D1
VIN
VSUP3
GPFET
PH3
VINPROT
PGND3
HSCTRL
VMON3
HSSENSE
COMP3
BUCK3 output voltage
Q1
WAKE
VSENSE2
VREG
COMP2
BOOT1
VMON2
GU
PGND2
PH1
PH2
GL
VSUP2
PGND1
BOOT2
Q2
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
Sense and
Monitoring
resistors
BUCK2
Sense and
Monitoring
resistors
BUCK1
IRQ
RESN
PRESN
VT_REF
PH5
VBOOST
VSENSE5
PGND5
VT_REF
Compensation network BOOST
COMP5
VSENSE1
COMP1
Compensation network BUCK1
BUCK1 output voltage
S1
plane
BOOST output
voltage
Analog Signal Ground trace
ground
VMON1
BUCK2 output voltage
S2
Q3
Power
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
VSENSE3
Exposed Thermal
Pad area
EXTSUP
Sense and
Monitoring
resistors
BUCK3
Sense resistors
BOOST
Analog Signal Ground trace
Figure 41. TPS65311-Q1 Layout Example
54
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12 Device and Documentation Support
12.1 Documentation Support
For related documentation see the following:
• Texas Instruments, TPS65310A-Q1 Efficiency application report
• Texas Instruments, TPS65310AEVM and TPS65311EVM Evaluation Module user's guide
• Texas Instruments, TPS65311-Q1 BUCK1 Controller DCR Current Sensing application report
• Texas Instruments, TPS65311-Q1/TPS65310A-Q1 GPFET Soft Start Using a Capacitor Between GPFET Pin
and PMOS-Protection Switch Source Pin application report
• Texas Instruments, TPS65311-Q1/TPS65310A-Q1 Monitoring and Diagnostic Mechanism Definitions
application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65311QRVJRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RVJ
56
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TPS65311
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65311QRVJRQ1
Package Package Pins
Type Drawing
VQFN
RVJ
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
8.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.3
2.25
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65311QRVJRQ1
VQFN
RVJ
56
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
8.1
7.9
B
A
0.1 MIN
8.1
7.9
(0.13)
SECTION A-A
PIN 1 INDEX AREA
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5.2±0.1
(0.2) TYP
15
52X 0.5
28
14
4X
6.5
SYMM
A
57
1
PIN 1 ID
(OPTIONAL)
(0.16)
29
A
42
43
56
SYMM
56X 0.55
0.35
5.2±0.1
56X 0.30
0.20
0.1
0.05
C A B
C
4225251/A 09/2019
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
(7.75)
(5.2)
SYMM
56X (0.65)
56
43
1
42
56X (0.25)
52X (0.5)
SYMM
(7.75)
57
8X (1.27)
(5.2)
6X (1.08)
(Ø0.2) VIA
TYP
14
29
(R0.05)
TYP
15
28
8X (1.27)
6X (1.08)
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225251/A 09/2019
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
(7.75)
SYMM
56X (0.65)
56
43
1
42
57
56X (0.25)
16X
SQ (1.07)
52X (0.5)
SYMM
8X (0.635)
(7.75)
6X (1.27)
METAL TYP
14
(R0.05)
TYP
29
15
28
8X (0.635)
6X (1.27)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 10X
4225251/A 09/2019
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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