Texas Instruments | TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package (Rev. C) | Datasheet | Texas Instruments TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package (Rev. C) Datasheet

Texas Instruments TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package (Rev. C) Datasheet
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TLV62569, TLV62569P
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
Up to 95% Efficiency
Low RDS(ON) Switches 100 mΩ / 60 mΩ
2.5-V to 5.5-V Input Voltage Range
Adjustable Output Voltage from 0.6 V to VIN
Power Save Mode for Light Load Efficiency
100% Duty Cycle for Lowest Dropout
35-µA Operating Quiescent Current
1.5-MHz Typical Switching Frequency
Power Good Output
Over Current Protection
Internal Soft Startup
Thermal Shutdown Protection
Available in SOT Package
Pin-to-Pin Compatible with TLV62568
Create a Custom Design Using the TLV62569
With the WEBENCH® Power Designer
The TLV62569 provides an adjustable output voltage
via an external resistor divider. An internal soft start
circuit limits the inrush current during startup. Other
features like over current protection, thermal
shutdown protection and power good are built-in. The
device is available in a SOT23 and SOT563 package.
Device Information(1)
PART NUMBER
PACKAGE
TLV62569DBV
SOT23 (5)
TLV62569PDDC
SOT23 (6)
TLV62569DRL
SOT563 (6)
TLV62569PDRL
SOT563 (6)
General Purpose POL Supply
Set Top Box
Network Video Camera
Wireless Router
Hard Disk Driver
PART NUMBER
TLV62569PDDC
TLV62569PDRL
The TLV62569 device is a synchronous step-down
buck DC-DC converter optimized for high efficiency
and compact solution size. The device integrates
switches capable of delivering an output current up to
2 A.
Simplified Schematic
TLV62569P
VIN
R3
499 k
1.60 mm x 1.60 mm
FUNCTION
MARKING
SYMBOL
-
16AF
TLV62569DBV
3 Description
C1
4.7 µF
2.90 mm × 2.80 mm
Device Comparison
Power Good
7G
-
19D
Power Good
19E
TLV62569DRL
VIN
2.5 V to 5.5 V
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
At medium to heavy loads, the device operates in
pulse width modulation (PWM) mode with 1.5-MHz
switching frequency. At light load, the device
automatically enters Power Save Mode (PSM) to
maintain high efficiency over the entire load current
range. In shutdown, the current consumption is
reduced to less than 2 μA.
Efficiency at 5-V Input Voltage
VOUT
1.8 V / 2.0 A
L1
2.2 µH
100
SW
EN
C2
10 µF
C3*
95
R1
200 k
90
PG GND FB
C3: Optional
Copyright Ú 2016, Texas Instruments Incorporated
R2
100 k
Efficiency (%)
VPG
85
80
75
70
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
65
60
0
0.2
0.4
0.6
0.8
1
1.2
Load (A)
1.4
1.6
1.8
2
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV62569, TLV62569P
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagrams .......................................
Feature Description...................................................
Device Functional Modes..........................................
6
6
6
7
8
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application .................................................... 8
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Thermal Considerations ........................................ 13
11 Device and Documentation Support ................. 14
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2017) to Revision C
Page
•
Changed TLV62569DRL and TLV62569PDRL to production status ..................................................................................... 1
•
Added marking symbols for TLV62569DRL and TLV62569PDRL in the Device Comparison table ..................................... 1
•
Added DRL package thermal information ............................................................................................................................. 4
•
Corrected editorial error of EN pin threshold voltage ............................................................................................................. 4
•
Added current limit for TLV62569DRL and TLV62569PDRL ................................................................................................ 5
•
Added TLV62569PDRL layout example............................................................................................................................... 13
Changes from Revision A (March 2017) to Revision B
Page
•
Changed TLV62569PDDC to production status .................................................................................................................... 1
•
Moved Device Comparison table to page 1 ........................................................................................................................... 1
•
Added DDC package thermal information .............................................................................................................................. 4
•
Added startup time of TLV62569PDDC.................................................................................................................................. 4
Changes from Original (December 2016) to Revision A
•
2
Page
Added WEBENCH® Model ................................................................................................................................................... 1
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SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
SOT23-5
DBV Package
(Top View)
SOT23-6
DDC Package
(Top View)
SOT563-6
DRL Package
(Top View)
FB
VIN
FB
PG
VIN
5
4
6
5
4
NC/PG EN
1
2
3
1
2
SW
6
5
4
1
2
3
3
FB GND VIN
EN
GND
SW
EN
GND
SW
Pin Functions
PIN NUMBER
NAME
I/O/PWR
DESCRIPTION
SOT23-5
SOT23-6
SOT563-6
EN
1
1
5
I
GND
2
2
2
PWR
Ground pin.
SW
3
3
4
PWR
Switch pin connected to the internal FET switches and inductor
terminal. Connect the inductor of the output filter to this pin.
VIN
4
4
3
PWR
Power supply voltage input.
PG
-
5
6
O
Power good open drain output pin for TLV62569P. The pull-up
resistor should not be connected to any voltage higher than 5.5V. If
it's not used, leave the pin floating.
FB
5
6
1
I
Feedback pin for the internal control loop. Connect this pin to an
external feedback divider.
NC
-
-
6
O
No connection pin for TLV62569DRL. The pin can be connected to
the output or the ground. Or leave it floating.
Device enable logic input. Logic high enables the device, logic low
disables the device and turns it into shutdown. Do not leave floating.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted) (1)
VIN, EN, PG
Voltage SW (DC)
(2)
SW (AC, less than 10ns) (3)
FB
MIN
MAX
UNIT
–0.3
6
V
–0.3
VIN+0.3
V
–3.0
9
V
–0.3
5.5
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and the device is not switching. Functional operation of the device at these or any other conditions beyond those indicated under
recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect
device reliability.
All voltage values are with respect to network ground terminal.
While switching
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6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
MAX
UNIT
VIN
Input voltage
MIN
2.5
TYP
5.5
V
VOUT
Output voltage
0.6
VIN
V
IOUT
Output current
0
2
A
TJ
Operating junction temperature
–40
125
°C
1
mA
ISINK_PG Sink current at PG pin
(1)
Refer to the Application and Implementation section for further information.
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
DBV
(5 Pins)
DDC
(6 Pins)
DRL
(6 Pins)
UNIT
188.2
106.2
146.3
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
137.5
52.9
51.0
°C/W
RθJB
Junction-to-board thermal resistance
41.2
31.2
27.0
°C/W
ψJT
Junction-to-top characterization parameter
31.4
11.3
2.2
°C/W
ψJB
Junction-to-board characterization parameter
40.6
31.6
27.6
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5
Electrical Characteristics
VIN = 5.0 V, TJ = 25°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN pin
Not switching
35
ISD
Shutdown current into VIN pin
EN = 0 V
0.1
2
µA
Under voltage lock out
VIN falling
2.3
2.45
V
VUVLO
Under voltage lock out hysteresis
TJSD
uA
100
Thermal shutdown
Junction temperature rising
150
Junction temperature falling
130
mV
°C
LOGIC INTERFACE
VIH
High-level threshold at EN pin
2.5 V ≤ VIN ≤ 5.5 V
VIL
Low-level threshold at EN pin
2.5 V ≤ VIN ≤ 5.5 V
0.95
0.4
TLV62569DBV
800
TLV62569PDDC, TLV62569DRL,
TLV62569PDRL
900
VFB rising, referenced to VFB nominal
95%
VFB falling, referenced to VFB nominal
90%
tSS
Soft startup time
VPG
Power good threshold
VPG,OL
Power good low-level output voltage
ISINK = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
tPG,DLY
Power good delay time
VFB falling
1.2
0.85
V
V
µs
0.4
V
0.01
µA
40
µs
OUTPUT
VFB
4
Feedback regulation voltage
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0.588
0.6
0.612
V
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Electrical Characteristics (continued)
VIN = 5.0 V, TJ = 25°C, unless otherwise noted
PARAMETER
RDS(on)
TEST CONDITIONS
MIN
TYP
High-side FET on resistance
100
Low-side FET on resistance
60
ILIM
High-side FET current limit
fSW
Switching frequency
TLV62569DBV, TLV62569PDDC
3
TLV62569DRL, TLV62569PDRL
2.5
VOUT = 2.5 V
MAX
UNIT
mΩ
A
1.5
MHz
6.6 Typical Characteristics
50
20
45
18
VIN = 2.5V
VIN = 3.6V
VIN = 5.0V
$
35
6KXWGRZQ &XUUHQW
$
4XLHVFHQW &XUUHQW
16
40
30
25
20
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
15
10
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
14
12
10
8
6
4
2
0
-40
5.5
-10
D001
Figure 1. Quiescent Current vs Input Voltage
20
50
80
Junction Temperature (°C)
110
140
D002
Figure 2. Shutdown Current vs Junction Temperature
0.3
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
FB Voltage Accuracy (%)
0.2
0.1
0.0
-0.1
-0.2
-0.3
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D003
Figure 3. FB Voltage Accuracy
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7 Detailed Description
7.1 Overview
The TLV62569 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off
time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagrams
PG
Soft Start
Thermal
Shutdown
UVLO
Control Logic
EN
VPG
+
VFB
±
VIN
GND
Peak Current Detect
VREF
+
_
FB
Modulator
SW
Gate
Drive
VSW
TOFF
VIN
Zero Current Detect
GND
Power Good feature is only available in TLV62569P
GND
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Figure 4. TLV62569 Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
where
•
•
6
RDS(ON) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
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Feature Description (continued)
7.3.3 Soft Startup
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
The TLV62569 is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit
The switch current limit prevents the device from high inductor current and drawing excessive current from a
battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.
The TLV62569 adopts the peak current control by sensing the current of the high-side switch. Once the high-side
switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down
the inductor current with an adaptive off-time.
7.3.5 Under Voltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.
7.3.6 Thermal Shutdown
The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising
threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal
operation automatically.
7.4 Device Functional Modes
7.4.1 Enabling/Disabling the Device
The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the
device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and should not be left floating.
7.4.2 Power Good
The TLV62569P has a power good output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
Table 1. PG Pin Logic
DEVICE CONDITIONS
Enable
EN = High, VFB ≥ VPG
LOGIC STATUS
HIGH Z
LOW
√
EN = High, VFB ≤ VPG
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
1.4 V < VIN < VUVLO
√
Power Supply Removal
VIN ≤ 1.4 V
√
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
2.5 V to 5.5 V
TLV62569P
VIN
C1
4.7 µF
R3
499 k
VOUT
1.8 V / 2.0 A
L1
2.2 µH
SW
C2
10 µF
EN
C3*
R1
200 k
VPG
PG GND FB
R2
100 k
C3: Optional
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Figure 5. TLV62569 1.8-V Output Application
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 5.5 V
Output voltage
1.8 V
Maximum output current
2.0 A
Table 3 lists the components used for the example.
Table 3. List of Components
REFERENCE
C1
4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L
C2
10 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A106KE51L
Murata
L1
2.2 µH, Power Inductor, size 4mmx4mm, XAL4020-222ME
Coilcraft
R1,R2,R3
C3
(1)
MANUFACTURER (1)
DESCRIPTION
Murata
Chip resistor,1%,size 0603
Std.
Optional, 6.8 pF if it is needed
Std.
See Third-party Products Disclaimer
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62569 device with the WEBENCH® Power Designer.
8
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1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting the Output Voltage
An external resistor divider is used to set output voltage according to Equation 2.
When sizing R2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of
200 kΩ for R2. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase
current consumption.
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
÷
÷ = 0.6V ´ ç 1 +
R2 ø
R2 ø
è
è
(2)
A feed forward capacitor, C3 improves the loop bandwidth to make a fast transient response (shown in
Figure 19). 6.8-pF capacitance is recommended for R2 of 100-kΩ resistance. A more detailed discussion on the
optimization for stability vs. transient response can be found in SLVA289.
8.2.2.3 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 4 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Further combinations should be checked for each individual application.
Table 4. Matrix of Output Capacitor and Inductor Combinations
L [µH] (1)
0.6 ≤ VOUT < 1.2
1
+
2.2
++ (3)
1.2 ≤ VOUT < 1.8
1.8 ≤ VOUT
(1)
(2)
(3)
COUT [µF] (2)
VOUT [V]
4.7
10
22
2 x 22
1
+
+
2.2
++ (3)
+
1
+
+
+
2.2
++ (3)
+
+
100
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
This LC combination is the standard value and recommended for most applications.
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8.2.2.4 Inductor Selection
The main parameters for inductor selection is inductor value and then saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, Equation 3 is given:
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where:
•
•
•
•
IOUT,MAX is the maximum output current
ΔIL is the inductor current ripple
fSW is the switching frequency
L is the inductor value
(3)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the TLV62569 allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-μF input
capacitance is sufficient; a larger value reduces input voltage ripple.
The TLV62569 is designed to operate with an output capacitor of 10 µF to 47 µF, as outlined in Table 4.
8.2.3 Application Performance Curves
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
VIN = 5 V, VOUT = 1.8 V, L = 2.2 μH, TA = 25 °C, unless otherwise noted.
85
80
75
60
1m
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
75
10m
65
100m
Load (A)
1
Submit Documentation Feedback
2
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
60
1m
10m
D004
Figure 6. 1.2-V Output Efficiency
10
80
70
70
65
85
100m
Load (A)
1
2
D005
Figure 7. 1.8-V Output Efficiency
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
TLV62569, TLV62569P
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
www.ti.com
85
80
75
85
80
75
70
70
65
65
VIN = 3.3 V
VIN = 5.0 V
60
1m
VIN = 5.0 V
10m
100m
Load (A)
1
60
1m
2
10m
3
2
D007
1.0
VOUT = 1.8 V
VOUT = 3.3 V
2.5
2
Line Regulation (%)
Load Regulation (%)
1
Figure 9. 3.3-V Output Efficiency
Figure 8. 2.5-V Output Efficiency
1.5
1
0.5
0
0.5
0.0
-0.5
IOUT = 0.5A
IOUT = 1.0A
IOUT = 2.0A
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
Load (A)
1.4
1.6
1.8
-1.0
2.5
2
3.0
D009
VIN = 5 V
2000
2000
Switching Frequency (kHz)
2500
1500
1000
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
500
0
0.2
0.4
4.0
4.5
Input Voltage (V)
5.0
5.5
D010
Figure 11. Line Regulation
2500
0
3.5
VOUT = 1.8 V
Figure 10. Load Regulation
Switching Frequency (kHz)
100m
Load (A)
D006
0.6
0.8
1
1.2
Load (A)
1.4
1.6
1.8
2
1500
1000
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
500
0
2.5
3
D011
VIN = 5 V
3.5
4
4.5
Input Voltage (V)
5
5.5
D012
IOUT = 1 A
Figure 12. Switching Frequency vs Load
Figure 13. Switching Frequency vs Input Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
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11
TLV62569, TLV62569P
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com
VSW
2V/DIV
VSW
2V/DIV
VOUT
10mV/DIV
AC
VOUT
0.1V/DIV
AC
ICOIL
0.5A/DIV
ICOIL
0.5A/DIV
7LPH
Time - 500ns/DIV
V ',9
D014
D013
IOUT = 1 A
IOUT = 0.1 A
Figure 14. PWM Operation
Figure 15. Power Save Mode Operation
VEN
3V/DIV
VEN
3V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
ICOIL
2A/DIV
ICOIL
0.5A/DIV
7LPH
V ',9
7LPH
V ',9
D015
IOUT = 2 A
D016
IOUT = 0.1 A
Figure 16. Startup and Shutdown with Load
Figure 17. Startup and Shutdown with Load
VOUT
0.2V/DIV
VOUT
0.2V/DIV
ICOIL
1A/DIV
ICOIL
1A/DIV
7LPH
V ',9
7LPH
V ',9
D017
Load Step 0.8 A to 2 A, 1A/μs slew rate
D018
Load Step 0.8 A to 2 A, 1A/μs slew rate
Figure 18. Load Transient
C3 = 6.8 pF
Figure 19. Load Transient
9 Power Supply Recommendations
The power supply to the TLV62569 must have a current rating according to the supply voltage, output voltage
and output current.
12
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Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
TLV62569, TLV62569P
www.ti.com
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62569 device.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
• The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
• GND layers might be used for shielding.
10.2 Layout Example
GND
L1
VIN
PAC101
C1
VOUT
VIN
SW
GND
FB
R2 PAR202
R1
EN
R1
R2
PAC601
C2
C1
PAR201
VIN
FB
GND
VIN
L1
PG
EN
SW
C2
VOUT
GND
Figure 20. TLV62569DBV Layout
Figure 21. TLV62569PDRL Layout
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow,
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component.
Two basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
Submit Documentation Feedback
13
TLV62569, TLV62569P
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62569 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
Semiconductor and IC Package Thermal Metrics Application Report (SPRA953)
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report
(SZZA017)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
14
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Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
TLV62569, TLV62569P
www.ti.com
SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017
11.5 Trademarks (continued)
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV62569 TLV62569P
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV62569DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
16AF
TLV62569DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
16AF
TLV62569DRLR
ACTIVE
SOT-5X3
DRL
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
19D
TLV62569DRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
19D
TLV62569PDDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(6D9, 6DW)
TLV62569PDDCT
ACTIVE
SOT-23-THIN
DDC
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(6D9, 6DW)
TLV62569PDRLR
ACTIVE
SOT-5X3
DRL
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
19E
TLV62569PDRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
19E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2020
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV62569DBVR
SOT-23
DBV
5
3000
180.0
8.4
TLV62569DBVR
SOT-23
DBV
5
3000
178.0
TLV62569DBVT
SOT-23
DBV
5
250
180.0
TLV62569DRLR
SOT-5X3
DRL
6
3000
TLV62569DRLT
SOT-5X3
DRL
6
TLV62569PDDCR
SOT23-THIN
DDC
TLV62569PDDCT
SOT23-THIN
TLV62569PDRLR
TLV62569PDRLT
3.2
3.2
1.4
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
250
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
6
3000
180.0
9.5
3.17
3.1
1.1
4.0
8.0
Q3
DDC
6
250
180.0
9.5
3.17
3.1
1.1
4.0
8.0
Q3
SOT-5X3
DRL
6
3000
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
SOT-5X3
DRL
6
250
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV62569DBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV62569DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV62569DBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
TLV62569DRLR
SOT-5X3
DRL
6
3000
210.0
185.0
35.0
TLV62569DRLT
SOT-5X3
DRL
6
250
210.0
185.0
35.0
TLV62569PDDCR
SOT-23-THIN
DDC
6
3000
184.0
184.0
19.0
TLV62569PDDCT
SOT-23-THIN
DDC
6
250
184.0
184.0
19.0
TLV62569PDRLR
SOT-5X3
DRL
6
3000
210.0
185.0
35.0
TLV62569PDRLT
SOT-5X3
DRL
6
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
SCALE 4.000
SOT
3.05
2.55
1.75
1.45
PIN 1
INDEX AREA
1.1 MAX
B
1
0.1 C
A
6
4X 0.95
3.05
2.75
1.9
4
3
0.5
0.3
0.2
0.1
TYP
0.0
6X
0 -8 TYP
0.20
TYP
0.12
C A B
C
SEATING PLANE
0.6
TYP
0.3
0.25
GAGE PLANE
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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