Texas Instruments | TPS2001D Current Limited, Power-Distribution Switches (Rev. A) | Datasheet | Texas Instruments TPS2001D Current Limited, Power-Distribution Switches (Rev. A) Datasheet

Texas Instruments TPS2001D Current Limited, Power-Distribution Switches (Rev. A) Datasheet
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TPS2001D
SLVSE25A – JULY 2017 – REVISED OCTOBER 2017
TPS2001D Current Limited, Power-Distribution Switches
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS2001D power-distribution switch is intended
for applications where heavy capacitive loads and
short circuits are likely to be encountered, such as
USB.
1
Single Power Switch Family
Rated Current of 2 A
±20% Accurate, Fixed, Constant Current Limit
Fast Overcurrent Response: 2 µs
Deglitched Fault Reporting
Output Discharge
Reverse Current Blocking
Built-In Soft Start
Ambient Temperature Range: –40°C to 85°C
UL Listed and CB-File No. E169910
The TPS2001D limits the output current to a safe
level by operating in a constant-current mode when
the output load exceeds the current limit threshold.
This provides a predictable fault current under all
conditions. The fast overload response time eases
the burden on the main 5-V supply to provide
regulated power when the output is shorted. The
power-switch rise and fall times are controlled to
minimize current surges during turnon and turnoff.
2 Applications
•
•
•
•
Device Information(1)
USB Ports and Hubs, Laptops, and Desktops
High-Definition Digital TVs
Set-Top Boxes
Short-Circuit Protection
PART NUMBER
TPS2001D
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
spacer
Typical Application Diagram
IN
OUT
0.1 mF
VIN
RFLT
10 kW
VOUT
150 mF
Fault Signal
FLT
Control Signal
EN
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2001D
SLVSE25A – JULY 2017 – REVISED OCTOBER 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: TJ = TA = 25°C.................
Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.........
Timing Requirements: TJ = TA = 25°C......................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
11.3 Power Dissipation and Junction Temperature ...... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Original (July 2017) to Revision A
Page
•
Added EN VIH MIN 1.8 V to the Recommended Operating Conditions for DBV package ..................................................... 4
•
Changed RDS(on) TYP from 72 to 66 and added MAX 77 for DBV package........................................................................... 5
•
Added RDS(on) MAX 77 for DBV package for 2-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C condition....................................... 5
•
Changed RDS(on) TYP from 72 to 66 for DBV package for 2-A rated output, and added MAX 106 ...................................... 6
•
Added EN Threshold, input rising MAX 1.8 V for DBV package ........................................................................................... 6
2
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5 Device Comparison Table (1)
(1)
MAXIMUM OPERATING
CURRENT
OUTPUT DISCHARGE
ENABLE
2A
Yes
High
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
DBV Package
5-Pin SOT-23
Top View
GND
1
8
OUT
IN
2
7
OUT
IN
3
6
OUT
EN
4
5
FLT
OUT
1
GND
2
FLT
3
5
IN
4
EN/EN
Pin Functions - DGK Package
PIN
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Enable input, logic high turns on power switch
FLT
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
GND
1
—
Ground connection
2, 3
PWR
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to
GND close to the IC
6, 7, 8
PWR
Power-switch output, connect to load
IN
OUT
Pin Functions - DBV Package
PIN
NAME
NO.
I/O
DESCRIPTION
EN or EN
4
I
Enable input, logic high turns on power switch
FLT
3
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
GND
2
—
Ground connection
IN
5
PWR
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to
GND close to the IC
OUT
1
PWR
Power-switch output, connect to load
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
–0.3
6
V
Voltage from IN to OUT
–6
6
V
Maximum junction temperature, TJ
Internally Limited
Storage temperature, Tstg
–60
Voltage on IN, OUT, EN, FLT
(1)
(2)
(3)
(4)
(4)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute maximum ratings apply over recommended junction temperature range.
Voltages are with respect to GND unless otherwise noted.
See Input and Output Capacitance.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
IEC 61000-4-2 contact discharge
±8000
IEC 61000-4-2 air-gap discharge (3)
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VOUT was surged on a PCB with input and output bypassing per the Typical Application Diagram on the first page (except input
capacitor was 22 µF) with no device failures.
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage, IN
VEN
Input voltage, EN
VIH
High-level input voltage, EN
VIL
Low-level input voltage, EN
IOUT
Continuous output current, OUT
TJ
Operating junction temperature
IFLT
Sink current into FLT
(1)
NOM
MAX
UNIT
4.5
5.5
V
0
5.5
V
DGK
2
DBV
1.8
V
0.7
(1)
V
2
A
–40
125
°C
0
5
mA
Some package and current rating may request an ambient temperature derating of 85°C.
7.4 Thermal Information
THERMAL METRIC
(1)
TPS2001D
TPS2001D
DBV
(SOT-23)
DGK
(VSSOP)
5 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
220.4
205.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.7
94.3
°C/W
RθJB
Junction-to-board thermal resistance
46.9
126.9
°C/W
ψJT
Junction-to-top characterization parameter
5.2
24.7
°C/W
ψJB
Junction-to-board characterization parameter
46.2
125.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
RθJACustom
See Power DIssipation and Junction Temperature
134.9
110.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: TJ = TA = 25°C
Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A. See Device Comparison Table (1) for the rated current of each part
number. Parametrics over a wider operational range are shown in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C (2).
TEST CONDITIONS (2)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(on)
Input – output resistance
2-A rated output, 25°C
DGK
72
84
mΩ
2-A rated output, –40°C ≤ (TJ , TA) ≤
85°C
DGK
72
98
mΩ
2-A rated output, 25°C
DBV
66
77
mΩ
2-A rated output, –40°C ≤ (TJ , TA) ≤
85°C
DBV
66
90
mΩ
2.9
3.4
A
0.01
1
CURRENT LIMIT
IOS (3)
Current limit,
See Figure 6
2-A rated output
2.35
SUPPLY CURRENT
ISD
Supply current, switch disabled
ISE
Supply current, switch enabled
Ilkg
Leakage current
IREV
Reverse leakage current
IOUT = 0 A
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
2
IOUT = 0 A
60
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
70
85
VOUT = 0 V, VIN = 5 V, disabled, measure IVIN
0.05
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 0 V,
VIN = 5 V, disabled, measure IVIN
0.1
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure
IVOUT
µA
1
2
VOUT = 5 V, VIN = 0 V, measure IVOUT
µA
µA
1
5
µA
OUTPUT DISCHARGE
RPD
(1)
(2)
(3)
(4)
Output pulldown resistance (4)
VIN = VOUT = 5 V, disabled
400
470
600
Ω
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit section for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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7.6 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C
Unless otherwise noted:4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C.
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(ON)
Input – output resistance
2-A rated output
DGK
72
112
mΩ
2-A rated output
DBV
66
106
mΩ
ENABLE INPUT (EN)
Threshold
Input rising
DGK
1
1.45
2
DBV
1
1.45
1.8
Hysteresis
Leakage current
V
0.07
0.13
0.2
V
VEN = 0 V or 5.5 V
–1
0
1
µA
2.3
2.9
3.6
A
CURRENT LIMIT
IOS (2)
Current limit,
See Figure 20
2-A rated output
tIOS
Short-circuit response time (3)
VIN = 5 V (see Figure 6),
One-half full load → RSHORT = 50 mΩ,
Measure from application to when current falls below 120% of
final value
2
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
IOUT = 0 A
0.01
10
µA
ISE
Supply current, switch enabled
IOUT = 0 A
65
90
µA
IREV
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measure IVOUT
0.2
20
µA
3.75
4
V
UNDERVOLTAGE LOCKOUT
VUVLO
Rising threshold
VIN↑
Hysteresis (3)
VIN↓
Output low voltage, FLT
IFLT = 1 mA
OFF-state leakage
VFLT = 5.5 V
FLT deglitch
FLT assertion or deassertion deglitch
3.5
0.14
V
FLT
tFLT
0.2
V
1
µA
ms
6
9
12
VIN = 4 V, VOUT = 5 V, disabled
350
560
1200
VIN = 5 V, VOUT = 5 V, disabled
300
470
800
In current limit
135
Not in current limit
155
OUTPUT DISCHARGE
RPD
Output pulldown resistance
Ω
THERMAL SHUTDOWN
Rising threshold (TJ)
Hysteresis
(1)
(2)
(3)
(3)
°C
20
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
7.7 Timing Requirements: TJ = TA = 25°C
MIN
NOM
MAX
UNIT
ENABLE INPUT (EN)
tON
Turnon time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑.
See Figure 1, Figure 3, and Figure 4
1.2
1.7
2.2
ms
tOFF
Turnoff time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓.
See Figure 1, Figure 3, and Figure 4
1.7
2.1
2.5
ms
tR
Rise time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See
Figure 2
0.5
0.7
1
ms
tF
Fall time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See
Figure 2
0.3
0.43
0.55
ms
6
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OUT
RL
CL
Figure 1. Output Rise and Fall Test Load
tR
VOUT
90%
tF
10%
Figure 2. Power-On and Power-Off Timing
VEN
50%
tON
50%
tOFF
90%
VOUT
10%
Figure 3. Enable Timing, Active High Enable
V/EN
50%
50%
tOFF
tON
90%
VOUT
10%
Figure 4. Enable Timing, Active Low Enable
120% x IOS
IOUT
IOS
0A
tIOS
Figure 5. Output Short-Circuit Parameters
VIN
Decreasing
Load
Resistance
VOUT
Slope = -RDS(ON)
0V
0A
IOUT
IOS
Figure 6. Output Characteristic Showing Current Limit
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7.8 Typical Characteristics
9.3
14
VIN = 5 V
All Versions, 5 V
85°C
12
IOUT sinking (mA)
tFLT (ms)
9.2
9.1
9.0
25°C
10
8
−40°C
6
125°C
4
8.9
2
8.8
−40
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
0
0.0
140
0.5
1.0
1.5
G019
Figure 7. Deglitch Period (TFLT) vs Temperature
2.0 2.5 3.0 3.5
Output Voltage (V)
4.0
4.5
5.0
5.5
G020
Figure 8. Output Discharge Current vs Output Voltage
7
All Unit Types, 5 V
6
IREV (µA)
5
4
3
2
1
0
−1
−40
Figure 9. Short Circuit Current (IOS) vs Temperature
120
140
G022
All Unit Types
0.8
0.8
0.6
0.6
ISD (µA)
ISD (µA)
20
40
60
80
100
Junction Temperature (°C)
1.0
Input Voltage = 5.5 V
0.4
125°C
0.4
0.2
0.2
0.0
0.0
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
−0.2
4.00
G023
Figure 11. Disabled Supply Current (ISD) vs Temperature
8
0
Figure 10. Reverse Leakage Current (IREV) vs Temperature
1.0
−0.2
−40
−20
85°C
−40°C and 25°C
4.25
4.50
4.75
5.00
Input Voltage (V)
5.25
5.50
G024
Figure 12. Disabled Supply Current (ISD) vs Input Voltage
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6.0
All unit types, VIN = 0 V
5.5
5.0
4.5
125°C
4.0
3.5
3.0
2.5
2.0
85°C
1.5
25°C
−40°C
1.0
0.5
0.0
−0.5
4.00
4.25
4.50
4.75
5.00
5.25
Output Voltage (V)
80
All Unit Types, VIN = 5.5 V
75
70
ISE (µA)
IREV (µA)
Typical Characteristics (continued)
65
60
55
5.50
50
−40
G025
Figure 13. Reverse Leakage Current (IREV) vs Output Voltage
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G026
Figure 14. Enabled Supply Current (ISE) vs Temperature
80
75
ISE (µA)
70
85°C
125°C
65
60
55
50
25°C
45
40
4.00
−40°C
4.25
4.50
4.75
5.00
Input Voltage (V)
5.25
5.50
G027
Figure 15. Enabled Supply Current (ISE) vs Input Voltage
Figure 16. Output Fall Time (TF) vs Temperature
Figure 17. Output Rise Time (TR) vs Temperature
Figure 18. Input-Output Resistance (RDS(ON)) vs Temperature
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8 Detailed Description
8.1 Overview
The TPS2001D is a current-limited, power-distribution switch providing 2-A continuous load current in 5-V
circuits. The device uses an N-channel MOSFET for low resistance, maintaining voltage regulation to the load. It
is designed for applications where short circuits or heavy capacitive loads are encountered. Device features
include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection,
overtemperature protection, and deglitched fault reporting.
8.2 Functional Block Diagram
Current
Sense
IN
Charge
Pump
EN or
EN
CS
OUT
Current
Limit
(Disabled+
UVLO)
Driver
UVLO
GND
FLT
OTSD
Thermal
Sense
9-ms
Deglitch
Copyright © 2016, Texas Instruments Incorporated
Figure 19. TPS2001D Block Diagram
8.3 Feature Description
8.3.1 Undervoltage Lockout
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large current
surges. FLT is high impedance when the TPS2001D is in UVLO.
8.3.2 Enable
The logic enable input (EN), controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current is reduced to less than 1 µA when the TPS2001D is disabled. Disabling the TPS2001D
immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic
levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times
are internally controlled. The rise time is controlled by both the TPS2001D and the external loading (especially
capacitance). Its fall time is controlled by the loading (R and C), and the output discharge (RPD). An output load
consisting of only a resistor experiences a fall time set by the device. An output load with parallel R and C
elements experiences a fall time determined by the (R × C) time constant if it is longer than the tF.
The enable must not be left open, and may be tied to VIN or GND depending on the device.
10
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Feature Description (continued)
8.3.3 Internal Charge Pump
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of
the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start
functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or
disabled.
8.3.4 Current Limit
The device responds to overloads by limiting output current to the static IOS levels shown in Electrical
Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a constant output
current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur. The
first overload condition occurs when either:
1. input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS)
2. input voltage is present and the TPS2001D is enabled into a short circuit.
The output voltage is held near zero potential with respect to ground and the TPS2001D ramps the output
current to IOS. The TPS2001D limits the current to IOS until the overload condition is removed or the device
begins to thermal cycle.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS (Figure 5 and Figure 6) when the specified overload (see Electrical
Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level,
input circuit, and rate of application. The current limit response will vary between simply settling to IOS, or turnoff
and controlled return to IOS. Similar to the previous case, the TPS2001D limits the current to IOS until the
overload condition is removed or the device begins to thermal cycle.
The TPS2001D thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction
temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current
limit. The device remains off until the junction temperature cools 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products that are similar to the
TPS2001D. Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with
Peaking in Figure 20. This type of limiting can be characterized by two parameters, the current limit corner (IOC),
and the short circuit current (IOS). IOC is often specified as a maximum value. The TPS2001D family of parts does
not present noticeable peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit
in Figure 20. This is why the IOC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
Current Limit
with Peaking
Flat Current
Limit
VIN
Decreasing
Load
Resistance
Decreasing
Load
Resistance
Slope = -RDS(ON)
VOUT
VO UT
Slope = -RDS(ON)
VIN
0V
0V
0A
IOUT
IOS IOC
0A
IOUT
I OS
Figure 20. Current Limit Profiles
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Feature Description (continued)
8.3.5 FLT
The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms
deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current
limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer does
not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An
input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS
as the ripple drives the device in and out of current limit.
If the TPS2001D is in current limit and the overtemperature circuit goes active, FLT goes true immediately;
however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is
entered. Disabling the TPS2001D clears an active FLT as soon as the switch turns off. FLT is high impedance
when the TPS2001D is disabled or in undervoltage lockout (UVLO).
8.3.6 Output Discharge
A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS2001D is
in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge
resistance as VIN falls towards 0 V. The output is be controlled by an external loadings when the device is in
ULVO or disabled.
8.4 Device Functional Modes
There are no other functional modes.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2001D current-limited power switch uses an N-channel MOSFET in applications requiring continuous
load current. The device enters constant-current mode when the load exceeds the current limit threshold.
9.2 Typical Application
TPS2001D
4.5 V-6.5 V
VOUT
0.1PF
1/2
IN
OUT
6/7/8
RFAULT
COUT
Fault
Signal
Control
Signal
5
FAULT
4
EN
GND
1
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the following input parameters:
1. The TPS2001D operates from a 5-V to ±0.5-V input rail.
2. What is the normal operation current, for example, the maximum allowable current drawn by portable
equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current
limit of power switch must exceed 900 mA to avoid false trigger during normal operation.
3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power
switch that must lower it to ensure power switch can protect the up-stream power when overload is
encountered at the output of power switch.
9.2.2 Detailed Design Procedure
To
1.
2.
3.
begin the design process a few parameters must be decided upon. The designer must know the following:
Normal input operation voltage
Output continuous current
Maximum up-stream power supply output current
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass
capacitor between IN and GND, as close to the device as possible for local noise decoupling.
All protection circuits have the potential for input voltage overshoots and output voltage undershoots.
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Typical Application (continued)
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the
abrupt reduction of output short-circuit current when the TPS2001D turns off and energy stored in the input
inductance drives the input voltage high. Input voltage droops may also occur with large load steps; and, as the
TPS2001D output is shorted. Applications with large input inductance (for example, connecting the evaluation
board to the bench power-supply through long cables) may require large input capacitance to reduce the voltage
overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the
TPS2001D responding to hard output short circuits isolates the input bus from faults. However, ceramic input
capacitance in the range of 1 µF to 22 µF adjacent to the TPS2001D input aids in both speeding the response
time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPS2001D has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage
down and potentially negative as it discharges. Applications with large output inductance (such as from a cable)
benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB
standard applications, a 120-µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor
is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of
capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF
ceramic capacitance on the output. The voltage undershoot must be controlled to less than 1.5 V for 10 µs.
9.2.3 Application Curves
Figure 22. TPS2001D Turnon into 2.5 Ω
Figure 23. TPS2001D Enable into Short
Figure 24. TPS2001D Pulsed Output Short
14
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10 Power Supply Recommendations
Design of the devices is for operation from an input voltage supply range of 4.5 V to 5.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.
11 Layout
11.1 Layout Guidelines
1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low
inductance trace.
2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections
using a low inductance trace.
11.2 Layout Example
0.100 x 0.175
& 5 18 mil vias
0.185 x 0.045
& 3 18 mil vias
0.08 x 0.250
0.15 x 0.15
50 mil trace
0.100 x 0.060
& 3 18 mil vias to
inner plane 2
0.07 x 0.08
10 mil trace
10 mil trace
Figure 25. DGK Package PCB Layout Example
GND: 0.052in2 Total
& 3 x 0.018in vias
COUT
0.050in trace
CIN
4 x 0.01in vias
VIN : 0.00925in2
& 3 x 0.018in vias
VOUT: 0.041in2 total
Figure 26. DBV Package PCB Layout Example
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11.3 Power Dissipation and Junction Temperature
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS2001D. The system designer can control choices of package, proximity to other power dissipating devices,
and printed-circuit board (PCB) design based on these calculations. These have a direct influence on maximum
junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by
system considerations. It is important to remember that these calculations do not include the effects of adjacent
heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the
pad improve the efficiency and reliability of both the TPS2001D part and the system. The following examples
were used to determine the θJA Custom thermal impedances noted in Thermal Information. They were based on
use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.
The θJA is 110.3°C/W. These values may be used in Equation 1 to determine the maximum junction temperature.
As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal
MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the
RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred
board construction from the Thermal Information table.
TJ = TA + ((IOUT2 × RDS(ON)) × θJA)
where
•
•
•
•
•
IOUT = rated OUT pin current (A)
RDS(ON) = Power switch ON-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
(1)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction or a package with lower θJA.
16
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS2001DDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1E6L
TPS2001DDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1E6L
TPS2001DDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1D6K
TPS2001DDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1D6K
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS2001DDBVR
SOT-23
3000
180.0
TPS2001DDBVT
TPS2001DDGKR
DBV
5
SOT-23
DBV
5
250
VSSOP
DGK
8
2500
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.2
3.2
1.4
4.0
180.0
8.4
3.2
3.2
1.4
330.0
12.4
5.3
3.4
1.4
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2001DDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TPS2001DDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
TPS2001DDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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