Texas Instruments | UCC2895-EP BiCMOS Advanced Phase-Shift PWM Controller (Rev. G) | Datasheet | Texas Instruments UCC2895-EP BiCMOS Advanced Phase-Shift PWM Controller (Rev. G) Datasheet

Texas Instruments UCC2895-EP BiCMOS Advanced Phase-Shift PWM Controller (Rev. G) Datasheet
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UCC2895-EP
SCBS809G – DECEMBER 2005 – REVISED SEPTEMBER 2017
UCC2895-EP BiCMOS Advanced Phase-Shift PWM Controller
1 Features
2 Description
•
•
•
•
The UCC2895-EP is a phase-shift pulse-width
modulation (PWM) controller that implements control
of a full-bridge power stage by phase shifting the
switching of one half bridge with respect to the other.
It allows constant frequency PWM in conjunction with
resonant zero-voltage switching to provide high
efficiency at high frequencies. The device can be
used either as a voltage-mode or current-mode
controller.
1
•
•
•
•
•
•
•
Programmable Output Turnon Delay
Adaptive Delay Set
Bidirectional Oscillator Synchronization
Capability for Voltage-Mode or Current-Mode
Control
Programmable Soft Start/Soft Stop and Chip
Disable Via a Single Pin
0% to 100% Duty-Cycle Control
7-MHz Error Amplifier
Operation to 1 MHz
Low-Active Current Consumption (5-mA Typ at
500 kHz)
Very-Low-Current Consumption During
Undervoltage Lockout (150-μA Typ)
Supports Defense, Aerospace, and Medical
Applications:
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
While the UCC2895-EP maintains the functionality of
the UC2875/6/7/8 family, it improves on that controller
family with additional features, such as enhanced
control logic, adaptive delay set, and shutdown
capability. Since the device is built in BCDMOS, it
operates with dramatically less supply current than its
bipolar counterparts. The UCC2895-EP can operate
with a maximum clock frequency of 1 MHz.
The M-temp UCC2895-EP device is offered in the 20pin SOIC (DW) package.
Device Information(1)
PART NUMBER
PACKAGE
UCC2895-EP
BODY SIZE (NOM)
SOIC (20)
7.50 mm × 12.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
UCC3895
1
EAN
2
EAOUT
3
Q1
EAP 20
7
SS/DISB
19
RAMP
OUTA
18
4
REF
OUTB
17
5
GND
PGND
16
6
SYNC
VCC
15
7
CT
OUTC
14
8
RT
OUTD
13
9
DELAB
CS
12
10
DELCD
ADS
11
VOUT
AC
VIN
VBIAS
B
D
UDG−98139
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC2895-EP
SCBS809G – DECEMBER 2005 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
5.1
5.2
5.3
5.4
5.5
5.6
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
6
Application and Implementation ........................ 11
6.1 Programming DELAB, DELCD, and Adaptive Delay
Set (ADS) ................................................................. 11
6.2 Circuit Description ................................................... 14
7
Device and Documentation Support.................. 16
7.1
7.2
7.3
7.4
7.5
8
Receiving Notification of Documentation Updates.. 16
Community Resources............................................ 16
Trademarks ............................................................. 16
Electrostatic Discharge Caution .............................. 16
Glossary .................................................................. 16
Mechanical, Packaging, and Orderable
Information ........................................................... 17
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2009) to Revision G
Page
•
Added Device Information table, ESD Ratings table, Thermal Information table, Application and Implementation
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Changed RAMP sink current MIN from 12 mA : to 10 mA..................................................................................................... 8
•
Changed VOL MAX from 270 mV : to 330 mV ........................................................................................................................ 9
2
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SCBS809G – DECEMBER 2005 – REVISED SEPTEMBER 2017
4 Pin Configuration and Functions
DW Package
20-Pin SOIC
Top View
DW PACKAGE
(TOP VIEW)
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
Pin Functions
PIN
NAME
ADS
NO.
11
I/O
DESCRIPTION
I
Adaptive delay set. This function sets the ratio between the maximum and minimum programmed
output delay dead time. When ADS is connected directly to CS, no delay modulation occurs.
Maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times
longer when CS = 0 than when CS = 2 V (the peak current threshold). ADS changes the output
voltage on the delay (DELAB and DELCD) pins by:
VDEL + [0.75
(VCS * VADS)] ) 0.5 V
where VCS and VADS are in volts. ADS must be limited to between 0 V and 2.5 V and must be less
than, or equal to, CS. DELAB and DELCD also are clamped to a minimum of 0.5 V.
CS
12
I
Current sense. CS is the inverting input of the current-sense comparator, and the noninverting input
of the overcurrent comparator and the ADS amplifier. The CS signal is used for cycle-by-cycle
current limiting in peak current-mode control and for overcurrent protection in all cases with a
secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also
results in a restart cycle, called soft stop, with full soft start.
Oscillator timing capacitor (see Figure 9). The UCC2895-EP oscillator charges CT via a programmed
current. The waveform on CT is a sawtooth, with a peak voltage of 2.35 V. The approximate oscillator
period is calculated by:
CT
7
tOSC +
I
5
RT
48
CT
) 120 ns
where CT is in farads, RT is in ohms, and tOSC is in seconds. CT can range from 100 pF to 880 pF.
Note that a large CT and a small RT combination results in extended fall times on the CT waveform.
The increased fall time increases the SYNC pulse width, thus, limiting the maximum phase shift
between OUTA/ OUTB and OUTC/ OUTD outputs, which limits the maximum duty cycle of the
converter.
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Pin Functions (continued)
PIN
NAME
NO.
DELAB,
DELCD
9, 10
I/O
I
DESCRIPTION
Delay programming between complementary outputs. DELAB programs the dead time between
switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This
delay is introduced between complementary outputs in the same leg of the external bridge. The
UCC2895-EP allows the user to select the delay in which the resonant switching of the external
power stages takes place. Separate delays are provided for the two half bridges to accommodate
differences in resonant capacitor charging currents. The delay in each stage is set according to the
formula:
tDELAY +
(25
10*12)
VDEL
RDEL
) 25 ns
where VDEL is in volts, RDEL is in ohms, and tDELAY is in seconds. DELAB and DELCD can source
approximately 1-mA maximum. Delay resistors must be chosen so that this maximum is not
exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For
optimum performance, keep stray capacitance on these pins at < 10 pF.
EAN
1
I
Error amplifier negative. Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
Error amplifier output. EAOUT also is connected internally to the noninverting input of the PWM
comparator and the no-load comparator. EAOUT is internally clamped to the soft-start voltage. The
no-load comparator shuts down the output stages when EAOUT falls below 500 mV and allows the
outputs to turn on again when EAOUT rises above 600 mV.
EAOUT
2
I/O
EAP
20
I
GND
5
—
Ground. Chip ground for all circuits except the output stages.
O
Outputs. These outputs are 100-mA complementary MOS drivers and are optimized to drive FET
driver circuits. OUTA and OUTB are fully complementary (assuming no programmed delay). They
operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended
to drive one half-bridge circuit in an external power stage. OUTC and OUTD drive the other half
bridge and have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect
to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase
relationship of OUTC and OUTD, with respect to OUTA and OUTB, requires other than the nominal
50% duty ratio on OUTC and OUTD during those transients.
—
Output stage ground. To keep output switching noise from critical analog circuits, the UCC2895-EP
has two different ground connections. PGND is the ground connection for the high-current output
stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since
PGND carries high current, board traces must be low impedance.
I
Inverting input of PWM comparator. RAMP receives either the CT waveform in voltage and average
current-mode controls, or the current signal (plus slope compensation) in peak current-mode control.
An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead
time.
O
5-V ± 1.2% voltage reference. REF supplies power to internal circuitry, and also can supply up to 5
mA to external loads. The reference is shut down during undervoltage lockout, but is operational
during all other disable modes. For best performance, bypass with a 0.1-μF low ESR, low ESL
capacitor to ground. Do not use more than 1 μF.
OUTA,
OUTB,
OUTC,
OUTD
PGND
RAMP
REF
18, 17, 14,
13
16
3
4
Error amplifier positive. Noninverting input to the error amplifier. Keep below 3.6 V for proper
operation.
Oscillator timing resistor (see Figure 9). The oscillator in the UCC2895-EP operates by charging an
external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as:
RT
8
IRT (A) + 3 V
RT (W)
I
RT can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging current also are
programmed by IRT.
4
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Pin Functions (continued)
PIN
NAME
SS/DISB
NO.
19
I/O
DESCRIPTION
I
Soft start/disable. SS/DISB combines two independent functions:
•
Disable mode. A rapid shutdown of the chip is accomplished by any one of the following:
externally forcing SS/DISB below 0.5 V, externally forcing REF below 4 V, VDD dropping below
the UVLO threshold, or an overcurrent fault is sensed (CS = 2.5 V).
In the case of REF pulled below 4 V or an UVLO condition, SS/DISB actively is pulled to ground
via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB sinks a current of 10 × IRT
until
SS/DISB
falls
below
0.5
V.
Note that, if SS/DISB is externally forced below 0.5 V, the pin starts to source current equal to
IRT. Also note that the only time the part switches into the low IDD current mode is when the part
is in undervoltage lockout.
•
Soft-start mode. After a fault or disable condition has passed and VDD is above the start
threshold and/or SS/DISB falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start
mode. The pin now sources current equal to IRT. A user-selected capacitor on SS/DISB
determines the soft start and soft-start time. In addition, a resistor in parallel with the capacitor
may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB actively clamps the
EAOUT voltage to approximately the SS/DISB voltage during both soft-start, soft-stop, and
disable conditions.
Synchronization (see Figure 9). SYNC is bidirectional. When used as an output, SYNC can be used
as a clock, which is the same as the chip’s internal clock. When used as an input, SYNC overrides
the chip’s internal oscillator and acts as its clock signal. This bidirectional feature allows
synchronization of multiple power supplies. SYNC also internally discharges the CT capacitor and
any filter capacitors that are present on RAMP. The internal SYNC circuitry is level sensitive, with an
input low threshold of 1.9 V and an input high threshold of 2.1 V. A resistor as small as 3.9 kΩ may
be tied between SYNC and GND to reduce the synchronization pulse width.
SYNC
6
I/O
VDD
15
I
Power supply. VDD must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor to
ground.
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5 Specifications
5.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
17
V
Supply current
30
mA
REF current
15
mA
OUT current
100
mA
V
Supply voltage
IDD < 10 mA
Analog inputs
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB
–0.3
REF + 0.3
Drive outputs
OUTA, OUTB, OUTC, OUTD
–0.3
to VCC + 0.3
V
Power dissipation
(at TA = 25°C)
N package
1
W
650
mW
Storage temperature, Tstg
DW package
–65
150
°C
Junction temperature, TJ
–55
150
°C
300
°C
Lead temperature
(1)
(2)
Soldering, 10 s
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Currents are positive into and negative out of the specified terminal.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±800
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
NOM
10
(2)
MAX
UNIT
16.5
V
CVDD
Supply voltage bypass capacitor
CREF
Reference bypass capacitor (3)
CT
Timing capacitor (for 500-KHz switching frequency)
RT
Timing resistor (for 500-KHz switching frequency)
RDEL_AB
RDEL_CD
Delay resistor
2.5
40
kΩ
TJ
Operating junction temperature (4)
–55
125
°C
(1)
(2)
(3)
(4)
6
10 x CREF
0.1
µF
4.7
200
µF
pF
82
It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a
seperate ground plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located
over this ground plane. Any connections associated with these pins to ground should be connected to this ground plane.
The VDD capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor
should be located as physically close as possible to the VDD pins.
The VREF capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for the VREF then it should be located near the VREF capacitor and connected to the VREF pin with a resistor of 51 Ω or greater.
The bulk capacitor on VDD must be a factor of 10 greater than the total VREF capacitance.
It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
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5.4 Thermal Information
UCC2895-EP
THERMAL METRIC (1)
DW (SOIC)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
59.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.3
°C/W
RθJB
Junction-to-board thermal resistance
27.8
°C/W
ψJT
Junction-to-top characterization parameter
7.4
°C/W
ψJB
Junction-to-board characterization parameter
27.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Electrical Characteristics
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs,
TA = TJ, TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Start threshold
10.2
11
11.8
V
Stop threshold
8.2
9
9.8
V
1
2
3
V
150
250
μA
mA
UVLO
Hysteresis
SUPPLY CURRENT
Start-up current
VDD = 8 V
IDD active
VCC clamp voltage
5
6
IDD = 10 mA
16.5
17.5
18.5
TJ = 25°C
4.94
5
5.06
10 V < VDD < 17.5 V, 0 mA < IREF < 5 mA
4.85
5
5.15
10
20
V
VOLTAGE REFERENCE
Output voltage
Short-circuit current
REF = 0 V, TJ = 25°C
V
mA
ERROR AMPLIFIER
Common-mode input voltage
–0.1
3.6
Offset voltage
–7
7
mV
V
Input bias current (EAP, EAN)
–1
1
μA
V
EAOUT VOH
EAP – EAN = 500 mV, IEAOUT = –0.5 mA
4
4.5
5
EAOUT VOL
EAP – EAN = 500 mV, IEAOUT = 0.5 mA
0
0.2
0.4
EAOUT source current
EAP – EAN = 500 mV, EAOUT = 2.5 V
1
1.5
mA
EAOUT sink current
EAP – EAN = –500 mV, EAOUT = 2.5 V
2.5
4.5
mA
75
85
dB
5
7
MHz
1.5
2.2
V/μs
No-load comparator turn-off threshold
0.45
0.5
0.55
V
No-load comparator turn-on threshold
0.55
0.6
0.69
V
0.035
0.1
0.165
V
Open-loop DC gain
Unity gain bandwidth (1)
Slew rate
EAN from 1 V to 0 V, EAP = 500 mV,
EAOUT from 0.5 V to 3 V (1)
No-load comparator hysteresis
(1)
V
Specified by design. Not production tested.
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Electrical Characteristics (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs,
TA = TJ, TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
OSCILLATOR
Frequency
TJ = 25°C
Total variation
Line, Temperature (1)
SYNC VIH
SYNC VIL
SYNC VOH
ISYNC = –400 μA, CT = 2.6 V
SYNC VOL
ISYNC = 100 μA, CT = 0 V
SYNC output pulse width
SYNC load = 3.9 kΩ and 30 pF in parallel
RT voltage
CT peak voltage
CT valley voltage
473
500
527
2.5%
5%
2.05
2.1
2.32
V
1.85
1.9
1.95
V
4.1
4.5
5
V
0
0.5
1
V
85
135
ns
2.9
3
3.1
V
2.25
2.35
2.55
V
0
0.2
0.65
V
0.72
0.85
1.05
V
0%
0.85%
1.5%
70
120
ns
5
μA
PWM COMPARATOR
EAOUT to RAMP/input offset voltage
RAMP = 0 V, DELAB = DELCD = REF
Minimum phase shift
(OUTA to OUTC, OUTB to OUTD)
RAMP = 0 V, EAOUT = 650 mV (2)
RAMP to OUTC/OUTD delay
RAMP from 0 V to 2.5 V, EAOUT = 1.2 V,
DELAB = DELCD = REF (3)
RAMP bias current
RAMP < 5 V, CT < 2.2 V
–5
RAMP sink current
RAMP = 5 V, CT < 2.6 V
10
19
mA
CURRENT SENSE
CS bias current
0 < CS < 2.5 V, 0 < ADS < 2.5 V
–4.5
20
μA
V
Peak current threshold
1.9
2
2.1
Overcurrent threshold
2.4
2.5
2.6
V
75
110
ns
CS to output delay
CS from 0 to 2.3 V, DELAB = DELCD = REF
SOFT START AND SHUTDOWN
Soft-start source current
SS/DISB = 3 V, CS = 1.9 V
–40
–35
–30
μA
Soft-start sink current
SS/DISB = 3 V, CS = 2.6 V
325
350
375
μA
0.44
0.5
0.56
V
Soft-start/disable comparator threshold
DELAY SET
0.45
0.5
0.55
ADS = 0 V, CS = 2 V
1.9
2
2.1
Output delay
ADS = CS = 0 V (1) (3)
450
525
600
ns
ADS bias current
0 V < ADS < 2.5 V, 0 V < CS < 2.5 V
–20
20
μA
DELAB/DELCD output voltage
(2)
(3)
8
ADS = CS = 0 V
V
Minimum phase shift is defined as:
t f(OUTA) * t f(OUTC)
F + 200
tPERIOD
or
t f(OUTB) * t f(OUTD)
F + 200
tPERIOD
where:
tf(OUTA) = falling edge of OUTA signal
tf(OUTB) = falling edge of OUTB signal
tf(OUTC) = falling edge of OUTC signal
tf(OUTD) = falling edge of OUTD signal
t(PERIOD) = period of OUTA or OUTB signal
Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is shown in Figure 1 and Figure 2, where:
tf(OUTA) = falling edge of OUTA signal
tr(OUTB) = rising edge of OUTB signal
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Electrical Characteristics (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs,
TA = TJ, TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOH (all outputs)
IOUT = –10 mA, VDD to output
250
400
mV
VOL (all outputs)
IOUT = 10 mA
150
330
mV
Rise time
CLOAD = 100 pF (1)
20
35
ns
(1)
20
35
ns
Fall time
CLOAD = 100 pF
tPERIOD
OUTA(1)
tDELAY = tf(OUTA) – tf(OUTC)
OUTC(2)
(1)
Also applies to OUTB.
(2)
Also applies to OUTD.
Figure 1. OUTA/OUTC Output Delay
OUTA(1)
tDELAY = tf(OUTA) – tr(OUTB)
OUTB(2)
(1)
Also applies to OUTC.
(2)
Also applies to OUTD.
Figure 2. OUTA/OUTB Output Delay
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5.6 Typical Characteristics
Vcs = 0 V
Vcs = 2 V
GAIN (dB)
2000
PHASE MARGIN (5C)
100
200
80
160
1400
1200
1000
800
60
120
40
80
20
40
600
400
PHASE MARGIN
(DEGREES)
1600
GAIN (dB)
OUTPUT DELAY (ns)
1800
200
0
0
10
20
30
0
40
0
1
RDEL (kW)
100
1000000
FREQUENCY (Hz)
Figure 3. Delay Programming (Characterizes Output Delay
Between A/B, C/D)
Figure 4. Error Amplifier Gain and Phase Margin
1
RT = 47 K
RT = 62 k
RT = 82 k
RT = 100 k
1600
0.95
FREQUENCY (kHz)
EAOUT TO RAMP OFFSET (V)
10000
0.9
0.85
1400
1200
1000
800
600
400
200
0.8
−60
−40
−20
0
20
40
60
80
100
0
120
100
TEMPERATURE (5C)
Figure 5. EAOUT To Ramp Offset Over Temperature
VDD = 10 V
VDD = 12 V
1000
CT (pF)
VDD = 15 V
Figure 6. Frequency vs RT and CT (Oscillator Frequency)
VDD = 10 V
VDD = 17 V
VDD = 12 V
VDD = 15 V
VDD = 17 V
13
9
12
11
IDD (mA)
IDD (mA)
8
7
6
10
9
8
7
6
5
5
4
4
0
400
800
1200
1600
0
400
OSCILLATOR FREQUENCY (kHz)
Figure 7. IDD vs VDD and Oscillator Frequency
(No Output Loading)
10
800
1200
1600
OSCILLATOR FREQUENCY (kHz)
Figure 8. IDD vs VDD and Oscillator Frequency
(With 0.1-Nf Output Loads)
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Programming DELAB, DELCD, and Adaptive Delay Set (ADS)
The UCC2895-EP allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit, according to the formula from the data sheet:
t DELAY +
(25
10 *12)
V DEL
R DEL
) 25 ns
For this equation, VDEL is determined in conjunction with the desire to utilize (or not utilize) the ADS feature from:
V DEL + [0.75
(V CS * V ADS)] ) 0.5 V
Figure 9 shows the resistors needed to program the delay periods and the ADS function.
UCC2895−EP
9
DELAB
10
DELCD
CS
12
ADS
11
RDELAB
RDELCD
Figure 9. Resistors Needed In Programming
The ADS allows the user to vary the delay times between switch commands within each of the converter’s two
legs. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider
from CS to GND to set VADS. From the previous equation for VDEL, if ADS is tied to GND, VDEL rises in direct
proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition, the maximum value of
VDEL is 2 V. If ADS is connected to a resistive divider between CS and GND, the term (VCS – VDS) becomes
smaller, reducing the level of VDEL. This decreases the amount of delay modulation. In the limit of ADS tied to
CS, VDEL = 0.5 V and no delay modulation occurs. In the case with maximum delay modulation (ADS = GND)
when the circuit goes from light load to heavy load, the variation of VDEL is from 0.5 V to 2 V. This causes the
delay times to vary by a 4:1 ratio as the load is changed.
The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of
the current flowing in the primary winding of the transformer, and can change by a factor of 10:1 or more as
circuit loading changes. Reference [1] delves into the many interrelated factors for choosing the optimum delay
times for the most efficient power conversion and illustrates an external circuit to enable ADS using the UC2879.
Implementing this adaptive feature is simplified in the UCC2895-EP controller, giving the user the ability to tailor
the delay times to suit a particular application, with a minimum of external parts.
[1] L. Balogh, "Design Review: 100W, 400 kHz, DC/DC Converter With Current Doubler Synchronous
Rectification Achieves 92% Efficiency," Unitrode Power Supply Design Seminar Manual, Unitrode Corporation,
1996, Topic 2.
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Programming DELAB, DELCD, and Adaptive Delay Set (ADS) (continued)
A = VADS/VCS RDELAY = 10 kW
A = 1.0
DELAY TIME (ns)
500
400
A = 0.8
300
A = 0.6
200
100
A = 0.4
A = 0.2
A = 0.1
0
0.5
1
1.5
2.0
2.5
CURRENT SENSE VOLTAGE (V)
Figure 10. Resistors Needed For Programming
CLOCK
RAMP
AND
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
UDG−98138
Figure 11. UCC2895-EP Timing (No Output Delay Shown)
12
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Programming DELAB, DELCD, and Adaptive Delay Set (ADS) (continued)
IRT
RT
Q
8
CT
7
Q
R
SYNC
RAMP
3
EAN
R Q
DELAY B
D S Q
DELAY C
OUTA
9
DELAB
17
OUTB
+
ERROR
AMP
20
+
1
+
CURRENT−SENSE
COMPARATOR
14
NO−LOAD
COMPARATOR
R Q
DELAY D
12
2.5 V
IRT
+
HI = ON
10
DELCD
13
OUTD
16
PGND
11
ADS
4
REF
5
GND
ADAPTIVE DELAY
SET AMPLIFIER
+
REF
OUTC
0.5 V / 0.6 V
+
OVERCURRENT
COMPARATOR
SS
18
DELAY A
2
2V
CS
D S Q
VDD
+
EAP
Q
6
0.8 V
EAOUT
15
D S Q
OSC
8(IRT )
Q
S
Q
R
UVLO COMPARATOR
+
11 V/9 V
DISABLE
COMPARATOR
0.5 V
+
19
HI = ON
0.5 V
REF
REFERENCE OK
COMPARATOR
+
4V
10(IRT )
UDG−98140
Figure 12. Block Diagram
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6.2 Circuit Description
REF
8IRT
RT
RT
VREF
IRT
CT
2.5 V
S
CLOCK
Q
+
CT
+
0.2 V
R
SYNC
CLOCK
UDG−98141
Figure 13. Oscillator Block Diagram
REF
0.5 V
100 kΩ
75 kΩ
TO DELAY A
AND DELAY B
BLOCKS
+
CS
DELAB
+
100 kΩ
ADS
75 kΩ
REF
+
TO DELAY C
AND DELAY D
BLOCKS
DELCD
UDG−98142
Figure 14. ADS Block Diagram
14
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Circuit Description (continued)
BUSED CURRENT
FROM ADS CIRCUIT
VREF
3.5 V
DELAB/CD
FROM PAD
DELAYED
CLOCK
SIGNAL
2.5 V
CLOCK
UDG−98143
Figure 15. Delay Block Diagram (One Delay Block Per Output)
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UCC2895-EP
SCBS809G – DECEMBER 2005 – REVISED SEPTEMBER 2017
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7 Device and Documentation Support
7.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
7.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
7.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
16
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SCBS809G – DECEMBER 2005 – REVISED SEPTEMBER 2017
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC2895MDWREP
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
UCC2895MEP
V62/06614-01XE
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
UCC2895MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC2895-EP :
• Catalog: UCC2895
• Automotive: UCC2895-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC2895MDWREP
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.1
2.65
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC2895MDWREP
SOIC
DW
20
2000
346.0
346.0
41.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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