Texas Instruments | TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator (Rev. A) | Datasheet | Texas Instruments TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator (Rev. A) Datasheet

Texas Instruments TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator (Rev. A) Datasheet
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TPS7A39
SBVS263A – JULY 2017 – REVISED SEPTEMBER 2017
TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator
1 Features
3 Description
•
•
•
The TPS7A39 device is a dual, monolithic, highPSRR, positive and negative low-dropout (LDO)
voltage regulator capable of sourcing (and sinking) up
to 150 mA of current. The regulated outputs can be
independently and externally adjusted to symmetrical
or asymmetrical voltages, making this device an ideal
dual, bipolar power supply for signal conditioning.
1
•
•
•
•
•
•
•
•
•
•
•
Positive and Negative LDOs in One Package
Wide Input Voltage Range: ±3.3 V to ±33 V
Wide Output Voltage Range:
– Positive Range: 1.2 V to 30 V
– Negative Range: –30 V to 0 V
Output Current: 150 mA per Channel
Monotonic Start-Up Tracking
High Power-Supply Rejection Ratio (PSRR):
– 69 dB (120 Hz)
– ≥ 50 dB (10 Hz to 2 MHz)
Output Voltage Noise: 21 µVRMS (10 Hz–100 kHz)
Buffered 1.2-V Reference Output
Stable With a 10-µF or Larger Output Capacitor
Single Positive-Logic Enable
Adjustable Soft-Start In-Rush Control
3-mm × 3-mm, 10-Pin WSON Package
Low Thermal Resistance: RθJA = 44.4°C/W
Operating Temperature Range: –40 to +125°C
2 Applications
•
•
•
•
•
•
•
Supply Rails for Op Amps, ADCs, DACs, and
Other High-Precision Analog Circuitry
Post DC-DC Regulation and Filtering
Analog I/O Modules
Test and Measurement
Rx, Tx, and PA Circuitry
Industrial Instrumentation
Medical Imaging
Both positive and negative outputs of the TPS7A39
ratiometrically track each other during startup to
mitigate floating conditions and other power-supply
sequencing issues common in dual-rail systems. The
negative output can regulate up to 0 V, extending the
common-mode range for single-supply amplifiers.
The TPS7A39 also features high PSRR to eliminate
power-supply noise, such as switching noise, that can
compromise signal integrity.
Both regulators are controlled with a single positive
logic enable pin for interfacing with standard digital
logic. A capacitor-programmable soft-start function
controls in-rush current and start-up time. The internal
reference voltage of the TPS7A39 can be overridden
with an external reference to enable precision
outputs, output voltage margining, or to track other
power supplies. Additionally, the TPS7A39 has a
buffered reference output that can be used as a
voltage reference for other components in the
system.
These features make the TPS7A39 a robust,
simplified solution to power operational amplifiers,
digital-to-analog converters (DACs), and other
precision analog circuitry.
Device Information(1)
PART NUMBER
PACKAGE
TPS7A39
WSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Powering the Signal Chain
Monotonic Start-Up Tracking
25
+5 V
+15 V
OUTP
INP
EN
20
Feedback
Network
±
ADC
+
Signal In
+15 V
EN
-15 V
INN
FBN
VOUTN
VINN
10
VS+
TPS7A39
BUF
VOUTP
15
NR/SS
VS-
Voltage (V)
FBP
VINP
5
0
-5
-10
GND
OUTN
-5 V
-15
-20
-25
0
20
40
60
80 100 120
Time (ms)
140
160
180
200
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A39
SBVS263A – JULY 2017 – REVISED SEPTEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Startup Characteristics..............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 19
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
24
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Applications ................................................ 34
9 Power-Supply Recommendations...................... 39
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Example .................................................... 40
10.3 Package Mounting ................................................ 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
41
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
Changes from Original (July 2017) to Revision A
•
2
Page
Released to production .......................................................................................................................................................... 1
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5 Pin Configuration and Functions
DSC Package
10-Pin WSON
Top View
INP
1
EN
2
10
Thermal Pad
OUTP
9
FBP
8
BUF
NR/SS
3
GND
4
7
FBN
INN
5
6
OUTN
Not to scale
Pin Functions
PIN
NO.
1
2
NAME
INP
EN
I/O
DESCRIPTION
I
Positive input. A 10-μF (1) or larger capacitor must be tied from this pin to ground to ensure stability.
Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section
for more information.
I
Enable pin. Driving this pin to logic high (VEN ≥ VIH(EN)) enables the device; driving this pin to logic low
(VEN ≤ VIL(EN)) disables the device. If enable functionality is not required, this pin must be connected to
INP; see the Application and Implementation section for more detail. The enable voltage cannot exceed
the input voltage (VEN ≤ VINP).
3
NR/SS
—
Noise-reduction, soft-start pin. Connecting an external capacitor between this pin and ground reduces
reference voltage noise and enables soft-start and start-up tracking. A 10-nF or larger capacitor (CNR/SS)
is recommended to be connected from NR/SS to GND to maximize or optimize ac performance and to
ensure start-up tracking. This pin can also be driven externally to provide greater output voltage
accuracy and lower noise, see the User-Settable Buffered Reference section for more information.
4
GND
—
Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance
connection.
5
INN
I
Negative input. A 10-μF (1) or larger capacitor must be tied from this pin to ground to ensure stability.
Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section
for more information.
6
OUTN
O
Negative output. A 10-μF (1) or larger capacitor must be tied from this pin to ground to ensure stability.
Place the output capacitor as close to the output as possible; see the Capacitor Recommendations
section for more information.
7
FBN
I
Negative output feedback pin. This pin is used to set the negative output voltage. Although not required,
a 10-nF feed-forward capacitor from FBN to OUTN (as close to the device as possible) is recommended
to maximize ac performance. Nominally this pin is regulated to VFBN. Do not connect to ground.
8
BUF
O
Buffered reference output. This pin is connected to FBN through R2 and the voltage at this node is
inverted and scaled up by the negative feedback network to provide the desired output voltage. The
buffered reference can be used to drive external circuits, and has a 1-mA maximum load.
9
FBP
I
Positive output feedback pin. This pin is used to set the positive output voltage. Although not required, a
10-nF feed-forward capacitor from FBP to OUTP (as close to the device as possible) is recommended to
maximize ac performance. Nominally this pin is regulated to VFBP. Do not connect this pin directly to
ground.
10
OUTP
O
Positive output. A 10-μF (1) or larger capacitor must be tied from this pin to ground to ensure stability.
Place the output capacitor as close to the output as possible; see the Capacitor Recommendations
section for more information.
Thermal Pad
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Pad
(1)
The nominal input and output capacitance must be greater than 2.2 µF; throughout this document the nominal derating on these
capacitors is 80%. Take care to ensure that the effective capacitance at the pin is greater than 2.2 µF.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1) (2)
INP
Voltage
MAX
36
INN
–36
0.3
OUTP
–0.3
VINP + 0.3 (3)
OUTN
VINN – 0.3 (4)
0.3
FBP
–0.3
VINP + 0.3 (5)
BUF
–1
VINP + 0.3 (5)
–0.3
VINP + 0.3 (6)
NR/SS
FBN
EN
VINN – 0.3 (7)
0.3
–0.3
VINP + 0.3 (8)
Buffer current
Temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
UNIT
V
Internally
limited
Output current
Current
MIN
–0.3
2
mA
Operating junction temperature, TJ
–55
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages with respect to the ground pin, unless otherwise noted.
The absolute maximum rating is VINP + 0.3 V or 33 V, whichever is smaller.
The absolute maximum rating is VINN – 0.3 V or –33 V, whichever is greater.
The absolute maximum rating is VINP + 0.3 V or 3 V, whichever is smaller.
The absolute maximum rating is VINP + 0.3 V or 2 V, whichever is smaller.
The absolute maximum rating is VINN – 0.3 V or –3 V, whichever is greater.
The absolute maximum rating is VINP + 0.3 V or 36 V, whichever is smaller.
6.2 ESD Ratings
VALUE
VESD
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
|VINx|
Supply voltage magnitude for either regulator
VEN
Enable supply voltage
VOUTP
VOUTN
NOM
MAX
UNIT
3.3
33
V
0
VINP
V
Positive regulated output voltage range
VFBP
30
V
Negative regulated output voltage range
–30
VFBN
V
150
mA
1000
µA
IOUTx
Output current for either regulator
IBUF
Output current from the BUF pin
CINx
Input capacitor for either regulator
0.005
(1)
0
120
4.7
10 (2)
(2)
COUTx
Output capacitor for either regulator
4.7
CNR/SS
Noise-reduction and soft-start capacitor
0 (3)
10
1000
nF
CFFP
Positive channel feed-forward capacitor; connect from VOUTP to FBP
0
10
100
nF
CFFN
Negative channel feed-forward capacitor; connect from VOUTN to FBN
0
10
100
nF
R2P
Lower positive feedback resistor
10
240
kΩ
R2N
Lower negative feedback resistor (from FBN to BUF)
10
240
kΩ
TJ
Operating junction temperature
125
°C
(1)
(2)
(3)
10
µF
µF
–40
Minimum load required when feedback resistors are not used. If feedback resistors are used, keeping R2x below 240 kΩ satisfies this
requirement.
The nominal input and output capacitor value of 10-µF accounts for the derating factors that apply to X5R and X7R ceramic capacitors.
The assumed overall derating is 80%.
For startup tracking to function correctly a minimum 4.7-nF CNR/SS capacitor must be used.
6.4 Thermal Information
TPS7A39
THERMAL METRIC (1)
DSC (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
44.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
33.7
°C/W
RθJB
Junction-to-board thermal resistance
19.4
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
19.5
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
2.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1 V or VIN(nom) = 3.3 V (whichever is greater), VINN(nom) = VOUTN(nom) – 1 V or
VINN(nom) = –3.3 V (whichever is less), VEN = VINP, IOUT = 1 mA, CINx = 2.2 μF, COUTx = 10 μF, CFFx = CNR/SS = open, R1N = R2N =
10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VINP
Input voltage range, positive channel
3.3
33
V
VINN
Input voltage range, negative channel
–33
–3.3
V
VUVLOP(rising)
Undervoltage lockout threshold,
positive channel
1.4
3.1
V
VUVLOP(hys)
VUVLON(falling)
VINP rising, VINN = –3.3 V
Undervoltage lockout threshold, positive
channel hysteresis
Undervoltage lockout threshold,
negative channel
VINP falling, VINN = –3.3 V
120
VINN falling, VINP = 3.3 V
–3.1
–1.4
VUVLON(hys)
Undervoltage lockout threshold, negative
channel, hysteresis
VNR/SS
Internal reference voltage
1.172
1.19
1.208
VFBP
Positive feedback voltage
1.170
1.188
1.206
VFBN
Negative feedback voltage
–10
3.7
10
Output voltage range (1)
VOUT
VINN rising, VINP = 3.3 V
mV
70
30
–30
VFBN (2)
–1.5
1.5
%VOUT
%VOUT
VOUTP accuracy
VINP(nom) ≤ VINP ≤ 33 V, 1 mA ≤ IOUTP ≤ 150 mA,
1.2 V ≤ VOUTP(nom) ≤ 30 V
VOUTN accuracy (3)
–33 V ≤ VINN ≤ VINN(nom), –150 mA ≤ IOUTN ≤
–1 mA, –30 V ≤ VOUTN(nom) ≤ –1.2 V
–3
3
–33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤
1 mA, –1.2 V < VOUTN(nom) < 0 V
–36
36
–33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤
1 mA, VOUTN(nom) = 0 V
–12
12
VINP(nom) ≤ VINP ≤ 33 V
ΔVOUT(ΔIOUT) /
VOUT(NOM)
Load regulation, positive channel
1 mA ≤ IOUTP ≤ 150 mA
–0.09
Load regulation, negative channel
–150 mA ≤ IOUTN ≤ –1 mA
0.715
Positive channel
Dropout voltage
Negative channel
0.035
175
300
IOUTP = 150 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V,
VFBP = 1.070 V
300
500
mV
IOUTN = –50 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V,
VFBN = 0.0695 V
–250
–145
IOUTN = –150 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V,
VFBN = 0.0695 V
–400
–275
Buffered reference output voltage
Buffered reference load regulation
IBUF = 100 µA to 1 mA
VBUF – VNR/SS
Output buffer offset voltage
VNR/SS = 0.25 V to 1.2 V
–4
VOUTP–VOUTN
DC output voltage difference with a forced
REF voltage
VNR/SS = 0.25 V to 1.2 V
–10
ILIM
Current limit
VNR/SS
V
1
3
mV/mA
8
mV
10
%VNR/SS
Positive channel
VOUTP = 90% VOUTP(nom)
200
330
500
Negative channel
VOUTN = 90% VOUTN(nom)
–500
–300
–200
75
150
Supply current
Negative channel
IOUTP = 0 mA, R2N = open, VINP = 33 V
IOUTP = 150 mA, R2N = open, VINP = 33 V
IOUTN = 0 mA, VOUTN(nom)= 0 V, R2N = open, VINN =
–33 V
Positive channel
VEN = 0.4 V, VINP = 33 V
Negative channel
VEN = 0.4 V, VINN = –33 V
mA
904
–150
IOUTN = 150 mA, R2N = open, VINN = –33 V
6
%VOUT
IOUTP = 50 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V,
VFBP = 1.070 V
VBUF/IBUF
(1)
(2)
(3)
%VOUT
0.125
VBUF
Positive channel
V
mV
–33 V ≤ VINN ≤ VOUT(nom) + 1 V
Line regulation, negative channel
Shutdown supply current
V
mV
VFBP
Line regulation, positive channel
ISHDN
V
Negative channel
ΔVOUT(ΔVIN) /
VOUT(NOM)
ISUPPLY
mV
Positive channel
Negative VOUT channel accuracy
VDO
V
µA
–60
–1053
3.75
–4.5
–2.25
6.5
µA
To ensure VOUT does not drift up while the device is disabled, a minimum load current of 5 µA is required.
VOUT(target) = 0 V, R1N = 10 kΩ, R2N = open.
The device is not tested under conditions where the power dissipated across the device, PD, exceeds 2 W.
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Electrical Characteristics (continued)
at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1 V or VIN(nom) = 3.3 V (whichever is greater), VINN(nom) = VOUTN(nom) – 1 V or
VINN(nom) = –3.3 V (whichever is less), VEN = VINP, IOUT = 1 mA, CINx = 2.2 μF, COUTx = 10 μF, CFFx = CNR/SS = open, R1N = R2N =
10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
IFBx
INR/SS
Soft-start charging current
VNR/SS = 0.9 V
IEN
Enable pin leakage current
VEN = VINP = 33 V
VIH(EN)
Enable high-level voltage
VIL(EN)
Enable low-level voltage
PSRR
Negative channel
Power-supply rejection ratio
Output noise voltage
Negative channel
RNR/SS
Tsd
–100
3
TYP
MAX
5.5
100
–9.7
nA
5.1
6.7
µA
1
µA
2.2
VINP
V
0
0.4
V
69
VINP = 3.3 V, VOUTP(nom) = VNR/SS, COUTP = 10 μF,
CNR/SS = 10 nF, BW = 10 Hz to 100 kHz
20.63
VINP = 6 V, VOUTP(nom) = 5 V, COUTP = 10 μF,
CNR/SS = CFF = 10 nF, BW = 10 Hz to 100 kHz
26.86
VINN = –3 V, VOUTN(nom) = –VNR/SS, COUTP = 10 μF,
CNR/SS = 10 nF, BW = 10 Hz to 100 kHz
22.13
VINN = –6 V, VOUTN(nom) = –5 V, COUTP = 10 μF,
CNR/SS = CFF= 10 nF, BW = 10 Hz to 100 kHz
28.68
dB
µVRMS
Filter resistor from band gap to NR pin
350
Thermal shutdown temperature
UNIT
0.02
|VIN| = 6 V, |VOUT(nom)| = 5 V, COUT = 10 μF,
CNR/SS = CFF= 10 nF, f = 120 Hz
Positive channel
Vn
MIN
Positive channel
Feedback pin leakage
current
Shutdown, temperature increasing
175
Reset, temperature decreasing
160
kΩ
°C
6.6 Startup Characteristics
at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1 V or VIN(nom) = 3.3 V (whichever is greater), VINN(nom) = VOUTN(nom) – 1 V or
VINN(nom) = –3.3 V (whichever is less), VEN = VINP, IOUT = 1 mA, CINx = 2.2 μF, COUTx = 10 μF, CFFx = CNR/SS = 4.7nF, R1N = R2N
= 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tEN(delay)
Delay time from EN low-to-high transition to 2.5%
VOUTP
From EN low-to-high transition to VOUTP = 2.5% ×
VOUTP(nom)
300
µs
tstart-up
Delay time from EN low-to-high transition to both
outputs reaching 95% of final value
From EN low-to-high transition to VOUTP =
VOUTP(nom) × 95% and VOUTN = VOUTN(nom) × 95%
1.1
ms
tPstart-Nstart
Delay time from VOUTP leaving a high-impedance
state to VOUTN leaving a high-impedance state
From VOUTP = VOUTP(nom) × 2.5% to VOUTN =
VOUTN(nom) × 2.5%
Δ|VOUTP –
VOUTN|
Voltage difference between the positive and
negative output
During tPstart-Nstart
–40
–17
40
µs
75
300
mV
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VEN
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VIH(EN)
Ttstart-upt
90%
VOUTP
VOUTN
tEN(delay)
tPstart-Nstart
90%
NOTE: Slow ramps (trise(VINx) > 10 ms typically) on VINx with EN tied to VINP does not meet the tracking specification. Use a
resistor divider from VINP to EN for these applications.
Figure 1. Start-Up Characteristics
8
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6.7 Typical Characteristics
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100
80
60
40
VIN = 5.5 V
VIN = 5.6 V
VIN = 5.7 V
VIN = 5.8 V
VIN = 5.9 V
VIN = 6.0 V
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
60
40
20
Figure 2. Positive PSRR vs Frequency and VINP
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 3. Negative PSRR vs Frequency and VINN
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100
VINN = -5.8 V
VINN = -5.9 V
VINN = -6.0 V
VOUTP = 5 V, IOUTP = 0 mA, VOUTN = –5 V, IOUTN = 150 mA,
CNR/SS = CFFx = 10 nF
100
80
60
40
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
80
60
40
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
20
0
10
10M
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CNR/SS = CFFx = 10 nF
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFx = 10 nF
Figure 4. Positive PSRR vs Frequency and IOUTP
Figure 5. Negative PSRR vs Frequency and IOUTN
100
Power Supply Rejection Ratio (dB)
100
Power Supply Rejection Ratio (dB)
VINN = -5.5 V
VINN = -5.6 V
VINN = -5.7 V
0
10
10M
VOUTP = 5 V, IOUTP = 150 mA, VOUTN = –5 V, IOUTN = 0 mA,
CNR/SS = CFFx = 10 nF
80
80
60
40
COUT = 4.7 PF
COUT = 10 PF
COUT = 22 PF
COUT = 47 PF
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CNR/SS = CFFx = 10 nF
Figure 6. Positive PSRR vs Frequency and COUTP
80
60
40
20
0
10
COUT = 4.7 PF
COUT = 10 PF
COUT = 22 PF
COUT = 47 PF
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFx = 10 nF, COUTP = 10 µF
Figure 7. Negative PSRR vs Frequency and COUTN
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100
80
60
40
20
CFF = 0 nF
CFF = 10 nF
CFF = 100 nF
0
10
100
1k
10k
100k
Frequency (Hz)
1M
80
60
40
20
0
10
10M
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CNR/SS = 10 nF
Figure 8. Positive PSRR vs Frequency and CFFP
40
CNR/SS = 0 nF
CNR/SS = 10 nF
CNR/SS = 100 nF
CNR/SS = 1000 nF
100
1k
10k
100k
Frequency (Hz)
1M
10M
60
40
20
CNR/SS = 0 nF
CNR/SS = 10 nF
CNR/SS = 100 nF
CNR/SS = 1000 nF
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CFFx = 10 nF
Figure 10. Positive PSRR vs Frequency and CNR/SS
Figure 11. Negative PSRR vs Frequency and CNR/SS
100
Power Supply Rejection Ratio (dB)
100
Power Supply Rejection Ratio (dB)
1M
80
0
10
10M
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CFFx = 10 nF
80
60
40
20
80
60
40
20
IOUT = 150 mA
100
1k
IOUT = 150 mA
10k
100k
Frequency (Hz)
1M
10M
0
10
Figure 12. Crosstalk Positive to Negative
10
10k
100k
Frequency (Hz)
Figure 9. Negative PSRR vs Frequency and CFFN
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
60
0
10
1k
100
80
0
10
100
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFP = 10 nF
100
20
CFFN = 0 nF
CFFN = 10 nF
CFFN = 100 nF
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100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 13. Crosstalk Negative to Positive
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
10
5
VOUT
1.188 V, 20.63 PVRMS
5 V, 26.86 PVRMS
15 V, 63.88 PVRMS
Noise (PV/—Hz)
Noise (PV/—Hz)
10
5
100
1k
10k
100k
Frequency (Hz)
1M
IOUTP = 150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTN = 0 mA,
CNR/SS = CFFx = 10 nF
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTN = 0 mA, CNR/SS = 10 nF
Figure 18. Positive Spectral Noise Density vs Frequency
and CFF
1M
10M
CNR/SS
0 nF, 53.32 PVRMS
10 nF, 26.68 PVRMS
100 nF, 23.21 PVRMS
1000 nF, 23.06 PVRMS
0.2
0.1
0.05
0.02
0.01
0.005
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 17. Negative Spectral Noise Density vs Frequency
and CNR/SS
10
5
Noise (PV/—Hz)
Noise (PV/—Hz)
0.2
0.1
0.05
10k
100k
Frequency (Hz)
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTP = 0 mA, CFFx = 10 nF
CFF
0 nF, 37.77 PVRMS
10 nF, 26.86 PVRMS
100 nF, 22.95 PVRMS
2
1
0.5
1k
2
1
0.5
0.002
0.001
10
Figure 16. Positive Spectral Noise Density vs Frequency
and CNR/SS
10
5
100
10
5
10M
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTN = 0 mA, CFFx = 10 nF
0.02
0.01
0.005
Figure 15. Negative Spectral Noise Density vs Frequency
and VOUTN
Noise (PV/—Hz)
Noise (PV/—Hz)
CNR/SS
0 nF, 68.08 PVRMS
10 nF, 26.86 PVRMS
100 nF, 21.74 PVRMS
1000 nF, 21.56 PVRMS
0.2
0.1
0.05
IOUTN = –150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTP = 0 mA,
CNR/SS = CFFx = 10 nF
Figure 14. Positive Spectral Noise Density vs Frequency
and VOUTP
10
5
2
1
0.5
0.002
0.001
10
10M
VOUT
-1.188 V, 22.13 PVRMS
-5 V, 28.68 PVRMS
-15 V, 47.10 PVRMS
CFF
0 nF, 45.08 PVRMS
10 nF, 26.68 PVRMS
100 nF, 23.53 PVRMS
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTP = 0 mA, CNR/SS = 10 nF
Figure 19. Negative Spectral Noise Density vs Frequency
and CFF
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
10
5
COUT
4.7 PF, 27.33 PVRMS
10 PF, 26.86 PVRMS
22 PF, 27.47 PVRMS
47 PF, 27.64 PVRMS
2
1
0.5
Noise (PV/—Hz)
Noise (PV/—Hz)
10
5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
Noise (PV/—Hz)
Noise (PV/—Hz)
0.02
0.01
0.005
100
1k
10k
100k
Frequency (Hz)
1M
10k
100k
Frequency (Hz)
1M
10M
IOUT
1 mA, 29.72 PVRMS
10 mA, 28.42 PVRMS
50 mA, 28.59 PVRMS
100 mA, 28.47 PVRMS
150 mA, 26.68 PVRMS
0.2
0.1
0.05
0.02
0.01
0.005
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTN = –5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA,
CNR/SS = CFFx = 10 nF
Figure 22. Positive Spectral Noise Density vs Frequency
and IOUT
Figure 23. Negative Spectral Noise Density vs Frequency
and IOUT
20
25
VINP
16
VINN
VOUTP
VOUTN
12
15
8
10
4
0
-4
VINP
VOUTP
VOUTN
VINN
5
0
-5
-8
-10
-12
-15
-16
-20
-20
EN
20
Voltage (V)
Voltage (V)
1k
2
1
0.5
0.002
0.001
10
10M
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CNR/SS = CFFx = 10 nF
-25
0
20
40
60
80 100 120
Time (ms)
140
160
VOUTP = –VOUTN = 5 V, VINP = –VINN = 12 V
180
200
0
20
40
60
80 100 120
Time (ms)
140
160
180
200
VOUTP = –VOUTN = 5 V, VINP = –VINN = 15 V
Figure 24. Startup (VINP = VEN)
12
100
10
5
0.2
0.1
0.05
0.002
0.001
10
0.02
0.01
0.005
Figure 21. Negative Spectral Noise Density vs Frequency
and COUT
IOUT
1 mA, 29.88 PVRMS
10 mA, 27.07 PVRMS
50 mA, 26.66 PVRMS
100 mA, 26.77 PVRMS
150 mA, 26.86 PVRMS
2
1
0.5
0.2
0.1
0.05
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTP = 0 mA, CNR/SS = CFFx = 10 nF
Figure 20. Positive Spectral Noise Density vs Frequency
and COUT
10
5
2
1
0.5
0.002
0.001
10
10M
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V,
IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
COUT
4.7 PF, 28.43 PVRMS
10 PF, 26.68 PVRMS
22 PF, 26.67 PVRMS
47 PF, 28.70 PVRMS
Figure 25. Startup With EN
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Typical Characteristics (continued)
-4.9
-5
-4.925
10
5.055
-6
-4.95
9
5.05
-7
-4.975
8
5.045
-8
-5
7
5.04
-9
-5.025
6
5.035
-10
-5.05
5
5.03
-11
20
40
60
5.025
100
80
-12
0
20
40
60
80
Time (Ps)
VINP = 5.5 V to 10 V at 1 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = 0 mA, IOUTP = 150 mA
VINP
VOUTP 5.15
-4.925
-6
-4.95
-7
-4.975
-8
-5
-9
-5.025
-5.05
8
5
7
4.95
6
4.9
-10
5
4.85
-11
40
60
Input Voltage (V)
5.05
Output Voltage (V)
Input Voltage (V)
-5
9
20
4.8
100
80
-5.075
VINN
VOUTN
-12
0
20
40
60
Time (Ps)
VINP = 5.5 V to 10 V at 4 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = 0 mA, IOUTP = 150 mA
0.05
0
20
40
60
80
100 120
Time (Ps)
140
160
180
0
200
VINP = 6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA,
IOUTP = 1 mA to 150 mA at 1 A/µs
Figure 30. Load Transient Positive Regulator
Output Voltage (V)
Output Current (A)
Output Voltage (V)
0.1
5
160
180
-5.1
200
0
VOUTP
IOUTP -0.025
-4.925
0.15
5.025
140
-4.9
VOUTP
IOUTP
5.05
100 120
Time (Ps)
Figure 29. Line Transient Negative Regulator
0.2
5.075
80
VINN = –5.5 V to –10 V at 4 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = –150 mA, IOUTP = 0 mA
Figure 28. Line Transient Positive Regulator
5.1
-5.1
200
-4.9
5.1
0
180
-4
10
4
160
Figure 27. Line Transient Negative Regulator
5.2
11
140
VINN = –5.5 V to –10 V at 1 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = –150 mA, IOUTP = 0 mA
Figure 26. Line Transient Positive Regulator
12
100 120
Time (Ps)
Output Voltage (V)
0
-5.075
VINN
VOUTN
-4.95
-0.05
-4.975
-0.075
-5
-0.1
-5.025
-0.125
-5.05
-0.15
-5.075
-0.175
-5.1
0
20
40
60
80
100 120
Time (Ps)
140
160
180
Output Current (A)
4
Input Voltage (V)
-4
11
5.065
VINP
VOUTP 5.06
Output Voltage (V)
Input Voltage (V)
12
Output Voltage (V)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
-0.2
200
VINN = –6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA,
IOUTN = –1 mA to –150 mA at 1 A/µs
Figure 31. Load Transient Negative Regulator
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
0.01
0.0075
Output Voltage (V)
0.006
0.0045
0.003
-40qC
0qC
25qC
85qC
125qC
0.005
Output Voltage (V)
-40qC
0qC
25qC
85qC
125qC
0
-0.005
0.0015
0
-33
-0.01
-30
-27
-24
-21 -18 -15 -12
Input Voltage (V)
-9
-6
0
-3
15
30
VOUTN = 0 V
Figure 32. Negative Line Regulation
1
Accuracy (%)
Accuracy (%)
150
0.5
0
-0.5
0.5
0
-0.5
-1
-1
-1.5
-1.5
-30
-27
-24
-21 -18 -15 -12
Input Voltage (V)
-9
-6
-40qC
0qC
25qC
85qC
125qC
1.5
-2
-33
-3
-30
VOUTN = –1.19 V
-27
-24
-21
Input Voltage (V)
-18
-15
VOUTN = –15 V
Figure 34. Negative Line Regulation
Figure 35. Negative Line Regulation
2
2
-40qC
0qC
25qC
85qC
125qC
1.5
0.5
0
-0.5
-40qC
0qC
25qC
1.5
85qC
125qC
1
Accuracy (%)
1
Accuracy (%)
135
Figure 33. Negative Load Regulation
-40qC
0qC
25qC
85qC
125qC
1
0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-31
-29
-27
Input Voltage (V)
-25
-23
0
30
60
90
Output Current (mA)
120
150
VOUTN = –1.2 V, VINN = –3.3 V
VOUTN = –24 V
Figure 36. Negative Line Regulation
14
120
2
1.5
-2
-33
60
75
90 105
Output Current (mA)
VOUTN = 0 V, VINN = –3.3 V
2
-2
-33
45
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Figure 37. Negative Load Regulation
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
2
2
-40qC
0qC
25qC
1.5
85qC
125qC
0.5
0
-0.5
0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
0
30
60
90
Output Current (mA)
120
150
0
30
VOUTN = –15 V, VINN = –16 V
Figure 38. Negative Load Regulation
120
150
Figure 39. Negative Load Regulation
2
-40qC
0qC
25qC
1.5
85qC
125qC
-40qC
0qC
25qC
1.5
85qC
125qC
1
Accuracy (%)
1
Accuracy (%)
60
90
Output Current (mA)
VOUTN = –30 V, VINN = –33 V
2
0.5
0
-0.5
0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
0
30
60
90
Output Current (mA)
120
150
0
30
VOUTP = 1.188 V, VINP = 3.3 V
60
90
Output Current (mA)
120
150
VOUTP = 15 V, VINP = 16 V
Figure 40. Positive Load Regulation
Figure 41. Positive Load Regulation
2
1
-40qC
0qC
25qC
1.5
85qC
125qC
1
-40qC
0qC
25qC
85qC
125qC
0.5
Accuracy (%)
Accuracy (%)
85qC
125qC
1
Accuracy (%)
1
Accuracy (%)
-40qC
0qC
25qC
1.5
0.5
0
-0.5
0
-0.5
-1
-1.5
-1
-2
0
30
60
90
Output Current (mA)
120
150
3
6
9
12
15
18
21
Input Voltage (V)
24
27
30
33
VOUTP = 1.188 V
VOUTP = 30 V, VINP = 33 V
Figure 42. Positive Load Regulation
Figure 43. Positive Line Regulation
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
1
1
-40qC
0qC
25qC
85qC
125qC
0.5
Accuracy (%)
Accuracy (%)
0.5
0
-40qC
0qC
25qC
85qC
125qC
-0.5
0
-0.5
-1
15
18
21
24
27
Input Voltage (V)
30
-1
23
33
25.5
28
Input Voltage (V)
VOUTP = 15 V
Figure 44. Positive Line Regulation
Figure 45. Positive Line Regulation
0
Output Voltage (V)
0.75
0.5
-40qC
0qC
25qC
85qC
125qC
-0.25
Output Voltage (V)
-40qC
0qC
25qC
85qC
125qC
1
-0.5
-0.75
-1
0.25
-1.25
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
0
500
50
100
500
450
450
400
400
Dropout Voltage (mV)
500
350
300
250
200
-40qC
0qC
200 250 300 350
Output Current (mA)
400
450
500
Figure 47. Negative Regulator Current Limit
Figure 46. Positive Regulator Current Limit
150
150
VOUTN = –1.19 V
VOUTP = 1.188 V
Dropout Voltage (mV)
33
VOUTP = 24 V
1.25
25qC
85qC
350
300
250
200
150
125qC
100
-40qC
0qC
25qC
85qC
125qC
100
3
6
9
12
15
18
21
Input Voltage (V)
24
27
30
Figure 48. Positive Regulator Dropout Voltage vs
Input Voltage
16
30.5
33
3
6
9
12
15
18
21
Input Voltage (V)
24
27
30
33
Figure 49. Negative Regulator Dropout Voltage vs
Input Voltage
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
550
550
-40qC
0qC
25qC
500
-40qC
0qC
25qC
500
450
Dropout Voltage (mV)
Dropout Voltage (mV)
450
85qC
125qC
400
350
300
250
200
150
400
350
300
250
200
150
100
100
50
50
0
85qC
125qC
0
0
30
60
90
Output Current (mA)
120
150
0
30
60
90
Output Current (mA)
VINP = 3.3 V
120
150
VOUTN = –3.3 V
Figure 50. Positive Regulator Dropout Voltage vs
Output Current
Figure 51. Negative Regulator Dropout Voltage vs
Output Current
2
10
-40qC
0qC
25qC
85qC
125qC
NR/SS Current (PA)
Enable Threshold (V)
8
1.75
1.5
6
4
1.25
2
Enable Falling
1
-50
Enable Rising
0
-25
0
25
50
Temperature (qC)
75
100
125
0
0.15
0.3
Figure 52. Enable Threshold vs Temperature
0.6 0.75 0.9 1.05
NR/SS Voltage (V)
1.2
1.35
1.5
Figure 53. INR/SS vs VNR/SS
0
6
-40qC
0qC
25qC
85qC
-40qC
0qC
125qC
Discharge Current (mA)
5
Discharge Current (mA)
0.45
4
3
2
25qC
85qC
125qC
-1
-2
-3
-4
1
0
0
5
10
15
20
Output Voltage (V)
25
30
Figure 54. Positive Output Discharge Current vs
Output Voltage
35
-5
-35
-30
-25
-20
-15
-10
Output Voltage (V)
-5
0
Figure 55. Negative Output Discharge Current vs
Output Voltage
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Typical Characteristics (continued)
at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is
less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise
noted)
0
2000
-400
Supply Current (PA)
Supply Current (PA)
1600
-40qC
0qC
25qC
85qC
125qC
1200
800
400
-40qC
0qC
25qC
-800
-1200
-1600
85qC
125qC
0
-2000
0
30
60
90
Output Current (mA)
120
150
0
15
30
45
VOUTP = 1.188 V
60
75
90 105
Output Current (mA)
120
135
150
VOUTN = –1.19 V
Figure 56. Positive Supply Current vs Output Current
Figure 57. Negative Supply Current vs Output Current
2
-40qC
0qC
25qC
1.5
85qC
125qC
Accuracy (%)
1
0.5
0
-0.5
-1
-1.5
-2
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (mA)
0.8
0.9
1
VOUTN = –1.19 V
Figure 58. Buffer Accuracy vs Buffer Current
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7 Detailed Description
7.1 Overview
The TPS7A39 is an innovative linear regulator (LDO) targeted at powering the signal chain, capable of up to
±33 V on the inputs and regulating up to ±30 V on the outputs at up to 150 mA of load current. The device uses
an LDO topology that, by design, delivers ratiometric start-up tracking in most applications. The TPS7A39 has
several other features, as listed in Table 1, that simplify using the device in a variety of applications.
NOTE
Throughout this document, x is used to designate that the condition or component applies
to both the positive and negative regulators (for example, CFFx means CFFP and CFFN).
Table 1. TPS7A39 Features
VOLTAGE REGULATION
SYSTEM START-UP
INTERNAL PROTECTION
Reference input/output
Ratiometric start-up tracking
Current limit
High-PSRR output
Programmable soft-start
Fast transient response
Sequencing controls
Thermal shutdown
7.2 Functional Block Diagram
Positive LDO
INP
+
UVLO P
2.6 V
+
±
±
OUTP
Current
Limit
Bandgap
Reference
INP
Internal
Enable
FBP
350 k
NR/SS
BUF
x1
UVLO P
Internal Enable
EN
UVLO N
FBN
Current
Limit
Thermal
Shutdown
OUTN
Internal
Enable
±
+
UVLO N
- 2.6 V
+
±
INN
Negative LDO
GND
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7.3 Feature Description
7.3.1 Voltage Regulation
7.3.1.1 DC Regulation
An LDO functions as a buffered op-amp in which the input signal is the internal reference voltage (VNR/SS), as
shown in Figure 59, and in normal regulation VFBP = VNR/SS. Sharing a single reference ensures that both
channels track each other during start-up.
VNR/SS is designed to have a very low-bandwidth at the input to the error amplifier through the use of a low-pass
filter. As such, the reference can be considered as a pure dc input signal.
As Figure 60 shows, the negative LDO on the device regulates with a VFBN = 0 V and inverts the positive
reference (VBUF). This topology allows the negative regulator to regulate down to 0 V.
VOUTP = VNR/SS × (1+R1P/R2P)
VINP
To Load
NR/SS
±
+
R1P
VFBP
GND
350 k
CNR/SS
R2P
Bandgap
Reference
GND
GND
Figure 59. Simplified Positive Regulation Circuit
VOUTN = VBUF × (-R1N/R2N)
VINN
To Load
±
+
R1N
VFBN
GND
R2N
VBUF
Figure 60. Simplified Negative Regulation Circuit
7.3.1.2 AC and Transient Response
Each LDO responds quickly to a transient on the input supply (line transient) or the output current (load
transient). This LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noisefloor (Vn), the LDO approximates an ideal power supply in ac and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other
channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The noise-reduction and soft-start capacitor (CNR/SS) and feed-forward capacitor (CFFx) easily reduce the device
noise floor and improve PSRR; see the Optimizing Noise and PSRR section for more information on optimizing
the noise and PSRR performance.
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Feature Description (continued)
7.3.2 User-Settable Buffered Reference
As Figure 61 shows, the device internally generated band-gap voltage outputs at the NR/SS pin. An internal
resistor (RNR) and an external capacitor (CNR/SS) control the rise time of the voltage at the VNR/SS pin, setting the
soft-start time. This network also filters out noise from the band gap, reducing the overall noise floor of the
device.
Driving the NR/SS pin with an external source can improve the device accuracy and can reduce the device noise
floor, along with enabling the device to regulate the positive channel to voltages below the device internal
reference.
+
SW
VFBN
x1
VBUF
±
R2N*
INR/SS
RNR/SS
VBandgap
VNR/SS
+
CNR/SS*
VFBP
±
GND
Note: * Denotes external components
NOTE: * denotes external components.
Figure 61. Simplified Reference Circuit
7.3.3 Active Discharge
When either EN or UVLOx are low, the device connects a resistance from VOUTx to GND, discharging the output
capacitance. The active discharge circuit requires |VOUTx| ≥ 0.6 V (typ) to discharge the output because the NPN
pulldown has a minimum VCE requirement.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. The TPS7A39 is a bipolar device, and as such, reverse voltage conditions
(|VOUTx| ≥ |VINX| + 0.3 V) can breakdown the emitter to base diode and also cause a breakdown of the parasitic
bipolar formed in the substrate; see the Reverse Current section for more details.
When either EN or UVLOx are low, the device outputs a small amount of leakage current. The leakage current is
typically handled by the maximum R2x resistor value of 240 kΩ. However, if the device is placed in unity gain (no
R2x resistor) this leakage current causes the output to slowly rise until the discharge circuit (as shown in
Figure 62) has enough headroom to clamp the output voltage (typically ±0.6 V).
UVLOP
Internal Enable
EN
10
UVLON
GND
Figure 62. Simplified Active Discharge Circuit
7.3.4 System Start-Up Controls
In many different applications, the power-supply output must turn-on within a specific window of time because of
sequencing requirements, ensuring proper operation of the load, or to minimize the loading on the input supply.
Both LDOs start-up are well-controlled and user-adjustable through the CNR/SS capacitor, solving the demanding
requirements faced by many power-supply design engineers in a simple fashion. For start-up tracking to work
correctly. a minimum 4.7-nF CNR/SS capacitor is required. For more information on startup tracking, see the
Noise-Reduction and Soft-Start Capacitor (CNR/SS) section.
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Feature Description (continued)
7.3.4.1 Start-Up Tracking
Figure 63 shows how both regulators use a common reference, which enables start-up tracking. Using the same
reference voltage for both the positive and negative regulators ensures that the regulators start-up together in a
controlled fashion; see Figure 24 and Figure 25.
Ramps on VINx with EN = VINP that are slower than the soft-start time do not have start-up tracking. If ramps
slower than the soft-start time are used then enable should be used to start the device to ensure start-up
tracking. A small mismatch between the positive and negative internal enable thresholds means that one channel
turns on at a slightly lower input voltage than the other channel. This mismatch is typically not a problem in most
applications and is easily solved by controlling the start-up with enable. The external signal can come from the
input power supply power-good indicator, a voltage supervisor output such as the TPS3701, or from another
source.
VOUTN = VBUF × (-R1N/R2N)
VOUTP = VNR/SS × (1+R1P/R2P)
VINN
VINP
R1N
±
+
±
+
R1P
VNR/SS
GND
R2N
R2P
GND
VBUF
x1
Figure 63. Simplified Regulation Circuit
7.3.4.2 Sequencing
Figure 64 and Table 2 describe how the turn-on and turn-off times of both LDOs (respectively) is controlled by
setting the enable circuit (EN) and undervoltage lockout circuit (UVLOP and UVLON).
UVLOP
Internal
Enable
EN
UVLON
Figure 64. Simplified Turn-On Control
Table 2. Sequencing Functionality Table
POSITIVE INPUT VOLTAGE
(VINP)
NEGATIVE INPUT VOLTAGE
(VINN)
VINP ≥ VUVLOP
VINN ≤ VUVLON
VINP ≥ VUVLOP
(1)
22
ENABLE STATUS
LDO
STATUS
ACTIVE
DISCHARGE
EN = 1
On
Off
EN = 0
Off
On (1)
VINN > VUVLON
EN = don't care
Off
On (1)
VINP < VUVLOP
VINN ≤ VUVLON
EN = don't care
Off
On (1)
VINP < VUVLOP – VHYSP
VINN > VUVLON – VHYSN
EN = don't care
Off
On (1)
The active discharge remains on as long as VINx and VOUTx provide enough headroom for the discharge circuit to function.
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7.3.4.2.1 Enable (EN)
The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the
rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN
≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. In
applications that do not use the enable control, connect EN to VINP.
A slow VINx ramp directly connecting EN to VINP can cause the start-up tracking to move out of specification.
Under slow ramp conditions, use a resistor divider from VINP to ensure start-up tracking.
7.3.4.2.2 Undervoltage Lockout (UVLO) Control
The UVLO circuit responds quickly to glitches on the input supplies and attempts to disable the output of the
device if either of these rails collapse.
As a result of the fast response time of the input supply UVLO circuit, fast and short line transients well below the
input supply UVLO falling threshold (brownouts) can cause momentary glitches during the edges of the transient.
These glitches are typical in most LDOs. The local input capacitance prevents severe brown-outs in most
applications; see the Undervoltage Lockout (UVLOx) Control section for more details. Fast line transients can
cause the outputs to momentarily shut off, and can be mitigated through using the recommended 10-µF input
capacitor. If this becomes a problem in the system, increasing the input capacitance prevents these glitches from
occurring.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as |VINx(min)|
• The input voltage is greater than the nominal output voltage added to the dropout voltage
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
• The output current is less than the current limit
• The device junction temperature is less than TSD
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturation
and no longer controls the current through the LDO. Line or load transients in dropout can result in large output
voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold
• The device junction temperature is greater than the thermal shutdown temperature
Table 3 shows the conditions that lead to the different modes of operation.
Table 3. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
IOUT
TJ
Normal mode
|VINx| > |VOUT(nom)| + |VDOx| and
|VINx| > |VINx(min)|
VEN > VIH
|IOUTx| < |ILIMx|
T J < 125°C
Dropout mode
|VINx(min)| < |VINx| < |VOUTx(nom)| +
|VDOx|
VEN > VIH
—
TJ < 125°C
—
VEN < VIL
—
TJ > TSD
Disabled mode
(any true condition disables the device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement the LDO to achieve a reliable design.
8.1.1 Setting the Output Voltages on Adjustable Devices
Figure 65 shows that each LDO resistor feedback network sets its output voltage. The positive LDO output
voltage range is VNR/SS to 30 V and the negative LDO output voltage range is 0 V to –30 V.
OUTP
CINP
COUTP
INP
CFFP
R1P
FBP
R2P
CNR/SS
NR/SS
TPS7A39
3mm x 3mm
BUF
R2N
FBN
EN
CINN
R1N
OUTN
INN
CFFN
COUTN
GND
Figure 65. Adjustable Operation
Equation 1 relates the values of R1P and R2P to VOUTP(NOM) and VNR/SS to set the positive output voltage.
Equation 2 relates the values of R1N and R2N to VOUTN(NOM) and VNR/SS to set the negative output voltage.
The positive LDO is configured as a noninverting op amp, whereas the negative LDO is an inverting op amp.
VOUTP = VNR/SS × (1 + R1P / R2P)
VOUTN = VNR/SS × (–R1N / R2N)
(1)
(2)
Substituting VNR/SS with VFBP on the positive channel and VNR/SS with VBUF on the negative channel gives a more
accurate relationship.
Equation 3 and Equation 2 are rearranged versions of Equation 1 and Equation 2, with the above substitutions
made.
R1P = (VOUTP / VFBP – 1) × R2P
R1N = –(VOUTN × R2P) / VBUF
(3)
(4)
The minimum bias current through both feedback networks is 5 µA to ensure accuracy.
For even tighter accuracy, take into account the input bias current into the error amplifiers (IFBP and IFBN) and use
0.1% resistors. Overriding the internal reference with a high accuracy external reference can also improve the
accuracy of the device.
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Application Information (continued)
Table 4 and Table 5 show the resistor combinations for several common output voltages using commercially
available, 1% tolerance resistors.
Table 4. Recommended Feedback-Resistor Values for the Positive LDO
(1)
FEEDBACK RESISTOR VALUES (1)
TARGETED OUTPUT
VOLTAGE (V)
R1P (kΩ)
R2P (kΩ)
CALCULATED OUTPUT
VOLTAGE (V)
1.5
2.67
10.0
1.50
1.8
5.23
10.0
1.80
2.5
11.0
10.0
2.49
3.0
15.4
10.0
3.00
3.3
17.8
10.0
3.29
5.0
32.4
10.0
5.02
9.0
66.5
10.0
9.07
12.0
90.9
10.0
12.0
15.0
115
10.0
14.8
24.0
191
10.0
23.8
30.0
243
10.0
29.8
R1P is connected from OUTP to FBP, R2P is connected from FBP to GND; see the Setting the Output Voltages on Adjustable Devices
section.
Table 5. Recommended Feedback-Resistor Values for the Negative LDO
(1)
FEEDBACK RESISTOR VALUES (1)
TARGETED OUTPUT
VOLTAGE (V)
R1N (kΩ)
R2N (kΩ)
CALCULATED OUTPUT
VOLTAGE (V)
-0.3
2.55
10.0
-0.303
-1.5
12.7
10.0
-1.51
-1.8
15.0
10.0
-1.78
-2.5
21.0
10.0
-2.49
-3.0
25.5
10.0
-3.03
-3.3
28.0
10.0
-3.33
-5.0
42.2
10.0
-5.04
-9.0
75.0
10.0
-8.91
-12.0
100
10.0
-11.9
-15.0
127
10.0
-15.1
-24.0
200
10.0
-23.8
-30.0
255
10.0
-30.3
R1N is connected from OUTN to FBN, R2N is connected from FBN to BUF; see the Setting the Output Voltages on Adjustable Devices
section.
8.1.2 Capacitor Recommendations
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output pins. The device is also designed to be stable with aluminum polymer and tantalum polymer
capacitors with ESR < 75 mΩ.
Electrolytic capacitors (along with higher ESR polymer capacitors) can also be used if capacitors (meeting the
minimum capacitance and ESR requirements ) are used in parallel.
Take the effective ESR for stability when the impedance of the capacitor is at its minimum. At the minimum level,
the capacitance and parasitic inductance cancel each other and provides the DC ESR.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good
capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large
variations in capacitance.
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Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for an effective capacitance derating of approximately 50%, but at higher VIN and
VOUT conditions (that is, VIN = 5.5 V to VOUT = 5.0 V) the derating can be greater than 50% and must be taken
into consideration.
For high performance applications polymer capacitors are ideal as they do not experience the large deratings of
ceramic capacitors.
8.1.3 Input and Output Capacitor (CINx and COUTx)
The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (2.2 µF or
greater of effective capacitance) at each input and output.
Locate the input and output capacitors as near as practical to the respective input and output pins to minimize
the trace inductance from the capacitor to the device. If the LDO is used to produce low output voltages (below
5 V), a 4.7-µF output capacitor can be used. If a 4.7-µF output capacitor is used, be sure to account for the
derating of the capacitors during design.
Large, fast line transients on the input supplies can cause the device output to momentarily turn off. Typically
these transients do not occur in most applications, but when these transients do occur use a larger input
capacitor to slow down the line transient. If the system has input line transients that are faster than 0.5 V/µs,
increase the input capacitance.
8.1.4 Feed-Forward Capacitor (CFFx)
Although a feed-forward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a
10-nF external CFFx capacitor optimizes the transient, noise, and PSRR performance. The maximum
recommended value for CFFx is 100 nF.
A larger CFFx can dominate the start-up time set by CNR/SS, for more information see the Pros and Cons of Using
a Feed-Forward Capacitor with a Low Dropout Regulator application report.
8.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
Although a noise-reduction and soft-start capacitor (CNR/SS) from the NR/SS pin to GND is not required, CNR/SS is
highly recommended to control the start-up time and reduce the noise-floor of the device. For start-up tracking to
function correctly, a minimum 4.7-nF capacitor is required. As the time constant formed by the feedback resistors
and feed-forward capacitors increases, the value of the CNR/SS capacitor must also be increased for startup
tracking to work correctly. To figure out how to calculate the time constant of the feedback network see the Pros
and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.
8.1.6 Buffered Reference Voltage
The voltage at the NR/SS pin, whether driven internally or externally, is buffered with a high-bandwidth, low-noise
op amp. The BUF pin can be used as a voltage reference in many signal chain applications.
8.1.7 Overriding Internal Reference
The internal reference of the LDO can be overridden using an external source to increase the accuracy of the
LDO and lower the output noise. To override the internal reference connect the external source to the NR/SS pin
of the LDO. In order to overdrive the internal reference the external source must be able to source or sink 100 µA
or greater.
The internal reference achieves a 2% accuracy from –40°C to +125°C; using an external reference can help
achieve better accuracy over temperature.
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8.1.8 Start-Up
8.1.8.1 Soft-Start Control (NR/SS)
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an
external capacitor (CNR/SS). This soft-start eliminates power-up initialization problems.
The output voltage (VOUTx) rises proportionally to VNR/SS during start-up. As such, the time required for VNR/SS to
reach its nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS),
and the internal reference (VNR/SS). Equation 5 calculates the approximate soft-start ramp time (tSS):
tSS = RNR/SS × CNR/SS × ln [(VNR/SS + INR/SS × RNR/SS) / (INR/SS×RNR/SS)]
(5)
Values for the soft-start charging currents, RNR/SS, and the device internal CNR/SS are provided in the table.
8.1.8.1.1 In-Rush Current
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, the in-rush current
can be estimated by Equation 6:
VOUTx(t)
COUTx ´ dVOUTx(t)
IOUTx(t) =
+
RLOAD
dt
where:
•
•
•
VOUTx(t) is the instantaneous output voltage of the turn-on ramp
dVOUTx(t) / dt is the slope of the VOUTx ramp
RLOAD is the resistive load impedance
(6)
8.1.8.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum
operational voltage range, and ensures that the device properly shuts down when the input supply collapses.
Figure 66 and Table 6 explain the UVLOx circuit response to various input voltage events, assuming VEN ≥
VIH(EN).
The positive and negative UVLO circuits are internally ANDed together. As such, if either supply collapses, both
outputs turn-off and VNR/SS is pulled low internally.
UVLOx Rising Threshold
UVLOx Hysteresis
VINx
C
VOUTx
tAt
tBt
tDt
tEt
tFt
tGt
Figure 66. Typical UVLOx Operation
28
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Table 6. Typical UVLOx Operation Description
REGION
EVENT
VOUTx STATUS
A
Turn-on, |VINx| ≤ |VUVLOx|
0
Start-up
COMMENT
B
Regulation
1
Regulates to target VOUTx
C
Brownout,|VINx| ≥ |VUVLOx –
VHYSx|
1
The output can fall out of regulation but the device is still enabled
D
Regulation
1
Regulates to target VOUTx
E
Brownout, |VINx| < |VUVLOx –
VHYSx|
0
The device is disabled and the output falls because of the load and
active discharge circuit. The device is reenabled when the UVLOx
rising threshold is reached by the input voltage and a normal startup then follows.
F
Regulation
1
Regulates to target VOUTx
G
Turn-off, |VINx| < |VUVLOx –
VHYSx|
0
The output falls because of the load and active discharge circuit
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During
this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time;
however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of
the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs
are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall
time of the input supply when operating near the minimum VINx.
8.1.9 AC and Transient Performance
LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output
isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop
gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The
output noise is primarily a result of the band-gap reference and error amplifier noise.
8.1.9.1
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency
spectrum (usually 10 Hz to 10 MHz). Equation 7 gives the PSRR calculation as a function of frequency for the
input signal [VINx(f)] and output signal [VOUTx(f)].
§ V (f ) ·
PSRR (dB) 20 Log10 ¨ INx
¸
© VOUTx (f ) ¹
(7)
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for
convenience.
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Power-Supply Rejection-Ratio (dB)
Figure 67 shows a simplified diagram of PSRR versus frequency.
Bandgap
Bandgap RC
Filter
Error Amplifier, Flat-Gain
Region
Error Amplifier,
Gain Roll-off
Output Capacitor
|ZCOUT| Decreasing
Output Capacitor
|ZCOUT| Increasing
10 Hz ± 1 MHz
Sub 10 Hz
100 kHz +
Frequency (Hz)
Figure 67. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply
voltages that exhibit ultra-low noise and ripple to sensitive system components.
8.1.9.2 Channel-to-Channel Output Isolation and Crosstalk
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting
the other output. This attenuation appears in load transient tests on the other output; however, to numerically
quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See the Layout Guidelines section on how to
best optimize the isolation performance.
8.1.9.3 Output Voltage Noise
The TPS7A39 is designed for system applications where minimizing noise on the power-supply rail is critical to
system performance. For example, the TPS7A39 can be used in a phase-locked loop (PLL)-based clocking
circuit that can be used for minimum phase noise, or in test and measurement systems where even small powersupply noise fluctuations reduce system dynamic range.
fN
1/
oi
se
Wide-band Noise
N
oi
se
n
R
ol
Integrated Noise
From Bandgap and Error Amplifier
ai
G
ff
l -O
Output Voltage Noise Density (nV/¥+])
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower
frequencies as a function of 1/f). Figure 68 shows a simplified output voltage noise density plot versus frequency.
Measurement Noise Floor
Frequency (Hz)
Figure 68. Output Voltage Noise Diagram
30
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For further details, see the How to Measure LDO Noise white paper.
8.1.9.4 Optimizing Noise and PSRR
Table 7 describes how the ultra-low noise floor and PSRR of the device can be improved in several ways.
Table 7. Effect of Various Parameters on AC Performance (1) (2)
NOISE
(1)
(2)
PSRR
PARAMETER
LOWFREQUENCY
MIDFREQUENCY
HIGHFREQUENCY
LOWFREQUENCY
CNR/SS
+++
No effect
No effect
CFFx
++
+++
+
MIDFREQUENCY
HIGHFREQUENCY
+++
+
No effect
++
+++
+
+++
COUTx
No effect
+
+++
No effect
+
|VINx| – |VOUTx|
+
+
+
+++
+++
++
PCB layout
++
++
+
+
+++
+++
The number of +s indicates the improvement in noise or PSRR performance by increasing the parameter value.
Shaded cells indicate the easiest improvement to noise or PSRR performance.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the
output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with
Equation 8. The effect of the CNR/SS capacitor increases when VOUTx(NOM) increases because the noise from the
reference is gained up when the output voltage increases. For low-noise applications, a 10-nF to 1-µF CNR/SS is
recommended.
fcutoff = 1 / (2 × π × RNR/SS × CNR/SS)
(8)
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feedforward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing
out the loop bandwidth, thus improving mid-band PSRR.
A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing
the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the
internal circuits. However, a high power dissipation across the die increases the output noise because of the
increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and
isolating VOUTx at high frequencies.
8.1.9.5
Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions illustrated in
Figure 69 are broken down in this section and are described in Table 8. Regions A, E, and H are where the
output voltage is in steady-state. Increasing the output capacitance improves the transient response (less dip);
however, the transient takes longer to recover when using a large output capacitor.
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VOUTx
B
F
A
C
D
E
G
H
IOUTx
Figure 69. Load Transient Waveform
Table 8. Load Transient Waveform Description
REGION
DESCRIPTION
COMMENT
A
Regulation
B
Output current ramping
Regulation
C
LDO responding to transient
Recovery from the dip results from the LDO increasing its sourcing current, and leads
to output voltage regulation.
D
Reaching thermal equilibrium
At high load currents the LDO takes some time to heat up. During this time the output
voltage changes slightly.
E
Regulation
F
Output current ramping
G
LDO responding to transient
H
Regulation
Initial voltage dip is a result of the depletion of the output capacitor charge.
Regulation
Initial voltage rise results from the LDO sourcing a large current, and leads to the
output capacitor charge to increase.
Recovery from the rise results from the LDO decreasing its sourcing current in
combination with the load discharging the output capacitor.
Regulation
8.1.10 DC Performance
8.1.10.1 Output Voltage Accuracy (VOUTx)
The device features an output voltage accuracy that includes the errors introduced by the internal reference, load
regulation, line regulation, process variation, and operating temperature as specified by the table. Output voltage
accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage
stated as a percent (for very low output voltages this specification is in mV).
8.1.10.2
Dropout Voltage (VDO)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (|VDO| = |VINx| – |VOUTx|) that is required for regulation. When VINx drops below the required VDOx
for the given load current, the device functions as a resistive switch and does not regulate output voltage.
Dropout voltage is proportional to the output current because the device is operating as a resistive switch.
8.1.11 Reverse Current
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the substrate of the device instead of the normal conducting
channel of the pass element. This current flow, at high enough magnitudes, degrades long-term reliability of the
device resulting from risks of electromigration and excess heat being dissipated across the device.
32
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Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUTP > VINP + 0.3 V and VOUTN < VINN – 0.3 V:
• If the device has a large COUTx and the input supply collapses quickly with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
If excessive reverse current flow is expected in the application, then external protection must be used to protect
the device. Figure 70 shows one approach of protecting the device.
Schottky Diode
INP
CINP
OUTP
Device
COUTP
GND
Figure 70. Example Circuit for Reverse Current Protection Using a Schottky Diode On Positive Rail
8.1.12 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 9 to approximate PD:
PD = (VINP – VOUTP) × IOUTP + (|VINN – VOUTN|) × |IOUTN|
(9)
Careful selection of the system voltage rails minimizes power dissipation and improves system efficiency. Proper
selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device
allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 10, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (θJA) of the combined PCB, device package, and the temperature of the ambient air
(TA).
TJ = TA + θJA × PD
(10)
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a welldesigned thermal layout, θJA is actually the sum of the WSON package junction-to-case (bottom) thermal
resistance (θJCbot) plus the thermal resistance contribution by the PCB copper.
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8.1.12.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the Electrical Characteristics table and are used in accordance with Equation 11.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 9
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(11)
8.2 Typical Applications
8.2.1 Design 1: Single-Ended to Differential Isolated Supply
TP1
OUTP
GND
D2
INP
Diode2
R1P
Diode1
+5V
EN
SN6505B
VINP
VCC
FBP
R2P
10 …F 0.1 …F
Diode3
D1
Diode4
NR/SS
TPS7A39
3mm x 3mm
10 nF
BUF
R2N
CLK
10 nF COUTP
TP2
10 …F 0.1 …F
FBN
To
Signal
R1N
10 …F 0.1 …F
EN
10 nF
OUTN
INN
COUTN
GND
Figure 71. Single-Ended to Differential Isolated Supply Schematic
8.2.1.1 Design Requirements
Table 9. Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Input supply
Must operate off of 5-V input
Output supply
Must have a 5-V and –5-V output
Positive output
current
Capable of sourcing 50 mA on positive output
50 mA (sourcing)
Negative output
current
Capable of sinking 50 mA on negative output
50 mA (sinking)
Isolation from 5-V
supply
Must be isolated from input supply
Efficiency
Must have > 80% efficiency at 100 mA (1)
(1)
34
5-V input supply
±5-V output, ±2% accuracy
Isolated through center tapped transformer
85% efficiency when IOUTN = –50 mA and IOUTP =
50 mA
|IOUTN| = IOUTP = 50 mA.
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switcher Choice
This design incorporates a push-pull driver for center-tapped transformers that takes a single-ended supply and
converts the supply to an isolated split rail design. The SN6505B provides a simple small-form factor isolated
supply. The input voltage of the SN6505B can vary from 2.25 V to 5 V, which allows for use with a wide range of
input supplies. The output voltage can be adjusted through the turns ratio of the transformer. Based on the
choice of the transformer this design can be used to create output voltages from ±3.3 V to ±15 V. In this design
the SN6505B was paired with the 750315371 center-tapped transformer from Wurth Electronics™. This
transformer has a turns ratio of 1:1.1 and an isolation rating of 2500 VRMS (the total system isolation was never
tested).
8.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer
To create the isolated supply, the SN6505B uses a center-tapped transformer. A full bridge rectifier and
capacitors are required to regulate the signal before reaching the LDO because of the alternating nature of the
input signal. TI recommends having a fast switching and low forward voltage diode to improve efficiency because
of how fast the SN6505 switches; Schottky diodes work well. Figure 73 shows the switching nodes of the
SN6505 D1 and D2 and also shows where the transformer connects to the full bridge rectifier TP1 and TP2.
Figure 73 shows the switching waveforms across the rectifier diodes.
n
VOUT+ = n·VIN
VIN
VOUT- = n·VIN
Figure 72. Bridge Rectifier With Center-Tapped Secondary Enables Bipolar Outputs
8.2.1.2.3 Total Solution Efficiency
Equation 12 shows how the efficiency of the system can be measured by taking the output power and dividing by
the input power. IOUTP = |IOUTN| = IOUT / 2 because this system has two output rails to simplify the efficiency
measurement. When the necessary parameters are measured, and by using Equation 12, the overall system
efficiency can be plotted as in Figure 74. Figure 74 shows the overall system efficiency for this design, at the
maximum output current of 100 mA (IOUTP = 50 mA, IOUTN = –50 mA) the efficiency of the system is 85%.
η = (IOUTP × VOUTP + IOUTN × VOUTN) / (IIN × VIN)
(12)
8.2.1.2.4 Feedback Resistor Selection
Equation 13 and Equation 14 calculate the values of the feedback resistors.
VOUTP = VFBP × (1 + R1P / R2P)
VOUTN = VBUF × (–R1N / R2N)
(13)
(14)
For this design the recommended 10-kΩ resistors are used for R2P and R2N. R1P and R1N can be calculated by
substituting R2P and R2N into Equation 15 and Equation 16 because R2P and R2N are already selected
R1P = [(VOUTP / VFBP) – 1] × R2P = [(5 V / 1.188 V) – 1] × 10 kΩ = 32.2 kΩ
R1N = –VOUTN × R2N / VBUF = –(–5 V) × 10 kΩ / 1.19 V = 42 kΩ
(15)
(16)
After solving for Equation 15 and Equation 16, the closest one percent resistors are selected, R1N = 42.2 kΩ and
R1P = 32.4 kΩ.
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8.2.1.3 Application Curves
100
20
D1
TP1
TP2
90
12
80
8
70
Efficiency (%)
Voltage (V)
16
D2
4
0
-4
60
50
40
-8
30
-12
20
-16
10
-20
0
0
5
10
15
20
25
30
Time (Ps)
35
40
45
50
0
10
20
30
40
50
60
IOUT (mA)
70
80
90
100
IOUT = IOUTP + |IOUTN|, IOUTP = |IOUTN|
Figure 73. Switching Node of the SN6505B
Figure 74. Efficiency vs Output Current
10
VCC
8
VINP
VOUTP
VINN
10
5
VOUTN
6
Noise (PV/—Hz)
Voltage (V)
4
2
0
-2
-4
-6
-8
-10
0
10
20
30
40
50
60
Time (ms)
70
80
90
100
IOUT = 50 mA
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
10k
100k
Frequency (Hz)
1M
10M
Figure 76. OUTP Noise
Figure 75. System Startup
10
5
Noise (PV/—Hz)
1k
IOUT = 50 mA
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 77. OUTN Noise
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8.2.2 Design 2: Getting the Full Range of a SAR ADC
OUTP
COUTP
INP
CINP
VOUTP = 5.2 V
CFFP
R1P
6V
+
FBP
±
R2P
NR/SS
CNR/SS
TPS7A39
3mm x 3mm
BUF
R1N
3.3 V
+
FBN
±
EN
R2N
OUTN
INN
CINN
CFFN
COUTN
VOUTN = -0.2 V
GND
1 nF
1 kŸ
1 kŸ
Positive
Differential Input
VOUTP
±
2.2 Ÿ
OPA625
+
+
VOUTN
AINP
10 nF
Vin
±
ADC
OPA625_CM
10 nF
+
VOUTP
10 nF
OPA625
Negative
Differential Input
1 kŸ
±
VOUTN
AINN
2.2 Ÿ
1 kŸ
1 nF
Figure 78. Creating Power Rails for an Analog Front-End of an ADC
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8.2.2.1 Design Requirements
A common problem in analog-to-digital converters (ADCs) is that as the input signal approaches the edge of the
range of the ADC, the signal begins to become distorted. Often times this is not because of a limitation of the
ADC, but is a result of the analog front-end (AFE). In the AFE, the signal begins to approach the rails of the op
amp and the signal begins to lose linearity and becomes distorted. This distortion is because when the rail-to-rail
op amp begins to enter the nonlinear region of operation within 100 mV of the rail, the signal-to-noise ratio (SNR)
starts to degrade and the total harmonic distortion (THD) of the ADC increases. To prevent the op amp from
exiting the linear region of operation, the design must use a power supply that can generate rails 200 mV above
and below the input range of the ADC.
8.2.2.2 Detailed Design Procedure
In this design, the ADS8900B is used as the ADC. This ADC features a differential input, so from a 5-V reference
the ADC is able to encode values between ±5 V. In many applications, single-supply op amps are powered with
rails from 0 V to 5 V, which causes the input signal to become distorted when the full range signal is applied. The
FFT of a 10-VPP (peak-to-peak) sine wave using a single 5-V rail to bias the amplifiers is illustrated in Figure 79.
In this test the SNR was calculated to be 54.89 dB and the THD was calculated to be –40.68 dB.
There is a simple solution to improve the SNR and THD of the ADC: bias the amplifiers in the analog front end
with a 5.2-V rail and a –0.2-V rail. Using these rails allows the amplifier to operate in the linear region in the 0-V
to 5-V range needed by the ADC. The FFT of a 10-VPP sine wave using a 5.2-V rail and a –0.2-V rail is illustrated
in Figure 80. In this test the SNR was calculated to be 102.535 dB and the THD was calculated to be
–121.66 dB. Using –0.2-V and 5.2-V rail voltages still allows for common 5-V (5.5 V max) op amps to be used in
the design.
8.2.2.3 Detailed Design Description
8.2.2.3.1 Regulation of –0.2 V
The TPS7A39 has an innovative feature of regulating the negative rail down to zero volts. This regulation is
achieved by using an inverting amplifier and using the positive-buffered reference as the input signal to the
amplifier. Regulating to –0.2 V eliminates the nonlinearity and distortion present when using the full rail range of
the amplifiers.
8.2.2.3.2 Feedback Resistor Selection
Use Equation 17 and Equation 18 to calculate the values of the feedback resistors:
VOUTP = VFBP × (1 + R1P / R2P)
VOUTN = VBUF × (–R1N / R2N)
(17)
(18)
For this design the recommended 10-kΩ resistors are used for R2P and R2N. R1P and R1N can be calculated by
substituting R2P and R2N into Equation 19 and Equation 20 because R2P and R2N are already selected.
R1P = [(VOUTP / VFBP) – 1] × R2P = [(5.2 V / 1.188 V) – 1] × 10 kΩ = 33.8 kΩ
R1N = –VOUTN × R2N / VBUF = –(–5 V) × 10 kΩ / 1.19 V = 1.68 kΩ
(19)
(20)
After solving for Equation 19 and Equation 20, the closest one percent resistors are selected, R1N = 1.69 kΩ and
R1P = 34 kΩ.
38
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0
0
-20
-20
-40
-40
-60
-60
Amplitude (dBC)
Amplitude (dBC)
8.2.2.4 Application Curves
-80
-100
-120
-140
-80
-100
-120
-140
-160
-160
-180
-180
-200
100
1k
10k
100k
-200
100
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
fIN = 1 kHz, VPP = 10.0 V
fIN = 1 kHz, VPP = 10.0 V
Figure 79. FFT Using 5-V and 0-V Supply Rails
Figure 80. FFT Using 5.2-V and –0.2-V Supply Rails
9 Power-Supply Recommendations
The input supply for the LDO must be within the recommended operating conditions. The input voltage must
provide adequate headroom in order for the device to have a regulated output. Place the 10-µF input capacitors
as close to the device as possible. If the input supply is noisy, additional input capacitors can help improve the
output noise performance.
10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with capacitors.
Tie the GND pin directly to the thermal pad under the device. The thermal pad must be connected to any internal
PCB ground planes using multiple vias directly under the device.
Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the
regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because these circuits can impact system performance
negatively, and even cause instability.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane star connected only at
the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to
the GND pin of the device.
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SBVS263A – JULY 2017 – REVISED SEPTEMBER 2017
www.ti.com
GND
FBN
INN
BUF
Thermal Pad
INP
FBP
NR/
SS
OUTP
EN
10.2 Layout Example
OUTN
Figure 81. Layout Example for Adjustable Option
10.3 Package Mounting
Solder pad footprint recommendations for the TPS7A39 are available at the end of this document and at
www.ti.com.
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SBVS263A – JULY 2017 – REVISED SEPTEMBER 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A39.
The TPS7A39EVM-865 evaluation module (and related user guide) can be requested at the Texas Instruments
website through the product folder or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A39 is available through the product folder under Tools
& Software.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS3701 36-V Window Comparator with Internal Reference for Over- and Undervoltage Detection
• SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
• ADS890xB 20-Bit, High-Speed SAR ADCs With Integrated Reference Buffer, and Enhanced Performance
Features
• Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
• Using New Thermal Metrics
• TPS7A39EVM-865 User's Guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
Wurth Electronics is a trademark of Würth Elektronik GmbH and Co.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
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Product Folder Links: TPS7A39
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A3901DSCR
ACTIVE
WSON
DSC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A3901
TPS7A3901DSCT
ACTIVE
WSON
DSC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A3901
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7A3901DSCR
WSON
DSC
10
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
TPS7A3901DSCT
WSON
DSC
10
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A3901DSCR
WSON
DSC
10
3000
370.0
355.0
55.0
TPS7A3901DSCT
WSON
DSC
10
250
195.0
200.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSC0010J
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8
0.7
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4221826/D 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSC0010J
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221826/D 08/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSC0010J
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4221826/D 08/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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