Texas Instruments | TPS25200 5-V eFuse With Precision Adjustable Current Limit and Overvoltage Clamp (Rev. C) | Datasheet | Texas Instruments TPS25200 5-V eFuse With Precision Adjustable Current Limit and Overvoltage Clamp (Rev. C) Datasheet

Texas Instruments TPS25200 5-V eFuse With Precision Adjustable Current Limit and Overvoltage Clamp (Rev. C) Datasheet
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TPS25200
SLVSCJ0C – MARCH 2014 – REVISED SEPTEMBER 2017
TPS25200 5-V eFuse With Precision Adjustable Current Limit and Overvoltage Clamp
1 Features
3 Description
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The TPS25200 is a 5-V eFuse with precision current
limit and overvoltage clamp. The device provides
robust protection for load and source during
overvoltage and overcurrent events.
1
2.5-V to 6.5-V Operation
Input Withstands Up to 20 V
7.6-V Input Overvoltage Shutoff
5.25-V to 5.55-V Fixed Overvoltge Clamp
0.6-μs Overvoltage Lockout Response
3.5-μs Short Circuit Response
Integrated 60-mΩ High-Side MOSFET
Up to 2.5 A Continuous Load Current
±6% Current-Limit Accuracy at 2.9 A
Reverse Current Blocking While Disabled
Built-in Soft Start
Pin-to-Pin Compatible with TPS2553
UL 2367 Recognized
– File No. 169910
– RILIM ≥ 33 kΩ (3.12 A Maximum)
The TPS25200 is an intelligent protected load switch
with VIN tolerant to 20 V. In the event that an incorrect
voltage is applied at IN, the output clamps to 5.4 V to
protect the load. If the voltage at IN exceeds 7.6 V,
the device disconnects the load to prevent damage to
the device and/or load.
The TPS25200 has an internal 60-mΩ power switch
and is intended for protecting source, device, and
load under a variety of abnormal conditions. The
device provides up to 2.5 A of continuous load
current. Current limit is programmable from 85 mA to
2.9 A with a single resistor to ground. During overload
events output current is limited to the level set by
RILIM. If a persistent overload occurs the device
eventually goes into thermal shutoff to prevent
damage to the TPS25200.
2 Applications
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USB Power Switch
USB Slave Devices
Cell/Smart Phones
3G, 4G Wireless Data-card
Solid State Drives (SSD)
3-V or 5-V Adapter Powered Devices
Device Information
ORDER NUMBER
TPS25200
PACKAGE
BODY SIZE
WSON (6)
2.00 mm × 2.00 mm
VOUT vs VIN
Simplified Schematic
VIO
VOUT (V)
Over Voltage Clamp
(OVC)
300 kΩ
Fault signal
TPS25200DRV
5.4 V
VIN
6
300 kΩ
IN
OUT
1
ILIM
2
FAULT
3
VOUT
CIN
5 GND
4
EN
PowerPAD
Turn Off
MOSFET
C OUT
R ILIM
UVLO(2.35V)
OVLO(7.6V)
20 V
VIN (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25200
SLVSCJ0C – MARCH 2014 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision A (March 2014) to Revision B
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Added UL certification status to Features section ................................................................................................................. 1
Changes from Revision B (February 2017) to Revision C
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Page
Page
Changed Package from SON to WSON in the Device Information table .............................................................................. 1
Changes from Original (March 2014) to Revision A
Page
•
Changed the toff TYP value From: 0.24 ms To: 0.22 ms ....................................................................................................... 6
•
Added condition: VEN = VIN = 0 V to Figure 3 ......................................................................................................................... 7
•
Changed Figure 8 graph title From: Discharge Resistance To: VIN ....................................................................................... 7
•
Changed Equation 4 From = 2470 mA to = 2479 mA.......................................................................................................... 15
2
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5 Pin Configuration and Functions
DRV Package
6-Pin SOT
Top View
OUT
ILIM
1
FAULT
3
2
Power
PAD
6
IN
5
GND
EN
4
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Logic-level control input. When is driven high, the power switch is enabled. When it is driven low,
turn power switch off. This pin cannot be left floating and it must be limited below the absolute
maximum rating if tied to VIN
FAULT
3
O
Active-low open-drain output, asserted during overcurrent, overvoltage or overtemperature.
Connect a pull up resistor to the logic I/O voltage
GND
5
—
Ground connection; connect externally to PowerPAD
ILIM
2
O
External resistor used to set current-limit threshold; Recommended 33 kΩ ≤ RILIM ≤ 1100 kΩ
IN
6
I
Input voltage; connect a 0.1-μF or greater ceramic capacitor from IN to GND as close to the IC as
possible
OUT
1
O
Protected power switch VOUT
PAD
—
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PowerPAD to GND terminal externally
PowerPAD™
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
MIN
MAX
UNIT
Voltage on IN
–0.3
20
V
Voltage on OUT, EN, ILIM, FAULT
–0.3
7
V
–7
20
V
Voltage from IN to OUT
IO
Continuous output current
Thermally Limited
Continuous FAULT output sink current
25
mA
Continuous ILIM output source current
150
µA
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
(1)
Internally limited
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolutemaximum- rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
MIN
MAX
2.5
6.5
Enable terminal voltage
0
6.5
V
Continuous FAULT sink current
0
10
mA
2.5
A
33
1100
kΩ
–40
125
°C
VIN
Input voltage of IN
VEN
IFAULT
IOUT
Continuous output current of OUT
RILIM
Current-limit set resistors
TJ
Operating junction temperature
UNIT
V
6.4 Thermal Information
TPS25200
THERMAL METRIC (1)
DRV (SOT)
UNIT
6 PINS
θJA
Junction-to-ambient thermal resistance
66.5
°C/W
θJCtop
Junction-to-case (top) thermal resistance
83.4
°C/W
θJB
Junction-to-board thermal resistance
36.1
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
36.5
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
7.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Conditions are –40°C ≤ TJ ≤ +125°C and 2.5 V ≤ VIN ≤ 6.5 V. VEN = VIN, RILIM = 33 kΩ. Positive current into terminals. Typical
value is at 25°C. All voltages are with respect to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C
60
70
–40°C ≤ TJ ≤ +85°C
60
90
–40°C ≤ TJ ≤ +125°C
60
99
UNIT
POWER SWITCH
rDS(on)
IN–OUT resistance (1)
2.5 V ≤ VIN ≤ 5 V,
IOUT = 2.5 A
mΩ
ENABLE INPUT EN
EN terminal turnon threshold
Input rising
EN terminal turnoff threshold
Input falling
1.9
0.6
IEN
Leakage current
V
330 (2)
Hyesteresis
VEN = 0 V or 5.5 V
V
–2
mV
2
µA
480
625
Ω
DISCHARGE
RDCHG
OUT discharge resistance
VOUT = 5 V, VEN = 0 V
CURRENT LIMIT
IOS
Current - limit, See Figure 12
RILIM = 33 kΩ
2773
2952
3127
RILIM = 40.2 kΩ
2270
2423
2570
RILIM = 56 kΩ
1620
1740
1860
RILIM = 80.6 kΩ
1110
1206
1300
RILIM = 150 kΩ
590
647
710
RILIM = 1100 kΩ
40
83
130
IN rising
6.8
7.6
8.45
mA
OVERVOLTAGE LOCKOUT, IN
V(OVLO)
IN rising OVLO threshold voltage
70 (2)
Hysteresis
V
mV
VOLTAGE CLAMP, OUT
V(OVC)
OUT clamp voltage threshold
CL = 1 µF, RL = 100 Ω, VIN = 6.5 V
5.25
5.4
5.55
0.8
5
1000
1700
RILIM = 33 kΩ
V
SUPPLY CURRENT
VEN = 0 V, VIN = 5 V
IIN(off)
Supply current, low-level output
IIN(on)
Supply current, high-level output
VIN = 5 V,
No load on OUT
143
200
RILIM = 150 kΩ
134
190
IREV
Reverse leakage current
VOUT = 6.5V, VIN = VEN = 0 V, TJ = 25°C,
measure IOUT
3
5
2.35
2.45
VEN = 0 or 5 V, VIN = 20 V
µA
µA
µA
UNDERVOLTAGE LOCKOUT, IN
VUVLO
IN rising UVLO threshold voltage
IN rising
30 (2)
Hysteresis
V
mV
FAULT FLAG
VOL
Output low voltage, FAULT
IFAULT = 1 mA
Off-state leakage
VFAULT = 6.5 V
50
180
mV
1
µA
THERMAL SHUTDOWN
Thermal shutdown threshold, OTSD2
155
Thermal shutdown threshold only in
current-limit, OTSD1
135
Hysteresis
(1)
(2)
°C
20
(2)
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
These parameters are provided for reference only and does not constitute part of TI's published device specifications for purposes of
TI's product warranty.
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6.6 Timing Requirements
Conditions are –40°C ≤ TJ ≤ +125°C and 2.5 V ≤ VIN ≤ 6.5 V. VEN = VIN, RILIM = 33 kΩ. Positive current are into terminals.
Typical value is at 25°C. All voltages are with respect to GND (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.05
3.2
0.18
0.2
5.12
7.3
ms
0.22
0.3
ms
POWER SWITCH
tr
OUT voltage rise time
tf
OUT voltage fall time
CL = 1 µF, RL = 100 Ω, (see Figure 10)
ms
ENABLE INPUT EN
ton
Turnon time
toff
Turnoff time
2.5 V ≤ VIN ≤ 5 V, CL = 1 µF, RL = 100 Ω,
(see Figure 10)
CURRENT LIMIT
t(IOS)
VIN = 5 V (see Figure 12)
3.5 (1)
µs
Turnoff delay for OVLO
VIN 5 V to 10 V with 1-V/µs ramp up rate,
VOUT with 100-Ω load
0.6 (1)
µs
FAULT deglitch
FAULT assertion or de-assertion due to
overcurrent condition
Short-circuit response time
OVERVOLTAGE LOCKOUT, IN
t(OVLO_off_delay)
FAULT FLAG
(1)
6
5
8
12
ms
This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.7 Typical Characteristics
200
3.0
VIN
2.5 V
VIN == 2.5
180
140
2.0
IIN(off) ( A)
120
IIN(on) ( A)
VIN = 55 V
VIN
2.5
160
100
80
1.5
1.0
60
40
VIN == 2.5
VIN
2.5 VV
20
0.5
VIN == 55VV
VIN
0
0.0
±50
0
50
100
150
Junction Temperature (ƒC)
±50
0
50
100
150
Junction Temperature (ƒC)
C001
RILIM = 33 KΩ
C002
RILIM = 33 KΩ
Figure 1. IIN(on) vs Junction Temperature
Figure 2. IIN(off) vs Junction Temperature
100
6
90
5
80
VOUT = 6.5 V
rDS(on) (mŸ)
IREV ( A)
VIN = 5 V
70
4
3
2
60
50
40
30
20
1
10
0
0
0
±50
50
100
150
Junction Temperature (ƒC)
0
±50
50
100
150
Junction Temperature (ƒC)
C003
C004
VEN = VIN = 0 V
Figure 3. IREV vs Junction Temperature
Figure 4. rDS(ON) vs Junction Temperature
5.50
7.8
Output Clamp Voltage (V)
Overvoltage Protection Threshod (V)
7.8
7.7
7.7
7.6
7.6
7.5
5.45
5.40
5.35
7.5
7.4
5.30
0
±50
50
100
150
Junction Temperature (ƒC)
0
±50
VEN = VIN = 0 V
50
100
150
Junction Temperature (ƒC)
C005
CL = 1 µF
Figure 5. V(OVLO) vs Junction Temperature
RL = 100 Ω
C005
VIN = 6.5 V
Figure 6. VO(VC) vs Junction Temperature
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Typical Characteristics (continued)
540
3000
530
Discharge Resistance (:)
3500
IOS (mA)
2500
2000
RILIM=33K
R
ILIM = 33 K
R
ILIM = 80.6 K
RILIM=80.6K
1500
RILIM=40.2K
R
ILIM = 40.2 K
R
ILIM = 150 K
RILIM=150K
1000
500
520
510
500
490
480
470
0
460
±50
0
50
100
150
Junction Temperature (ƒC)
2
3
4
5
6
7
VIN
C007
Figure 7. IOS vs Junction Temperature
C001
Figure 8. Discharge Resistance vs VIN
7 Parameter Measurement Information
OUT
90%
VOUT
RL
tr
tf
10%
CL
Figure 9. Output Rise-Fall Test Load
Figure 10. Power-On and Off Timing
IOS
VEN
50%
50%
IOUT
ton
toff
90%
VOUT
tIOS
10%
Figure 11. Enable Timing, Active High Enable
8
Figure 12. Output Short Circuit Parameters
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8 Detailed Description
8.1 Overview
The TPS25200 is an intelligent low voltage switch or e-Fuse with robust overcurrent and overvoltage protection
which are suitable for a variety of applications.
The TPS25200 current limited power switch uses N-channel MOSFETs in applications requiring up to 2.5 A of
continuous load current. The device allows the user to program the current-limit threshold between 85 mA and
2.9 A (typical) via an external resistor. The device enters constant-current mode when the load exceeds the
current-limit threshold.
The TPS25200 Input can withstand 20-V DC voltage, but clamps VOUT to a precision regulated 5.4 V and shuts
down in the event VIN exceeds 7.6 V. The device also integrates overcurrent and short circuit protection. The
precision overcurrent limit helps to minimize over design of the input power supply while the fast response short
circuit protection isolates the load when a short circuit is detected.
The additional features include:
• Enable the device can be put into a sleep mode for portable applications.
• Overtemperature protection to safely shutdown in the event of an overcurrent event or a slight overvoltage
event where the VOUT clamp is engaged over and extended period of time.
• Deglitched fault reporting to filter the Fault signal to ensure the TPS25200 do not provide false fault alerts.
• Output discharge pull-down to help ensue a load is in fact off and not in some undefined operational state.
• Reverse blocking when disabled to prevent back-drive from an active load inadvertently causing
undetermined behavior in the application.
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8.2 Functional Block Diagram
Current
Sense
CS
IN
OUT
UVLO
Charge
Pump
Driver
Current
Limit
disable + UVLO + OVLO + OTSD
OVLO
See Note A
EN
Zener Diode
OTSD
Thermal
Sense
OVC
GND
8-ms
Deglitch
FAULT
A.
ILIM
6.4-V Typical Clamp Voltage
8.3 Feature Description
8.3.1 Enable
This logic enable input controls the power switch and device supply current. A logic high input on EN enables the
driver, control circuits, and power switch. The enable input is compatible with both TTL and CMOS logic levels.
EN can be tied to VIN with a pull up resistor, and is protected with an integrated zener diode. Use a sufficiently
large (300-kΩ) pull up resistor to ensure that the V(EN) is limited below the absolute maximum rating.
8.3.2 Thermal Sense
The TPS25200 self protects by using two independent thermal sensing circuits that monitor the operating
temperature of the power switch and disable operation if the temperature exceeds recommended operating
conditions. The TPS25200 device operates in constant-current mode during an overcurrent condition, which
increases the voltage drop across power switch. The power dissipation in the package is proportional to the
voltage drop across the power switch, which increases the junction temperature during an overcurrent condition.
The first thermal sensor (OTSD1) turns off the power switch when the die temperature exceeds 135°C
(minimum) and the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on after
the device has cooled approximately 20°C.
10
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Feature Description (continued)
The TPS25200 also has a second ambient thermal sensor (OTSD2). The ambient thermal sensor turns off the
power switch when the die temperature exceeds 155°C (minimum) regardless of whether the power switch is in
current limit and turns on the power switch after the device has cooled approximately 20°C. The TPS25200
continues to cycle off and on until the fault is removed.
8.3.3 Overcurrent Protection
The TPS25200 thermally protects itself by thermal cycling during an extended overcurrent condition. The device
turns off when the junction temperature exceeds 135°C (typical) while in current limit. The device remains off
until the junction temperature cools 20°C (typical) and then restarts. The TPS25200 cycles on/off until the
overload is removed (see Figure 26 and Figure 29).
The TPS25200 responds to an overcurrent condition by limiting their output current to the IOS levels shown in
Figure 12. When an overcurrent condition is detected, the device maintains a constant output current and the
output voltage is reduced accordingly. During an over current event, two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS25200 ramps the
output current to IOS. The TPS25200 devices limit the current to IOS until the overload condition is removed or the
device begins to thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see Figure 12). The
current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and limits the output current to IOS. Similar to the previous case,
the TPS25200 limits the current to IOS until the overload condition is removed or the device begins to thermal
cycle.
8.3.4 FAULT Response
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or overvoltage
condition. The TPS25200 asserts the FAULT signal until the fault condition is removed and the device resumes
normal operation. The TPS25200 is designed to eliminate false FAULT reporting by using an internal delay
"deglitch" circuit for overcurrent (8-ms typical) conditions without the need for external circuitry. This ensures that
FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The
deglitch circuitry delays entering and leaving current-limit induced fault conditions.
The FAULT signal is not deglitched when the MOSFET is disabled due to an overtemperature condition but is
deglitched after the device has cooled and begins to turnon. This unidirectional deglitch prevents FAULT
oscillation during an overtemperature event.
The FAULT signal is not deglitched when the MOSFET is disabled into OVLO or out of OVLO. The TPS25200
does not assert the FAULT during output voltage clamp mode.
Connect FAULT with a pull up resistor to a low voltage I/O rail.
8.3.5 Output Discharge
A 480-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS25200 is
in UVLO, disabled or OVLO. The pull down capability decreases as VIN decreases (Figure 8).
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8.4 Device Functional Modes
The TPS25200 VIN can withstand up to 20 V. Within 0 V to 20 V range, it can be divided to four modes as shown
in Figure 13.
VOUT (V)
Over Voltage Clamp
(OVC)
5.4 V
Turn Off
MOSFET
UVLO(2.35V)
OVLO(7.6V)
20 V
VIN (V)
Figure 13. Output vs Input Voltage
8.4.1 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted on and off cycling due to input voltage droop during
turnon.
8.4.2 Overcurrent Protection (OCP)
When 2.35 V < VIN < 5.4 V, the TPS25200 is a traditional power switch, providing overcurrent protection.
8.4.3 Overvoltage Clamp (OVC)
When 5.4 V < VIN < 7.6 V, the overvoltage clamp (OVC) circuit clamps the output voltage to 5.4 V. Within this VIN
range, the overcurrent protection remains active.
8.4.4 Overvoltage Lockout (OVLO)
When VIN exceeds 7.6 V, the overvoltage lockout (OVLO) circuit turns off the protected power switch.
12
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9 Application and Implementation
9.1 Application Information
The TPS25200 is a 5-V eFuse with precision current limit and over-voltage clamp. When a slave device such as
a mobile data-card device is hot plugged into a USB port as shown in Figure 14, an input transient voltage could
damage the slave device due to the cable inductance. Placing the TPS25200 at the input of mobile device as
over-voltage and overcurrent protector can safeguard these slave devices. Input transients also occur when the
current through the cable parasitic inductance changes abruptly. This can occur when the TPS25200 turns off
the internal MOSFET in response to an overvoltage or overcurrent event. The TPS25200 can withstand the
transient without a bypass bulk capacitor, or other external overvoltage protection components at input side. The
TPS25200 also can be used at host side as a traditional power switch pin-to-pin compatible with the TPS2553.
Rcable
Mobile Device
Lcable
OUT
IN
TPS25200
5V
USB Port
Load
GND
Figure 14. Hot Plug Into 5V USB port with Parasitic Cable Resistance and Inductance
9.2 Typical Application
VIO
300 kΩ
Fault signal
TPS25200DRV
0.1µF
VIN
300 kΩ
VOUT
6
IN
OUT
1
5
GND
ILIM
2
4
EN
FAULT
3
22mF
PowerPAD
RILIM
Figure 15. Overvoltage and Overcurrent Protector—Typical Application Schematic
Use the IOS in the Electrical Characteristics table or IOS in Equation 1 to select the RILIM.
9.2.1 Design Requirements
For this design example, use the desgin parameters in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Normal input operation voltage
5V
Output transient voltage
6.5 V
Minimum current limit
2.1 A
Maximum currnt limit
2.9 A
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9.2.2 Detailed Design Procedure
9.2.2.1 Step by Step Design Produce
To
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Normal Input Operation Voltage
Output transient voltage
Minimum Current Limit
Maximum Current Limit
9.2.2.2 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, a 0.1-µF or greater ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise decoupling.
When VIN ramp up exceed 7.6 V, VOUT follows VIN until the TPS25200 turns off the internal MOSFET after
t(OVLO_off_delay). Since t(OVLO_off_delay) largely depends on the VIN ramp rate, VOUT sees some peak voltage.
Increasing the output capacitance can lower the output peak voltage as shown in Figure 16.
Output Peak Voltage (V)
10
8
6
4
2
0
0
10
20
30
Output Cap ( F)
40
50
C008
Figure 16. VOUT Peak Voltage vs COUT
(VIN Step From 5 V to 15 V with 1-V/µs Ramp Up Rate)
9.2.2.3 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable via an external resistor. The TPS25200 uses an internal
regulation loop to provide a regulated voltage on the ILIM terminal. The current-limit threshold is proportional to
the current sourced out of ILIM. The recommended 1% resistor range for RILIM is 33 kΩ ≤ RILIM ≤ 1100 kΩ to
ensure stability of the internal regulation loop. Many applications require that the minimum current limit is above a
certain current level or that the maximum current limit is below a certain current level, so it is important to
consider the tolerance of the overcurrent threshold when selecting a value for RILIM. The current-limit threshold
equations (IOS) in Equation 1 approximate the resulting overcurrent threshold for a given external resistor value
RILIM. See the Electrical Characteristics table for specific current limit settings. The traces routing the RILIM
resistor to the TPS25200 must be as short as possible to reduce parasitic effects on the current-limit accuracy.
RILIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or 2)
below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current limit above a
minimum threshold is important to ensure start up into full load or heavy capacitive loads. The resulting maximum
current-limit threshold is the intersection of the selected value of RILIM and the IOS(max) curve.
14
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To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(max) curve and choose a value of RILIM above this value. Programming the current limit below a
maximum threshold is important to avoid current limiting upstream power supplies causing the input voltage bus
to droop. The resulting minimum current-limit threshold is the intersection of the selected value of RILIM and the
IOS(min) curve. See Figure 17 and Figure 18.
96754V
+ 30
IOSmax (mA) =
R 0.985kW
ILIM
IOSnom (mA) =
98322V
RILIM1.003kW
IOSmin (mA) =
97399
- 30
RILIM1.015kW
(1)
3500
800
3000
700
Current Limit Threshold (mA)
Current Limit Threshold (mA)
Where 33 kΩ ≤ RILIM ≤ 1100 kΩ.
2500
IOS(typ)
2000
IOS(max)
1500
1000
IOS(min)
500
0
600
500
IOS(typ)
400
IOS(max)
300
200
100
IOS(min)
0
30
40
50
60
70
80
90 100 110 120 130 140 150
Current Limit Resistor (k:)
150
33 kΩ ≤ RILIM ≤ 150 kΩ
250
350
450
550
650
750
850
950 1050 1150
Current Limit Resistor (k:)
C001
C001
150 kΩ ≤ RILIM ≤ 1100 kΩ
Figure 17. Current-Limit Threshold vs RILIM I
Figure 18. Current-Limit Threshold vs RILIM II
9.2.2.4 Design Above a Minimum Current Limit
Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 2.1 A must be delivered to the load so that the minimum desired current-limit threshold is 2100 mA. Use the
IOS equations (Equation 1) and Figure 17 to select RILIM as shown in Equation 2.
IOSmin (mA) = 2100 mA
IOSmin (mA) =
97399V
RILIM1.015kW
- 30
1
1
æ 97399 ö 1.015 æ 97399 ö 1.015
=ç
= 43.22 kW
RILIM (kW) = ç
÷
÷
ç IOS(min) + 30 ÷
è 2100 + 30 ø
è
ø
(2)
Select the closest 1% resistor less than the calculated value: RILIM = 42.2 kΩ. This sets the minimum current-limit
threshold at 2130 mA as shown in Equation 3.
97399V
97399
- 30 =
- 30 = 2130mA
IOSmin (mA) =
1.015
RILIM
kW
(42.2 x 1.01)1.015
(3)
Use the IOS equations (Equation 1), Figure 17, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold as shown in Equation 4.
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IOSmax (mA) =
IOSmax (mA) =
96754
RILIM0.985
www.ti.com
+ 30
96754
(42.2 ´ 0.99)0.985
+ 30 = 2479 mA
(4)
The resulting current-limit threshold minimum is 2130 mA and maximum is 2479 mA with RILIM = 42.2kΩ ± 1%.
9.2.2.5 Design Below a Maximum Current Limit
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that 2.9 A must be delivered to the load so that the minimum desired current-limit threshold is 2900 mA. Use the
IOS equations (Equation 1) and Figure 18 to select RILIM as shown in Equation 5.
IOSmax (mA) = 2900mA
IOSmax (mA) =
96754
RILIM0.985kW
+ 30
1
1
æ 96754 ö 0.985 æ 96754 ö 0.985
=ç
= 35.57 kW
RILIM (kW) = ç
÷
÷
ç IOS(max) - 30 ÷
è 2900 - 30 ø
è
ø
(5)
Select the closest 1% resistor greater than the calculated value: RILIM = 36 kΩ. This sets the maximum currentlimit threshold at 2894 mA as shown in Equation 6.
96754V
96754
+ 30 =
+ 30 = 2894mA
IOSmax (mA) =
0.985
RILIM
kW
(36 x 0.99 )0.985
(6)
Use the IOS equations, Figure 18, and the previously calculated value for RILIM to calculate the minimum resulting
current-limit threshold as shown in Equation 7.
97399
IOSmin (mA) =
- 30
RILIM1.015
IOSmin (mA) =
97399
(36 ´ 1.01)1.015
- 30 = 2508mA
(7)
The resulting minimum current-limit threshold minimum is 2592 mA and maximum is 2894 mA with RILIM = 36 kΩ
± 1%.
16
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9.2.2.6 Power Dissipation and Junction Temperature
The low on-resistance of the internal N-channel MOSFET allows small surface-mount packages to pass large
currents. It is good design practice to estimate power dissipation and junction temperature. The below analysis
gives an approximation for calculating junction temperature based on the power dissipation in the package.
However, it is important to note that thermal analysis is strongly dependent on additional system level factors.
Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices
dissipating power. Good thermal design practice must include all system level factors in addition to individual
component analysis. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and
operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read
rDS(on) from the typical characteristics graph. When VIN is lower than V(OVC), the TPS2500 is an traditional power
switch. Using this value, the power dissipation can be calculated by usnig Equation 8.
PD = rDS(on) × IOUT2
(8)
When VIN exceed V(OVC), but lower than V(OVLO), the TPS25200 clamp output to fixed V(OVC), the power
dissipation can be calculated by using Equation 9.
PD = (VIN – V(OVC)) × IOUT
where
•
•
•
•
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
V(OVC) = Overvoltage clamp voltage (V)
IOUT = Maximum current-limit threshold (A)
(9)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature using Equation 10.
TJ = PD × θJA + TA
where
•
•
•
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C /W)
PD = Total power dissipation (W)
(10)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θJA, and thermal resistance is highly dependent on the individual package and board
layout.
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Application Curves
VOUT
VOUT
VIN
VIN
9
0.32
8
0.28
7
0.2
5
0.16
4
0.12
3
2
0
±1.0
±0.5
0.0
0.5
1.0
1.5
2.0
±80
12
11
10
9
8
7
6
5
4
3
2
1
0
±1
-0.04
40
80
120
160
Time (Ps)
C009
Figure 20. VIN Step 5 V to 8 V With 4.7 μF // 100 Ω
11
VIN
VIN
VOUT
VOUT
/FAULT
/FAULT
V
VIN
IN
10
V
VOUT
OUT
9
VIN, VOUT (V)
8
7
6
5
4
3
2
1
0
-1
0
2
4
6
-6
8
Time (s)
-4
-2
0
2
4
Time (us)
C010
C012
Figure 22. 5 V to 10 V OVLO Response Time
Figure 21. Pulse Overvoltage With 100 Ω
5
5
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
-1
±1
EN
V
VOUT
IN
V
IOUT
OUT
0
±1
±4
1
6
Time (ms)
11
IOUT (A)
EN, VOUT (V)
5
16
EN
VIN
VOUT
V
IOUT
OUT
4
-1
-1.2
-0.2
0.8
Time (ms)
C013
Figure 23. Turnon Delay and Rise Time 150 µF || 2.5 Ω
5
IOUT (A)
-2
EN, VOUT (V)
0
0
±40
C001
Figure 19. VOUT vs VIN (0 V to 10 V)
18
0.04
/FAULT
IIOUT
OUT
±1
±1.5
0.08
V
VIN
IN
V
VOUT
OUT
1
Time (s)
VIN, VOUT, /FAULT (V)
0.24
6
IOUT (A)
12
11
10
9
8
7
6
5
4
3
2
1
0
±1
±2.0
VIN, VOUT, /FAULT (V)
VIN, VOUT (V)
9.2.3
www.ti.com
1.8
2.8
C013
Figure 24. Turnoff Delay and Fall Time 150 µF || 2.5 Ω
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5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
0
0
0
-1
±1
1
EN
/FAULT
IIOUT
OUT
±2
2
6
10
14
Time (ms)
IOUT
IOUT
/FAULT
20
40
60
80
Time (ms)
C016
Figure 26. 2.5 Ω to Output Short Transient Response
6
6
V
VOUT
OUT
IIOUT
OUT
/FAULT
6
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
-1
±1
±1
±70
±50
±30
10
±10
VOUT, /FAULT (V)
5
IOUT (A)
VOUT, /FAULT (V)
V
VOUT
OUT
0
C015
Figure 25. Enable into Output Short
6
-1
±20
18
30
0
20
40
60
80
Time (ms)
C016
Figure 27. Output Short to 2.5-Ω Load Recovery Response
6
-1
±20
Time (ms)
C016
Figure 28. No Load to Output Short Transient Response
6
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
-1
±1
-1
±70
±50
±30
±10
10
Time (ms)
IOUT (A)
IIOUT
OUT
/FAULT
VOUT (V)
6
VOUT
VOUT
30
IOUT (A)
±1
IIOUT
OUT
/FAULT
6
VOUT
V
OUT
V
IOUT
IN
5
IOUT (A)
0
VVOUT
OUT
IOUT (A)
6
VOUT, /FAULT (V)
6
1
VOUT, /FAULT (V)
6
6
IOUT (A)
EN, /FAULT (V)
www.ti.com
±1
-0.8
C016
Figure 29. Output Short to No Load Recovery Response
0
0.8
1.6
2.4
3.2
Time (ms)
Figure 30. Hot-Short With 50 mΩ
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19
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SLVSCJ0C – MARCH 2014 – REVISED SEPTEMBER 2017
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5
VOUT (V)
60
VOUT
VOUT
IOUT
IOUT
50
4
40
3
30
2
20
1
10
0
0
IOUT (A)
6
-10
±1
-20
±2
±4
±2
2
±0
4
6
Time (Ps)
C021
Figure 31. 50-mΩ Hot-Short Response Time
20
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10 Power Supply Recommendations
The TPS25200 is designed for 2.7 V < VIN < 5 V (typical) voltage rails. While there is a VOUT clamp, it is not
intended to be used to regulate VOUT at approximately 5.4 V with 6 V < VIN < 7 V. This is a protection feature
only.
11 Layout
11.1 Layout Guidelines
•
•
•
•
For all applications, a 0.1-µF or greater ceramic bypass capacitor between IN and GND is recommended as
close to the device as possible for local noise decoupling.
For output capacitance, refer to Figure 16, low ESR ceramic cap is recommended.
The traces routing the RILIM resistor to the device must be as short as possible to reduce parasitic effects on
the current limit accuracy.
The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.
11.2 Layout Example
VIA to Power Ground Plane
FAULT
EN
IN
4
3
5
2
6
1
ILIM
High Frequency
Bypass Capacitor
OUT
Power Ground
VI/O
Figure 32. TPS25200 Board Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
TPS25200 EVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS25200DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SKB
TPS25200DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SKB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2017
OTHER QUALIFIED VERSIONS OF TPS25200 :
• Automotive: TPS25200-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.15
4.0
8.0
Q2
TPS25200DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
TPS25200DRVR
WSON
DRV
6
3000
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
TPS25200DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS25200DRVT
WSON
DRV
6
250
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25200DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TPS25200DRVR
WSON
DRV
6
3000
205.0
200.0
33.0
TPS25200DRVT
WSON
DRV
6
250
210.0
185.0
35.0
TPS25200DRVT
WSON
DRV
6
250
205.0
200.0
33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A
C
B
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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