Texas Instruments | TPS548D21 1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 40-A SWIFT™ Synchronous Step-Down Converter Supporting AVSO and Full Differential Sense (Rev. A) | Datasheet | Texas Instruments TPS548D21 1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 40-A SWIFT™ Synchronous Step-Down Converter Supporting AVSO and Full Differential Sense (Rev. A) Datasheet

Texas Instruments TPS548D21 1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 40-A SWIFT™ Synchronous Step-Down Converter Supporting AVSO and Full Differential Sense (Rev. A) Datasheet
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TPS548D21
SLUSCI8A – JULY 2016 – REVISED AUGUST 2017
TPS548D21 1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 40-A SWIFT™
Synchronous Step-Down Converter Supporting AVSO and Full Differential Sense
1 Features
2 Applications
•
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1
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Conversion Input Voltage Range (PVIN): 1.5 V to
16 V
Input Bias Voltage (VDD) Range: 4.5 V to 22 V
Output Voltage Range: 0.6 V to 5.5 V
Integrated, 2.9-mΩ and 1.2-mΩ Power MOSFETs
With 40-A Continuous Output Current
Voltage Reference 0.6 V to 1.2 V in 50-mV Steps
Using VSEL Pin
±0.5%, 0.9-VREF Tolerance Range: –40°C to
+125°C Junction Temperature
True Differential Remote Sense Amplifier
D-CAP3™ Control Loop
Analog AVS Optimization via REFIN_TRK Pin
Adaptive On-Time Control with 4 Selectable
Frequency Settings: 425 kHz, 650 kHz, 875 kHz,
and 1.05 MHz
Temperature Compensated and Programmable
Current Limit with RILIM and OC Clamp
Choice of Hiccup or Latch-Off OVP or UVP
VDD UVLO External Adjustment by Precision EN
Hysteresis
Prebias Start-up Support
FCCM Mode During All Operation
Full Suite of Fault Protection and PGOOD
7 mm × 5 mm × 1.5 mm, 40-Pin, Stack Clipped
LQFN-CLIP Package
Create a Custom Design Using the TPS548D21
With the WEBENCH® Power Designer
•
•
Enterprise Storage, SSD, NAS
Wireless and Wired Communication Infrastructure
Industrial PCs, Automation, ATE, PLC, Video
Surveillance
Enterprise Server, Switches, Routers
ASIC, SoC, FPGA, DSP Core, and I/O Rails
3 Description
The TPS548D21 device is a compact single buck
converter with adaptive on-time, D-CAP3 mode
control. It is designed for high accuracy, high
efficiency, fast transient response, ease-of-use, low
external component count and space-conscious
power systems.
This device features full differential sense, TI
integrated FETs with a high-side on-resistance of
2.9 mΩ and a low-side on-resistance of 1.2 mΩ. The
device also features accurate 0.5%, 0.9-V reference
with an ambient temperature range between –40°C
and +125°C. Competitive features include: very low
external component count, accurate load regulation
and line regulation, FCCM mode operation, and
internal soft-start control.
The TPS548D21 device is available in 7-mm × 5-mm,
40-pin, LQFN-CLIP (RVF) package (RoHs exempt).
Device Information(1)
PART NUMBER
TPS548D21
PACKAGE
BODY SIZE (NOM)
LQFN-CLIP (40)
7.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
PGOOD
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
NC
VDD
DRGND
BP
MODE
AGND
VSEL
FSEL
PVIN
PGND
PGOOD
PGND
ILIM
PGND
TPS548D21
PGND
Load
PGND
+
±
SW
SW
SW
SW
SW
SW
PGND
SW
NU
NU
VOSNS
NU
RSP
BOOT
REFIN_TRK
EN_UVLO
RSN
EXT. SOURCE
PGND
PGND
ENABLE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS548D21
SLUSCI8A – JULY 2016 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
15
7.5 Programming........................................................... 15
8
Applications and Implementation ...................... 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 23
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Custom Design With WEBENCH® Tools .............
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to Revision A
Page
•
Changed package name to correct one ................................................................................................................................ 1
•
Added MIN and MAX values for VDD UVLO rising threshold ................................................................................................ 5
•
Added MIN and MAX for all Soft Start settings and table notes 3 and 4 in Electrical Characteristics................................... 7
•
Added last sentence of Overview to replace incomplete phrase from previous paragraph ................................................. 11
•
Changed VOUT = 5 V to VOUT = 5.5 V for Figure 12 ............................................................................................................. 12
•
Added Application Workaround to Support 4-ms and 8-ms SS Settings subsection........................................................... 18
•
Added Figure 15 and Figure 16............................................................................................................................................ 18
•
Deleted "programmable" between "8 ms" and "delay" ........................................................................................................ 21
•
Added new sentence before last sentence of Application Information ................................................................................ 22
•
Changed "286 µF" to "28.6 µF" ........................................................................................................................................... 27
•
Changed "150 ns" to "300 ns" in definition of tOFF(min), Equation 9 ....................................................................................... 28
•
Changed "963 µF" to "969 µF" ............................................................................................................................................ 28
2
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5 Pin Configuration and Functions
31
30
29
28
27
26
25
24
23
22
21
BP
AGND
DRGND
VDD
NC
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
33
32
FSEL
RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
VSEL
40
VOSNS
15
PGND
14
PGND
13
SW
RSP
PGND
SW
39
Thermal Pad
SW
RSN
16
SW
38
PGND
SW
REFIN_TRK
17
SW
37
PGND
SW
ILIM
18
BOOT
36
PGND
EN_UVLO
PGOOD
NU
35
19
NU
MODE
20
PGND
NU
34
PGND
1
2
3
4
5
6
7
8
9
10
11
12
Pin Functions
PIN
NAME
NO.
I/O/P (1)
DESCRIPTION
AGND
30
G
Ground pin for internal analog circuits.
BOOT
5
P
Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW
node. Internally connected to BP via bootstrap PMOS switch.
BP
31
O
LDO output
DRGND
29
P
Internal gate driver return.
EN_UVLO
4
I
Enable pin that can turn on the DC/DC switching converter. Use also to program the required
PVIN UVLO when PVIN and VDD are connected together.
FSEL
32
I
Program switching frequency, internal ramp amplitude and FCCM mode.
ILIM
36
I/O
MODE
34
I
Program overcurrent limit by connecting a resistor to ground.
Mode selection pin. Select the control mode (DCAP3 or DCAP), internal VREF operation, and
soft-start timing selection.
NC
27
NU
1, 2, 3
O
Not used pins.
13, 14, 15,
16, 17, 18,
19, 20
P
Power ground of internal FETs.
PGND
PGOOD
No connect.
35
O
Open drain power good status signal.
PVIN
21, 22, 23,
24, 25, 26
P
Power supply input for integrated power MOSFET pair.
RSN
38
I
Inverting input of the differential remote sense amplifier.
RSP
39
I
Non-inverting input of the differential remote sense amplifier.
REFIN_TRK
37
I
System reference voltage that can be overridden by the external voltage source for tracking
and sequencing application.
SW
6 , 7, 8, 9,
10, 11, 12
I/O
VDD
28
P
Controller power supply input.
VOSNS
40
I
Output voltage monitor input pin.
VSEL
33
I
Program the initial start-up and or reference voltage without feedback resistor dividers (from
0.6 V to 1.2 V in 50-mV increments).
(1)
Output switching terminal of power converter. Connect the pins to the output inductor.
I = input, O = output, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
PVIN
–0.3
25
VDD
–0.3
25
BOOT
–0.3
34
DC
–0.3
7.7
< 10 ns
–0.3
9.0
BOOT to SW
Input voltage
(1) (2)
NU
–0.3
6
EN_UVLO, VOSNS, MODE, FSEL, ILIM
–0.3
7.7
RSP, REFIN_TRK, VSEL
–0.3
3.6
RSN
–0.3
0.3
PGND, AGND, DRGND
–0.3
0.3
–0.3
25
DC
SW
V
–5
27
–0.3
7.7
V
Junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage
(1)
(2)
< 10 ns
UNIT
PGOOD, BP
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
PVIN
1.5
16
VDD
4.5
22
–0.1
24.5
DC
–0.1
6.5
< 10 ns
BOOT
BOOT to SW
Input voltage
–0.1
7
NU
–0.1
5.5
EN_UVLO, VOSNS, MODE, FSEL, ILIM
–0.1
5.5
RSP, REFIN_TRK, VSEL
–0.1
3.3
RSN
–0.1
0.1
PGND, AGND, DRGND
–0.1
0.1
–0.1
18
–5
27
SW
Output voltage
DC
< 10 ns
PGOOD, BP
Junction temperature, TJ
4
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UNIT
V
–0.1
7
V
–40
125
°C
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6.4 Thermal Information
TPS548D21
THERMAL METRIC (1)
RVF (LQFN-CLIP)
UNIT
(40 PINS)
RθJA
Junction-to-ambient thermal resistance
28.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.3
°C/W
RθJB
Junction-to-board thermal resistance
3.6
°C/W
ψJT
Junction-to-top characterization parameter
0.96
°C/W
ψJB
Junction-to-board characterization parameter
3.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
MOSFET ON-RESISTANCE (RDS(on))
RDS(on)
High-side FET
(VBOOT – VSW) = 5 V, ID = 25 A, TJ = 25°C
2.9
mΩ
Low-side FET
VVDD = 5 V, ID = 25 A, TJ = 25°C
1.2
mΩ
INPUT SUPPLY AND CURRENT
VVDD
VDD supply voltage
Nominal VDD voltage range
IVDD
VDD bias current
No load, power conversion enabled (no switching),
TA = 25°C,
IVDDSTBY
VDD standby current
No load, power conversion disabled, TA = 25°C
4.5
22
V
2
mA
700
µA
UNDERVOLTAGE LOCKOUT
VVDD_UVLO
VDD UVLO rising threshold
VVDD_UVLO(HYS)
VDD UVLO hysteresis
4.23
4.25
4.34
V
VEN_ON_TH
EN_UVLO on threshold
1.45
1.6
1.75
V
VEN_HYS
EN_UVLO hysteresis
270
300
340
mV
IEN_LKG
EN_UVLO input leakage
current
–1
0
1
µA
0.2
VEN_UVLO = 5 V
V
INTERNAL REFERENCE VOLTAGE AND EXTERNAL REFIN TRACKING RANGE
VINTREF
Internal REF voltage
VINTREFTOL
Internal REF voltage
tolerance
900.4
VINTREF
Internal REF voltage range
0.6
1.2
V
VTRKIN_CM
External REFIN voltage range
0
1.25
V
VTRKIN_MAG
External REFIN margin range
0.5
1.25
V
VSEQIN_CM
REFIN_TRK voltage range
0
3.3
V
–2.5
2.5
mV
–40°C ≤ TJ ≤ 125°C
–0.5%
mV
0.5%
OUTPUT VOLTAGE
VIOS_LPCMP
Loop comparator input offset
voltage (1)
IRSP
RSP input current
VRSP = 600 mV
IVO(dis)
VO discharge current
VVO = 0.5 V, power conversion disabled
–1
1
µA
8
12
mA
5
7
MHz
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBW
Unity gain bandwidth (1)
A0
Open loop gain (1)
SR
Slew rate (1)
VIRNG
Input range (1)
–0.2
1.8
V
VOFFSET
Input offset voltage (1)
–3.5
3.5
mV
75
dB
±4.7
V/µsec
INTERNAL BOOT STRAP SWITCH
VF
Forward voltage
VBP-BOOT, IF = 10 mA, TA = 25°C
IBOOT
VBST leakage current
VBOOT = 30 V, VSW = 25 V, TA = 25°C
(1)
0.1
0.2
V
0.01
1.5
µA
Specified by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
380
425
475
585
650
740
790
875
995
950
1050
1250
UNIT
SWITCHING FREQUENCY
fSW
VO switching frequency (2)
tON(min)
Minimum on time (1)
tOFF(min)
Minimum off time (1)
VIN = 12 V, VVO = 1 V, TA = 25°C
60
DRVH falling to rising
kHz
ns
300
ns
MODE, VSEL, FSEL DETECTION
Open
VDETECT_TH
MODE, VSEL, and FSEL
detection voltage
VBP = 2.93 V,
RHIGH = 100 kΩ
1.9091
RLOW = 165 kΩ
1.8243
RLOW = 147 kΩ
1.7438
RLOW = 133 kΩ
1.6725
RLOW = 121 kΩ
1.6042
RLOW = 110 kΩ
1.5348
RLOW = 100 kΩ
1.465
RLOW = 90.9 kΩ
1.3952
RLOW = 82.5 kΩ
1.3245
RLOW = 75 kΩ
1.2557
RLOW = 68.1 kΩ
1.187
RLOW = 60.4 kΩ
1.1033
RLOW = 53.6 kΩ
1.0224
RLOW = 47.5 kΩ
0.9436
RLOW = 42.2 kΩ
0.8695
RLOW = 37.4 kΩ
0.7975
RLOW = 33.2 kΩ
0.7303
RLOW = 29.4 kΩ
0.6657
RLOW = 25.5 kΩ
0.5953
RLOW = 22.1 kΩ
0.5303
RLOW = 19.1 kΩ
0.4699
RLOW = 16.5 kΩ
0.415
RLOW = 14.3 kΩ
0.3666
RLOW = 12.1 kΩ
0.3163
RLOW = 10 kΩ
0.2664
RLOW = 7.87 kΩ
0.2138
RLOW = 6.19 kΩ
0.1708
RLOW = 4.64 kΩ
0.1299
RLOW = 3.16 kΩ
0.0898
RLOW = 1.78 kΩ
0.0512
RLOW = 0 Ω
(2)
6
VBP
RLOW = 187 kΩ
V
GND
Correlated with close loop EVM measurement at load current of 30 A.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
RMODE_LOW = 60.4 kΩ
7
8 (3)
10
RMODE_LOW = 53.6 kΩ
3.6
4 (4)
5.2
RMODE_LOW = 47.5 kΩ
1.6
2
2.8
RMODE_LOW = 42.2 kΩ
0.8
1
1.6
UNIT
SOFT START
tSS
Soft-start time
VOUT rising from 0 V to
95% of final set point,
RMODE_HIGH = 100 kΩ
ms
POWER-ON DELAY
tPODLY
Power-on delay time
256
µs
PGOOD COMPARATOR
PGOOD in from higher
PGOOD in from lower
VPGTH
PGOOD threshold
105
108
111
105
108
111 %VREFIN_TRK
89
92
95
89
92
95 %VREFIN_TRK
PGOOD out to higher
PGOOD out to lower
IPG
PGOOD sink current
VPGOOD = 0.5 V
IPGLK
PGOOD leakage current
VPGOOD = 5 V
tPGDLY
PGOOD delay time
%VREF
%VREF
120
%VREF
120
%VREFIN_TRK
68
%VREF
68
%VREFIN_TRK
6.9
–1
Delay for PGOOD going in
0
mA
1
8.192
Delay for PGOOD coming out
μA
ms
2
µs
1.2
V
CURRENT DETECTION
VILM
VILIM voltage range
On-resistance (RDS(on)) sensing
RLIM = 130 kΩ
OC tolerance
IOCL_VA
Valley current limit threshold
RLIM = 97.6 kΩ
OC tolerance
RLIM = 64.9 kΩ
OC tolerance
IOCL_VA_N
Negative valley current limit
threshold
ICLMP_LO
Clamp current at VLIM clamp
at lowest
ICLMP_HI
Clamp current at VLIM clamp
at highest
VZC
Zero cross detection offset
(3)
(4)
(5)
0.1
40
A
±10% (5)
30
A
±15% (5)
20
A
±20%
RLIM = 130 kΩ
–40
RLIM = 97.6 kΩ
–30
RLIM = 64.9 kΩ
–20
VILIM_CLMP = 0.1 V, TA = 25°C
6.25
A
VILIM_CLMP = 1.2 V, TA = 25°C
75
A
0
mV
A
In order to use the 8-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
In order to use the 4-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
Calculated from 20-A test data. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PROTECTIONS AND OOB
Wake-up
3.32
Shutdown
3.11
VBPUVLO
BP UVLO threshold voltage
VOVP
OVP threshold voltage
OVP detect voltage
VOV_MAX_DEF
Default OVMAX threshold
voltage
Default OV_MAX detect threshold voltage
tOVPDLY
OVP response time
100-mV over drive
VUVP
UVP threshold voltage
tUVPDLY
UVP delay filter delay time
VOOB
UVP detect voltage
117%
120%
123%
VREF
117%
120%
123%
VREFIN_TRK
1.50
Hiccup blanking time
V
1
µs
65%
68%
71%
VREF
65%
68%
71%
VREFIN_TRK
1
OOB threshold voltage
tHICDLY
V
ms
8%
VREF
8%
VREFIN_TRK
tSS = 1 ms
16
ms
tSS = 2 ms
24
ms
tSS = 4 ms
38
ms
tSS = 8 ms
67
ms
BP VOLTAGE
VBP
BP LDO output voltage
VIN = 12 V, 0 A ≤ ILOAD ≤ 10 mA,
VBPDO
BP LDO dropout voltage
VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
IBPMAX
BP LDO overcurrent limit
VIN = 12 V, TA = 25°C
5.07
V
365
100
mV
mA
THERMAL SHUTDOWN
TSDN
8
Built-In thermal shutdown
threshold (1)
Shutdown temperature
Hysteresis
155
165
30
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°C
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100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
6.6 Typical Characteristics
85
80
75
70
85
80
75
70
VIN = 1.5 V
VIN = 12 V
VIN = 16 V
65
VIN = 8 V
VIN = 12 V
VIN = 16 V
65
60
60
0
4
8
VOUT = 1 V
VDD = 5 V
12
16
20
24
Load Current (A)
28
32
36
40
0
3
FCCM
fSW = 650 kHz
VOUT = 5.5 V
VDD = 5 V
Figure 1. Efficiency vs Output Current
VIN = 12 V
VOUT = 1 V
fSW = 650 kHz
Natural convection
IOUT = 40 A
fSW = 650 kHz
Airflow = 400 LFM
9
12
15
18
Load Current (A)
21
24
27
30
D001
FCCM
fSW = 425 kHz
Figure 2. Efficiency vs Output Current
VIN = 12 V
VOUT = 1 V
Figure 3. Thermal Image
VIN = 12 V
VOUT = 1 V
6
D001
fSW = 650 kHz
Airflow = 200 LFM
IOUT = 40 A
Figure 4. Thermal Image
IOUT = 40 A
VIN = 12 V
VOUT = 5.5 V
Figure 5. Thermal Image
fSW = 425 kHz
Natural convection
IOUT = 30 A
Figure 6. Thermal Image
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Typical Characteristics (continued)
VIN = 12 V
VOUT = 5.5 V
fSW = 425 kHz
Airflow = 200 LFM
IOUT = 30 A
VIN = 12 V
VOUT = 5.5 V
fSW = 425 kHz
Airflow = 400 LFM
Figure 7. Thermal Image
VOUT = 1 V
IOUT from 8 A to 32 A
Figure 8. Thermal Image
VIN = 12 V
2.5 A/µs
Figure 9. Transient Response Peak-to-Peak
10
IOUT = 30 A
VOUT = 5.5 V
IOUT from 6 A to 24 A
VIN = 12 V
2.5 A/µs
Figure 10. Transient Response Peak-to-Peak
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7 Detailed Description
7.1 Overview
TPS548D21 device is a high-efficiency, single channel, FET-integrated, synchronous buck converter. It is
suitable for point-of-load applications with 40 A or lower output current in storage, telecom, and similar digital
applications. The device features proprietary D-CAP3 mode control combined with adaptive on-time architecture.
This combination is ideal for building modern high/low duty ratio, ultra-fast load step response DC-DC converters.
TPS548D21 device has integrated MOSFETs rated at 40-A TDC.
The converter input voltage range is from 1.5 V up to 16 V, and the VDD input voltage range is from 4.5 V to
22 V. The output voltage ranges from 0.6 V to 5.5 V.
Stable operation with all ceramic output capacitors is supported, since the D-CAP3 mode uses emulated current
information to control the modulation. An advantage of this control scheme is that it does not require phase
compensation network outside which makes it easy to use and also enables low external component count.
Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage
while increasing switching frequency as needed during load step transient.
The default preset switching frequency for this device is 650 kHz. Switching frequency is also programmable
from 4 preset values via resistor setting by FSEL pin.
7.2 Functional Block Diagram
REFIN_TRK
External
soft-start
VREF ± 32%
EN_UVLO
Internal
soft-start
MUX
VREF + 8/16 %
+
UV
+
+
OV
+
Delay
Control
BOOT
VREF + 20%
RSN
PGOOD
VREF ± 8/16 %
PVIN
+
RSP
PWM
+
VOSNS
VOUT
+
+
D-CAP3TM
Ramp Generator
VREF
Reference
Generator
VSEL
FSEL
XCON
Switching
Frequency
Programmer
Control
Logic
tON
One-Shot
SW
BP
x
(1/16)
+
ZC
PGND
ILIM
x
(±1/16)
AGND
+
OCP
LDO
Regulator
VDD
DRGND
MODE
MODE Logic
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7.3 Feature Description
7.3.1 40-A FET
The TPS548D21 device is a high-performance, integrated FET converter supporting current rating up to 40 A
thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB
layout area. The drain-to-source breakdown voltage for these FETs is 25 V DC and 27 V transient for 10 ns.
Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 27 V. In order to limit the switch
node ringing of the device, it is recommended to add a R-C snubber from the SW node to the PGND pins. Refer
to the Layout Guidelines section for the detailed recommendations.
7.3.2 On-Resistance
The typical on-resistance (RDS(on)) for the high-side MOSFET is 2.9 mΩ and typical on-resistance for the low-side
MOSFET is 1.2 mΩ with a nominal gate voltage (VGS) of 5 V.
7.3.3 Package Size, Efficiency and Thermal Performance
110
110
100
100
Ambient Temperature (°C)
Ambient Temperature (°C)
The TPS548D21 device is available in a 7 mm × 5 mm, LQFN-CLIP package with 40 power and I/O pins. It
employs TI proprietary MCM packaging technology with thermal pad. With a properly designed system layout,
applications achieve optimized safe operating area (SOA) performance. The curves shown in Figure 11 and
Figure 12 are based on the orderable evaluation module design. (See SLUUBG3 to order the EVM)
90
80
70
60
50
100 LFM
200 LFM
400 LFM
Natural convection
40
90
80
70
60
50
100 LFM
200 LFM
400 LFM
Natural convection
40
30
30
0
5
VIN = 12 V
10
15
20
25
Output Current (A)
VOUT = 1 V
30
35
40
0
5
10
15
20
Output Current (A)
D001
fSW = 650 kHz
Figure 11. Safe Operating Area
VIN = 12 V
VOUT = 5.5 V
25
30
D001
fSW = 425 kHz
Figure 12. Safe Operating Area
7.3.4 Soft-Start Operation
In the TPS548D21 device the soft-start time controls the inrush current required to charge the output capacitor
bank during startup. The device offers selectable soft-start options of 1 ms, 2 ms, 4 ms and 8 ms. When the
device is enabled (either by EN or VDD UVLO), the reference voltage ramps from 0 V to the final level defined by
VSEL pin strap configuration, in a given soft-start time. The TPS548D21 device supports several soft-start times
between 1msec and 8msec selected by MODE pin configuration. Refer to MODE definition table for details.
7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
The TPS548D21 device provides fixed VDD undervoltage lockout threshold and hysteresis. The typical VDD
turn-on threshold is 4.25 V and hysteresis is 0.2 V. The VDD UVLO can be used in conjunction with the
EN_UVLO signal to provide proper power sequence to the converter design. UVLO is a non-latched protection.
7.3.6 EN_UVLO Pin Functionality
The EN_UVLO pin drives an input buffer with accurate threshold and can be used to program the exact required
turn-on and turn-off thresholds for switcher enable, VDD UVLO or VIN UVLO (if VIN and VDD are tied together).
If desired, an external resistor divider can be used to set and program the turn-on threshold for VDD or VIN
UVLO.
12
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Feature Description (continued)
Figure 13 shows how to program the input voltage UVLO using the EN_UVLO pin.
29
28
26
25
24
23
22
21
DRGND
VDD
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PGND 20
PGND 19
PGND 18
TPS548D21
PGND 17
PGND 16
EN_UVLO
PGND 15
PGND 14
PGND 13
4
PVIN
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Figure 13. Programming the UVLO Voltage
7.3.7 Fault Protections
This section describes positive and negative overcurrent limits, overvoltage protections, undervoltage protections
and over temperature protections.
7.3.7.1 Current Limit (ILIM) Functionality
240
TRIP Pin Resistance (:)
210
180
150
120
90
60
30
0
0
10
20
30
40
50
OCP Valley Current (A)
60
70
80
D001
Figure 14. Current Limit Resistance vs OCP Valley Overcurrent Limit
The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, RILIM. In order
to provide both good accuracy and cost effective solution, TPS548D21 device supports temperature
compensated internal MOSFET RDS(on) sensing.
Also, the TPS548D21 device performs both positive and negative inductor current limiting with the same
magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the
high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.
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Feature Description (continued)
The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit
has 3000 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (RDS(on)).
The GND pin is used as the positive current sensing node.
TPS548D21 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored during the
OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. VILIM sets the valley level of the inductor current.
7.3.7.2 VDD Undervoltage Lockout (UVLO)
The TPS548D21 device has an UVLO protection function for the VDD supply input. The on-threshold voltage is
4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO
pin voltage. The supply voltage (VVDD) must be above the on-threshold to begin the pin strap detection.
7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage
becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The
UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS548D21 device operates in this cycle until the output
voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side
FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the
EN pin.
During the AVSO operation with the MODE[3] = '1' and MODE[2] = 2 = ”don't care”, the device is programmed to
regulate to the externally applied reference voltage source and use the internal soft-start ramp. The above
descriptions of the OVP and UVP functionality apply based on the external applied reference voltage. With the
MODE[3] = '0' and MODE[2] = '1', the device is programmed to regulate to the internal reference voltage and use
the externally applied soft-start ramp voltage. The above descriptions of the OVP and UVP functionality apply
based on the internal reference voltage."
Table 1. Overvoltage Protection Details
14
REFERENCE
VOLTAGE
(VREF)
SOFT-START
RAMP
STARTUP OVP
THRESHOLD
OPERATING
OVP
THRESHOLD
OVP DELAY
100 mV OD
(µs)
OVP RESET
Internal
Internal
1.2 × Internal
VREF
1.2 × Internal
VREF
1
UVP
Internal
External
1.2 × Internal
VREF
1.2 × Internal
VREF
1
UVP and
VSEL <0>
External
Internal
Fixed 1.5 V
during initial
startup
1.2 × Final
external
reference
1
UVP and
VSEL <0>
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7.3.7.4 Overtemperature Protection
TPS548D21 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature
exceeds the threshold value (default value 165°C), TPS548D21 device is shut off. When the temperature falls
about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.
7.4 Device Functional Modes
7.4.1 DCAP3 Control Topology
The TPS548D21 employs an artificial ramp generator that stabilizes the loop. The ramp amplitude is
automatically adjusted as a function of selected switching frequency (fSW) The ramp amplitude is a function of
duty cycle (VOUT-to-VIN ratio). Consequently, two additional pin-strap bits (FSEL[2:1]) are provided for fine tuning
the internal ramp amplitude. The device uses an improved DCAP3 control loop architecture that incorporates a
steady-state error integrator. The slow integrator improves the output voltage DC accuracy greatly and presents
minimal impact to small signal transient response. To further enhance the small signal stability of the control
loop, the device uses a modified ramp generator that supports a wider range of output LC stage.
7.4.2 DCAP Control Topology
For advanced users of this device, the internal DCAP3 ramp can be disabled using the MODE[4] pin strap bit.
This situation requires an external RCC network to ensure control loop stability. Place this RCC network across
the output inductor. Use a range between 10 mV and 15 mV of injected RSP pin ripple. If no feedback resistor
divider network is used, insert a 10-kΩ resistor between the VOUT pin and the RSP pin.
7.5 Programming
7.5.1 AVSO
See Progammable Analog Configurations
7.5.2 Programmable Pin-Strap Settings
FSEL, VSEL and MODE. Description: a 1% or better 100-kΩ resistor is needed from BP to each of the three
pins. The bottom resistor from each pin to ground (see Table 2) in conjunction with the top resistor defines each
pin strap selection. The pin detection checks for external resistor divider ratio during initial power up (VDD is
brought down below approximately 3 V) when BP LDO output is at approximately 2.9 V.
7.5.2.1 Frequency Selection (FSEL) Pin
The TPS548D21 device allows users to select the switching frequency, light load and internal ramp amplitude by
using FSEL pin. Table 2 lists the divider resistor values for the selection. The 1% tolerance resistors with typical
temperature coefficient of ±100ppm/°C are recommended. Higher performance resistors can be used if tighter
noise margin is required for more reliable frequency selection detection.
FSEL pin strap configuration programs the switching frequency, internal ramp compensation and light load
conduction mode.
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Programming (continued)
Table 2. FSEL Pin Strap Configurations
FSEL[4]
FSEL[3]
FSEL[1:0]
11: 1.05 MHz
10: 875 kHz
01: 650 kHz
00: 425 kHz
(1)
16
FSEL[2]
FSEL[1]
FSEL[0]
RFSEL (kΩ)
RCSP_FSEL[1:0]
CM
11: R × 3
1: FCCM
Open
10: R × 2
1: FCCM
165
01: R × 1
1: FCCM
133
00: R/2
1: FCCM
110
11: R × 3
1: FCCM
90.9
10: R × 2
1: FCCM
75
01: R × 1
1: FCCM
60.4
00: R/2
1: FCCM
47.5
11: R × 3
1: FCCM
37.4
10: R × 2
1: FCCM
29.4
01: R × 1
1: FCCM
22.1
00: R/2
1: FCCM
16.5
11: R × 3
1: FCCM
12.1
10: R × 2
1: FCCM
7.87
01: R × 1
1: FCCM
4.64
00: R/2
1: FCCM
1.78
(1)
1% or better and connect to ground
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7.5.2.2 VSEL Pin
VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The
initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI
designated discrete internal reference voltages. Table 3 lists internal reference voltage selections.
Table 3. Internal Reference Voltage Selections
VSEL[4]
VSEL[3]
VSEL[2]
VSEL[1]
1111: 0.975 V
1110: 1.1992 V
1101: 1.1504 V
1100: 1.0996 V
1011: 1.0508 V
1010: 1.0000 V
1001: 0.9492 V
1000: 0.9023 V
0111: 0.9004 V
0110: 0.8496 V
0101: 0.8008 V
0100: 0.7500 V
0011: 0.6992 V
0010: 0.6504 V
0001: 0.5996 V
0000: 0.975 V
(1)
VSEL[0]
RVSEL (kΩ)
1: Latch-Off
Open
0: Hiccup
187
1: Latch-Off
165
0: Hiccup
147
1: Latch-Off
133
0: Hiccup
121
1: Latch-Off
110
0: Hiccup
100
1: Latch-Off
90.9
0: Hiccup
82.5
1: Latch-Off
75
0: Hiccup
68.1
1: Latch-Off
60.4
0: Hiccup
53.6
1: Latch-Off
47.5
0: Hiccup
42.2
1: Latch-Off
37.4
0: Hiccup
33.2
1: Latch-Off
29.4
0: Hiccup
25.5
1: Latch-Off
22.1
0: Hiccup
19.1
1: Latch-Off
16.5
0: Hiccup
14.3
1: Latch-Off
12.1
0: Hiccup
10
1: Latch-Off
7.87
0: Hiccup
6.19
1: Latch-Off
4.64
0: Hiccup
3.16
1: Latch-Off
1.78
0: Hiccup
0
(1)
1% or better and connect to ground
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7.5.2.3 DCAP3 Control and Mode Selection
The MODE pinstrap configuration programs the control topology REFIN_TRK pin functionality, and internal soft
start timing selections. The TPS548D21 device supports both DCAP3 and DCAP operation.
a. MODE[4] selection bit is used to set the control topology. If MODE[4] bit is “0”, it selects DCAP operation. If
MODE[4] bit is “1”, it selects DCAP3 operation.
b. MODE[3] and MODE[2] selection bits are used to set the REFIN_TRK pin functionality.
c. MODE[1] and MODE[0] selection bits are used to set the internal soft start timing.
Table 4. MODE Pin Selection
MODE[4]
MODE[3]
MODE[2]
MODE[1]
MODE[0]
133
10: 4 ms (2)
121
01: 2 ms
110
11: 8 ms
1: External
Reference
1: DCAP3
0: Internal SS
1: External SS
0: Internal
Reference
0: Internal SS
1: External
Reference
0: DCAP
0: Internal SS
1: External SS
0: Internal
Reference
0: Internal SS
(1)
(2)
RMODE (kΩ)
(2)
00: 1 ms
100
11: 8 ms
90.9
10: 4 ms
82.5
01: 2 ms
75
00: 1 ms
68.1
11: 8 ms (2)
60.4
10: 4 ms (2)
53.6
01: 2 ms
47.5
00: 1 ms
42.2
11: 8 ms (2)
22.1
(2)
19.1
10: 4 ms
01: 2 ms
16.5
00: 1 ms
14.3
11: 8 ms
12.1
10: 4 ms
10
01: 2 ms
7.87
00: 1 ms
6.19
11: 8 ms
4.64
10: 4 ms
3.16
01: 2 ms
1.78
00: 1 ms
0
(1)
1% or better and connect to ground
See Application Workaround to Support 4-ms and 8-ms SS Settings.
7.5.2.4 Application Workaround to Support 4-ms and 8-ms SS Settings
In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The
recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time
delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD_UVLO
level and the minimum turnon threshold of EN_UVLO is at least TDELAY_MIN.
TDELAY_MIN = K × VREF
where
•
•
•
K = 9 ms/V for SS setting of 4 ms
K = 18 ms/V for SS setting of 8 ms
VREF is the internal reference voltage programmed by VSEL pin strap
(1)
For example, if SS setting is 4 ms and VREF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8
ms, the minimum delay should be programmed at least 18 ms. See Figure 15 and Figure 16 for detailed timing
requirement.
18
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Figure 15. Proper Sequencing of VDD and EN_UVLO to Support the Use of 4-ms SS Setting
VDD
VDD_UVLO
Maximum Threshold
4.34 V
EN_UVLO
Minimum
TDELAY_MIN
EN_UVLO
Minimum ON Threshold 1.45 V
Figure 16. Minimum Delay Between VDD and EN_UVLO to Support the Use of 4-ms and 8-ms SS settings
The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.
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7.5.3 Programmable Analog Configurations
REFIN_TRK functionality:
• REFIN_TRK functionality is configured by MODE[3] and MODE[2] pin strap bits. See table for detailed
information regarding MODE bits.
• If MODE[3] = '0' and MODE[2] = '0', the device is programmed to regulate to the internal reference voltage
and use the internal soft start ramp. Therefore, one should not apply any external voltage source on the
REFIN_TRK pin.
• In MODE[3] = '0' and MODE[2] = '1', the device is programmed to regulate to the internal reference voltage
and use the externally applied soft start ramp voltage. Therefore, one must apply a voltage ramp that meets
the following requirements:
1. Must start from 0V.
2. The external applied ramp must begin to ramp up after the POD is complete.
3. Controlled rise time of at least 1 ms minimum duration.
4. The magnitude of the ramp voltage has to be at least 300 mV above the pre-selected internal reference
voltage as determined by the VSEL pin strap setting.
5. It is expected for the externally applied ramp voltage to rise to at least 1 V above the internal reference
voltage after it crosses over the threshold mentioned in #3.
• If MODE[3] = '1' and MODE[2] = 2 = ”don’t care”, the device is programmed to regulate to the externally
applied reference voltage source and use the internal soft start ramp. Therefore, one must supply a voltage
source on the REFIN_TRK pin that is between 0.5 V and 1.25 V. In addition, the output impedance of the
external voltage source must be much less than 100 kΩ. If the external voltage source must transition up and
down between any two voltage levels, the slew rate must be no more than 1 mV/µs. If the external voltage
source is between 0 V and 0.5 V, the control loop would remain functional but the regulation accuracy is not
specified. The external voltage source is not allowed to drive the REFIN_TRK pin above 1.25 V in order to
prevent the overvoltage fault event from happening at 1.5 V.
7.5.3.1 RSP/RSN Remote Sensing Functionality
RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for
output voltage programming, the RSP pin should be connected to the mid-point of the resistor divider and the
RSN pin should always be connected to the load return. In the case where feedback resistors are not required as
when the VSEL programs the output voltage set point, the RSP pin should be connected to the positive sensing
point of the load and the RSN pin should always be connected to the load return.
RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier.
The feedback resistor divider should use resistor values much less than 100 kΩ.
7.5.3.1.1 Output Differential Remote Sensing Amplifier
The examples in this section show simplified remote sensing circuitry where each example uses an internal
reference of 1.0 V. Figure 17 shows remote sensing without feedback resistors, with an output voltage set point
of 1 V. Figure 18 shows remote sensing using feedback resistors, with an output voltage set point of 5 V.
20
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TPS548D21
TPS548D21
38 RSN
38 RSN
39 RSP
39 RSP
40 VOSNS
40 VOSNS
BOOT
BOOT
5
5
Load
Load
+
+
±
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Figure 17. Remote Sensing Without Feedback
Resistors
±
Figure 18. Remote Sensing With Feedback
Resistors
7.5.3.2 Power Good (PGOOD Pin) Functionality
The TPS548D21 device has power-good output that registers high when switcher output is within the target. The
power-good function is activated after soft-start has finished. When the soft-start ramp reaches 300 mV above
the internal reference voltage, SSend signal goes high to enable the PGOOD detection function. If the output
voltage becomes within ±8% of the target value, internal comparators detect power-good state and the power
good signal becomes high after an 8 ms delay. If the output voltage goes outside of ±16% of the target value, the
power good signal becomes low after two microsecond (2-µs) internal delay. The open-drain power-good output
must be pulled up externally. The internal N-channel MOSFET does not pull down until the VDD supply is above
1.2 V.
During the AVSO operation with the MODE[3] = '1' and MODE[2] = 2 = ”don't care”, the device is programmed to
regulate to the externally applied reference voltage source and use the internal soft start ramp. All of the above
descriptions of the PGOOD functionality apply except the SSend signal goes high to enable the PGOOD
detection function when the external applied voltage source rise to 425 mV threshold.
In MODE[3] = '0' and MODE[2] = '0', the device is programmed to regulate to the internal reference voltage and
use the internal soft start ramp. All of the above descriptions of PGOOD functionality apply.
In MODE[3] = '0' and MODE[2] = '1', the device is programmed to regulate to the internal reference voltage and
use the externally applied soft start ramp voltage. All of the above descriptions of PGOOD functionality apply.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS548D21 device is a highly-integrated synchronous step-down DC-DC converters. These devices are
used to convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 40 A.
One of the key features for the TPS548D21 device is the ability to allow user to control the reference voltage with
the external source on the REFIN_TRK pin when the external tracking option is chosen by the pin strap resistor
value set by the MODE pin. The TPS548D21 device starts tracking from 0 V. The TPS548D21 operates in
FCCM in all operation. Note: If DCM at start-up is needed, please use the TPS549D22 device. Use the following
design procedure to select key component values for this family of devices.
22
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8.2 Typical Applications
8.2.1 TPS548D21 1.5-V to 16-V Input, 1-V Output, 40-A Converter
J1
VIN = 6V - 16V
C1
DNP 330uF
C11
100µF
DNP
C2
22µF
C12
330uF
C3
22µF
C13
22µF
C4
22µF
C5
22µF
DNPC14
22uF
DNPC15
22uF
TP5
SW
L1
C6
22µF
DNPC16
22uF
C7
22µF
DNPC17
22uF
C8
22µF
C18
22uF
C9
22µF
C19
22uF
C10
2200pF
C20
22µF
J2
PGND
R1
1.00
VDD
TP1
TP2
21
22
23
24
25
26
TP4
R6
200k
CNTL/EN_UVLO
J4
VDD
LOW
28
CNTL
R12
100k
C34
DNP
1uF
C35
1µF
CLK
DATA
ALERT
BP
DRGND
MODE
TP9
BP
C44
DNP
1uF
FSEL
C45
4.7µF
VSEL
TP12
ILIM
4
3
2
1
FSEL
VSEL
ILIM
REFIN_TRK
VOSNS
U1
C46
35
RSP
39
250nH
R10
0
TP6
DNPC21
R5
DNP
470pF
1.50k
C22
0.1µF
100k
DNP
C36
1000pF
NC
27
13
14
15
16
17
18
19
20
29
30
41
R8 DNPC32
1.10k 6800pF
J3
R3
DNP
0
VOUT = 1V
I_OUT = 40A MAX
C25
100µF
C26
100µF
C27
100µF
C28
100µF
C29
100µF
DNPC30
100uF
C23
470µF
C24
470µF
C33
100µF
R14
DNP
0
38
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
DRGND
AGND
PAD
R11
0
CHA
C31
DNP
0.1uF
R13
TP7
TP3
Remote Sense pos/neg should run as balanced pair
R4
0
CHB
R7
0
TP19
R9
PGOOD
DNP
3.01
TP8 BP
PGND
RSN
32
40
PGOOD
NU
NU
NU
BP
37
5
BOOT
EN_UVLO
MODE
DRGND
R19
137k
VDD
31
33
6
7
8
9
10
11
12
SW
SW
SW
SW
SW
SW
SW
34
36
TP14
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
R2
DNP
0
R15
10.0k
C39
100µF
C40
100µF
C41
100µF
C42
100µF
DNPC43
100uF
C37
DNP470uF
C38
470µF
R16
J5
0
TP10
TP13
TP18
PGND
PGND
NT1
NT2
Net-Tie
Net-Tie
R17
DNP
0
TP11
R18
DNP
0
PGND
TPS548D21RVF
1000pF
AGND DRGND PGND AGND
BP
R20
100k
DRGND
R21
100k
R22
100k
J6
1
3
5
7
9
DNP
2
4
6
8
10
DATA
TP17
ADDR
ALERT
TP16
MODE
CLK
TP15
VSEL
PGND
----- GND NET TIES -----
AGND
TP20
CLK DNP
TP21
DATADNP
TP22
DNP
ALERT
PMBus
VSEL
MODE
R23
37.4k
FSEL
R24
100k
R25
22.1k
AGND
AGND
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Figure 19. Typical Application Schematic
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8.2.2 Design Requirements
For this design example, use the input parameters shown in Table 5.
Table 5. Design Example Specifications
PARAMETER
VIN
Input voltage
VIN(ripple)
Input ripple voltage
VOUT
Output voltage
TEST CONDITION
MIN
TYP
MAX
5
12
16
V
0.4
V
IOUT = 40 A
1
Line regulation
5 V ≤ VIN ≤ 16 V
UNIT
V
0.5%
Load regulation
0 V ≤ IOUT ≤ 40 A
VPP
Output ripple voltage
IOUT = 40 A
20
mV
VOVER
Transient response overshoot
ISTEP = 24 A
90
mV
VUNDER
Transient response undershoot
ISTEP = 24 A
90
IOUT
Output current
5 V ≤ VIN ≤ 16 V
tSS
Soft-start time
VIN = 12 V
IOC
Overcurrent trip point (1)
η
Peak Efficiency
fSW
Switching frequency
(1)
0.5%
mV
40
IOUT = 20 A, VIN = 12 V, VDD = 5 V
A
1
ms
46
A
90%
650
kHz
DC overcurrent level
8.2.3 Design Procedure
8.2.3.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS548D21 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.3.2 Switching Frequency Selection
Select a switching frequency for the regulator. There is a trade off between higher and lower switching
frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and
smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher
switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.
In this design, a moderate switching frequency of 650 kHz achieves both a small solution size and a highefficiency operation with the frequency selected.
Select one of four switching frequencies and FSEL resistor values from Table 6. The recommended high-side
RFSEL value is 100 kΩ (1%). Choose a low-side resistor value from Table 6 based on the choice of switching
frequency. For each switching frequency selection, there are multiple values of RFSEL(LS) to choose from. In order
to select the correct value, additional considerations (internal ramp compensation and light load operation) other
than switching frequency need to be included.
24
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Table 6. FSEL Pin Selection
SWITCHING
FREQUENCY
fSW (kHz)
FSEL VOLTAGE
VFSEL (V)
MAXIMUM
MINIMUM
HIGH-SIDE RESISTOR
RFSEL(HS)
(kΩ) 1% or better
LOW-SIDE RESISTOR
RFSEL(LS) (kΩ)
1% or better
Open
187
165
1050
2.93
1.465
100
147
133
121
110
100
90.9
82.5
75
875
1.396
0.869
100
68.1
60.4
53.6
47.5
42.2
37.4
33.2
29.4
650
0.798
0.366
100
25.5
22.1
19.1
16.5
14.3
12.1
10
7.87
425
0.317
0
100
6.19
4.64
3.16
1.78
0
There is some limited freedom to choose FSEL resistors that have other than the recommended values. The
criteria is to ensure that for particular selection of switching frequency, the FSEL voltage is within the maximum
and minimum FSEL voltage levels listed in Table 6. Use Equation 2 to calculate the FSEL voltage. Select FSEL
resistors that include tolerances of 1% or better.
RFSEL(LS)
VFSEL = VBP(det) ´
RFSEL(HS) + RFSEL(LS)
where
•
VBP(det) is the voltage used by the device to program the level of valid FSEL pin voltage during initial device
start-up (2.9 V typ)
(2)
In addition to serving the frequency select purpose, the FSEL pin can also be used to program internal ramp
compensation (DCAP3) and light-load conduction mode. When DCAP3 mode is selected (see section 8.2.3.9),
internal ramp compensation is used for stabilizing the converter design. The internal ramp compensation is a
function of the switching frequency (fSW) and the duty cycle range (the output voltage-to-input voltage ratio).
Table 7 summarizes the ramp choices using these functions.
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Table 7. Switching Frequency Selection
SWITCHING FREQUENCY
SETTING
(fSW) (kHz)
RAMP
SELECT
OPTION
425
650
875
1050
TIME
CONSTANT
t (µs)
VOUT RANGE
(FIXED VIN = 12 V)
DUTY CYCLE RANGE
(VOUT/VIN) (%)
MIN
MAX
MIN
MAX
R/2
9
0.6
0.9
5
7.5
R×1
16.8
0.9
1.5
7.5
12.5
R×2
32.3
1.5
2.5
12.5
21
R×3
55.6
2.5
5.5
>21
R/2
7
0.6
0.9
5
7.5
R×1
13.5
0.9
1.5
7.5
12.5
R×2
25.9
1.5
2.5
12.5
21
R×3
44.5
2.5
5.5
R/2
5.6
0.6
0.9
5
7.5
R×1
10.4
0.9
1.5
7.5
12.5
R×2
20
1.5
2.5
12.5
21
R×3
34.4
2.5
5.5
>21
R/2
3.8
0.6
0.9
5
7.5
R×1
7.1
0.9
1.5
7.5
12.5
R×2
13.6
1.5
2.5
12.5
21
R×3
23.3
2.5
5.5
>21
>21
The FSEL pin programs the light-load selection. TPS548D21 device supports FCCM operations. For better load
regulation from no load to full load, it is recommended to program the device to operate in FCCM mode.
RFSEL(LS) can be determined after determining the switching frequency, ramp and light-load operation. Table 2
lists the full range of choices.
8.2.3.3 Inductor Selection
To calculate the value of the output inductor, use Equation 3. The coefficient KIND represents the amount of
inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple
current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general,
maintain a KIND coefficient between 0 and 15 for balanced performance. Using this target ripple current, the
required inductor size can be calculated as shown in Equation 3
L1 =
VOUT
kVIN :max ; × fSW o
×
VIN F VOUT
kIOUT :max ; × K IND o
=
1 V × (16 V F 1 V)
= 0.24 JH
:16 V × 650 kHz × 40 A × 0.15;
(3)
Selecting a KIND of 0.15, the target inductance L1 = 250 nH. Using the next standard value, the 250 nH is chosen
in this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current,
and peak current can be calculated using Equation 4, Equation 5 and Equation 6. These values should be used
to select an inductor with approximately the target inductance value, and current ratings that allow normal
operation with some margin.
IRIPPLE =
VOUT
kVIN :max ; × fSW o
IL(rms ) = ¨(IOUT )² +
IL(peak )
×
VIN :max ; F VOUT
1 V × (16 V F 1 V)
=
= 5.64 A
16 V × 650 kHz × 250 nH
L1
1
× (IRIPPLE )² = 40 A
12
1
= (IOUT ) + × (IRIPPLE ) = 43 A
2
(4)
(5)
(6)
The Wurth ferrite 744309025 inductor is rated for 50 ARMS current, and 48-A saturation. Using this inductor, the
ripple current IRIPPLE= 5.64 A, the RMS inductor current IL(rms)= 40 A, and peak inductor current IL(peak)= 43 A.
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8.2.3.4 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
• Stability
• Regulator response to a change in load current or load transient
• Output voltage ripple
These three considerations are important when designing regulators that must operate where the electrical
conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these
three criteria.
8.2.3.4.1 Minimum Output Capacitance to Ensure Stability
To prevent sub-harmonic multiple pulsing behavior, TPS548D21 application designs must strictly follow the small
signal stability considerations described in Equation 7.
COUT (min ) >
t ON
zR
VREF
×
×
2
LOUT VOUT
where
•
•
•
•
•
•
COUT(min) is the minimum output capacitance needed to meet the stability requirement of the design
tON is the on-time information based on the switching frequency and duty cycle (in this design, 133 ns)
τ is the ramp compensation time constant of the design based on the switching frequency and duty cycle, (in
this design, 13.45 µs, refer to Table 7)
LOUT is the output inductance (in the design, 0.25 µH)
VREF is the user-selected reference voltage level (in this design, 1 V)
VOUT is the output voltage (in this design, 1 V)
(7)
The minimum output capacitance calculated from Equation 7 is 28.6 µF. The stability is ensured when the
amount of the output capacitance is 28.6 µF or greater. And when all MLCCs (multi-layer ceramic capacitors) are
used, both DC and AC derating effects must be considered to ensure that the minimum output capacitance
requirement is met with sufficient margin.
8.2.3.4.2 Response to a Load Transient
The output capacitance must supply the load with the required current when current is not immediately provided
by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects
the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.
Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load step and
release.
NOTE
There are other factors that can impact the amount of output capacitance for a specific
design, such as ripple and stability.
COUT :min _under ; =
2
V
× t SW
LOUT × k¿ILOAD :max ; o × l OUT
VIN:min ; + t OFF :min ; p
VIN:min ; VOUT
2 × ¿VLOAD :insert ; × Fl V
p × t SW
IN:min ;
t OFF :min ; G × VOUT
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2
COUT :min _over ;
LOUT × k¿ILOAD :max ; o
=
2 × ¿VLOAD :release ; × VOUT
where
•
•
•
•
•
•
•
•
•
•
COUT(min_under) is the minimum output capacitance to meet the undershoot requirement
COUT(min_over)is the minimum output capacitance to meet the overshoot requirement
L is the output inductance value (0.25 µH)
∆ILOAD(max) is the maximum transient step (24 A)
VOUT is the output voltage value (1 V)
tSW is the switching period (1.538 µs)
VIN(min) is the minimum input voltage for the design (10.8 V)
tOFF(min) is the minimum off time of the device (300 ns)
∆VLOAD(insert) is the undershoot requirement (30 mV)
∆VLOAD(release) is the overshoot requirement (30 mV)
(9)
Most of the above parameters can be found in Table 5.
The minimum output capacitance to meet the undershoot requirement is 969 µF. The minimum output
capacitance to meet the overshoot requirement is 2400 µF. This example uses a combination of POSCAP and
MLCC capacitors to meet the overshoot requirement.
• POSCAP bank #1: 4 × 470 µF, 2.5 V, 6 mΩ per capacitor
• MLCC bank #2: 10 × 100 µF, 2.5 V, 1 mΩ per capacitor with DC+AC derating factor of 60%
Recalculating the worst-case overshoot using the described capacitor bank design, the overshoot is 29 mV,
which meets the 30 mV overshoot specification requirement.
8.2.3.4.3 Output Voltage Ripple
The output voltage ripple is another important design consideration. Equation 10 calculates the minimum output
capacitance required to meet the output voltage ripple specification. This criterion is the requirement when the
impedance of the output capacitance is dominated by ESR.
COUT (min )RIPPLE =
IRIPPLE
= 108 JF
8 × fSW × VOUT :ripple ;
(10)
In this case, the maximum output voltage ripple is 10 mV. For this requirement, the minimum capacitance for
ripple requirement yields 108 µF. Because this capacitance value is significantly lower compared to that of
transient requirement, determine the capacitance bank from step 8.2.3.3.2. Because the output capacitor bank
consists of both POSCAP and MLCC type capacitors, it is important to consider the ripple effect at the switching
frequency due to effective ESR. Use Equation 11 to determine the maximum ESR of the output capacitor bank
for the switching frequency.
IRIPPLE
VOUT:ripple; F
8 × fSW × COUT
ESR MAX =
= 1.7 m3
IRIPPLE
(11)
Estimate the effective ESR at the switching frequency by obtaining the impedance vs. frequency characteristics
of the output capacitors. The parallel impedance of capacitor bank #1 and capacitor bank #2 at the switching
frequency of the design example is estimated to be 1.2 mΩ, which is less than that of the maximum ESR value.
Therefore, the output voltage ripple requirement (7 mV) can be met. For detailed calculation on the effective ESR
please contact the factory to obtain a user-friendly Excel based design tool.
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8.2.3.5 Input Capacitor Selection
The TPS548D21 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a
value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input
decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high
switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage
ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple to the device during full load. The input ripple current can be
calculated using Equation 12.
(VIN :min ; F VOUT )
VOUT
ICIN (rms ) = IOUT (max ) × ¨
×
= 16 Arms
VIN :min ;
VIN :min ;
(12)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 13 and Equation 14. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a
resistive portion, VRIPPLE(esr).
CIN (min ) =
IOUT (max ) × VOUT
= 38.5 JF
VRIPPLE :cap ; × VIN :max ; × fSW
ESR CIN (max )
(13)
VRIPPLE(ESR)
=
= 7 m3
I
IOUT :max ; + @ RIPPLE A
2
(14)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input
ripple for VRIPPLE(cap), and 0.3-V input ripple for VRIPPLE(esr). Using Equation 13 and Equation 14, the minimum
input capacitance for this design is 38.5 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25V ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for
the power stage.
8.2.3.6 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with
a voltage rating of 25 V or higher.
8.2.3.7 BP Pin
Bypass the BP pin to DRGND with 4.7-µF of capacitance. In order for the regulator to function properly, it is
important that these capacitors be localized to the TPS548D21 , with low-impedance return paths. See Layout
Guidelines section for more information.
8.2.3.8 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS548D21 within absolute maximum ratings without ringing reduction
techniques, some designs may require external components to further reduce ringing levels. This example uses
two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between
the SW area and GND.
The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the
outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and
discharge once the high-side MOSFET is turned on. For this example twoone 2.2-nF, 25-V, 0603-sized highfrequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Its ideal
placement is shown in Figure 19.
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Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF
capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125
W, nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.
8.2.3.9 Optimize Reference Voltage (VSEL)
Optimize the reference voltage by choosing a value for RVSEL. The TPS548D21 device is designed with a wide
range of precision reference voltage support from 0.6 V to 1.2 V with an available step change of 50 mV.
Program these reference voltages using the VSEL pin strap configurations. Please refer to Table 3 for internal
reference voltage selections. In addition to providing initial boot voltage value, use the VSEL pin to program
hiccup and latch-off mode.
There are two ways to program the output voltage set point. If the output voltage set point is one of the 16
available reference and boot voltage options, no feedback resistors are required for output voltage programming.
In the case where feedback resistors are not needed, connect the RSP pin to the positive sensing point of the
load. Always connect the RSN pin to the load return sensing point.
In this design example, since the output voltage set point is 1V, selecting RVSEL(LS) of either 75 kΩ (latch off) or
68.1 kΩ (hiccup) as shown in . If the output voltage set point is NOT one of the 16 available reference or boot
voltage options, feedback resistors are required for output voltage programming. Connect the RSP pin to the
mid-point of the resistor divider. Always connect the RSN pin to the load return sensing point as shown in
Figure 17 and Figure 18.
The general guideline to select boot and internal reference voltage is to select the reference voltage closest to
the output voltage set point. In addition, because the RSP and RSN pins are extremely high-impedance input
terminals of the true differential remote sense amplifier, use a feedback resistor divider with values much less
than 100 kΩ.
8.2.3.10 MODE Pin Selection
MODE pin strap configuration is used to program control internal/external reference, and internal/external soft
start timing selections. TPS548D21 supports both DCAP3 and DCAP operation. For general POL applications, it
is strongly recommended to configure the control topology to be DCAP3 due to its simple to use and no external
compensation features. In the rare instance where DCAP is needed, an RCC network across the output inductor
is needed to generate sufficient ripple voltage on the RSP pin. In this design example, RMODE(LS) of 42.2 kΩ is
selected for DCAP3 and soft start time of 1 ms.
8.2.3.11 Overcurrent Limit Design.
The TPS548D21 device uses the ILIM pin to set the OCP level. Connect the ILIM pin to GND through the voltage
setting resistor, RILIM. In order to provide both good accuracy and cost effective solution, this device supports
temperature compensated MOSFET on-resistance (RDS(on)) sensing. Also, this device performs both positive and
negative inductor current limiting with the same magnitudes. Positive current limit is normally used to protect the
inductor from saturation therefore causing damage to the high-side and low-side FETs. Negative current limit is
used to protect the low-side FET during OVP discharge.
The inductor current is monitored by the voltage between PGND pin and SW pin during the OFF time. The ILIM
pin has 3000 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance. The
PGND pin is used as the positive current sensing node.
TPS548D21 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. The voltage on the ILIM pin (VILIM) sets the valley level of the inductor current. The range
of value of the RILIM resistor is between 21 kΩ and 237 kΩ. The range of valley OCL is between 6.25 A and 75 A
(typical). If the RILIM resistance is outside of the recommended range, OCL accuracy and function cannot be
ensured. (see Table 8)
30
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Table 8. Closed Loop EVM Measurement of OCP Settings
RILIM
(kΩ)
OVERCURRENT PROTECTION VALLEY (A)
MIN
NOM
MAX
237
—
75
—
127
36
40
44
95.3
27
30
33
63.4
18
20
22
32.4
9
10
11
21
—
6.25
—
Use Equation 15 to relate the valley OCL to the RILIM resistance.
OCLVALLEY = 0.3178 × R ILIM F 0.3046
where
•
•
RILIM is in kΩ
OCLVALLEY is in A
(15)
In this design example, the desired valley OCL is 43 A, the calculated RILIM is 137 kΩ. Use Equation 16 to
calculate the DC OCL to be 46 A.
OCLDC = OCLVALLEY + 0.5 × IRIPPLE
where
•
•
RILIM is in kΩ
OCLDC is in A
(16)
In an overcurrent condition, the current to the load exceeds the inductor current and the output voltage falls.
When the output voltage crosses the under-voltage fault threshold for at least 1msec, the behavior of the device
depends on the VSEL pin strap setting. If hiccup mode is selected, the device will restart after 16-ms delay (1-ms
soft-start option). If the overcurrent condition persists, the OC hiccup behavior repeats. During latch-off mode
operation the device shuts down until the EN pin is toggled or VDD pin is power cycled.
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8.2.4
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Application Curves
100
95
Efficiency (%)
90
85
80
75
70
65
60
0
FCCM
VIN = 12 V
VDD = 5 V
4
8
12
16
20
24
Load Current (A)
28
32
36
40
D001
fSW = 625 kHz
VOUT = 1 V
Figure 20. Efficiency vs. Load Current
Figure 21. Transient Response Peak-to-Peak
Figure 22. REAL Tracking 0 V to 1.2 V
Figure 23. Sequencing From 0 V to 3.3 V
VIN = 12 V
VOUT = 1 V
fSW = 650 kHz
Airflow = 200 LFM
IOUT = 40 A
Figure 24. Thermal Image
32
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9 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 1.5 V and 16 V. Ensure the supply is
well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance,
as is the quality of the PCB layout and grounding scheme. See the recommendations in the Layout section.
10 Layout
10.1 Layout Guidelines
Consider these layout guidelines before starting a layout work using TPS548D21.
• It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14,
15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or
plane.
• Include as many thermal vias as possible to support a 40-A thermal operation. For example, a total of 35
thermal vias are used (outer diameter of 20 mil) in the TPS548D21EVM-784 available for purchase at ti.com.
(SLUUBG3)
• Placed the power components (including input/output capacitors, output inductor and TPS548D21device) on
one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground,
in order to shield and isolate the small signal traces from noisy power lines.
• Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the
input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF)
as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch
node ringing.
• Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane
connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace
connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
• Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output
inductor) are as short and wide as possible. In the TPS548D21EVM-784 EVM design, the SW trace width is
200 mil. Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine
these connections.
• Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and
FSEL) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise
coupling. In addition, place MODE, VSEL and FSEL programming resistors near the device pins.
• The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high
impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.
Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit
uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load
sense point) for accurate output voltage result.
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10.2 Layout Example
34
Figure 25. EVM Top View
Figure 26. EVM Top Layer
Figure 27. EVM Inner Layer 1
Figure 28. EVM Inner Layer 2
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Layout Example (continued)
Figure 29. EVM Inner Layer 3
Figure 30. EVM Inner Layer 4
Figure 31. EVM Bottom Layer
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Layout Example (continued)
10.2.1 Mounting and Thermal Profile Recommendation
Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the
reflow process can affect electrical performance. Figure 32 shows the recommended reflow oven thermal profile.
Proper post-assembly cleaning is also critical to device performance. See the Application Report, QFN/SON PCB
Attachment, (SLUA271) for more information.
tP
Temperature (°C)
TP
TL
TS(max)
tL
TS(min)
rRAMP(up)
tS
rRAMP(down)
t25P
25
Time (s)
Figure 32. Recommended Reflow Oven Thermal Profile
Table 9. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
RAMP UP AND RAMP DOWN
rRAMP(up)
Average ramp-up rate, TS(max) to TP
3
°C/s
rRAMP(down)
Average ramp-down rate, TP to TS(max)
6
°C/s
PRE-HEAT
TS
Pre-heat temperature
tS
Pre-heat time, TS(min) to TS(max)
150
200
°C
60
180
s
REFLOW
TL
Liquidus temperature
TP
Peak temperature
tL
Time maintained above liquidus temperature, TL
tP
Time maintained within 5°C of peak temperature, TP
t25P
Total time from 25°C to peak temperature, TP
36
217
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°C
260
°C
60
150
s
20
40
s
480
s
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Product Folder Links: TPS548D21
TPS548D21
www.ti.com
SLUSCI8A – JULY 2016 – REVISED AUGUST 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS548D21 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP3, NexFET, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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www.ti.com
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS548D21RVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS548D21
TPS548D21RVFT
ACTIVE
LQFN-CLIP
RVF
40
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS548D21
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS548D21RVFR
LQFNCLIP
RVF
40
2500
330.0
16.4
5.35
7.35
1.7
8.0
16.0
Q1
TPS548D21RVFT
LQFNCLIP
RVF
40
250
180.0
16.4
5.35
7.35
1.7
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS548D21RVFR
LQFN-CLIP
RVF
40
2500
367.0
367.0
38.0
TPS548D21RVFT
LQFN-CLIP
RVF
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVF0040A
LQFN-CLIP - 1.52 mm max height
SCALE 2.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
7.1
6.9
C
1.52
1.32
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
3.3
36X 0.5
(0.2) TYP
0.1
13
12
2X
5.5
EXPOSED
THERMAL PAD
20
21
41
SYMM
5.3
0.1
32
1
40X
PIN 1 ID
(OPTIONAL)
40
33
SYMM
40X
0.3
0.2
0.1
0.05
C A B
0.5
0.3
4222989/B 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220.
www.ti.com
EXAMPLE BOARD LAYOUT
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.3)
6X (1.4)
40
33
40X (0.6)
1
32
40X (0.25)
2X
(1.12)
36X (0.5)
6X
(1.28)
41
SYMM
(6.8)
(5.3)
(R0.05) TYP
( 0.2) TYP
VIA
12
21
13
20
SYMM
(4.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222989/B 10/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.815) TYP
40
33
40X (0.6)
1
41
32
40X (0.25)
(1.28)
TYP
36X (0.5)
(0.64)
TYP
SYMM
(6.8)
(R0.05) TYP
8X
(1.08)
12
21
METAL
TYP
20
13
8X (1.43)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222989/B 10/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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