Texas Instruments | TLC5951 24-Channel, 12-Bit PWM LED Driver With 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control (Rev. E) | Datasheet | Texas Instruments TLC5951 24-Channel, 12-Bit PWM LED Driver With 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control (Rev. E) Datasheet

Texas Instruments TLC5951 24-Channel, 12-Bit PWM LED Driver With 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control (Rev. E) Datasheet
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TLC5951
SBVS127E – MARCH 2009 – REVISED JULY 2017
TLC5951 24-Channel, 12-Bit PWM LED Driver With 7-Bit Dot Correction
and 3-Group, 8-Bit Global Brightness Control
1 Features
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
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24-Channel Constant-Current Sink Output
Current Capability: 40 mA
Selectable Grayscale (GS) Control With PWM:
12-Bit (4096 Step), 10-Bit (1024 Step), 8-Bit (256
Step)
Three Independent Grayscale Clocks for Three
Color Groups
Dot Correction (DC): 7-Bit (128 Step)
Global Brightness Control (BC) for Each Color
Group: 8-Bit (256 Step)
Auto Display Repeat Function
Independent Data Port for GS and BC and DC
Data
Communication Path Between Each Data Port
LED Power-Supply Voltage up to 15 V
VCC = 3 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel = ±1.5%
– Device-to-Device = ±3%
CMOS Logic Level I/O
Data Transfer Rate: 30 MHz
33-MHz Grayscale Control Clock
Continuous Base LED-Open Detection (LOD)
Continuous Base LED-Short Detection (LSD)
Thermal Shutdown (TSD) With Auto Restart
Grouped Delay to Prevent Inrush Current
Operating Ambient Temperature: –40°C to 85°C
Packages: HTSSOP-38, QFN-40
2 Applications
•
•
Full-Color LED Displays
LED Signboards
3 Description
The TLC5951 device is a 24-channel, constantcurrent sink driver. Each channel has an individuallyadjustable, 4096-step, pulse-width modulation (PWM)
grayscale (GS) brightness control and 128-step
constant-current dot correction (DC). The dot
correction adjusts brightness deviation between
channels and other LED drivers. The output channels
are grouped into three groups of eight channels.
Each channel group has a 256-step global brightness
control (BC) function and an individual grayscale
clock input.
Device Information(1)
PART NUMBER
TLC5951
PACKAGE
BODY SIZE (NOM)
HTSSOP (38)
12.50 mm × 6.20 mm
VQFN (40)
6.00 × 6.00 mm
WQFN (40)
6.00 × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Multiple Daisy-Chained TLC5951 Devices)
VLED
GSSIN
DCSIN
...
...
...
...
...
...
OUTR0/G0/B0 . . . OUTR7/G7/B7
OUTR0/G0/B0 . . . OUTR7/G7/B7
GSSIN
GSSOUT
GSSIN
GSSOUT
DCSIN
DCSOUT
DCSIN
DCSOUT
GSSCK
GSLAT
DCSCK
GSSCK
GSLAT
GSLAT
DCSCK
XBLNK
DCSCK
VCC
XBLNK
GSCKR
Controller
GSSCK
GSCKR
GSCKG
GSCKG
GCCKB
GSCKB
TLC5951
IC1
GSCKR
GSCKG
GND
GSCKB
IREF
VCC
TLC5951
ICn
GND
IREF
RIREF
FLAGS
READ
VCC
XBLNK
VCC
RIREF
7
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5951
SBVS127E – MARCH 2009 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6
7.1 Absolute Maximum Ratings .................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions...................... 7
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics.......................................... 8
7.6 Switching Characteristics....................................... 10
7.7 Typical Characteristics ............................................ 15
8
Parameter Measurement Information ................ 20
8.1
Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 20
8.2 Test Circuits ............................................................ 20
9
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
22
23
23
10 Device and Documentation Support ................. 38
10.1
10.2
10.3
10.4
10.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
11 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2013) to Revision E
Page
•
Added WQFN package to the Device Information table......................................................................................................... 1
•
Changed Typical Application Circuit diagram......................................................................................................................... 1
•
Changed ordering of the OUTxy pin numbers in the Pin Functions table to match the pinout diagram ............................... 5
•
Deleted ESD rating specifications from the Absolute Maximum Ratings table ..................................................................... 6
•
Added ESD Ratings table to the data sheet........................................................................................................................... 6
•
Added Thermal Information table to the data sheet ............................................................................................................... 7
•
Deleted Dissipation Ratings table from the data sheet .......................................................................................................... 7
Changes from Revision C (August 2013) to Revision D
Page
•
Added ΔIOLC5 and ΔIOLC6 parameters to Electrical Characteristics table ................................................................................ 9
•
Added footnote 6 to footnote 9 in Electrical Characteristics table.......................................................................................... 9
Changes from Revision B (December 2009) to Revision C
Page
•
Changed AC Characteristics, tWH0 and tWL0 parameter associated pin names ..................................................................... 7
•
Updated Figure 3.................................................................................................................................................................. 12
•
Updated Figure 4.................................................................................................................................................................. 13
•
Updated Figure 7.................................................................................................................................................................. 15
•
Updated Figure 33................................................................................................................................................................ 18
•
Updated Figure 48................................................................................................................................................................ 35
•
Changed description of Continuous Base LOD, LSD, and TEF section .............................................................................. 37
Changes from Revision A (April 2009) to Revision B
Page
•
Changed product status from mixed to production data ........................................................................................................ 1
•
Deleted footnote 1 from RHA pinout ...................................................................................................................................... 4
•
Changed test conditions of tD8 in Switching Characteristics table........................................................................................ 10
2
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SBVS127E – MARCH 2009 – REVISED JULY 2017
•
Changed header for second column in Table 9 ................................................................................................................... 33
•
Changed description for bits 175–168, 183–176, and 191–184 in Table 13 ....................................................................... 36
Changes from Original (March 2009) to Revision A
Page
•
Changed TSU3 minimum specification to 40 ns in the Recommended Operating Conditions table ....................................... 7
•
Changed VO minimum specification to maximum specification in the Recommended Operating Conditions table .............. 7
•
Changed IOH minimum specification to maximum specification in the Recommended Operating Conditions table .............. 7
•
Changed IOL minimum specification to maximum specification in the Recommended Operating Conditions table............... 7
•
Changed IOLC minimum specification to maximum specification in the Recommended Operating Conditions table............. 7
•
Changed fCLK (SCLK) minimum specification to maximum specification in the Recommended Operating Conditions table..... 7
•
Changed fCLK (GSCKR/G/B) minimum specification to maximum specification in the Recommended Operating Conditions
table ........................................................................................................................................................................................ 7
•
Changed ICC2 typical value to 6 mA in the Electrical Characteristics table ............................................................................ 8
•
Changed ICC3 typical value to 12 mA and maximum value to 27 mA in the Electrical Characteristics table ......................... 8
•
Changed ICC4 typical value to 21 mA and maximum value to 55 mA in the Electrical Characteristics table ......................... 8
•
Changed ΔIOLC2 typical value to ±1% in the Electrical Characteristics table .......................................................................... 8
•
Changed ΔIOLC3 typical value to ±0.5% in the Electrical Characteristics table ....................................................................... 8
•
Changed fourth paragraph of Maximum Constant Sink Current Value section to reference correct graph......................... 24
•
Changed DC function adjustment range description to reflect proper adjustment range for each control in Dot
Correction (DC) Function section ......................................................................................................................................... 24
•
Changed brightness control to dot correction data in 288-Bit Common Shift Register section ........................................... 30
•
Corrected number of bits contained within the DC, BC, FC, and UD shift register in the DC, BC, FC, and UD Shift
Register section .................................................................................................................................................................... 32
•
Corrected typo about which bits are written in the DC, BC, FC, and UD Data Latch section.............................................. 32
•
Corrected percentage of adjustment rage selected in the Dot Correction Data Latch section ............................................ 32
•
Deleted second paragraph of Status Information Data (SID) section .................................................................................. 34
•
Updated LOD bit = 1 condition description in the Continuous Base LOD, LSD, and TEF section ...................................... 37
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SBVS127E – MARCH 2009 – REVISED JULY 2017
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5 Description (Continued)
GS, DC, and BC data are accessible via a serial interface port. DC and BC can be programmed via a dedicated
serial interface port.
The TLC5951 device has three error-detection circuits for LED-open detection (LOD), LED-short detection (LSD),
and thermal error flag (TEF). LOD detects a broken or disconnected LED, LSD detects a shorted LED, and TEF
indicates an overtemperature condition.
6 Pin Configuration and Functions
DAP PowerPAD Package
38-Pin HTSSOP With Exposed Thermal Pad
(Top View)
32
OUTG7
OUTB7
29
OUTG6
28
OUTR6
Pad
NC
4
27
GSSCK
GSSOUT
5
26
GSSIN
Thermal
Pad
DCSOUT
6
25
DCSIN
NC
7
24
DCSCK
OUTB4
8
23
XBLNK
OUTR4
9
22
VCC
OUTG4
10
21
IREF
OUTG3
16
23
OUTG4
OUTR3
17
22
OUTR4
OUTB3
18
21
OUTB4
GSSOUT
19
20
DCSOUT
Not to scale
20
OUTB5
19
24
GND
15
OUTG7
OUTB2
18
OUTR5
17
OUTG5
25
OUTB7
26
14
OUTR7
13
OUTR2
16
OUTG2
OUTG6
OUTB6
15
27
GSLAT
14
12
GSCKG
28
OUTB6
OUTB1
29
3
OUTR6
11
30
2
OUTB3
13
OUTR1
Thermal
OUTR3
12
10
GSCKR
OUTR5
9
OUTR7
30
OUTG5
OUTB0
OUTG1
31
1
11
8
OUTG3
OUTB5
OUTR0
GSCKB
7
OUTG0
OUTG0
31
GND
32
33
OUTR0
6
OUTB0
IREF
GSCKB
33
34
34
5
OUTG1
VCC
GSCKR
OUTR1
35
35
4
OUTB1
XBLNK
GSCKG
36
36
37
3
OUTG2
DCSCK
GSLAT
OUTR2
DCSIN
37
38
38
2
39
1
OUTB2
GSSIN
GSSCK
40
RHA and RTA Packages
40-Pin VQFN and WQFN With Exposed Thermal Pads
(Top View)
Not to scale
NC = no internal connection
Pin Functions
PIN
NAME
NO.
DAP
I/O
DESCRIPTION
RHA, RTA
DCSCK
37
24
I
Serial-data shift clock for the 216-bit DC, BC, FC, and UD shift register. Data
present on DCSIN are shifted into the LSB of the shift register with the DCSCK
rising edge. Data in the shift register are shifted toward the MSB at each DCSCK
rising edge. The MSB data of the register appear on DCSOUT. The 216-bit data in
the shift register are automatically copied to the DC, BC, FC, and UD data latch 3
ms to 7 ms following the last rising edge after DCSCK stops switching.
DCSIN
38
25
I
Serial data input for the 216-bit DC, BC, FC, and UD shift register. DCSIN is
connected to the LSB of the shift register.
DCSOUT
20
6
O
Serial data output of the 216-bit shift register. DCSOUT is connected to the MSB of
the shift register. Data are clocked out at the rising edge of DCSCK.
GND
33
20
—
Power ground
GSCKB
6
31
I
Reference clock for the GS PWM control for the BLUE LED output group. When
XBLNK is high, each GSCKR rising edge increments the BLUE LED GS counter
for PWM control.
GSCKG
4
29
I
Reference clock for the GS PWM control for the GREEN LED output group. When
XBLNK is high, each GSCKR rising edge increments the GREEN LED GS counter
for PWM control.
4
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SBVS127E – MARCH 2009 – REVISED JULY 2017
Pin Functions (continued)
PIN
NAME
GSCKR
GSLAT
GSSCK
NO.
DAP
RHA, RTA
5
30
3
2
28
27
I/O
DESCRIPTION
I
Reference clock for the GS pulse-width modulation (PWM) control for the RED
LED output group. When XBLNK is high, each GSCKR rising edge increments the
RED LED GS counter for PWM control.
I
Data in the 288-bit common shift register are copied to the GS data latch or to the
DC, BC, and FC data latch at the rising edge of GSLAT. The level of GSLAT at the
last GSSCK before the GSLAT rising edge determines which of the two latches the
data are transferred into. When GSLAT is low at the last GSSCK rising edge, all
288 bits in the common shift register are copied to the GS data latch. When
GSLAT is high at the last GSSCK rising edge, bits 0–198 are copied to the DC,
BC, and FC data latch and bits 199–215 are copied to the 216-bit DC, BC, FC, and
UD shift register. The GSLAT rising edge for a DC, BC, FC, and UD data write
must be input more than 7 ms after a data write through the DCSIN pin.
I
Serial data shift clock for the 288-bit common shift register for GS, DC, BC, and FC
data. Data present on GSSIN are shifted into the LSB of the shift register with the
rising edge of GSSCK. Data in the shift register are shifted toward the MSB at
each rising edge of GSSCK. The MSB data of the shift register appear on
GSSOUT.
GSSIN
1
26
I
Serial data input for the 288-bit common shift register for grayscale (GS), dot
correction (DC), global brightness control (BC), and function control (FC) data.
GSSIN is connected to the LSB of the 288-bit common shift register. This pin is
internally pulled to GND with a 500-kΩ resistor.
GSSOUT
19
5
O
Serial data output of the 288-bit common shift register. LED-open detection (LOD),
LED-short detection (LSD), thermal error flag (TEF), and 199-bit data in the DC,
BC, and FC data latch can be read via GSSOUT. GSSOUT is connected to the
MSB of the shift register. Data are clocked out at the rising edge of GSSCK.
IREF
34
21
I/O
A resistor connected between IREF and GND sets the maximum current for all
constant-current outputs.
NC
—
4, 7
—
No internal connection
O
Constant-current outputs for the BLUE LED group. These outputs are controlled
with the GSCKB clock signal.
The BLUE LED group is divided into four subgroups: OUTB0 and OUTB4,
OUTB1and OUTB5, OUTB2 and OUTB6, and OUTB3 and OUTB7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant-current
capability. Different voltages can be applied to each output.
O
Constant-current outputs for the GREEN LED group. These outputs are controlled
with the GSCKG clock signal.
The GREEN LED group is divided into four subgroups: OUTG0 and OUTG4,
OUTG1 and OUTG5, OUTG2 and OUTG6, and OUTG3 and OUTG7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant-current
capability. Different voltages can be applied to each output.
OUTB0–
OUTB7
OUTG0–
OUTG7
OUTR0–
OUTR7
VCC
XBLNK
9, 12, 15,
18, 21, 24,
27, 30
7, 10, 13,
16, 23, 26,
29, 32
34, 37, 40,
3, 8, 11, 14,
17
32, 35, 38,
1, 10, 13,
16, 19
8, 11, 14,
17, 22, 25,
28, 31
33, 36, 39,
2, 9, 12, 15,
18
O
Constant-current outputs for the RED LED group. These outputs are controlled
with the GSCKR clock signal.
The RED LED group is divided into four subgroups: OUTR0 and OUTR4, OUTR1
and OUTR5, OUTR2 and OUTR6, and OUTR3 and OUTR7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant-current
capability. Different voltages can be applied to each output.
35
22
—
Power supply
36
23
I
When XBLNK is low, all constant-current outputs (OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7) are forced off. The grayscale counters for
each color group are reset to 0, and the grayscale PWM timing controller is
initialized. When XBLNK is high, all constant-current outputs are controlled by the
grayscale PWM timing controller for each color LED. This pin is internally pulled to
GND with a 500-kΩ resistor.
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SBVS127E – MARCH 2009 – REVISED JULY 2017
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7 Specifications
Absolute Maximum Ratings (1)
7.1
(2)
Over operating ambient temperature range, unless otherwise noted.
MIN
MAX
–0.3
6
UNIT
V
50
mA
VCC
Supply voltage
VCC
IOUT
Output current (dc)
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7
VIN
Input voltage range
GSSIN, GSSCK, GSLAT, GSCKR, GSCKG, GSCKB, DCSIN,
DCSCK, XBLNK, IREF
–0.3
VCC + 0.3
V
VOUT
Output voltage range
GSSOUT, DCSOUT
–0.3
VCC + 0.3
V
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7
–0.3
16
V
TJ(max)
Operation junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
6
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3
SBVS127E – MARCH 2009 – REVISED JULY 2017
Recommended Operating Conditions
At TA = –40°C to 85°C, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS: VCC = 3 V to 5.5 V
VCC
Supply voltage
3
OUTR0–OUTR7, OUTG0–OUTG7,
OUTB0–OUTB7
5.5
V
15
V
V
VO
Voltage applied to output
VIH
High level input voltage
0.7 × VCC
VCC
VIL
Low level input voltage
GND
0.3 × VCC
IOH
High level output current
GSSOUT, DCSOUT
–1
mA
IOL
Low level output current
GSSOUT, DCSOUT
1
mA
IOLC
Constant output sink current
OUTR0–OUTR7, OUTG0–OUTG7,
OUTB0–OUTB7
40
mA
TA
Operating ambient
temperature
–40
85
°C
TJ
Operating junction
temperature
–40
125
°C
V
AC CHARACTERISTICS, VCC = 3 V to 5.5 V
fCLK (SCK)
Data-shift clock frequency
GSSCK, DCSCK
30
MHz
fCLK
Grayscale clock frequency
GSCKR, GSCKG, GSCKB
33
MHz
(GSCKR/G/B)
tWH0 and tWL0
GSSCK, DCSCK, GSCKR, GSCKG, GSCKB
10
ns
GSLAT
30
ns
tWL2
XBLNK
30
ns
tSU0
GSSIN → GSSCK↑, DCSIN → DCSCK↑
tSU1
XBLNK↑ → GSCKR↑, GSCKG↑, or GSCKB↑
tSU2
GSLAT↑ → GSSCK↑
tSU3
tWH1 and tWL1
Pulse duration
Setup time
tSU4
5
ns
10
ns
150
ns
GSLAT↑ for GS data → GSCKR↑, GSCKG↑,
or GSCKB↑ when display timing reset mode
is disabled
40
ns
GSLAT↑ for GS data → GSCKR↑, GSCKG↑,
or GSCKB↑ when display timing reset mode
is enabled
100
ns
GSSIN → GSSCK↑, DCSIN → DCSCK↑
tH0
tH1
Hold time
tH2
5
ns
GSLAT↑ → GSSCK↑
35
ns
GSLAT↓ → GSSCK↑
5
ns
7.4 Thermal Information
TLC5951
THERMAL METRIC (1)
DAP (HTSSOP)
RHA (VQFN)
RTA (WQFN)
38 PINS
40 PINS
40 PINS
UNIT
RθJA
Junction-to-ambient thermal resistanceDeleted Dissipation
Ratings
27.8
28
27.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
14.7
27.7
12.4
°C/W
RθJB
Junction-to-board thermal resistance
6.7
9.3
8.7
°C/W
ψJT
Junction-to-top characterization parameter
0.2
0.2
0.1
°C/W
ψJB
Junction-to-board characterization parameter
6.8
9.3
8.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
1.3
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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TLC5951
SBVS127E – MARCH 2009 – REVISED JULY 2017
7.5
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Electrical Characteristics
At TA = –40°C to 85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC
= 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
VOH
High-level output voltage
At GSSOUT, DCSOUT, IOH = –1 mA
VOL
Low-level output voltage
At GSSOUT, DCSOUT, IOL = 1 mA
Input current
At GSSCK, GSLAT, DCSIN, DCSCK, GSCKR, -G, -B with VI =
VCC,
At GSSIN, GSSCK, GSLAT, DCSIN, XBLNK, DCSCK, GSCKR, G, -B with VI = GND
II
TYP
MAX
UNIT
VCC
V
0.4
V
1
μA
VCC – 0.4
–1
ICC1
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,
GSCKR, -G, -B = low, VOUTRn/Gn/Bn = 1 V, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
RIREF = 24 kΩ (IOUTRn/Gn/Bn = 2 mA target)
1
3
mA
ICC2
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,
GSCKR, -G, -B = low, VOUTRn/Gn/Bn = 1 V, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
RIREF = 2.4 kΩ (IOUTRn/Gn/Bn = 20 mA target)
6
10
mA
ICC3
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,
GSCKR, -G, -B = 33 MHz, VOUTRn/Gn/Bn = 1 V,
GSRn, -Gn, -Bn = FFFh, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
RIREF = 2.4 kΩ (IOUTRn/Gn/Bn = 20 mA target), auto repeat on
12
27
mA
ICC4
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,
GSCKR, -G, -B = 33 MHz, VOUTRn/Gn/Bn = 1 V,
GSRn, -Gn, -Bn = FFFh, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target), auto repeat on
21
55
mA
IOLC
Constant output current
At OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
40
45
mA
IOLKG
Leakage output current
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
XBLNK = low, VOUTRn/Gn/Bn = VOUTfix = 15 V, RIREF = 1.2 kΩ
0.1
μA
ΔIOLC
Constant-current error (1)
(channel-to-channel in
same color group)
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±1.5%
±4%
ΔIOLC1
Constant-current error (2)
(color group to color
group in same device)
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±1%
±3%
Supply current
(1)
The deviation of each output in the same color group from the average of the same color group (OUTR0–OUTR7, OUTG0–OUTG7, or
D (%) =
(2)
35
IOUTXn (N = 0-7)
(IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7)
-1
´ 100
8
OUTB0–OUTB7) constant current. The deviation is calculated by the formula
,
where (X = R, G, or B; n = 0–7).
The deviation of each color group in the same device from the average of all constant current. The deviation is calculated by the formula
(IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7)
D (%) =
8
-1
´ 100
(IOUTR0+¼+IOUTR7 + IOUTG0+¼+IOUTG7 + IOUTB0+¼+IOUTB7)
24
8
, where (X = R, G, or B).
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Electrical Characteristics (continued)
At TA = –40°C to 85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC
= 3.3 V.
PARAMETER
ΔIOLC2
ΔIOLC3
TEST CONDITIONS
Constant-current error (3)
(device to device)
Line regulation
(4)
(5)
TYP
MAX
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
MIN
±1%
±6%
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±0.5
±2
%/V
At OUTR0–OUTR7, OUTG0–OUTG7 and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±1
±3
%/V
ΔIOLC4
Load regulation
ΔIOLC5
Constant-current
error (6) (7)
(channel-to-channel in
same device)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = On, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 0.5 V, TA = 25°C,
RIREF = 9.6 kΩ (IOUTRn/Gn/Bn = 5 mA target)
10%
ΔIOLC6
Constant-current
error (7) (8) (9)
(device-to-device)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = On, BCR, -G, -B = FFh,
DCRn, -Gn, -Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 0.5 V, TA = 25°C,
RIREF = 9.6 kΩ (IOUTRn/Gn/Bn = 5 mA target)
12%
(3)
UNIT
The deviation of the constant-current average from the ideal constant-current value. The deviation is calculated by the formula
(IOUTR0+¼+IOUTR7 + IOUTG0+¼+IOUTG7 + IOUTB0+¼+IOUTB7)
- (Ideal Output Current)
24
D (%) =
´ 100
Ideal Output Current
IOUT(IDEAL, mA) = 40 ´
Ideal current is calculated by the formula
D (%/V) =
(4)
(5)
(6)
´
100
5.5 V - 3 V
(IOUTXn at VOUTXn = 3 V) - (IOUTXn at VOUTXn = 1 V)
(IOUTXn at VOUTXn = 1 V)
´
, where (X = R, G, or B; n = 0–7).
100
3V-1V
Max (IOUT24) - Min (IOUT24)
(IOUTR0 + ... + IOUTR7 + IOUTG0 + ... + IOUTG7 + IOUTB0 + ... + IOUTB7)
.
24
Applicable only to QFN-40 package.
The deviation of the maximum of all 24 channels of 30 devices from the minimum of all 24 channels of 30 devices. The deviation is
calculated by
D (%) =
(9)
(IOUTXn at VCC = 3.0 V)
Load regulation is calculated by
, where (X = R, G, or B; n = 0–7).
The deviation of the maximum of all 24 channels from the minimum of all 24 channels of the same device. The deviation is calculated by
D (%) =
(7)
(8)
(IOUTXn at VCC = 5.5 V) - (IOUTXn at VCC = 3.0 V)
Line regulation is calculated by
D (%/V) =
1.20
RIREF (W)
Max [IOUTD1 (24 Ch), IOUTD2 (24 Ch)...IOUTD30 (24 Ch)] - Min [IOUTD1 (24 Ch), IOUTD2 (24 Ch)...IOUTD30 (24 Ch)]
Average [IOUTD1 (24 Ch), IOUTD2 (24 Ch)...IOUTD30 (24 Ch)]
.
Not production tested, verified by characterization.
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Electrical Characteristics (continued)
At TA = –40°C to 85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC
= 3.3 V.
PARAMETER
MIN
TYP
MAX
UNIT
Junction temperature
150
163
175
°C
Thermal error flag
hysteresis (10)
Junction temperature
5
10
20
°C
VLOD
LED open-detection
threshold
All OUTRn, -Gn, -Bn = on
0.2
0.25
0.3
V
VLSD
LED short-detection
threshold
All OUTRn, -Gn, -Bn = on
2.4
2.5
2.6
V
VIREF
Reference voltage output
RIREF = 1.2 kΩ
1.17
1.2
1.23
V
RPDWN
Pulldown resistor
At XBLNK, GSSIN
250
500
750
kΩ
TTEF
Thermal error flag
threshold (10)
THYS
TEST CONDITIONS
(10) Not tested; specified by design.
7.6
Switching Characteristics
At TA = –40°C to 85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 100 Ω, RIREF = 1.2 kΩ, and VLED = 5 V, unless otherwise noted.
Typical values are at TA = 25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
tR0
GSSOUT, DCSOUT
tR1
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
Rise time
TYP MAX UNIT
6
15
ns
10
30
ns
tF0
GSSOUT, DCSOUT
6
15
ns
tF1
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with dc high
adjustment range
10
30
ns
tD0
GSSCK↑ to GSSOUT, DCSCK↑ to DCSOUT
15
25
ns
tD1
GSLAT↑ to GSSOUT
50
100
ns
tD2
XBLNK↓ to OUTR0, OUTG0, OUTB0, OUTR4, OUTG4, OUTB4 off
20
40
ns
tD3
GSCKR, -G, -B↑ to OUTR0/G0/B0, OUTR4/G4/B4 on,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
5
18
40
ns
tD4
GSCKR, -G, -B↑ to OUTR1/G1/B1, OUTR5/G5/B5 on,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
20
42
73
ns
GSCKR, -G, -B↑ to OUTR2/G2/B2, OUTR6/G6/B6 on,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
35
66
106
ns
tD6
GSCKR, -G, -B↑ to OUTR3/G3/B3, OUTR7/G7/B7 on,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
50
90
140
ns
tD7
Internal latch pulse generation delay from DCSCK
3
5
7
ms
tD8
GSLAT↑ to IOUTRn/Gn/Bn changing by dot correction control
(control data are 0Ch → 72h or 72h → 0Ch with dc high adjustment
range), BCR, -G, -B = FFh
30
50
ns
tD9
GSLAT↑ to IOUTRn/Gn/Bn changing by global brightness control
(control data are 19h ≥ E6h or E6h ≥ 19h with DCRn, -Gn, -Bn = 7Fh
with DC high adjustment range)
100
300
ns
5
ns
Fall time
tD5
Propagation delay
tON_ERR
(1)
10
Output on-time error,
tOUT_ON – tGSCKR/G/B (1)
GSDATA = 001h, GSCKR, -G, -B = 33 MHz,
with BCR, -G, -B = FFh and DCRn, -Gn, -Bn = 7Fh with DC high
adjustment range
–15
Output on-time error (tON_ERR) is calculated by the formula tON_ERR (ns) = tOUT_ON – tGSCKR/G/B. tOUT_ON indicates the actual on-time of
the constant current driver. tGSCKR is the period of GSCKR, tGSCKG is the period of GSCKG, and tGSCKB is the period of GSCKB.
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SBVS127E – MARCH 2009 – REVISED JULY 2017
TWH0, TWL0, TWH1, TWL1, TWL2:
VCC
INPUT
50%
GND
TWH
TWL
TSU0, TSU1, TSU2, TSU3, TSU4, TH0, TH1, TH2:
VCC
CLOCK
(1)
INPUT
50%
GND
TSU
TH
VCC
DATA/CONTROL
(1)
INPUT
50%
GND
(1)
Input-pulse rise and fall times are 1 ns to 3 ns.
Figure 1. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5, tD6, tD7, tD8, tD9:
VCC
(1)
INPUT
50%
GND
tD
VOH or VOUTRn/Gn/BnH
90%
OUTPUT
50%
10%
VOL or VOUTRn/Gn/BnL
tR or tF
(2)
Input-pulse rise and fall times are 1 ns to 3 ns.
Figure 2. Output Timing
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TLC5951
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GSR0
0A
GSSIN
GSB7
11B
GSB7
10B
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GSB7
9B
GSB7
8B
GSR0
3B
GSB7
7B
GSR0
2B
TH0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
6C
GSB7
5C
1
2
3
4
5
6
7
GSB7
4C
GSB7
3C
TWH0
fCLK (SCLK)
TSU0
GSR0
0B
GSR0
1B
TSU2
GSSCK
1
2
3
4
5
285
286
287
288
TWL0
TH1
TWH1
GSLAT
TSU3, TSU4
XBLNK
fCLK (GSCKR/G/B)
TWL2
Shift Register Data Are Transferred to GS Data Latch
TSU1
GSCKR
(GSCKG)
(GSCKB)
TWH0
TWL0
Grayscale Data Latch
(Internal)
Dot Correction/
Brightness Control Function
Control Data Latch (Internal)
Previous Data
Latest Data
GSB7
10B
GSB7
9B
GSB7
8B
GSB7
7B
GSR0
3B
GSR0
2B
GSR0
1B
GSR0
0B
DCR0
Bit 0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
9C
GSB7
8C
GSB7
7C
Common Shift Register
Bit 1 (Internal)
DCR0
Bit 0
GSB7
11B
GSB7
10B
GSB7
9B
GSB7
8B
GSR0
4B
GSR0
3B
GSR0
2B
GSR0
1B
DCR0
Bit 1
DCR0
0B
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
9C
GSB7
8C
Common Shift Register
Bit 286 (Internal)
LOD
B6A
LOD
B5A
LOD
B4A
LOD
B3A
LOD
B2A
DCR0
1A
DCR0
0A
GSR0
11B
GSR0
10B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LOD
B2B
LOD
B1B
LOD
B0B
LOD
G7B
LOD
G6B
GSSOUT
LOD
B7A
LOD
B6A
LOD
B5A
LOD
B4A
LOD
B3A
DCR0
1A
DCR0
0A
GSB7
11B
LOD
B7B
¼
¼
¼
¼
GSB7
11B
¼
Common Shift Register
Bit 0 (Internal)
tD0
tR0/tF0
OUTR0, OUTR4
(OUTG0, OUTG4)
(OUTB0, OUTB4)
OFF
OUTR1, OUTR5
(OUTG1, OUTG5)
(OUTB1, OUTB5)
OFF
OUTR2, OUTR6
(OUTG2, OUTG6)
(OUTB2, OUTB6)
OFF
OUTR3, OUTR7
(OUTG3, OUTG7)
(OUTB3, OUTB7)
OFF
ON
(VOUTRnH)
DCR0
3A
DCR0
2A
LOD
B5B
LOD
B6B
LOD
B4B
SID Data Are Transferred to
288-Bit Common Shift Register
LOD
B3B
LOD
B2B
LOD
B1B
LOD
B0B
LOD
G7B
tD2
ON
(VOUTRnL)
tF1
tD3
ON
ON
tR1
tD4
ON
ON
tD5
ON
ON
tD6
Figure 3. Grayscale Data-Write Timing
12
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GSR0
0A
GSSIN
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
DCR0
3B
DCR0
2B
DCR0
1B
TH0
TWH0
fCLK (SCLK)
TSU0
DCR0
0B
TH1
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
1
2
3
4
5
6
7
8
9
TSU2
GSSCK
1
2
3
4
5
285
286
287
TWL0
288
TWL1
GSLAT
TH2
XBLNK
fCLK (GSCKR/G/B)
TWL2
Shift Register Data Are Transferred
to DC/BC/FC/UD Data Latch
TSU1
GSCKR
(GSCKG)
(GSCKB)
TWH0
TWL0
Grayscale Data Latch
(Internal)
Dot Correction/
Brightness Control Function
Control Data Latch (Internal)
Latest Data
Previous Data
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
DCR0
3B
DCR0
2B
DCR0
1B
DCR0
0B
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
Common Shift Register
Bit 1 (Internal)
DCR0
1A
DCR0
0A
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
DCR0
4B
DCR0
3B
DCR0
2B
DCR0
1B
DCR0
0B
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
DCR0
1A
DCR0
0A
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
NO
VAL62
NO
VAL68
NO
VAL67
NO
VAL66
DCR0
1A
DCR0
0A
NO
VAL71
¼
¼
¼
Common Shift Register
Bit 286 (Internal)
¼
DCR0
0A
¼
Common Shift Register
Bit 0 (Internal)
tD0
NO
VAL71
GSSOUT
NO
NO
VAL70 VAL69
tR0/tF0
OUTR0, OUTR4
(OUTG0, OUTG4)
(OUTB0, OUTB4)
OFF
OUTR1, OUTR5
(OUTG1, OUTG5)
(OUTB1, OUTB5)
OFF
OUTR2, OUTR6
(OUTG2, OUTG6)
(OUTB2, OUTB6)
OFF
OUTR3, OUTR7
(OUTG3, OUTG7)
(OUTB3, OUTB7)
OFF
ON
NO
VAL70
SID Data Are Not Transferred to
288-Bit Common Shift Register
(VOUTRnH)
(VOUTRnL)
DCR0
2A
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
tD2
ON
tD3
ON
ON
tD4
ON
ON
tD5
ON
ON
tD6
tD8, tD9
Figure 4. Dot Correction, Global Brightness Control, Function Control, and User-Defined
Data-Write Timing From GS Data Path
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DCR0
0A
DCSIN
USER
16B
USER
15B
USER
13B
USER
14B
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DCR0
3B
USER
12B
DCR0
2B
DCR0
0B
DCR0
1B
USER
16C
USER
15C
USER
14C
USER
13C
USER
12C
USER
11C
USER
10C
TH0
TSU0
TWH0
DCSCK
1
2
3
4
5
213
214
215
TWL0
216
tD7
Auto Generated
Latch Pulse
(Internal)
Grayscale
Data Latch
(Internal)
DC/BC/FC/UD
Data Latch
(Internal)
Previous Data
Latest Data
tD0
USER
16A
DCSOUT
USER
15A
USER
14A
USER
13A
USER
12A
USER DCR0
3A
11A
DCR0
2A
DCR0
1A
USER
16B
DCR0
0A
USER
15B
USER
13B
USER
14B
USER
12B
USER
11B
USER
10B
USER
9B
tR0/tF0
Figure 5. Dot Correction, Global Brightness Control, and Function Control
Data-Write Timing From DC Data Path
GSSIN
GSR0
0B
GSR0
1B
287
288
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
1
2
3
4
5
TSU2
GSB6
0C
46
GSG6
11C
47
GSG5
1C
GSG6
10C
48
49
93
GSR5
11C
GSG5
0C
94
95
96
GSR0
0C
GSR0
1C
286
287
288
GSSCK
TH1 TWH1
GSLAT
GS Data Latch
(Internal)
Previous Data
Latest Data
DC/BC/FC/UC
Data Latch
(Internal)
GSR0
2B
GSR0
1B
GSR0
0B
DCR0
0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB6
2C
GSB6
1C
GSB6
0C
GSG5
2C
GSG5
1C
GSG5
0C
GSR0
2C
GSR0
1C
GSR0
0C
Common Shift
Register Bit 1
(Internal)
GSR0
3B
GSR0
2B
GSR0
1B
DCR0
1
DCR0
0
GSB7
11C
GSB7
10C
GSB7
9C
GSB6
3C
GSB6
2C
GSB6
1C
GSG5
3C
GSG5
2C
GSG5
1C
GSR0
3C
GSR0
2C
GSR0
1C
GSB7
11B
GSB7
10B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LOD
B2B
LSD
B0B
TEF
Reserved
FUNC
1
FUNC
0
BCB
6
DCR
0
GSB7
11C
GSB7
10C
GSB7
11B
LOD
B7B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LSD
R1B
LSD
R0B
TEF
FUNC
2
FUNC
1
FUNC
0
DCR
1
DCR
0
GSB7
11C
¼
GSSOUT
(Common Shift
Register Bit 287)
¼
Common Shift
Register Bit 286
(Internal)
¼
Common Shift
Register Bit 0
(Internal)
tD1
Figure 6. Status Information Data-Read Timing
14
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7.7 Typical Characteristics
at TA = 25°C and VCC = 3.3 V, unless otherwise noted
6000
Power Dissipation Rate (mW)
RIREF, Reference Resistor (kW)
100
24
10
9.6
4.8
3.2
2.4
1.6
1.92
0
10
TLC5951RHA
3000
2000
TLC5951DAP, Not Soldered
1000
0
-40
40
30
20
TLC5951DAP, Soldered
4000
1.20
1.37
1
5000
-20
Figure 7. Reference Resistor vs Output Current
45
IO = 30 mA
25
IO = 20 mA
20
15
IO = 10 mA
10
IO = 5 mA
43
100
80
TA = +85°C
42
41
40
TA = +25°C
39
TA = -40°C
38
37
IO = 2 mA
5
IOLCMax = 40 mA, VCC = +3.3 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
36
0
35
0
45
0.5
1.0
1.5
2.5
2.0
0
3.0
0.5
1.0
1.5
2.0
2.5
Output Voltage (V)
Output Voltage (V)
Figure 9. Output Current vs Output Voltage
Figure 10. Output Current vs Output Voltage
44
30
IO = 30 mA
25
IO = 20 mA
20
15
IO = 10 mA
10
IO = 5 mA
43
Output Current (mA)
TA = +25°C, VCC = +5 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
35
3.0
45
IO = 40 mA
40
Output Current (mA)
60
Figure 8. Power Dissipation vs Temperature
Output Current (mA)
Output Current (mA)
30
40
44
TA = +25°C, VCC = +3.3 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
35
20
45
IO = 40 mA
40
0
Free-Air Temperature (°C)
Maximum Output Current (mA)
TA = +85°C
42
41
40
TA = +25°C
39
TA = -40°C
38
37
IO = 2 mA
5
IOLCMax = 40 mA, VCC = +5 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
36
0
35
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
Output Voltage (V)
Output Voltage (V)
Figure 11. Output Current vs Output Voltage
Figure 12. Output Current vs Output Voltage
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Typical Characteristics (continued)
at TA = 25°C and VCC = 3.3 V, unless otherwise noted
4
2
2
1
1
0
-1
-2
-40
-20
20
0
VCC = 3.3 V
-3
VCC = 5 V
40
60
80
-4
100
VCC = 5 V
-40
-20
20
0
40
60
80
100
Ambient Temperature (°)
Ambient Temperature (°)
Figure 13. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel, Red Color)
Figure 14. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel, Green Color)
4
2
2
1
1
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
-4
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCRn = 7Fh with High Adjustment Range
BCR = FFh
3
DIOLC (%)
DIOLC (%)
4
IOLCMax = 40 mA
DCBn = 7Fh with High Adjustment Range
BCB = FFh
3
-40
-20
20
0
VCC = 3.3 V
-3
VCC = 5 V
40
60
80
-4
100
VCC = 5 V
0
10
20
30
40
Ambient Temperature (°)
Output Current (mA)
Figure 15. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel, Blue Color)
Figure 16. Constant-Current Error vs Output (Channel-toChannel, Red Color)
4
2
2
1
0
-1
-2
1
0
-1
-2
VCC = 3.3 V
-3
-4
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCBn = 7Fh with High Adjustment Range
BCB = FFh
3
DIOLC (%)
DIOLC (%)
4
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCGn = 7Fh with High Adjustment Range
BCG = FFh
3
16
0
-1
-2
VCC = 3.3 V
-3
-4
IOLCMax = 40 mA
DCGn = 7Fh with High Adjustment Range
BCG = FFh
3
DIOLC (%)
DIOLC (%)
4
IOLCMax = 40 mA
DCRn = 7Fh with High Adjustment Range
BCR = FFh
3
0
10
VCC = 3.3 V
-3
VCC = 5 V
20
30
40
-4
VCC = 5 V
0
10
20
30
40
Output Current (mA)
Output Current (mA)
Figure 17. Constant-Current Error vs Output (Channel-toChannel, Green Color)
Figure 18. Constant-Current Error vs Output (Channel-toChannel, Blue Color)
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Typical Characteristics (continued)
at TA = 25°C and VCC = 3.3 V, unless otherwise noted
4
3
2
2
1
0
-1
-2
1
0
-1
-2
VCC = 3.3 V
-3
-4
Constant Current = 13 mA to 40 mA
Set By DCGn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCG = FFh
3
DIOLC (%)
DIOLC (%)
4
Constant Current = 13 mA to 40 mA
Set By DCRn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCR = FFh
10
15
20
VCC = 3.3 V
-3
VCC = 5 V
25
30
35
-4
40
VCC = 5 V
10
15
20
25
30
35
40
Output Current (mA)
Output Current (mA)
Figure 19. Constant-Current Error vs Output (Channel-toChannel, Red Color)
Figure 20. Constant-Current Error vs Output (Channel-toChannel, Green Color)
4
2
2
1
0
-1
-2
1
0
-1
-2
VCC = 3.3 V
-3
-4
Constant Current = 2 mA to 27 mA
Set By DCRn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCR = FFh
3
DIOLC (%)
DIOLC (%)
4
Constant Current = 13 mA to 40 mA
Set By DCBn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCB = FFh
3
10
15
20
VCC = 3.3 V
-3
VCC = 5 V
25
30
35
-4
40
VCC = 5 V
0
5
10
15
20
25
30
Output Current (mA)
Output Current (mA)
Figure 21. Constant-Current Error vs Output (Channel-toChannel, Blue Color)
Figure 22. Constant-Current Error vs Output (Channel-toChannel, Red Color)
4
3
2
2
1
0
-1
-2
1
0
-1
-2
VCC = 3.3 V
-3
-4
Constant Current = 2 mA to 27 mA
Set By DCBn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCB = FFh
3
DIOLC (%)
DIOLC (%)
4
Constant Current = 2 mA to 27 mA
Set By DCGn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCG = FFh
0
5
10
VCC = 3.3 V
-3
VCC = 5 V
15
20
25
30
-4
VCC = 5 V
0
5
10
15
20
25
30
Output Current (mA)
Output Current (mA)
Figure 23. Constant-Current Error vs Output (Channel-toChannel, Green Color)
Figure 24. Constant-Current Error vs Output (Channel-toChannel, Blue Color)
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Typical Characteristics (continued)
at TA = 25°C and VCC = 3.3 V, unless otherwise noted
4
3
2
2
1
0
-1
-2
0
-1
10
VCC = 3.3 V
40
30
20
-4
VCC = 5 V
0
10
40
30
20
Output Current (mA)
Output Current (mA)
Figure 25. Constant-Current Error vs Output (Channel-toChannel, Red Color)
Figure 26. Constant-Current Error vs Output (Channel-toChannel, Green Color)
1
0
-1
-2
-4
35
IO = 40 mA
30
25
20
15
IO = 20 mA
10
VCC = 3.3 V
-3
High Adjustment Range
TA = +25°C, BCx = FFh
VCC = 3.3 V
40
Output Current (mA)
2
DIOLC (%)
45
Constant Current = 2 mA to 40 mA
Set By BCB with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCBn = FFh
3
5
VCC = 5 V
IO = 2 mA
0
0
10
40
30
20
0
16
32
48
64
80
96
112
128
Output Current (mA)
Dot Correction Data (dec)
Figure 27. Constant-Current Error vs Output (Channel-toChannel, Blue Color)
Figure 28. Dot Correction Linearity (IOLCMax With Upper
Range)
45
45
Low Adjustment Range
TA = +25°C, BCx = FFh
VCC = 3.3 V
35
30
25
20
IO = 40 mA
15
IOLCMax = 40 mA
BCx = FFh
VCC = 3.3 V
40
Output Current (mA)
40
Output Current (mA)
0
-3
VCC = 5 V
4
IO = 20 mA
10
35
High Adjustment Range
30
25
20
15
TA = -40°C
10
5
TA = +25°C
5
IO = 2 mA
0
TA = +85°C
Low Adjustment Range
0
0
18
1
-2
VCC = 3.3 V
-3
-4
Constant Current = 2 mA to 40 mA
Set By BCG with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCGn = FFh
3
DIOLC (%)
DIOLC (%)
4
Constant Current = 2 mA to 40 mA
Set By BCR with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCRn = FFh
16
32
48
64
80
96
112
128
0
16
32
48
64
80
96
112
128
Dot Correction Data (dec)
Dot Correction Data (dec)
Figure 29. Dot Correction Linearity (IOLCMax With Lower
Range)
Figure 30. Dot Correction Linearity (IOLCMax With Upper And
Lower Range)
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Typical Characteristics (continued)
at TA = 25°C and VCC = 3.3 V, unless otherwise noted
45
35
High Adjustment Range
IOLCMax = 40 mA
DCXn = 7Fh
VCC = 3.3 V
40
30
Output Current (mA)
Output Current (mA)
45
High Adjustment Range
TA = +25°C
DCXn = 7Fh
VCC = 3.3 V
40
IO = 40 mA
25
20
15
IO = 20 mA
10
35
30
25
20
15
TA = -40°C
10
5
TA = +25°C
5
IO = 2 mA
0
TA = +85°C
0
0
32
64
96
128
160
192
224
0
256
32
64
96
128
160
192
224
256
Brightness Correction Data (dec)
Brightness Correction Data (dec)
Figure 31. Global Brightness Control Linearity (IOLCMax With
Upper Range)
Figure 32. Global Brightness Control Linearity (Ambient
Temperature With Upper Range)
GSCKR
OUTR0
OUTR7
IOLCMax = 40 mA, BCX = 7Fh
DCXn = 7Fh with High Adjustment Range
TA = +25°C, GSCKR/G/B = 33 MHz
VCC = 3.3 V, VLED = 5 V, RL = 100 W, CL = 15 pF
Time (25 ns/div)
Figure 33. Constant-Current Output-Voltage Waveform
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8 Parameter Measurement Information
8.1
Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
INPUT
GND
GND
Figure 34. GSSCK, GSLAT, DCSIN, DCSCK, GSCKR,
GSCKG, GSCKB
Figure 35. GSSIN, XBLNK
OUTn
VCC
GND
SOUT
Figure 37. OUTR0, -G0, -B0 Through OUTR7, -G7, -B7
GND
Figure 36. GSSOUT, DCSOUT
8.2 Test Circuits
RL
VCC
VCC
OUTXn
IREF
RIREF
VCC
(2)
VLED
(1)
GND
SOUT
VCC
CL
GND
X = R, G, or B; n = 0–7.
Figure 38. Rise-Time and Fall-Time Test Circuit for OUTRn,
-Gn, -Bn
CL
(1)
CL includes measurement probe and jig capacitance.
Figure 39. Rise-Time and Fall-Time Test Circuit for
GSSOUT and DCSOUT
VCC OUTR0
¼
VCC
IREF
(1)
¼
RIREF
OUTXn
GND OUTB7
VOUTfix
(1)
VOUTRn/Gn/Bn
X = R, G, or B; n = 0–7.
Figure 40. Constant-Current Test Circuit for OUTRn, -Gn, -Bn
20
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9 Detailed Description
9.1 Overview
The TLC5951 device is a 24-channel, constant-current sink driver. Each channel has an individually-adjustable,
4096-step, pulse-width modulation (PWM) grayscale (GS) brightness control and 128-step constant-current dot
correction (DC). The dot correction adjusts brightness deviation between channels and other LED drivers. The
output channels are grouped into three groups of eight channels. Each color group has a 256-step global
brightness control (BC) function and an individual grayscale clock input. GS, DC, and BC data are accessible via
a serial interface port. DC and BC can be programmed via a dedicated serial interface port.
The TLC5951 has a 40-mA current capability. One external resistor determines the maximum current limit that
applies to all channels.
The TLC5951 device has three error-detection circuits for LED-open detection (LOD), LED-short detection (LSD),
and thermal error flag (TEF). LOD detects a broken or disconnected LED, LSD detects a shorted LED, and TEF
indicates an overtemperature condition.
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9.2 Functional Block Diagram
VCC
33rd GSCKR/G/B After XBLNK
Goes High or Internal Blank Signal
VCC
(1)
LOD/LSD Data Latch for R/G/B
216
48
LSB
MSB
GSSIN
288-Bit Common Shift Register
0
GSSOUT
287
288
Lower 216
GSSCK
LSB
MSB
Grayscale Data Latch
(12 Bits x 24 Channels)
Latch
Select
GSLAT
0
Higher 17
LSB
DCSIN
287
MSB
216-Bit DC/BC/FC/UD Shift Register
0
215
Lower 199
216
288
DCSCK
DCSOUT
LSB
MSB
Dot Correction (7-Bit x 24-Channels)/
Brightness Control (8-Bit x 3 Group)/
Function Control (7-Bit)/User-Defined (17-Bit) Data Latch
Auto Latch
Pulse Gen
0
215
216
216
TMGRST
3
GSCKR
GS Counter
for RED
GSCKG
Lower 198
96
12
DSPRPT/PWMMODE
12-Bit PWM
Timing Control
GS Counter
for GREEN
12
3
3
12-Bit PWM
Timing Control
96
GSCKB
8
GS Counter
for BLUE
3
96
3
8
12
12-Bit PWM
Timing Control
8
195
XBLNK
4-Grouped
Switch Delay
Reference
Current
Control
IREF
4-Grouped
Switch Delay
4-Grouped
Switch Delay
8
8
8
8
8
24
8
171
8-Bit Brightness
Control
8-Bit Brightness
Control
8-Bit Brightness
Control
24-Channel Constant-Current Driver with 7-Bit Dot Correction
GND
Thermal
Detection
48
GND
LED Open Detection (LOD)/LED Short Detection (LSD)
¼
¼
¼
OUTR0 ¼ OUTR7 OUTG0 ¼ OUTG7 OUTB0 ¼ OUTB7
22
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9.3 Feature Description
9.3.1 Thermal-Shutdown and Thermal-Error Flags
The thermal shutdown (TSD) function turns off all constant-current outputs on the device when the junction
temperature (TJ) exceeds the threshold (TTEF = 163°C, typ) and sets the thermal error flag (TEF) to 1. All outputs
are latched off when TEF is set to 1 and remain off until the next grayscale cycle after XBLNK goes high and the
junction temperature drops below (TTEF – THYST). TEF remains as 1 until GSLAT is input with low temperature.
TEF is set to 0 once the junction temperature drops below (TTEF – THYST), but the output does not turn on until
the first GSCKR, -G, or -B in the next display period even if TEF is set to 0.
GSLAT
GSCK
Grayscale
Data Latch
XBLNK
Old Latched GS Data
New Latched GS Data
(1)
4094 4096
4093 4095
1 2 3 4
1 2 3
GSCKR/G/B
IC Junction
Temperature (TJ)
TJ < T(TEF)
TJ ³ T(TEF)
TJ < T(TEF) - T(HYS)
TJ ³ T(TEF)
The TEF bit of SID is rest to ‘0’ at the rising edge of GSSCK
after the falling edge of GSLAT for a GS data write.
'1'
TEF in SID
(Internal Data)
'0'
'0'
OUTRn/Gn/Bn is forced off when TJ exceeds T(TEF).
Also, the TEF bit is set to ‘1’ at the same time.
OFF
OUTRn/Gn/Bn
OFF
ON
ON
OUTRn/Gn/Bn is turned off at the rising edge of GSCKR/G/B
after the rising edge of XBLNK.
(1)
An internal signal also works to turn the constant outputs, the same as the XBLNK input. The internal blank signal is
generated at the rising edge of the GSLAT input signal for GS data with the display-timing reset enabled. Also, the
signal is generated at the 4096th GSCKR, -G, or -B when auto repeat mode is enabled. XBLNK can be connected to
VCC when the display timing reset or auto repeat is enabled.
Figure 41. TEF and TSD Timing
9.3.2 Noise Reduction
Large surge currents may flow through the device and the board on which the device is mounted if all 24 outputs
turn on simultaneously at the start of each grayscale cycle. These large current surges could induce detrimental
noise and electromagnetic interference (EMI) into other circuits. The TLC5951 device turns the outputs on in a
series delay for each group independently to provide a circuit soft-start feature. The output current sinks are
grouped into four groups in each color group. For example, for the RED color output, the first grouped outputs
that are turned on or off are OUTR0 and OUTR4. The second grouped outputs that are turned on or off are
OUTR1 and OUTR5. The third grouped outputs are OUTR2 and OUTR6, and the fourth grouped outputs are
OUTR3 and OUTR7. Each grouped output is turned on and off sequentially with a small delay between groups.
However, each color output on and off is controlled by the color grayscale clock.
9.4 Device Functional Modes
9.4.1 Maximum Constant Sink-Current Value
The TLC5951 maximum constant sink-current value for each channel, IOLCMax, is determined by an external
resistor, RIREF, placed between RIREF and GND. The RIREF resistor value is calculated with Equation 1.
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Device Functional Modes (continued)
RIREF (kW) =
VIREF (V)
´ 40
IOLCMax (mA)
where:
•
VIREF = the internal reference voltage on IREF (1.2 V, typically)
(1)
IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when it is turned on, the dot
correction is set to the maximum value of 7Fh (127d), and the global brightness control data are set to the
maximum value of FFh (255d). Each output sink current can be reduced by lowering the output dot correction or
brightness control value.
RIREF must be between 1.2 kΩ and 24 kΩ to keep IOLCMax between 40 mA (typ) and 2mA (typ); the output may be
unstable when IOLCMax is set lower than 2 mA. Output currents lower than 2 mA can be achieved by setting
IOLCMax to 2 mA or higher and then using dot correction and global brightness control to lower the output current.
Figure 7 and Table 1 show the constant sink current versus external resistor, RIREF, characteristics. Multiple
outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each
output.
Table 1. Maximum Constant-Current Output Versus
External Resistor Value
IOLCMax (mA, Typical)
RIREF (kΩ)
40
1.2
35
1.371
30
1.6
25
1.92
20
2.4
15
3.2
10
4.8
5
9.6
2
24
9.4.2 Dot Correction (DC) Function
The TLC5951 device has the capability to adjust the output current of each channel (OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7) individually. This function is called dot correction (DC). The DC function
allows the brightness and color deviations of LEDs connected to each output to be individually adjusted. Each
output DC is programmed with a 7-bit word for each channel output. Each channel output current is adjusted in
128 steps within one of two adjustment ranges. The dot-correction high-adjustment range allows the output
current to be adjusted from 33.3% to 100% of the maximum output current, IOLCMax. The dot-correction-low
adjustment range allows the output current to be adjusted from 0% to 66.7% of IOLCMax. The range control bits in
the function control latch select the high or low adjustment range. Equation 2 and Equation 3 calculate the actual
output current as a function of RIREF, DC value, adjustment range, and brightness control value. There are three
range control bits that control the DC adjustment range for three groups of outputs: OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7. DC data are programmed into the TLC5951 device via the serial
interface.
When the device is powered on, the DC data in the 216-bit common shift register and data latch contain random
data. Therefore, DC data must be written to the DC latch before turning the constant-current output on.
Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the
proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.
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9.4.3 Global Brightness Control (BC) Function
The TLC5951 device has the capability to adjust the output current of each color group simultaneously. This
function is called global brightness control (BC). The global brightness control for each of the three color groups,
(OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7), is programmed with a separate 8-bit word. The BC of
each group is adjusted with 256 steps from 0% to 100%. 0% corresponds to 0 mA. 100% corresponds to the
maximum output current programmed by RIREF and each output DC value. Note that even though the BC values
for all color groups are identical, the output currents can be different if the DC values are different. Equation 2
and Equation 3 calculates the actual output current as a function of RIREF, the DC adjustment range, and the
brightness control value. BC data are programmed into the TLC5951 device via the serial interface.
When the device is powered on, the BC data in the 216-bit common shift register and data latch contain random
data. Therefore, BC data must be written to the BC latch before turning the constant-current output on.
Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the
proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.
Equation 2 determines the output sink current for each color group when the dot-correction high-adjustment
range is chosen.
1
2
DC
IOLCMax (mA) +
IOLCMax (mA) ´
3
3
127
IOUT (mA) =
´
BC
255
(2)
Equation 3 determines the output sink current for each color group when the dot-correction low-adjustment range
is chosen.
IOUT (mA) =
2
DC
IOLCMax (mA) ´
3
127
´
BC
255
where:
•
•
•
IOLCMax = the maximum channel current for each channel determined by RIREF
DC = the decimal dot correction value for the output. This value ranges between 0 and 127.
BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.
(3)
Table 2. Output Current vs DC Data and IOLCMax With
Dot-Correction High-Adjustment Range (BC Data = FFh)
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
BC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
FF
33.3
13.33
0.67
000 0001
1
01
FF
33.9
13.54
0.68
000 0010
2
02
FF
34.4
13.75
0.69
—
—
—
—
—
—
—
111 1101
125
7D
FF
99
39.58
1.98
111 1110
126
7E
FF
99.5
39.79
1.99
111 1111
127
7F
FF
100
40
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Table 3. Output Current vs DC Data and IOLCMax With
Dot-Correction Low-Adjustment Range (BC Data = FFh)
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
BC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
FF
0
0
0
000 0001
1
01
FF
0.5
0.21
0.01
000 0010
2
02
FF
1
0.42
0.01
—
—
—
—
—
—
—
111 1101
125
7D
FF
65.6
26.25
1.31
111 1110
126
7E
FF
66.1
26.46
1.32
111 1111
127
7F
FF
66.7
26.67
1.33
Table 4. Output Current Versus Bc Data and IOLCMax With
Dot Correction High Adjustment Range (DC Data = 7fh)
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
DC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
7F
0
0
0
000 0001
1
01
7F
0.4
0.16
0.01
000 0010
2
02
7F
0.8
0.31
0.02
—
—
—
—
—
—
—
111 1101
253
FD
7F
99.2
39.69
1.98
111 1110
254
FE
7F
99.6
39.84
1.99
111 1111
255
FF
7F
100
40
2
Table 5. Output Current vs BC Data, DC Data, and IOLCMax With
Dot-Correction High-Adjustment Range
BC DATA
(Hex)
BC DATA
(Decimal)
DC DATA
(Hex)
DC DATA
(Decimal)
PERCENTAGE
OF IOLCMax (%)
IOLCMax = 40 mA
(mA, Typical)
IOLCMax = 2 mA
(mA, Typical)
00
0
20
32
0
0
0
—
—
—
—
—
—
—
33
51
20
32
10.02
4.01
0.2
—
—
—
—
—
—
—
80
128
20
32
25.16
10.06
0.5
—
—
—
—
—
—
—
CC
204
20
32
40.10
16.04
0.8
—
—
—
—
—
—
—
FF
255
20
32
50.13
13.33
1.0
9.4.4 Grayscale (GS) Function (PWM Control)
The TLC5951 device can adjust the brightness of each output channel using a pulse width modulation (PWM)
control scheme. The use of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness.
The grayscale circuitry is duplicated for each of the three color groups.
The PWM operation for each color group is controlled by a 12-bit GS counter. Three GS counters are
implemented to control each of the three color outputs, OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7.
Each counter increments on each rising edge of the grayscale reference clock (GSCKR, GSCKG, or GSCKB).
The falling edge of XBLNK resets the three counter values to 0. The grayscale counter values are held at 0 while
XBLNK is low, even if the GS clock input is toggled high and low. Pulling XBLNK high enables the GS clock. The
first rising edge of a GS clock after XBLNK goes high increments the corresponding grayscale counter by one
and switches on all outputs with a non-zero GS value programmed into the GS latch. Each additional rising edge
on a GS clock increases the corresponding GS counter by one.
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The GS counters keep track of the number of clock pulses from the respective GS clock inputs (GSCKR,
GSCKG, and GSCKB). Each output stays on while the counter is less than or equal to the programmed
grayscale value. Each output turns off at the rising edge of the GS counter value when the counter is larger than
the output grayscale latch value.
Equation 4 calculates each output (OUTRn, -Gn, -Bn) on-time (tOUT_ON):
tOUTON (ns) = TGSCLKR/G/B (ns) ´ GSn
where:
•
•
•
IOLCMax = the maximum channel current for each channel determined by RIREF
DC = the decimal dot correction value for the output. This value ranges between 0 and 127.
BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.
(4)
When new GS data are latched into the GS data latch with the rising edge on GSLAT during a PWM cycle, the
GS data latch registers are immediately updated. This latching can cause the outputs to turn on or off
unexpectedly. For proper operation, GS data should only be latched into the device at the end of a display period
when XBLNK is low. Table 6 summarizes the GS data value versus the output on-time duty cycle.
When the device is powered up, the 288-bit common shift register and GS data latch contain random data.
Therefore, GS data must be written to the GS latch before turning the constant-current output on. Additionally,
XBLNK should be low when the device is powered up to prevent the outputs from turning on before the proper
GS values are programmed into the registers. All constant-current outputs are off when XBLNK is low.
If there are any unconnected outputs (OUTRn, OUTGn, and OUTBn), including LEDs in a failed short or failed
open condition, the GS data corresponding to the unconnected output should be set to 0 before turning on the
LEDs. Otherwise, the VCC supply current (IVCC) increases while that constant-current output is programmed to
be on.
Table 6. Output Duty Cycle and On-Time Versus GS Data
GS DATA
(Binary)
GS DATA
(Decimal)
GS DATA
(Hex)
OUTPUT ON-TIME DUTY
CYCLE (%)
OUTPUT ON-TIME (33MHz GS Clock) (ns)
0000 0000 0000
0
000
0
0
0000 0000 0001
1
001
0.02
30
0000 0000 0010
2
002
0.05
61
—
—
—
—
—
0111 1111 1111
2047
7FF
49.99
62 030
1000 0000 0000
2048
800
50.01
62 061
1000 0000 0001
2049
801
50.04
62 091
—
—
—
—
—
1111 1111 1101
4093
FFD
99.95
124 030
1111 1111 1110
4094
FFE
99.98
124 061
1111 1111 1111
4095
FFF
100
124 091
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9.4.4.1 PWM Counter 12-Bit Mode Without Auto Repeat
XBLNK
(1)
GSCKR
GSCKG
GSCKB
OUTRn/Gn/Bn
(GSDATA = 000h)
OFF (VOUTRn/Gn/BnH)
OFF
OUTRn/Gn/Bn
(GSDATA = 002h)
ON
(VOUTRn/Gn/BnL)
OFF
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 2
(VOUTRn/Gn/BnL)
ON
(VOUTRn/Gn/BnL)
ON
(VOUTRn/Gn/BnL)
T = GSCKR/G/B ´ 2048
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
T = GSCKR/G/B ´ 2049
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
¼
¼
¼
T = GSCKR/G/B ´ 4093
T = GSCKR/G/B ´ 4094
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
T = GSCKR/G/B ´ 4095
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
OUTRn/Gn/Bn turns on at the first rising edge of GSCKR/G/B after
XBLNK goes high except when Grayscale data are zero.
(1)
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
OFF
OUTRn/Gn/Bn
(GSDATA = FFFh)
(VOUTRn/Gn/BnH)
ON
OFF
OUTRn/Gn/Bn
(GSDATA = FFEh)
¼
¼
¼
T = GSCKR/G/B ´ 2047
OFF
OUTRn/Gn/Bn
(GSDATA = FFDh)
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 3
OFF
OUTRn/Gn/Bn
(GSDATA = 801h)
¼
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 1
OFF
OUTRn/Gn/Bn
(GSDATA = 800h)
1 2 3 4
¼
Drivers do not turn on when Grayscale data are zero.
OFF
OUTRn/Gn/Bn
(GSDATA = 7FFh)
¼
GS counter starts to count GSCKR/G/B after
XBLNK goes high.
OFF
OUTRn/Gn/Bn
(GSDATA = 003h)
4095
4096
4097 ¼
¼
ON (VOUTRn/Gn/BnL)
OUTRn/Gn/Bn
(GSDATA = 001h)
2048
2049
2050
1 2 3 4 ¼
OUTRn/Gn/Bn does not turn on again until XBLNK goes low once
in case of no auto repeat mode.
The internal blank signal is generated at the rising edge of the GSLAT input signal for GS data with the display-timing
reset enabled. Also, the signal is generated at the 4096th GSCKR, -G, or -B when the auto repeat mode is enabled.
XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.
Figure 42. PWM Operation 1
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9.4.4.2 PWM Counter 8-, 10-, or 12-Bit Mode Without Auto Repeat
XBLNK
1 2 3 4
GSCKR
GSCKG
GSCKB
255
256
1023
1024
1025
257
¼
¼
¼
4095
4096
4097
¼
1 2 3 4
¼
¼
GS counter starts to count GSCKR/G/B after XBLNK goes high.
PWM 8-Bit Mode
(FC Bit 1/0 = 1/1)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF (VOUTRn/Gn/BnH)
ON (VOUTRn/Gn/Bn)
OUTRn/Gn/Bn is forced off even if GS data is greater than 0FFh.
OUTRn/Gn/Bn does not turn on again until XBLNK goes low.
PWM 10-Bit Mode
(FC Bit 1/0 = 1/0)
OUTRn/Gn/Bn
(GSDATA = FFFh)
T = GSCKR/G/B ´ 255
OFF (VOUTXnH)
T = GSCKR/G/B ´ 1023
ON (VOUTRn/Gn/Bn)
OUTRn/Gn/Bn is forced off even if GS data are greater than 3FFh.
OUTRn/Gn/Bn does not turn on again until XBLNK goes low.
PWM 12-Bit Mode
(FC Bit 1/0 = 0/X)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF (VOUTXnH)
T = GSCKR/G/B ´ 4095
ON (VOUTRn/Gn/Bn)
Figure 43. PWM Operation 2
9.4.4.3 PWM Counter 8-, 10-, or 12-Bit Mode With Auto Repeat
XBLNK
1 2 3
GSCKR
GSCKG
GSCKB
¼
256
255 257
¼
¼
1023
1024
1025
¼
¼
4095
4096
1 2
¼
¼
¼
4095
4096
1 2
¼
4095
4096
1 2
¼
¼
1
¼
GS counter starts to count GSCKR/G/B after XBLNK goes high.
PWM 8-Bit Mode
(FC Bit 1/0 = 1/1)
OUTRn/Gn/Bn
(GSDATA = 0FFh to FFFh)
OFF
T=
GSCKR/G/B ´ 255
T = GSCKR/G/B ´ 1
ON
OUTRn/Gn/Bn is forced off even if
GS data are greater than 0FFh.
PWM 10-Bit Mode
(FC Bit 1/0 = 1/0)
OUTRn/Gn/Bn
(GSDATA = 3FFh to FFFh)
PWM 12-Bit Mode
(FC Bit 1/0 = 0/X)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF
x2 of off period
is generated.
x11 of off period
is generated.
x15 of off period
is generated.
T = GSCKR/G/B ´ 1023
ON
OUTRn/Gn/Bn is forced off even if
GS data are greater than 3FFh.
OFF
x2 of off period
is generated.
x3 of off period
is generated.
T = GSCKR/G/B ´ 4095
ON
Figure 44. PWM Operation 3
9.4.5 Register and Data Latch Configuration
The TLC5951 device has two data latches to store information: the grayscale (GS) data latch and the DC, BC,
FC, and UD data latch. The GS data latch can be written as 288-bit data through GSSIN with GSSCK. The DC,
BC, FC, and UD data latch can be written as data through DCSIN with DCSCK. Also, DC, BC, and FC data can
be written to the DC, BC, FC, and UD data latch through GSSIN with GSSCK. UD data are written to the upper
17 bits of the 216-bit DC, BC, FC, and UD shift register at the same time. The data in the DC, BC, FC, and UD
data latch can be read via GSSOUT with GSSCK. Figure 45 shows the grayscale shift register and data latch
configuration.
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From 216-Bit DC/BC/FC/UD Data Latch
From LSD/LOD/TEF Data Holder
49
288-Bit Common Shift Register
These 49 bits of data are loaded into the
upper 49 bits of the 288-bit shift register
when GSLAT is low at the last GSSCK
rising edge before the rising edge of GSLAT.
These 216 bits of data are loaded into the
lower 216 bits of the 288-bit shift register when
GSLAT is low at the last GSSCK rising edge
before the rising edge of GSLAT.
216
LSB
MSB
GSSOUT
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
282
284
286
283
285
287
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
0
2
4
1
3
5
¼
GSSIN
GSSCK
288
Lower 216 Bits of 288 Bits
288
Grayscale Data Latch (12 Bits ´ 24 Channels)
MSB
287
OUTB7
Bit 11
276
¼
36
47
OUTB7
Bit 0
OUTR1
Bit 11
¼
GS Data for OUTB7
¼
24
35
OUTR1 OUTB0
Bit 0
Bit 11
GS Data for OUTR1
¼
GS Data for OUTB0
12
23
OUTB0 OUTG0
Bit 0
Bit 11
11
OUTG0 OUTR0
Bit 0
Bit 11
¼
GS Data for OUTG0
This latch
pulse is
generated
when GSLAT
is low at the
last GSSCK
rising edge
before the
GSLAT
rising edge.
LSB
0
¼
OUTR0
Bit 0
GS Data for OUTR0
288
To PWM Timing Control Block for Each Color
Upper 17 Bits of 216 Bits
These 17 bits of data are loaded into the upper 17 bits of the 216-bit shift register when GSLAT
is high at the last GSSCK rising edge before the GSLAT rising edge. The other bits remain unchanged.
216-Bit DC/BC/FC/UD Shift Register
DCSOUT
MSB
215
214
Data
Bit 215
Data
Bit 214
¼
¼
197
196
195
Data
Bit 197
Data
Bit 196
Data
Bit 195
Lower 199 Bits of 216 Bits
216
These 199 bits of data are loaded into the lower 199 bits of the
216-bit shift register when GSLAT is high at the last GSSCK
rising edge before the GSLAT rising edge. The User Defined
bit data in the 216-bit data latch remain unchanged.
¼
5
4
3
2
1
0
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
These 216 bits of data are automatically loaded into the
216-bit data latch by the latch pulse generated 3ms-7ms
after the DCSCK rising edge is not input.
DCSIN
DCSCK
Dot Correction (7 Bits ´ 24 Channels)/
Global Brightness Control (8 Bits ´ 3 Group)/
Function Control (7 Bits)
User Defined (17 Bits)
216-Bit DC/BC/FC/UD Data Latch
MSB
215-199 198-192 191-184 183-176 175-168 167-161 160-154 153-147
User
Defined
Bits 16-0
FUNC
Bits 6-0
BRIGHT BRIGHT BRIGHT DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 7-0
Bits 7-0
Bits 6-0
Bits 7-0
Bits 6-0
OUTB0-7 OUTG0-7 OUTR0-7 OUTB7
OUTG7
OUTR7
Function Global Brightness Control
Control
27-21
¼
20-14
13-7
LSB
6-0
DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 6-0
Bits 6-0
Bits 6-0
OUTR1
OUTG0 OUTR0
OUTB0
Dot Correction
This latch pulse is generated when
GSLAT is high at the last GSSCK
rising edge before the GSLAT
rising edge. Otherwise, the latch
pulse is generated 3 ms to 7 ms
after the DCSCK rising edge.
216
216
24
7
To GS Counter/PWM Timing
Control Block
To Global Brightness
Control Block
To 288-Bit Common
Shift Register
171
To Dot Correction
Control Block
Figure 45. Grayscale Shift Register and Data Latch Configuration
9.4.5.1 288-Bit Common Shift Register
The 288-bit common shift register is used to shift data from the GSSIN pin into the TLC5951. The data shifted
into this register are used for grayscale data, global brightness control, and dot correction data. The register LSB
is connected to GSSIN and the MSB is connected to GSSOUT. On each GSSCK rising edge, the data on GSSIN
are shifted into the register LSB and all 288 bits are shifted towards the MSB. The register MSB is always
connected to GSSOUT.
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The level of GSLAT at the last GSSCK before the GSLAT rising edge determines which latch the data are
transferred into. When GSLAT is low at the last GSSCK rising edge, all 288 bits are latched into the grayscale
data latch. When GSLAT is high at the last GSSCK rising edge, bits 0–198 are copied to bits 0–198 in the DC,
BC, FC, and UD data latch and bits 199–215 are copied to bits 199–215 in the 216-bit DC, BC, FC, and UD shift
register at the GSLAT rising edge. To avoid data from being corrupted, the GSLAT rising edge must be input
more than 7 ms after the last DCSCK for a DC, BC, FC, and UD data write. When the IC powers on, the 288-bit
common shift register contains random data.
9.4.5.2 Grayscale Data Latch
The grayscale (GS) data latch is 288 bits long. This latch contains the 12-bit PWM grayscale value for each of
the TLC5951 constant-current outputs. The PWM grayscale values in this latch set the PWM on-time for each
constant-current driver. See Table 6 for the on-time duty of each GS data bit. Figure 46 shows the shift register
and latch configuration. Refer to Figure 3 for the timing diagram for writing data into the GS shift register and
latch.
Data are latched from the 288-bit common shift register into the GS data latch at the rising edge of the GSLAT
pin. The conditions for latching data into this register are described in the 288-Bit Common Shift Register section.
When data are latched into the GS data latch, the new data are immediately available on the constant-current
outputs. For this reason, data should only be latched when XBLNK is low. If data are latched with XBLNK high,
the outputs may turn on or off unexpectedly.
MSB
287
OUTB7
Bit 11
276
¼
OUTB7
Bit 0
GS Data for OUTB7
36
47
¼
OUTR1
Bit 11
¼
OUTR1 OUTB0
Bit 0
Bit 11
GS Data for OUTR1
24
35
¼
OUTB0 OUTG0
Bit 0
Bit 11
GS Data for OUTB0
12
23
¼
OUTG0 OUTR0
Bit 0
Bit 11
GS Data for OUTG0
LSB
0
11
¼
OUTR0
Bit 0
GS Data for OUTR0
Figure 46. Grayscale Data-Latch Configuration
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When the IC powers on, the grayscale data latch contains random data. Therefore, grayscale data must be
written to the 288-bit common shift register and latched into the GS data latch before turning on the constantcurrent outputs. XBLNK should be low when powering on the TLC5951 to force all outputs off until the internal
registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data bit
assignment is shown in Table 7.
Table 7. Grayscale Data-Bit Assignment
BITS
DATA
BITS
DATA
11–0
OUTR0
155–144
OUTR4
23–12
OUTG0
167–156
OUTG4
35–24
OUTB0
179–168
OUTB4
47–36
OUTR1
191–180
OUTR5
59–48
OUTG1
203–192
OUTG5
71–60
OUTB1
215–204
OUTB5
83–72
OUTR2
227–216
OUTR6
95–84
OUTG2
239–228
OUTG6
107–96
OUTB2
251–240
OUTB6
119–108
OUTR3
263–252
OUTR7
131–120
OUTG3
275–264
OUTG7
143–132
OUTB3
287–276
OUTB7
9.4.5.3 DC, BC, FC, and UD Shift Register
The 216-bit DC, BC, FC, and UD shift register is used to shift data from the DSSIN pin into the TLC5951 device.
The data shifted into this register are used for the dot correction (DC), global brightness control (BC), function
control (FC), and user-defined (UD) data latches. Each of these latches is described in the following sections.
The register LSB is connected to DCSIN and the MSB is connected to DCSOUT. On each DCSCK rising edge,
the data on DCSIN are shifted into the register LSB and all 216 bits are shifted towards the MSB. The register
MSB is always connected to DCOUT. When the device is powered on, the 216-bit DC, BC, FC, and UD shift
register contains random data.
9.4.5.3.1 DC, BC, FC, and UD Data Latch
The 216-bit DC, BC, FC, and UD data latch contains dot correction (DC) data, global brightness control (BC)
data, function control (FC) data, and user-defined (UD) data. Data can be written into this latch from the DC, BC,
FC, and UD shift register. Furthermore, DC, BC, and FC data can be written into this latch from the 288-bit
common shift register. At this time, UD data are written to bits 199–215 in the 216-bit DC, BC, FC, and UD shift
register data latch. When the IC is powered on, the DC, BC, FC, and UD data latch contains random data.
MSB
215-199 198-192 191-184 183-176 175-168 167-161 160-154 153-147 146-140
User
Defined
Bits 16-0
FUNC
Bits 6-0
BRIGHT BRIGHT BRIGHT DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 7-0
Bits 7-0
Bits 6-0
Bits 6-0
Bits 7-0
Bits 6-0
OUTR7
OUTG7
OUTB0-7 OUTG0-7 OUTR0-7 OUTB7
OUTB6
User Function Global Brightness Control
Defined Control
27-21
¼
20-14
13-7
LSB
6-0
DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 6-0
Bits 6-0
Bits 6-0
OUTB0
OUTG0 OUTR0
OUTR1
Dot Correction
Figure 47. DC, BC, FC, and UD Data–Latch Configuration
9.4.5.3.2 Dot–Correction Data Latch
The dot correction (DC) data latch is 168 bits long. The DC data latch consists of bits 0–167 in the DC, BC, FC,
and UD data latch. This latch contains the 7–bit DC value for each of the TLC5951 constant–current outputs.
Each DC value individually adjusts the output current for each constant–current driver. As explained in the Dot
Correction (DC) Function section, the DC values are used to adjust the output current from 0% to 66.7% of the
maximum value when the dot correction low adjustment range is selected and from 33.3% to 100% of the
maximum value when the dot correction high adjustment range is selected. The adjustment range is selected by
the range control bits in the function control latch.
32
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Table 2 and Table 3 show how the DC data affect the percentage of the maximum current for each output. See
Figure 47 for the DC data latch configuration. Figure 4 illustrates the timing diagram for writing data from the GS
data path into the shift registers and latches. Figure 5 illustrates the timing diagram for writing data from the DC
data path into the shift registers and DC latches. DC data are automatically latched from the DC, BC, FC, and
UD shift register into the DC data latch with an internal latch signal. The internal latch signal is generated in 3 ms
to 7 ms after the last DCSCK rising edge.
When the device powers on, the DC data latch contains random data. Therefore, DC data must be written into
the TLC5951 device and latched into the DC data latch before turning on the constant-current outputs. XBLNK
should be low when powering on the TLC5951 device to force all outputs off until the internal registers can be
programmed. All constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in
Table 8.
Table 8. Dot-Correction Data-Bit Assignment
BITS
DATA
BITS
DATA
6–0
OUTR0
90–84
OUTR4
13–7
OUTG0
97–91
OUTG4
20–14
OUTB0
104–98
OUTB4
27–21
OUTR1
111–105
OUTR5
34–28
OUTG1
118–112
OUTG5
41–35
OUTB1
125–119
OUTB5
48–42
OUTR2
132–126
OUTR6
55–49
OUTG2
139–133
OUTG6
62–56
OUTB2
146–140
OUTB6
69–63
OUTR3
153–147
OUTR7
76–70
OUTG3
160–154
OUTG7
83–77
OUTB3
167–161
OUTB7
9.4.5.3.3 Global-Brightness Control-Data Latch
The global brightness control (BC) data latch is 24 bits long. The BC data latch consists of bits 168–191 in the
DC, BC, FC, and UD data latch.
The data of the BC data latch are used to adjust the constant-current values for eight channel constant-current
drivers of each color group. The current can be adjusted from 0% to 100% of each output current adjusted by
brightness control with 8-bit resolution. Table 4 describes the percentage of the maximum current for each
brightness control data.
When the IC is powered on, the data in the BC data latch are not set to a specific default value. Therefore,
brightness control data must be written to the BC latch before turning on the constant-current output. The data bit
assignment is shown in Table 9.
Table 9. Data-Bit Assignment
BITS
GLOBAL BRIGHTNESS CONTROL DATA BITS 7–0
175–168
OUTR0–OUTR7 group
183–176
OUTG0–OUTG7 group
191–184
OUTB0–OUTB7 group
9.4.5.3.4 Function-Control Data Latch
The function control (FC) data latch is 7 bits in length and is used to select the dot-correction adjustment range,
grayscale counter mode, enabling of the auto display repeat, and display timing reset function. When the device
is powered on, the data in the FC latch are not set to a specific default value. Therefore, function control data
must be written to the FC data latch before turning on the constant-current output.
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Table 10. Data-Bit Assignment
BIT
DESCRIPTION
192
Dot correction adjustment range for the RED color output (0 = lower range, 1 = higher range).
When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the red LED driver group.
When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current
set by an external resistor.
193
Dot correction adjustment range for the GREEN color output (0 = lower range, 1 = higher range).
When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the green LED driver group.
When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current
set by an external resistor.
194
Dot correction adjustment range for the BLUE color output (0 = lower range, 1 = higher range).
When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the blue LED driver group.
When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current
set by an external resistor.
195
Auto display repeat mode (0 = disabled, 1 = enabled).
When this bit is 0, the auto repeat function is disabled. Each output driver is turned on and off once after XBLNK goes high.
When this bit is 1, each output driver is repeatedly toggled on and off every 4096th grayscale clock without the XBLNK level
changing when the GS counter is configured in the 12-bit mode. If the GS counter is configured in the 10-bit mode, the outputs
continue to cycle on and off every 1024th grayscale clock. If the GS counter is set to the 8-bit mode, the output on-off
repetition cycles every 256th grayscale clock.
196
Display timing reset mode (0 = disabled, 1 = enabled).
When this bit is 1, the GS counter is reset to 0 and all outputs are forced off at the GSLAT rising edge for a GS data write. This
function is identical to the low pulse of the XBLNK signal when input. Therefore, the XBLNK signal is not needed to control
from a display controller. PWM control starts again from the next input GSCKR, -G, or -B rising edge.
When this bit is 0, the GS counter is not reset and no outputs are forced off even if a GSLAT rising edge is input. In this mode,
the XBLNK signal should be input after the PWM control of all LEDs is finished. Otherwise, the PWM control might be not
exact.
198, 197
Grayscale counter mode select, bits 1–0.
The grayscale counter mode is selected by the setting of bits 1 and 0. Table 11 shows the GS counter mode.
Table 11. GS Counter-Mode Truth Table
GRAYSCALE COUNTER MODE
BIT 1
BIT 0
FUNCTION MODE
0
X (don't care)
12-bit counter mode (maximum output on-time = 4095 × GS clock)
1
0
10-bit counter mode (maximum output on-time = 1023 × GS clock)
1
1
8-bit counter mode (maximum output on-time = 255 × GS clock)
The grayscale data latch bit length is always 288 bits in any grayscale counter mode. All constant-current outputs
are forced off at the 256th grayscale clock in the 8-bit mode even if all grayscale data are FFFh. In 10-bit mode,
all outputs are forced off at 1024th grayscale clock even if all grayscale data are FFFh.
9.4.5.3.5 User-Defined Data Latch
The user-defined (UD) data latch is 17 bits in length and is not used for any device functionality. However, these
data can be used for communication between a controller connected to DCSIN and another controller connected
to GSSIN. When the device is powered on, the data in the UD latch are not set to a specific default value.
Table 12. Data-Bit Assignment
BITS
USER-DEFINED DATA BITS
215–199
16–0
9.4.6 Status Information Data (SID)
Status information data (SID) are 288 bits in length and are read-only data. SID consists of the LED opendetection (LOD) error, LED short-detection (LSD), thermal-error flag (TEF), and the data in the DC, BC, FC, and
UD data latch. The SID are shifted out onto GSSOUT with the GSSCK rising edge after GSLAT is input for a GS
data write. These SID are loaded into the 288-bit common shift register after data in the 288-bit common shift
register are copied to the data latch.
34
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LOD/LSD Data Latch (48 Bits)
216-Bit DC/BC/FC/UD Data Latch
LSB
MSB
LOD
Data of
OUTB7
¼
LOD
Data of
OUTR0
LSD
Data of
OUTB7
¼
LSD
Data of
OUTR0
TEF
BC Data
of
OUTBn
Common Common Common
Data Bit Data Bit Data Bit
191
215-199 198-192
User
Defined
Bits 16-0
17
Function
Control
Bits 6-0
¼
BC Data
of
OUTRn
DC Data
of
OUTB7
¼
DC Data
of
OUTR0
¼
Common Common
Data Bit Data Bit
167
168
¼
Common
Data Bit
0
7
(Reserved Data)
GSSOUT
Common
Data Bit
287
¼
Common Common
Data Bit Data Bit
263
264
¼
Common Common
Data Bit Data Bit
239
240
Common
Data Bit
238-216
GSSIN
GSSCK
LSB
MSB
288-Bit Common Shift Register
Figure 48. DC, BC, and FC Data-Load Assignment
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Table 13. Data-Bit Assignment
36
BITS
DESCRIPTION
6–0
Dot correction data bits 6–0 for OUTR0
13–7
Dot correction data bits 6–0 for OUTG0
20–14
Dot correction data bits 6–0 for OUTB0
27–21
Dot correction data bits 6–0 for OUTR1
34–28
Dot correction data bits 6–0 for OUTG1
41–35
Dot correction data bits 6–0 for OUTB1
48–42
Dot correction data bits 6–0 for OUTR2
55–49
Dot correction data bits 6–0 for OUTG2
62–56
Dot correction data bits 6–0 for OUTB2
69–63
Dot correction data bits 6–0 for OUTR3
76–70
Dot correction data bits 6–0 for OUTG3
83–77
Dot correction data bits 6–0 for OUTB3
90–84
Dot correction data bits 6–0 for OUTR4
97–91
Dot correction data bits 6–0 for OUTG4
104–98
Dot correction data bits 6–0 for OUTB4
111–105
Dot correction data bits 6–0 for OUTR5
118–112
Dot correction data bits 6–0 for OUTG5
125–119
Dot correction data bits 6–0 for OUTB5
132–126
Dot correction data bits 6–0 for OUTR6
139–133
Dot correction data bits 6–0 for OUTG6
146–140
Dot correction data bits 6–0 for OUTB6
153–147
Dot correction data bits 6–0 for OUTR7
160–154
Dot correction data bits 6–0 for OUTG7
167–161
Dot correction data bits 6–0 for OUTB7
175–168
Global brightness-control data bits 7–0 for OUTR0–OUTR7 group
183–176
Global brightness-control data bits 7–0 for OUTG0–OUTG7 group
191–184
Global brightness-control data bits 7–0 for OUTB0–OUTB7 group
198–192
Function control data bits 6–0
215–199
User-defined data bits 16–0
238–216
Reserved for TI test
239
Thermal error flag (TEF)
1 = High temperature condition, 0 = Normal temperature condition
247–240
LED short detection (LSD) data for OUTR7–OUTR0
1 = LED is shorted, 0 = Normal operation
255–248
LSD data for OUTG7–OUTG0
1 = LED is shorted, 0 = Normal operation
263–256
LSD data for OUTB7–OUTB0
1 = LED is shorted, 0 = Normal operation
271–264
LED open detection (LOD) data for OUTR7–OUTR0
1 = LED is open or connected to GND, 0 = Normal operation
279–272
LOD data for OUTG7–OUTG0
1 = LED is open or connected to GND, 0 = Normal operation
287–280
LOD data for OUTB7–OUTB0
1 = LED is open or connected to GND, 0 = Normal operation
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9.4.7 Continuous Base LOD, LSD, and TEF
The LOD and LSD data are updated at the rising edge of the 33rd GSCKR, -G, or -B pulse after XBLNK goes
high and the data are retained until the next 33rd GSCKR, -G, or -B. LOD and LSD data are valid when GS data
are equal to or higher than 20h (32d). If GS data are less than 20h (32d), LOD and LSD data are not valid and
must be ignored. A 1 in an LOD bit indicates an open LED or shorted LED to GND with a low-impedance
condition for the corresponding output. A 0 indicates normal operation. A 1 in an LSD bit indicates a shorted LED
condition for the corresponding output. A 0 indicates normal operation. When the device is powered on, LOD and
LSD data do not show correct values. Therefore, LOD and LSD data must be read from the 33rd GSCKR, -G, or
-B pulse input after XBLNK goes high.
The TEF bit indicates that the device temperature is too high. The TEF flag also indicates that the device has
turned off all drivers to avoid damage by overheating the device. A 1 in the TEF bit means that the device
temperature has exceeded the detect temperature threshold (TTEF) and all outputs are turned off. A 0 in the TEF
bit indicates normal operation with normal temperature conditions. The device automatically turns the drivers
back on when the device temperature decreases to less than (TTEF – THYST). Table 14 shows a truth table for
LOD, LSD, and TEF.
Table 14. LOD, LSD, and TEF Truth Table
CONDITION
SID DATA
LED OPEN DETECTION (LODn)
LED SHORT DETECTION (LSDn)
THERMAL ERROR FLAG (TEF)
0
LED is not open
(VOUTRn/Gn/Bn > VLOD)
LED is not shorted
(VOUTRn/Gn/Bn ≤ VLSD)
Device temperature is lower than highside detect temperature
(Temperature ≤ TTEF)
1
LED is open or shorted to GND
(VOUTRn/Gn/Bn ≤ VLOD)
LED is shorted between anode and
cathode or shorted to higher-voltage side
(VOUTRn/Gn/Bn > VLSD)
Device temperature is higher than highside detect temperature and driver is
forced off
(Temperature > TTEF)
XBLNK
(1)
1 2 3 4
GSCKR
GSCKG
GSCKB
30 31 32 33 34 35
4094 4096
4093 4095
1 2 3
30 31 32 33 34 35
1st GSCLK Period
OFF
OUTRn/Gn/Bn
(Data = FFFh)
ON
VOUTRn/Gn/Bn
GND
LOD/LSD Data Latch
(Internal)
(1)
Old LOD/LSD Data
If the OUTRn/Gn/Bn voltage (VOUTRn/Gn/Bn) is less than VLOD (0.25 V, typ) at the rising edge of the 33rd
GSCKR/G/B after the rising edge of XBLNK or internal blank, the LOD sets the SID bit corresponding
to the output equal to ‘1’.
Also, if the OUTRn/Gn/Bn voltage is greater than than VLSD (2.5 V, typ) at the rising edge of the 33rd
GSCKR/G/B after the falling edge of XBLNK or internal blank, the LSD sets the SID bit equal to ‘1’.
New LOD/LSD Data
The internal blank signal is generated at the rising edge of the GSLAT input signal for GS data with the display-timing
reset enabled. Also, the signal is generated at the 4096th GSCK when auto repeat mode is enabled. XBLNK can be
connected to VCC when the display timing reset or auto repeat is enabled.
Figure 49. LED-Open Detection (LOD), LED-Shorted Detection, and Data-Update Timing
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC5951DAP
ACTIVE
HTSSOP
DAP
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5951
TLC5951DAPR
ACTIVE
HTSSOP
DAP
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5951
TLC5951RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
TLC
5951
TLC5951RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
TLC
5951
TLC5951RTAR
ACTIVE
WQFN
RTA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
TLC5951
RTA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC5951DAPR
HTSSOP
DAP
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
TLC5951RHAR
VQFN
RHA
40
2500
330.0
TLC5951RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
16.4
6.3
6.3
1.1
12.0
16.0
TLC5951RHAT
VQFN
RHA
40
250
Q2
330.0
16.4
6.3
6.3
1.1
12.0
16.0
TLC5951RTAR
WQFN
RTA
40
2500
Q2
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC5951DAPR
HTSSOP
DAP
38
2000
350.0
350.0
43.0
TLC5951RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
TLC5951RHAR
VQFN
RHA
40
2500
338.0
355.0
50.0
TLC5951RHAT
VQFN
RHA
40
250
338.0
355.0
50.0
TLC5951RTAR
WQFN
RTA
40
2500
338.0
355.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
4.15±0.1
(0.2) TYP
11
20
36X 0.5
10
21
SYMM
41
2X
4.5
1
PIN1 IDENTIFICATION
(OPTIONAL)
30
31
40
SYMM
40X 0.5
0.3
40X 0.28
0.16
0.1
0.05
C A B
C
4219112/A 07/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
( 4.15)
40
31
40X (0.6)
40X (0.22)
1
30
36X (0.5)
SYMM
41
2X 2X
(4.5) (5.8)
2X
(0.685)
2X
(1.14)
(R0.05) TYP
10
21
12X (Ø0.2) VIA
TYP
20
11
2X (1.14)
2X (0.685)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219112/A 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
9X ( 1.17)
40
31
40X (0.6)
40X (0.22)
1
41
30
36X (0.5)
SYMM
2X 2X
(4.5) (5.8)
2X
(1.37)
(R0.05) TYP
10
21
EXPOSED
METAL
20
11
2X (1.37)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED COVERAGE BY AREA
SCALE: 15X
4219112/A 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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