Texas Instruments | TPS65100-Q1 Triple-Output LCD Supply With Linear Regulator and VCOM Buffer (Rev. C) | Datasheet | Texas Instruments TPS65100-Q1 Triple-Output LCD Supply With Linear Regulator and VCOM Buffer (Rev. C) Datasheet

Texas Instruments TPS65100-Q1 Triple-Output LCD Supply With Linear Regulator and VCOM Buffer (Rev. C) Datasheet
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TPS65100-Q1
SLVS849C – JULY 2008 – REVISED SEPTEMBER 2017
TPS65100-Q1 Triple-Output LCD Supply With Linear Regulator and VCOM Buffer
1 Features
3 Description
•
•
The TPS65100-Q1 device offers a compact and small
power supply solution that provides all three voltages
required by thin-film transistor (TFT) LCD displays.
The auxiliary linear regulator controller can be used
to generate a 3.3-V logic power rail for systems
powered by a 5-V supply rail only.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C5
Input Voltage Range: 2.7-V to 5.8-V
VO1 Boost Converter
– Up to 15 V Output Voltage
– Virtual Synchronous Converter Topology
– < 1% Output Voltage Accuracy
– 1.6-MHz Fixed Switching Frequency
– 2.3-A Switch Current Limit
VO2 Negative Regulated Charge Pump
– Down to -12 V / 20 mA
VO3 Positive Regulated Charge Pump
– Up to 30 V / 20 mA
Three Independently Adjustable Outputs
Integrated VCOM Buffer
Auxiliary 3.3-V Linear Regulator Controller
Internal Soft Start
Internal Power-On Sequencing
Protection Features
– Short-Circuit Detection of all Outputs
– Overvoltage Protection of all Outputs
– Thermal Shutdown
Available in TSSOP-24 PowerPAD™ Package
2 Applications
•
•
•
•
•
Infotainment Systems
Automotive Displays
Instrument Clusters
Center Consoles
Rear Seat Entertainment
The main output, VO1, is a 1.6-MHz fixed-frequency
PWM boost converter that provides the source-drive
voltage for the LCD display. The TPS65100-Q1 has a
typical switch current limit of 2.3 A. A fully integrated
adjustable charge pump doubler-tripler provides the
positive LCD gate-drive voltage. An externally
adjustable negative charge pump provides the
negative gate-drive voltage.
The TPS65100-Q1 has an integrated VCOM buffer to
power the LCD backplane. For LCD panels powered
by 5 V only, the TPS65100-Q1 device has a linear
regulator controller using an external transistor to
provide a regulated 3.3-V output for the digital
circuits. For maximum safety, the TPS65100-Q1
device goes into shutdown as soon as one of the
outputs is out of regulation. The device can be
enabled again by toggling the input or the enable
(EN) pin to GND.
Device Information(1)
PART NUMBER
TPS65100-Q1
PACKAGE
TSSOP (24) with
PowerPAD
BODY SIZE (NOM)
4.40 mm × 7.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPS65100-Q1 Overview
VIN
2.7 V to 5.8 V
Boost
Converter
VO1
Up to 15 V / 400 mA
Positive Charge
Pump
VO3
Up to 30 V / 20 mA
Negative
Charge Pump
VO2
Up to 12 V / 20 mA
VCOM Buffer
VCOM
Linear Regulator
Controller
VO4
3.3 V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65100-Q1
SLVS849C – JULY 2008 – REVISED SEPTEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
10.3 Thermal Considerations ........................................ 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2016) to Revision C
Page
•
Changed Features List .......................................................................................................................................................... 1
•
Changed from TA to TJ in the Conditions statement of and changed temperature from 85°C to 125°C................................ 6
•
Changed the MAIN BOOST CONVERTER VREF spec from 1.205 MIN to 1.198, and MAX from 1.203 to 1.230 ................. 6
•
Changed VFB spec from 1.113 MIN to 1.126, and MAX from 1.154 to 1.161 ........................................................................ 6
•
Changed rDS(ON) for VO1 = 10 V, Isw = 500 mA condition, from 290 to 325 MAX; and, for the VO1 = 5 V, Isw = 500
mA condition, changed from 420 to 455 MAX........................................................................................................................ 6
•
Changed fSW Condition from TA to TJ and changed fSW spec for 0°C ≤ TJ ≤ 125°C condition from 1.295 MIN to 1.195
MIN; and, changed the MIN from 1.191 to 1.091, for the –40°C ≤ TJ ≤ 125°C condition; .................................................... 6
•
Changed from TA to TJ in the Conditions statement of and changed temperature from 85°C to 125°C................................ 7
•
Changed NEGATIVE CHARGE PUMP VO2 VREF spec from 1.205 MIN to 1.198, and MAX from 1.219 to 1.226 ................ 7
•
Changed POSITIVE CHARGE PUMP VO3 VREF spec from 1.205 MIN to 1.198, and MAX from 1.219 to 1.226.................. 7
•
Changed VFB spec from 1.187 MIN to 1.180, and MAX from 1.238 to 1.245 ........................................................................ 7
•
Changed POSITIVE CHARGE PUMP VO3, VD spec from 720 MAX to 800 .......................................................................... 7
•
Changed from TA to TJ in the Conditions statement of and changed temperature from 85°C to 125°C................................ 8
Changes from Revision A (April 2012) to Revision B
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, Feature
Description section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Deleted Ordering Information table. See Mechanical, Packaging, and Orderable Information for more information. ........... 4
•
Changed R1 and R2 values ................................................................................................................................................. 17
•
Added clarification on linear regulator use for VI = 5 V, but not VI = 3.3 V. ......................................................................... 19
2
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Changes from Original (July 2008) to Revision A
•
Page
Added thermal table for PWP Package.................................................................................................................................. 6
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5 Pin Configuration and Functions
PWP Package
24-Pin TSSOP
Top View
FB1
1
24
EN
FB4
2
23
ENR
BASE
3
22
COMP
VIN
4
21
FB2
SW
5
20
REF
SW
6
19
GND
18
DRV
Thermal
Pad
PGND
7
PGND
8
17
C1–
SUP
9
16
C1+
VCOM
10
15
C2–/MODE
VCOMIN
11
14
C2+
FB3
12
13
OUT3
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BASE
3
O
Base drive output for the external transistor
C1+
16
—
Positive terminal of the charge pump flying capacitor
C1–
17
—
Negative terminal of the charge pump flying capacitor
C2+
14
—
Positive terminal for the charge pump flying capacitor. If the device runs in voltage doubler mode, this
pin should be left open.
C2–/MODE
15
—
Negative terminal of the charge pump flying capacitor and charge pump MODE pin. If the flying
capacitor is connected to this pin, the converter operates in a voltage tripler mode. If the charge pump
needs to operate in a voltage doubler mode, the flying capacitor is removed and the C2–/MODE pin
should be connected to GND.
COMP
22
—
Compensation pin for the main boost converter. A small capacitor is connected to this pin.
DRV
18
O
External charge pump driver
EN
24
I
Enable pin of the device. This pin should be terminated and not be left floating. A logic high enables the
device and a logic low shuts down the device.
ENR
23
I
Enable pin of the linear regulator controller. This pin should be terminated and not be left floating. Logic
high enables the regulator and a logic low puts the regulator in shutdown.
FB1
1
I
Feedback pin of the boost converter
FB2
21
I
Feedback pin of negative charge pump
FB3
12
I
Feedback pin of positive charge pump
FB4
2
I
Feedback pin of the linear regulator controller. The linear regulator controller is set to a fixed output
voltage of 3.3 V or 3 V depending on the version.
OUT3
13
PWR
REF
20
O
Internal reference output typically 1.23 V
SUP
9
I
Supply of the positive and negative charge pump, boost converter gate-drive circuit, and VCOM buffer.
Should be connected to the output of the main boost converter and cannot be connected to any other
voltage source. For performance reasons, do not connect a bypass capacitor directly to this pin.
4
Positive charge pump output
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SW
5, 6
PWR
Switch pin of the boost converter
VCOM
10
PWR
VCOM buffer output
VCOMIN
11
I
VIN
4
PWR
Input voltage pin of the device
GND
19
GND
Connect this pin to common ground plane under the thermal power pad.
PGND
7, 8
GND
Power ground
—
GND
The exposed PowerPAD should be connected to the power ground (PGND).
Thermal pad
Positive input terminal of the VCOM buffer. When the VCOM buffer is not used, this terminal can be
connected to GND to reduce the overall quiescent current of the IC.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage range (2)
MAX
UNIT
VIN
–0.3
6
SUP
–0.3
15.5
EN, MODE, ENR
–0.3
VI + 0.3
V
Voltage
VCOMIN
14
V
Voltage (2)
SW
20
V
Continuous power dissipation
See Thermal Information
Operating junction temperature range
–40
Lead temperature (soldering, 10 seconds)
Storage temperature, Tstg
(1)
(2)
–65
150
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
Machine model (MM)
±100
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VI
Input voltage
(1)
L
Inductor
TA
Operating free-air temperature
(1)
NOM
2.7
MAX
5.8
4.7
–40
UNIT
V
μH
125
°C
See Inductor Selection for further information.
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6.4 Thermal Information
TPS65100-Q1
THERMAL METRIC (1)
PWP (TSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
37.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.5
°C/W
RθJB
Junction-to-board thermal resistance
16.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
16.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VI = 3.3 V, EN = VIN, VO1 = 10 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ENR = VCOMIN = GND, VO3 = 2 × VO1,
Boost converter not switching
0.7
0.9
UNIT
SUPPLY CURRENT
IQ
Quiescent current into VIN
mA
IQCharge
Charge pump quiescent current into
SUP
VO1 = SUP = 10 V, VO3 = 2 × VO1
1.7
2.7
VO1 = SUP = 10 V, VO3 = 3 × VO1
3.9
6
IQVCOM
VCOM quiescent current into SUP
ENR = GND, VO1 = SUP = 10 V
750
1300
μA
IQEN
LDO controller quiescent current
into VIN
ENR = VIN, EN = GND
300
800
μA
ISD
Shutdown current into VIN
EN = ENR = GND
1
10
μA
VUVLO
Undervoltage lockout threshold
VIN falling
2.2
2.4
Thermal shutdown
Temperature rising
160
mA
V
°C
LOGIC SIGNALS EN, ENR
VIH
High-level input voltage
VIL
Low-level input voltage
ILeak
Input leakage current
1.5
EN = GND or VIN
V
0.01
0.4
V
0.1
μA
15
V
MAIN BOOST CONVERTER
VO1
Output voltage range
5
VO1 - VI
Minimum input to output
voltage difference
1
VREF
Reference voltage
1.198
1.213
1.230
VFB
Feedback regulation voltage
1.126
1.146
1.161
V
IFB
Feedback input bias current
10
100
nA
rDS(ON)
N-MOSFET on-resistance (Q1)
VO1 = 10 V, Isw = 500 mA
195
325
VO1 = 5 V, Isw = 500 mA
285
455
ILIM
N-MOSFET switch current limit (Q1)
2.3
2.7
rDS(ON)
P-MOSFET on-resistance (Q2)
VO1 = 10 V, Isw = 100 mA
9
15
VO1 = 5 V, Isw = 100 mA
14
22
IMAX
Maximum P-MOSFET peak switch
current
ILeak
Switch leakage current
fSW
6
Oscillator frequency
1.6
Vsw = 15 V
V
mΩ
A
Ω
1
A
μA
1
10
0°C ≤ TJ ≤ 125°C
1.195
1.6
2.1
–40°C ≤ TJ ≤ 125°C
1.091
1.6
2.1
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V
MHz
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Electrical Characteristics (continued)
VI = 3.3 V, EN = VIN, VO1 = 10 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Line regulation
2.7 V ≤ VI ≤ 5.7 V, Iload = 100 mA
Load regulation
0 mA ≤ IO ≤ 300 mA
MIN
TYP
MAX
UNIT
0.012
%/V
0.2
%/A
NEGATIVE CHARGE PUMP VO2
VO2
Output voltage range
VREF
Reference voltage
VFB
Feedback regulation voltage
IFB
Feedback input bias current
rDS(ON)
IO
Q8 P-channel switch rDS(ON)
Q9 N-channel switch rDS(ON)
–2
1.213
1.226
–36
0
36
mV
10
100
nA
IO = 20 mA
Maximum output current
V
1.198
4.3
8
2.9
4.4
20
Line regulation
7 V ≤ VO1 ≤ 15 V, Iload = 10 mA, VO2 = –5 V
Load regulation
1 mA ≤ IO ≤ 20 mA, VO2 = –5 V
V
Ω
mA
0.09
%/V
0.126
%/mA
POSITIVE CHARGE PUMP VO3
VO3
Output voltage range
30
V
VREF
Reference voltage
1.198
1.213
1.226
V
VFB
Feedback regulation voltage
1.180
1.214
1.245
V
IFB
Feedback input bias current
10
100
nA
Q3 P-channel switch rDS(ON)
9.9
15.5
Q4 N-channel switch rDS(ON)
1.1
1.8
4.6
8.5
1.2
2.2
610
800
rDS(ON)
Q5 P-channel switch rDS(ON)
IO = 20 mA
Q6 N-channel switch rDS(ON)
VD
D1–D4 Shottky diode forward
voltage
IO
Maximum output current
ID1–D4 = 40 mA
20
Ω
mV
mA
Line regulation
10 V ≤ VO1 ≤ 15 V, Iload = 10 mA, VO3 = 27 V
0.56
%/V
Load regulation
1 mA ≤ IO ≤ 20 mA, VO3 = 27 V
0.05
%/mA
LINEAR REGULATOR CONTROLLER VO4
VO4
Output voltage
IBASE
Maximum base drive current
4.5 V ≤ VI ≤ 5.5 V, 10 mA ≤ IO ≤ 500 mA
VI - VO4 - VBE ≥ 0.5 V
(1)
VI - VO4 - VBE ≥ 0.75 V
(1)
3.2
3.3
13.5
19
20
27
Line regulation
4.75 V ≤ VI ≤ 5.5 V, Iload = 500 mA
0.186
Load regulation
1 mA ≤ IO ≤ 500 mA, VI = 5 V
0.064
Start up current
VO4 ≤ 0.8 V
11
20
3.4
V
mA
%/V
%/A
25
mA
VCOM BUFFER
VCM
Common mode input range
VOS
Input offset voltage
DC Load regulation
IB
(VO1) - 2
–25
25
IO = ±25 mA
–30
37
IO = ±50 mA
–45
55
IO = ±100 mA
–72
85
IO = ±150 mA
–97
110
VCOMIN Input bias current
IPeak
(1)
2.25
IO = 0 mA
Peak output current
–300
–30
300
V
mV
mV
nA
VO1 = 15 V
1.2
A
VO1 = 10 V
0.65
A
VO1 = 5 V
0.15
A
With VI = supply voltage of the TPS65100-Q1, VO4 = output voltage of the regulator, VBE = basis emitter voltage of external transistor
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Electrical Characteristics (continued)
VI = 3.3 V, EN = VIN, VO1 = 10 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO1 Rising
–12 –8.75% VO1
–6
V
VO2 Rising
–13
–9% VO2
–5
V
VO3 Rising
–11
–8% VO3
–5
V
FAULT PROTECTION THRESHOLDS
V(th,
Vo1)
V(th,
Vo2)
V(th,
Vo3)
Shutdown threshold
6.6 Typical Characteristics
1.9
8
fSW – Switching Frequency − MHz
− N−Channel Main Switch − mW
r
DS(on)
350
300
Vo1 = 5 V
250
200
Vo1 = 10 V
150
Vo1 = 15 V
100
−40
−20
0
20
40
60
80
100
1.8
VI = 2.7 V
1.7
VI = 3.3 V
1.6
VI = 5.8 V
1.5
1.4
1.3
−40
−20
0
20
40
60
80
100
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 1. rDS(ON) N-Channel Main Switch vs
Junction Temperature
Figure 2. Switching Frequency vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS65100-Q1 is a complete bias supply for LCD displays. It contains a main boost converter to supply the
source driver. It operates with a fixed switching frequency of 1.6 MHz to allow for small external components.
The boost converter output voltage VO1 is also the input voltage, connected via the pin SUP, for the positive and
negative charge pumps and the bias supply for the VCOM buffer.
The linear regulator controller is independent from this system with its own enable pin. This design allows the
linear regulator controller to continue to operate while the other supply rails are disabled or in shutdown due to a
fault condition on one of their outputs.
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7.2 Functional Block Diagram
VIN
SW
SW
Q2
FB1
FB2
FB3
Bias Vref = 1.213 V
Thermal Shutdown
Start-Up Sequencing
Undervoltage Detection
Short-Circuit Protection
S
D
Main boost
converter
EN
Current Limit
and
Soft Start
1.6-MHz
Oscillator
SUP
Control Logic
Gate Drive Circuit
D
Q1
S
COMP
GM Amplifier
Comparator
Sawtooth
Generator
FB1
VFB
1.146 V
SUP
SUP
(VO)
FB3
Positive
Charge Pump
GM Amplifier
Low Gain
VFB
1.146 V
Vref
1.214 V
Negative
Charge Pump
SUP
Q8
D
Q3
S
Current
Control
C1−
Gain Select
(Doubler or
Tripple Mode)
D
Q4
S
SUP
Soft Start
D
C1+
Current
Control
Soft Start
S
DRV
D
Q7
S
D
Q9
SUP
SUP
S
Vo3
D1
D2
D Q5
D4
S
C2+
FB2
D
Vref
0V
S
D3
Q6
C2−
Reference
Output
Vref
1.213 V
REF
SUP
Vin
Soft Start
Iref = 20 mA
Soft Start
Short Circuit
Detect
D
Q11
S
~1 V
FB4
VCOM
D
Linear
Regulator
Controller
S
Vref
1.213 V
D
Q12
S
Q10
Disable
VCOM
Buffer
ENR
BASE
VCOMIN
GND
PGND
PGND
7.3 Feature Description
7.3.1 Main Boost Converter
The main boost converter operates with PWM and a fixed switching frequency of 1.6 MHz. The converter uses a
unique fast-response voltage-mode controller scheme with input voltage feedforward. This achieves excellent line
and load regulation (0.2%/A load regulation typical) and allows the use of small external components. For higher
flexibility to the selection of external component values the device uses external loop compensation. The
TPS65100-Q1 device maintains continuous conduction even at light load currents because of an internal PMOS
10
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Feature Description (continued)
in parallel connected between SW and SUP pin. When the inductor current is positive, the external schottky
diode with the lower forward voltage conducts the current. This causes the converter to operate with a fixed
frequency in continuous conduction mode over the entire load current range. This avoids the ringing on the
switch pin as seen with a standard nonsynchronous boost converter and allows a simpler compensation for the
boost converter.
7.3.2 VCOM Buffer
VCOMIN is the input of the VCOM buffer. If VCOM is not required connect VCOMIN pin to Ground and thereby
reduce the overall quiescent current.
The VCOM buffer features soft start to avoid a large voltage drop at VO1. During operation the VCOMIN pin
cannot be pulled dynamically to ground.
7.3.3 Positive Charge Pump
The TPS65100-Q1 device has a fully regulated integrated positive charge pump generating VO3. The input
voltage for the charge pump is applied to the SUP pin that is equal to the output of the main boost converter VO1.
The charge pump is capable of supplying a minimum load current of 20 mA. Depending on the voltage difference
between VO1 and VO3 higher load currents are possible (see Figure 17 and Figure 18).
7.3.4 Negative Charge Pump
The TPS65100-Q1 device has a regulated negative charge pump using two external Schottky diodes. The input
voltage for the charge pump is applied to the SUP pin that is connected to the output of the main boost converter
VO1. The charge pump inverts the main boost converter output voltage and is capable of supplying a minimum
load current of 20 mA. Depending on the voltage difference between VO1 and VO2, higher load currents are
possible (see Figure 16).
7.3.5 Linear Regulator Controller
The TPS65100-Q1 device includes a linear regulator controller to generate a 3.3-V rail which is useful when the
system is powered from a 5-V supply. The regulator is independent from the other voltage rails of the device and
has its own enable (ENR). Since most of the systems require this voltage rail to come up first it is recommended
to use a R-C delay on EN. This delays the start-up of the main boost converter which will reduce the inrush
current as well.
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7.4 Device Functional Modes
7.4.1 Enable and Power-ON Sequencing (EN, ENR)
The device has two enable pins. These pins should be terminated and should not be left floating to prevent
unpredictable operation. Pulling the enable pin (EN) high enables the device and starts the power-on sequencing
with the main boost converter VO1 coming up first, then the negative and positive charge pump and the VCOM
buffer. If the VCOMIN pin is held low, the VCOM buffer remains disabled. The linear regulator has an
independent enable pin (ENR). Pulling this pin low disables the regulator, and pulling this pin high enables this
regulator.
If the enable pin EN is pulled high, the device starts its power-ON sequencing. The main boost converter starts
up first with its soft start. If the output voltage has reached 91.25% of its output voltage, the negative charge
pump comes up next. The negative charge pump starts with a soft start and when the output voltage has
reached 91% of the nominal value, the positive charge pump comes up with a soft start. The VCOM buffer is
enabled as soon as the positive charge pump has reached its nominal value and VCOMIN is greater than
typically 1 V. Pulling the enable pin low shuts down the device. Depended on load current and output
capacitance, each of the outputs goes down.
7.4.2 Soft Start
The main boost converter as well as the charge pumps, linear regulator, and VCOM buffer have an internal soft
start. This avoids heavy voltage drops at the input voltage rail or at the output of the main boost converter VO1
during start-up caused by high inrush currents (see Figure 14 and Figure 15). During soft start of the main boost
converter VO1, the internal current limit threshold is increased in three steps. The device starts with the first step,
where the current limit is set to 2/5 of the typical current limit (2/5 of 2.3 A) for 1024 clock cycles, then increased
to 3/5 of the current limit for 1024 clock cycles, and finally raised to the full current limit.
7.4.3 Fault Protection
All the outputs of the TPS65100-Q1 device have short-circuit detection that can force the device into shutdown.
The main boost converter has overvoltage and undervoltage protection. If the output voltage VO1 rises above the
overvoltage protection threshold of 105% of VO1 (typical), the device stops switching but remains operational.
When the output voltage falls below this threshold again, the converter continues operation. When the output
voltage falls below power good threshold of 91.25% of VO1 (typical), in case of a short-circuit condition, then the
TPS65100-Q1 device goes into shutdown. Because there is a direct pass from the input to the output through the
diode, the short-circuit condition remains. If this condition needs to be avoided, a fuse at the input or an output
disconnect using a single transistor and resistor is required. The negative and positive charge pumps have an
undervoltage lockout to protect the LCD panel from possible latchup conditions in the event of a short-circuit
condition or faulty operation. When the negative output voltage is less than 90.5% (typical) of its output voltage
(closer to ground), the device enters shutdown. When the positive charge pump output voltage VO3 is below 92%
(typical) of its output voltage, the device goes into shutdown as well. See the electrical characteristics table under
fault protection thresholds. The device can be enabled again by toggling the enable pin (EN) below 0.4 V or by
cycling the input voltage below the UVLO of 1.7 V. The linear regulator reduces the output current to typical 20
mA under a short-circuit condition when the output voltage is < 1 V (typical). See the functional block diagram.
The linear regulator does not go into shutdown under a short-circuit condition.
7.4.4 Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to excessive heat and power dissipation. Typically,
the thermal shutdown threshold is 160°C. If this temperature is reached, the device goes into shutdown. The
device can be enabled by toggling the enable pin to low and back to high or by cycling the input voltage to GND
and back to VI again.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Figure 3 shows a general overview of the device and connections used in an application. Ranges are shown for
several parameters to demonstrate the flexibility available to the application designer.
L1
4.7 mH
VI
2.7 to 5.8 V
C3
22 mF
Vo1
Up to 15 V/350 mA
D1
TPS65100-Q1
C5
C4
22 mF
R1
C13
10 nF
Vo1
VIN
COMP
R7
VCOMIN
Vo2
Up to 12 V/20 mA
C12
D3
R3
C6
0.22 mF
ENR
0.22 mF
C2
C2+
C2-/MODE
C1+
C1-
D2
FB1
SUP
EN
C1
0.22 mF
R8
SW
SW
0.22 mF
R2
Vo3
up to 30 V/20 mA
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
R5
PGND
BASE
C7
0.22 mF
GND
R4
R6
C11
220 nF
Q1
BCP68
VI
C9
1 mF
Vo4
3.3 V
C10
4.7 mF
Vcom
C8
1 mF
Figure 3. Simplified Schematic
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8.2 Typical Applications
8.2.1 Supply for a Typical Approximately 7-inch Display
A typical application requirement is to boost a 3.3-V or 5-V input to a 10-V, 13.5-V, or 15-V output. The Detailed
Design Procedure section explains the step-by-step development.
VI
3.3 V
L1
4.2 mH
C3
22 mF
VO1
R9
15 kW
R7
500 kW
VIN
SW
COMP
SW
VCOMIN
R8
500 kW
C14
1 nF
EN
C1
0.22 mF
D2
VO2
-5 V/20 mA
C12
R3
619 kW
C5
0.22 mF
C8
6.8 pF
TPS65100-Q1
C9
1 nF
0.22 mF
D3
ENR
R1
432 kW
FB1
C2
C1+
C1-
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
C4
22 mF
R2
56.2 kW
SUP
C2+
C2-/MODE
BASE
VO1
10 V/300 mA
D1
0.22 mF
VO3
23 V/20 mA
R5
1 MW
C6
0.22 mF
PGND
GND
R4
150 kW
R6
56.2 kW
C11
22 nF
Vcom
5V
C7
1 mF
Figure 4. Supply for a 7-inch Display Diagram
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
14
DESIGN PARAMETER
EXAMPLE VALUE
VI
3.3 V
VO1
10 V
VO2
–5 V
VO3
23 V
Switch voltage drop, VSW
0.5 V
Schottky diode forward voltage, VD
0.8 V
VCOM
5V
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Boost Converter Design Procedure
The first step in the design procedure is to calculate the maximum possible output current of the main boost
converter under certain input and output voltage conditions. This example is for a 3.3-V to 10-V conversion:
1. Duty cycle
VO + VD - VI
10 V + 0.8 V - 3.3 V
D=
=
= 0.73
VO + VD - VSW 10 V + 0.8 V - 0.5 V
(1)
2. Average inductor current
I
300 mA
IL = O =
= 1.11 A
1 - D 1 - 0.73
3. Inductor peak-to-peak ripple current
(V - VSW )´ D (3.3 V - 0.5 V )´ 0.73
DIL = I
=
= 304 mA
ƒS ´ L
1.6 MHz ´ 4.2 µH
(2)
(3)
4. Peak switch current
DI
304 mA
I swpeak = IL + L = 1.11 A +
= 1.26 A
2
2
(4)
The integrated switch, the inductor, and the external Schottky diode must be able to handle the peak switch
current. The calculated peak switch current must be equal to or lower than the minimum N-MOSFET switch
current limit specified in Electrical Characteristics. If the peak switch current is higher, the converter cannot
support the required load current. This calculation must be done for the minimum input voltage, where the peak
switch current is highest. The calculation includes conduction losses like switch rDS(ON) (0.5 V) and diode forward
drop voltage losses (0.8 V). Additional switching losses and inductor core and winding losses require a slightly
higher peak switch current in the actual application. This calculation still allows for good design and component
selection.
8.2.1.2.1.1 Inductor Selection
Several inductors work with the TPS65100-Q1 device and, particularly with the external compensation,
performance can be adjusted to application requirements. The main parameter for inductor selection is the
saturation current of the inductor, which should be higher than the peak switch current as previously calculated,
with additional margin to allow for heavy load transients and extreme start-up conditions. Another method is to
choose an inductor with a saturation current at least as high as the minimum switch current limit of 1.6 A. The
different switch-current limits allow selection of a physically smaller inductor when less output current is required.
Another important parameter is inductor DC resistance. Usually, the lower the DC resistance, the higher the
efficiency. However, inductor DC resistance is not the only parameter determining the efficiency. Especially for a
boost converter where the inductor is the energy storage element, the type and material of the inductor
influences the efficiency as well. At the high switching frequency of 1.6 MHz, inductor core losses, proximity
effects, and skin effects are more important. Usually, an inductor with a larger form factor yields higher efficiency.
The efficiency difference between different inductors can vary between 2% to 10%. TI recommends inductor
values between 3.3 μH and 6.8 μH.
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8.2.1.2.1.2 Output Capacitor Selection
For the best output voltage filtering, TI recommends a low ESR output capacitor. Ceramic capacitors have a low
ESR value, but depending on the application, tantalum capacitors can be used as well. A 22-μF ceramic output
capacitor works for most of the applications. Higher capacitor values can be used to improve the load transient
regulation. The output voltage ripple can be calculated as:
DVO =
ö
IO æ 1
IP ´ L
´ç
÷ + IP ´ ESR
C O è ƒ S VO + VD - VI ø
where
•
•
•
•
•
•
•
IP = Peak switch current as calculated in the previous section with ISW(peak)
L = Selected inductor value
IO = Normal load current
ƒS = Switching frequency
VD = Rectifier diode forward voltage (typical 0.3 V)
CO = Selected output capacitor
ESR = Output capacitor ESR value
(5)
8.2.1.2.1.3 Input Capacitor Selection
For good input voltage filtering, TI recommends low ESR ceramic capacitors. A 22-μF ceramic input capacitor is
sufficient for most of the applications. For better input voltage filtering, this value can be increased.
8.2.1.2.1.4 Rectifier Diode Selection
To achieve high efficiency, a Schottky diode should be used. The voltage rating must be higher than the
maximum output voltage of the converter. The average forward current must be equal to the average inductor
current of the converter. The main parameter influencing the efficiency of the converter is the forward voltage and
the reverse leakage current of the diode; both must be as low as possible.
8.2.1.2.1.5 Converter Loop Design and Stability
The TPS65100-Q1 device converter loop can be externally compensated and allows access to the internal
transconductance error amplifier output at the COMP pin. A small feedforward capacitor across the upper
feedback resistor divider speeds up the circuit as well. To test the converter stability and load transient
performance of the converter, a load step from 50 mA to 250 mA is applied, and the output voltage of the
converter is monitored. Applying load steps to the converter output is a good tool to judge the stability of such a
boost converter.
8.2.1.2.1.6 Design Procedure Quick Steps
1.
2.
3.
4.
16
Select the feedback resistor divider to set the output voltage.
Select the feedforward capacitor to place a zero at 50 kHz.
Select the compensation capacitor on pin COMP. The smaller the value, the higher the low frequency gain.
Use a 50-kΩ potentiometer in series to CC and monitor VO1 during load transients. Fine tune the load
transient by adjusting the potentiometer. Select a resistor value that comes closest to the potentiometer
resistor value. This needs to be done at the highest VI and highest load current since the stability is most
critical at these conditions.
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8.2.1.2.1.7 Setting the Output Voltage and Selecting the Feedforward Capacitor
The output voltage is set by the external resistor divider and is calculated as:
R1 ö
æ
VO = 1.146 V ´ ç 1 +
÷
R2
è
ø
(6)
Across the upper resistor a bypass capacitor is required to speed up the circuit during load transients as shown
in Figure 5.
VO1
Up to 10 V/150 mA
D1
C8
6.8 pF
R1
432 kW
C4
22 mF
SW
SW
FB1
SUP
C2
C2+
0.22 mF
R2
56.2 kW
C2-/MODE
Figure 5. Feed-forward Capacitor
Together with R1 the bypass capacitor C8 sets a zero in the control loop at approximately 50 kHz:
1
ƒZ =
2 ´ p ´ C8 ´ R1
(7)
A value closest to the calculated value should be used. Larger feedforward capacitor values reduce the load
regulation of the converter and cause load steps as shown in Figure 6.
Load Step
Figure 6. Load Step Caused By A Too Large Feed-forward Capacitor Value
For more information on how to calculate a Boost Converter's Output Stage refer to Basic Calculation of a Boost
Converter's Power Stage.
8.2.1.2.2 Negative Charge Pump
The negative charge pump provides a regulated output voltage by inverting the main output voltage VO1. The
negative charge pump output voltage within its output voltage range is set with external feedback resistors.
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The maximum load current of the negative charge pump depends on the voltage drop across the external
Schottky diodes and the internal on resistance of the charge pump MOSFETS. When the voltage drop across
these components is larger than the voltage difference from VO1 to VO2, the charge pump is in dropout, providing
the maximum possible output current. Therefore, the higher the voltage difference between VO1 and VO2, the
higher the possible load current. See Figure 16 for the possible output current versus boost converter voltage
VO1.
Estimating the maximum output voltage range of a single negative charge-pump stage:
VO(min) = –( VO1 - 2 × VD - IO × ( 2 × rDS(ON)Q8 + 2 × rDS(ON)Q9 ))
(8)
Setting the output voltage:
R3
R3
VO = –VREF ´
= –1.213 V ´
R4
R4
VO
VO
R3 = R4 ´
= R4 ´
VREF
1.213 V
(9)
(10)
The lower feedback resistor value R4 should be in a range between 40 kΩ to 120 kΩ or the overall feedback
resistance should be within 500 kΩ to 1 MΩ. Smaller values load the reference too heavily and larger values may
cause stability problems. For this design, 619 kΩ and 150 kΩ were chosen, delivering –5 V. The negative charge
pump requires two external-Schottky diodes. The peak current rating of the Schottky diode has to be twice the
load current of the output. For a 20-mA output current, the dual Schottky diode BAT54 or similar is a good
choice.
8.2.1.2.3 Positive Charge Pump
The positive charge pump can be operated in a voltage doubler mode or a voltage tripler mode.
The output voltage needs to be within the voltage ranges of the configuration, see Voltage Doubler Mode and
Voltage Tripler Mode. The output voltage within its limitation is set by the external resistor divider and is
calculated as:
æ R5 ö
VOUT = 1.214 ´ ç 1 +
÷
è R6 ø
(11)
æV
ö
æV
ö
R5 = R6 ´ ç OUT - 1÷ = R6 ´ ç OUT - 1÷
V
1.214
è
ø
è FB
ø
(12)
The maximum load current of the positive charge pump depends on the voltage drop across the internal Schottky
diodes, the internal ON-resistance of the charge pump MOSFETS, and the impedance of the flying capacitor.
When the voltage drop across these components is larger than the voltage difference VO1 × 2 to VO3 (doubler
mode) or VO1 × 3 to VO3 (tripler mode), then the charge pump is in dropout, providing the maximum possible
output current. Therefore, the higher the voltage difference between VO1 x 2 (doubler) or VO1 × 3 (tripler) to VO3,
the higher the possible load current. See Figure 17 and Figure 18 for output current versus boost converter
voltage, VO1, and the following calculations.
8.2.1.2.3.1 Voltage Doubler Mode
•
•
Leave C2+ pin open
Connect C2–/Mode to GND
The following shows first order formulas to calculate the minimum and maximum output voltages of the positive
charge pump in doubler mode
• Minimum: VO3min = VO1
• Maximum: VO3max = 2 × VO1 – (2 VF + 2 × IO × (2 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4))
For detailed information how to estimate the output voltage ranges refer to How to Estimate the Output Voltage
Range of the Charge Pumps in the TPS6510x and TPS6514x. SLVA918
8.2.1.2.3.2 Voltage Tripler Mode
•
18
Connect flying capacitor to C2+ and C2–/MODE
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The following shows first order formulas to calculate the minimum and maximum output voltages of the positive
charge pump in doubler mode
• Minimum: VO3min = 2 × VO1 – (2 VF + 2 × IO × (2 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4))
• Maximum: VO3max = 3 × VO1 – (4 × VF + 2 × IO × (3 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4 ))
For detailed information how to estimate the output voltage ranges refer to How to Estimate the Output Voltage
Range of the Charge Pumps in the TPS6510x and TPS6514x SLVA918.
8.2.1.2.4 VCOM Buffer
The VCOM buffer is typically used to drive the backplane of a TFT panel. The VCOM output voltage is typically
set to half of the main output voltage VO1 plus a small shift to implement the specific compensation voltage. The
TFT video signal gets coupled through the TFT storage capacitor plus the LCD cell capacitance to the output of
the VCOM buffer. Because of these, short current pulses in the positive and negative direction appear at the
output of the VCOM buffer. To minimize the output voltage ripple caused by the current pulses, a
transconductance amplifier having a current source output and an output capacitor is used. The output capacitor
supports the high frequency part of the current pulses drawn from the LCD panel. The VCOM buffer only needs
to handle the low frequency portion of the current pulses. A 1-μF ceramic output capacitor is sufficient for most of
the applications. When using other output capacitor values it is important to keep in mind that the output
capacitor is part of the VCOM buffer loop stabilization.
The VCOM buffer has an integrated soft start to avoid voltage drops on VO1 during start-up. The soft start is
implemented as such that the VCOMIN is held low until the VCOM buffer is fully biased and the common mode
range is reached. Then the positive input is released and the VCOM buffer output slowly comes up. Usually a 1nF capacitor on VCOMIN to GND is used to filter high frequency noise coupled in from VO1. The size of this
capacitor together with the upper feedback resistor value determines the start-up time. The larger the capacitor
from VCOMIN to GND, the slower the soft start.
8.2.1.2.5 Linear Regulator Controller
The TPS65100-Q1 device includes a linear regulator controller to generate a 3.3-V rail when the system is
powered from a 5-V supply. Because an external NPN transistor is required, the input voltage of the TPS65100Q1 device applied to VIN needs to be higher than the output voltage of the regulator. To provide a minimum
base drive current of 13.5 mA, a minimum internal voltage drop of 500 mV from VI to Vbase is required. This can
be translated into a minimum input voltage on VI for a certain output voltage as Equation 13 shows:
VI(min) = VO4 + VBE + 0.5 V
(13)
The current design operating from VI = 3.3 V cannot support this and the linear regulator is not used. The second
example operating from VI = 5 V has the 3.3-V regulator implemented.
The base drive current together with the hFE of the external transistor determines the possible output current.
External transistors are selected depending on the output current, power dissipation, and PCB space
requirements of the application. The device is stable with a 4.7-μF ceramic output capacitor. Larger output
capacitor values can be used to improve the load transient response when higher load currents are required.
8.2.1.3 Application Curves
Table 2. Table Of Graphs
FIGURE
Main Boost Converter
Efficiency VO1
vs Load current
Figure 7
Efficiency VO1
vs Load current
Figure 8
Efficiency VO1
vs Input voltage
Figure 9
PWM operation, continuous mode
Figure 10
PWM operation at light load
Figure 11
Load transient response, CO = 22 μF
Figure 12
Load transient response, CO = 2 × 22 μF
Figure 13
Power-up sequencing
Figure 14
Soft start VO1
Figure 15
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Table 2. Table Of Graphs (continued)
FIGURE
Negative Charge Pump
VO2 Maximum load current
vs Output voltage VO1
Figure 16
VO3 Maximum load current
vs Output voltage VO1 (doubler mode)
Figure 17
VO3 Maximum load current
vs Output voltage VO1 (tripler mode)
Figure 18
Positive Charge Pump
100
100
90
90
Vo1 = 6 V
80
Vo1 = 10 V
70
Efficiency − %
Efficiency − %
80
60
50
Vo1 = 15 V
40
70
Vo1 = 10 V
60
50
Vo1 = 15 V
40
30
30
VI = 3.3 V
Vo2, Vo3 = No Load, Switching
20
10
VI = 5 V
Vo2, Vo3 = No Load, Switching
20
10
1
10
100
IL − Load Current − mA
1k
1
Figure 7. Efficiency VO1 vs Load Current
10
100
IL − Load Current − mA
1k
Figure 8. Efficiency VO1 vs Load Current
100
ILoad at Vo1 = 100 mA
Vo2, Vo3 = No Load, Switching
VSW
10 V/div
Efficiency - %
95
Vo1 = 6 V
90
Vo1 = 10 V
85
VO
50 mV/div
Vo1 = 15 V
80
IL
1 A/div
75
70
2.5
VI = 3.3 V
VO = 10 V / 300 mA
3
3.5
4
4.5
5
VI - Input V oltage - V
5.5
6
250 ns/div
Figure 9. Efficiency VO1 vs Input Voltage
20
Figure 10. PWM Operation Continuous Mode
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VSW
10 V/div
VO1
200 mV/div
VO
50 mV/div
VI = 3.3 V
VO = 10 V / 10 mA
IO
50 mA to 250 mA
IL
500 mA/div
VI = 3.3 V
VO1 = 10 V, CO = 22 mF
250 ns/div
100 ms/div
Figure 11. PWM Operation At Light Load
Figure 12. Load Transient Response 1 x CO
VI = 3.3 V
VO1 = 10 V, CO = 2 × 22 mF
VO1
5 V/div
VO1
100 mV/div
VO2
5 V/div
VO3
10 V/div
IO
50 mA to 250 mA
VI = 3.3 V
VO = 10 V
VCOM CI = 1 nF
VCOM
2 V/div
500 ms/div
100 ms/div
Figure 14. Power-Up Sequencing
Figure 13. Load Transient Response 2 x CO
0.20
Vo2 = −8 V
VI = 3.3 V
VO = 10 V
IO = 300 mA
0.18
TA = −40°C
I O − Output Current − A
0.16
VO1
5 V/div
II
500 mA/div
0.14
TA = 85°C
0.12
0.10
TA = 25°C
0.08
0.06
0.04
0.02
0
8.8
10.8
11.8
12.8
13.8
14.8
Vo1 − Output Voltage − V
500 ms/div
Figure 15. Soft Start VO1
9.8
Figure 16. VO2 Maximum Load Current
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0.12
0.14
TA = −40°C
Vo3 = 18 V (Doubler Mode)
0.10
TA = −40°C
I O − Output Current − A
I O − Output Current − A
0.12
TA = 85°C
0.10
TA = 25°C
0.08
0.06
0.04
TA = 25°C
0.08
TA = 85°C
0.06
0.04
0.02
0.02
Vo3 = 28 V (Tripler Mode)
0
9
10
11
12
13
14
0
15
9
10
11
12
13
14
15
Vo1 − Output Voltage − V
Vo1 − Output Voltage − V
Figure 17. VO3 Maximum Load Current (Doubler Mode)
Figure 18. VO3 Maximum Load Current (Tripler Mode)
8.2.2 Supply for a Typical Approximately 8-inch Display
L1
4.7 mH
CDRH5D18-4R1
VIN
5V
C3
22 mF
VO1
R9
4.3 kW
R7
500 kW
C14
1 nF
VIN
C1
0.22 mF
VO2
-7 V/20 mA
C12
0.22 mF
D2
C6
0.22 mF
R3
750 kW
D3
SW
VCOMIN
FB1
R2
75 kW
SUP
ENR
C2+
C1+
C1-
C2-/MODE
VO3
23 V/20 mA
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
BASE
C7
0.22 mF
R5
1 MW
PGND
GND
R4
130 kW
C11
220 nF
C4
22 mF
R1
820 kW
SW
COMP
EN
R8
500 kW
C5
3.3 pF
TPS65100-Q1
C9
2.2 nF
VO1
13.5 V/400 mA
D1
R6
56.2 kW
Q1
BCP68
Vin
C12
1 mF
Vcom
7V
VO4
3.3 V/500 mA
C10
4.7 mF
C8
1 mF
Figure 19. Simplified Schematic for a Typical Approximately 8-inch Display
9 Power Supply Recommendations
Apply a supply voltage of 2.7 V to 5.8 V to the VIN pin. In case the 3.3-V linear regulator is supposed to be used,
a higher minimum voltage needs to be applied, allowing for some drop-out. As in most cases, the 3.3-V rail
needs to come up before the main boost-converter does, an RC-element on the EN pin can delay the ramp of
the boost converter.
22
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TPS65100-Q1
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SLVS849C – JULY 2008 – REVISED SEPTEMBER 2017
10 Layout
10.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high-peak currents
and switching frequencies. If the layout is not carefully designed, the regulator might show stability and EMI
problems. TI recommends the following PCB layout guidelines for the TPS65100-Q1 device:
• Connect PGND and AGND together on the same ground plane.
• Connect all capacitor grounds and PGND together on a common ground plane.
• Place the input filter capacitor as close as possible to the input pin of the IC.
• Route first the traces carrying high-switching currents with wide and short traces.
• Isolate analog signal paths from power paths.
• If vias are necessary, try to use more than one in parallel to decrease parasitics, especially for power traces.
• Solder the thermal pad to the PCB for good thermal performance
10.2 Layout Example
High-switching-current paths
Figure 20. Layout Example
10.3 Thermal Considerations
An influential component of thermal performance of a package is board design. To take full advantage of the
heat dissipation abilities of the PowerPAD package with exposed thermal die, a board that acts similar to a heat
sink and allows the use of an exposed (and solderable) deep downset pad should be used. For further
information, see PowerPAD Thermally Enhanced Package, SLMA002, and PowerPAD Made Easy, SLMA004.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002
• PowerPAD Made Easy, SLMA004
• How to Compensate with the TPS6510x and TPS6514x, SLVA813.
• Basic Calculation of a Boost Converter's Power Stage, SLVA372
• Customizing Your TPS6510x/TPS6514x, SLVA192
• Power Management Guide 2016 at www.ti.com
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65100QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
24
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
65100Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS65100-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2017
• Catalog: TPS65100
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65100QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65100QPWPRQ1
HTSSOP
PWP
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 2.200
PLASTIC SMALL OUTLINE
6.6
TYP
6.2
PIN 1 ID
AREA
A
SEATING PLANE
0.1 C
22X 0.65
24
1
C
2X
7.15
7.9
7.7
NOTE 3
12
B
13
24X
4.5
4.3
0.30
0.19
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
(1)
2.40
1.65
DETAIL A
TYPICAL
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
( 0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
BASED ON
0.125 THICK
STENCIL
SYMM
22X (0.65)
13
12
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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