Texas Instruments | TPS3700-Q1 Window Comparator for Over- and Undervoltage Detection (Rev. B) | Datasheet | Texas Instruments TPS3700-Q1 Window Comparator for Over- and Undervoltage Detection (Rev. B) Datasheet

Texas Instruments TPS3700-Q1 Window Comparator for Over- and Undervoltage Detection (Rev. B) Datasheet
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TPS3700-Q1
SLVSCI7B – MARCH 2014 – REVISED JULY 2017
TPS3700-Q1 Window Comparator for Over- and Undervoltage Detection
1 Features
3 Description
•
•
The TPS3700-Q1 wide-supply voltage window
comparator operates over a 1.8-V to 18-V range. The
device has two high-accuracy comparators with an
internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and
undervoltage detection. The TPS3700-Q1 device can
be used as a window comparator or as two
independent voltage monitors; the monitored voltage
can be set with the use of external resistors.
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
Wide Supply Voltage Range: 1.8 to 18 V
Adjustable Threshold: Down to 400 mV
Open-Drain Outputs for Overvoltage and
Undervoltage Detection
Low Quiescent Current: 5.5 µA (typ)
High Threshold Accuracy:
– 1% Over Temperature
– 0.25% (typ)
Internal Hysteresis: 5.5 mV (typ)
Available in ThinSOT23-6 and WSON Packages
1
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
•
Automotive Safety Applications
Body Electronics
Infotainment
Low Battery Detection
Power Sequencing
Industrial Control Systems
FPGA and ASIC Applications
Microcontroller and DSP Applications
The OUTA terminal is driven low when the voltage at
the INA+ terminal drops below (VIT+ – Vhys), and goes
high when the voltage returns above the respective
threshold (VIT+). The OUTB terminal is driven low
when the voltage at the INB– terminal rises above
VIT+, and goes high when the voltage drops below the
respective threshold (VIT+ – Vhys). Both comparators
in the TPS3700-Q1 device include built-in hysteresis
for filtering to reject brief glitches, thereby ensuring
stable output operation without false triggering.
The TPS3700-Q1 device is available in a
ThinSOT23-6 package and is specified over the
junction temperature range of –40°C to 125°C.
Device Information(1)
ORDER NUMBER
TPS3700QDDCRQ1
PACKAGE
BODY SIZE
SOT23 (6)
2.90 mm × 1.60 mm
WSON (6)
1.50 mm x 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
VMON
1.8 V to 18 V
RP1
OUTA
INA+
RP2
R2
Device
INA+
VIT+
INB±
VIT+
OUTB
INB–
R3
To a reset
or enable
input of
the system.
OUTB
OUTA
0.1 µF
VDD
R1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3700-Q1
SLVSCI7B – MARCH 2014 – REVISED JULY 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
Changes from Revision A (April 2014) to Revision B
Page
•
Added WSON Package to Device Information Table............................................................................................................. 1
•
Added WSON Package to Pin Configuration and Function table ......................................................................................... 3
Changes from Original (March 2014) to Revision A
•
2
Page
Changed device status from Product Preview to Production Data. ...................................................................................... 1
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6 Pin Configuration and Functions
DDC Package
SOT-6
Top View
DSE Package
WSON-6
Top View
OUTA
1
6
OUTB
GND
2
5
VDD
INA+
3
4
INB-
OUTB
1
6
OUTA
VDD
2
5
GND
INB-
3
4
INA+
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DDC
DSE
GND
2
5
—
INA+
3
4
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal drops below the threshold voltage (VIT+ –
VHYS), OUTA is driven low.
INB–
4
3
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal exceeds the threshold voltage (VIT+), OUTB is
driven low.
OUTA
1
6
O
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VIT+ – VHYS). The output goes high when the sense voltage returns
above the respective threshold (VIT+).
OUTB
6
1
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VIT+. The output goes high when the sense voltage returns below
the respective threshold (VIT+ – VHYS).
VDD
5
2
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted) (1)
Voltage
(2)
Current
MIN
MAX
VDD
–0.3
20
V
OUTA, OUTB
–0.3
20
V
INA+, INB–
–0.3
7
V
40
mA
125
°C
Output terminal current
Operating junction temperature, TJ
(1)
(2)
–40
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 Handling Ratings
Tstg
Storage temperature range
(2)
(3)
MAX
UNIT
–65
150
°C
Human body model (HBM) ESD stress voltage (2)
VESD (1)
(1)
MIN
2.5
Charge device model (CDM) ESD stress voltage (3)
kV
1
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
VDD
Supply voltage
VI
Input voltage
VO
Output voltage
MIN
MAX
1.8
18
UNIT
V
INA+, INB–
0
6
V
OUTA, OUTB
0
18
V
7.4 Thermal Information
THERMAL METRIC (1)
DDC
(6 TERMINALS)
RθJA
Junction-to-ambient thermal resistance
204.6
RθJC(top)
Junction-to-case (top) thermal resistance
50.5
RθJB
Junction-to-board thermal resistance
54.3
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
52.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
VDD
TEST CONDITIONS
Supply voltage range
V(POR)
VIT+
Power-on reset voltage
(1)
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (hys = VIT+ – VIT–)
VOL
Input current (at the INA+ or INB–
terminal)
Low-level output voltage
Ilkg(OD)
Open-drain output leakage-current
Supply current
Startup delay
UVLO
(1)
(2)
(3)
UNIT
V
0.8
V
400
404
mV
396
400
404
mV
387
394.5
400
mV
387
394.5
400
mV
5.5
12
mV
25
nA
VDD = 1.8 V
396
VDD = 18 V
VDD = 1.8 V
VDD = 18 V
VDD = 1.8 V and 18 V, VI = 6.5 V
–25
1
VDD = 1.8 V and 18 V, VI = 0.1 V
–15
1
15
nA
VDD = 1.3 V, IO = 0.4 mA
250
mV
VDD = 1.8 V, IO = 3 mA
250
mV
VDD = 5 V, IO = 5 mA
250
mV
VDD = 1.8 V and 18 V, VO = VDD
300
nA
VDD = 1.8 V, VO = 18 V
300
nA
5.5
11
µA
VDD = 5 V
6
13
µA
VDD = 12 V
6
13
µA
VDD = 18 V
7
13
µA
(2)
Undervoltage lockout (3)
MAX
18
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
VDD = 1.8 V, no load
IDD
TYP
1.8
Positive-going input threshold voltage
I(INA+)
I(INB–)
MIN
150
VDD falling
1.3
µs
1.7
V
The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.
When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR).
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7.6 Timing Requirements
Over operating temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
tPHL
High-to-low propagation delay (1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV
See Figure 1
18
µs
tPLH
Low-to-high propagation delay (1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV
See Figure 1
29
µs
(1)
High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 1. Timing Diagram
7.7 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tr
Output rise time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tf
Output fall time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
6
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MIN
TYP
MAX
UNIT
2.2
µs
0.22
µs
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7.8 Typical Characteristics
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
10
401
Positive-Going Input Threshold (mV)
9
Supply Current (µA)
8
7
6
5
4
3
40qC
0qC
25qC
85qC
125qC
2
1
0
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
400.6
399.4
-25
-10
5
D001
20
35
50
65
Temperature (qC)
80
95
110 125
D003
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
Low-to-High Propagation Delay (µs)
31
8
Hysteresis Voltage (mV)
1.8 V
5V
1.2 V
18 V
399.8
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD)
7
6
5
VDD
VDD
VDD
VDD
4
3
-40
-25
-10
5
20
35
50
65
Temperature (qC)
80
95
=
=
=
=
1.8 V
5V
12 V
18 V
27
25
23
21
19
17
15
13
11
9
-40
110 125
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
29
-25
D004
20
28
18
26
16
Input Pulse Duration (µs)
30
24
22
20
18
16
14
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
12
10
8
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D005
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Figure 4. Hysteresis (Vhys) vs Temperature
Low-to-High Propagation Delay (µs)
=
=
=
=
400.2
399
-40
18
VDD
VDD
VDD
VDD
INA+
INB–
14
12
10
8
6
4
2
110 125
D006
0
2.5
4
5.5
7
8.5
10
11.5
13
14.5
Positive-Going Input Threshold Overdrive (%)
16
D007
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
Figure 7. Minimum Pulse Width vs
Threshold Overdrive Voltage
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Typical Characteristics (continued)
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
11
2000
Low-Level Output Voltage(mV)
10
Supply Current (µA)
9
8
7
6
5
4
40qC
0qC
25qC
85qC
125qC
3
2
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
1
0
0
4
8
12
16
20
24
28
Output Sink Current (mA)
32
36
40
0
5
Figure 8. Supply Current (IDD) vs
Output Sink Current
1750
Low-Level Output Voltage (mV)
Low-Level Output Voltage(mV)
35
40
D009
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1500
1250
1000
750
500
250
0
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
5
10
D010
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
15
20
25
30
Output Sink Current (mA)
35
40
D011
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
Low-level output voltage (mV)
1750
Low-level output voltage (mV)
15
20
25
30
Output Sink Current (mA)
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
2000
1500
1250
1000
750
500
1500
1250
1000
750
500
250
250
0
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
5
D012
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
8
10
D008
10
15
20
25
30
Output Sink Current (mA)
35
40
D013
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
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8 Detailed Description
8.1 Overview
The TPS3700-Q1 device combines two comparators for overvoltage and undervoltage detection. The TPS3700Q1 device is a wide-supply voltage range (1.8 to 18 V) device with a high-accuracy rising input threshold of 400
mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V and can sink up to 40 mA.
The TPS3700-Q1 device is designed to assert the output signals, as shown in Table 1. Each input terminal can
be set to monitor any voltage above 0.4 V using an external resistor divider network. With the use of two input
terminals of different polarities, the TPS3700-Q1 device forms a window comparator. Broad voltage thresholds
can be supported that allow the device to be used in a wide array of applications.
Table 1. TPS3700-Q1 Truth Table
CONDITION
OUTPUT
INA+ > VIT+
OUTA high
Output A not asserted
STATUS
INA+ < VIT–
OUTA low
Output A asserted
INB– > VIT+
OUTB low
Output B asserted
INB– < VIT–
OUTB high
Output B not asserted
8.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
8.3 Feature Description
8.3.1 Inputs (INA+, INB–)
The TPS3700-Q1 device combines two comparators. Each comparator has one external input (inverting and
noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling
hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although
not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the
comparator input for extremely noisy applications in order to reduce sensitivity to transients and layout parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 1.
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Feature Description (continued)
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see
Figure 1. Together, these comparators form a window-detection function as discussed in the Window
Comparator section.
8.3.2 Outputs (OUTA, OUTB)
In a typical TPS3700-Q1 application, the outputs are connected to a reset or enable input of the processor (such
as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage
regulator (such as a DC-DC or low-dropout regulator [LDO]).
The TPS3700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to
hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to
the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels.
The TPS3700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. To ensure proper
voltage levels, some thought should be given while choosing the pullup resistor values. The pullup resistor value
is determined by VOL, sink-current capability, and output-leakage current (Ilkg(OD)). These values are specified in
the Electrical Characteristics table. By using wired-AND logic, OUTA and OUTB can merge into one logic signal.
Table 1 and the Inputs (INA+, INB–) section describe how the outputs are asserted or de-asserted. See Figure 1
for a timing diagram that describes the relationship between threshold voltages and the respective output.
8.3.3 Window Comparator
The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit
using a resistor divider network, as shown in Figure 14 and Figure 15. The input terminals can monitor any
system voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor
for undervoltage and overvoltage conditions, respectively.
VMON
(13.2 V to 10.8 V)
1.8 V to 18 V
VDD
RP1
(50 kW)
IN
OUTA
INA+
Voltage
Regulator VO
R2
(13.7 kW)
EN
Device
OUTB
INB–
R3
(69.8 kW)
OUT
R1
(2.21 MW)
UV VMON OV
OUT
GND
Figure 14. Window Comparator Block Diagram
10
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Feature Description (continued)
Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 15. Window Comparator Timing Diagram
8.3.4 Immunity to Input Terminal Voltage Transients
The TPS3700-Q1 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity
to transients is dependent on both transient duration and amplitude; see the Minimum Pulse Width vs Threshold
Overdrive Voltage curve (Figure 7) in the Typical Characteristics section.
8.4 Device Functional Modes
The TPS3700-Q1 has a single functional mode, which is on when VDD is greater than 1.8 V.
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9 Application and Implementation
9.1 Application Information
The TPS3700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8-V to
18-V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window
comparator or as two independent voltage monitors. The monitored voltages are set with the use of external
resistors.
9.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However some applications may require the outputs to be
pulled up to a higher or lower voltage than VDD in order to correctly interface with the reset and enable the
terminal of other devices.
VPULLUP
(Up To 18 V)
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 16. Interfacing to Voltages Other Than VDD
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Application Information (continued)
9.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 17. Monitoring the Same Voltage as VDD
9.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired thresholds in connected to the rail that is being monitored.
VMON
(26.4 V to 21.7 V)
1.8 V to 18 V
R1
(2.61 MW)
VDD
OUTA
INA+
R2
(8.06 kW)
Device
OUTB
INB–
R3
(40.2 kW)
To a reset or enable input
of the system.
GND
NOTE: The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 18. Monitoring a Voltage Other Than VDD
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Application Information (continued)
9.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
Some applications may want to monitor for overvoltage conditions on one rail while also monitoring for
undervoltage conditions on a different rail. In those applications two independent resistor dividers will need to be
used.
1.8 V to 18 V
OUTA
INA+
To a reset or enable
input of the system.
Device
12 V
OUTB
INB–
INA+
VIT+
INB–
VIT+
OUTB
5V
OUTA
VDD
GND
NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low when an
overvoltage condition is detected at the 12-V rail.
Figure 19. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail
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9.2 Typical Application
VDD
C1
0.1 µF
VPULLUP
R4
49.9 k
U1
TPS3700DDC
R1
2.21 M
VDD
INA+
INB±
R2
13.7 k
5
1
3
6
4
2
R5
49.9 k
OUTA
OUTB
GND
R3
69.8 k
Figure 20. Typical Application Schematic
9.2.1 Design Requirements
9.2.1.1 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the VDD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
9.2.1.2 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
9.2.2 Detailed Design Procedure
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltage.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100-times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
RT
R3 =
´ VIT+
VMON(OV)
where
•
VMON(OV) is the target voltage at which an overvoltage condition is detected
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Typical Application (continued)
Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
´ VIT+ - R3
VMON (no UV)
where
•
R2 =
VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
RT
´ (VIT+ - Vhys)
VMON(UV)
(3)
- R3
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
(4)
9.2.3 Application Curves
TJ = 25°C
OUTB
C2
(2 V/div)
C1
(2 V/div)
C2
(2 V/div)
OUTB
OUTA
C3
(2 V/div)
C1
(2 V/div)
C3
(2 V/div)
VDD
VDD = 5 V
Time (100 µs/div)
V(INA+) = 390 mV
OUTA
VDD
G013
V(INB–) = 410 mV
VDD = 5 V
Figure 21. Startup Delay
(Outputs Pulled Up to VDD)
Time (100 µs/div)
V(INA+) = 410 mV
G014
V(INB–) = 390 mV
Figure 22. Startup Delay
(Outputs Pulled Up to VDD)
10 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.8 V and 18 V.
16
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11 Layout
11.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (see Figure 23) or
both resistors can be tied to a single pullup resistor if a logical AND function is desired.
VPULLUP
VPULLUP
11.2 Layout Example
Figure 23. TPS3700-Q1 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Using the TPS3700 as a Negative Rail Over- and Undervoltage Detector, SLVA600
• Optimizing Resistor Dividers at a Comparator Input, SLVA450
• TPS3700EVM-114 Evaluation Module, SLVU683
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS3700QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PD7Q
TPS3700QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
5O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2017
OTHER QUALIFIED VERSIONS OF TPS3700-Q1 :
• Catalog: TPS3700
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS3700QDDCRQ1
SOT23-THIN
DDC
6
3000
179.0
8.4
TPS3700QDSERQ1
WSON
DSE
6
3000
179.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
1.8
1.8
1.0
4.0
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS3700QDDCRQ1
SOT-23-THIN
DDC
6
3000
195.0
200.0
45.0
TPS3700QDSERQ1
WSON
DSE
6
3000
195.0
200.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
SCALE 4.000
SOT
3.05
2.55
1.75
1.45
PIN 1
INDEX AREA
1.1 MAX
B
1
0.1 C
A
6
4X 0.95
3.05
2.75
1.9
4
3
0.5
0.3
0.2
0.1
TYP
0.0
6X
0 -8 TYP
0.20
TYP
0.12
C A B
C
SEATING PLANE
0.6
TYP
0.3
0.25
GAGE PLANE
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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