Texas Instruments | bq2408x-Q1 1-A, Single Chip, Li-Ion and Li-Pol Automotive Charger (Rev. B) | Datasheet | Texas Instruments bq2408x-Q1 1-A, Single Chip, Li-Ion and Li-Pol Automotive Charger (Rev. B) Datasheet

Texas Instruments bq2408x-Q1 1-A, Single Chip, Li-Ion and Li-Pol Automotive Charger (Rev. B) Datasheet
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bq24080-Q1, bq24081-Q1
SLUSCB6B – MAY 2015 – REVISED JUNE 2017
bq2408x-Q1 1-A, Single Chip, Li-Ion and Li-Pol Automotive Charger
1 Features
3 Description
•
The bq24080-Q1 and bq24081-Q1 are highly
integrated and flexible Li-Ion linear charge devices
targeted at space-limited charger applications. They
offer an integrated power FET and current sensor,
high-accuracy current and voltage regulation, charge
status, and charge termination, in a single monolithic
device. An external resistor sets the magnitude of the
charge current.
1
•
•
•
•
•
•
•
Integrated Power FET and Current Sensor for
Up to 1-A Charge Applications From AC Adapter
Precharge Conditioning With Safety Timer
Charge and Power-Good Status Output
Automatic Sleep Mode for Low Power
Consumption
Integrated Charge-Current Monitor
Fixed 7-Hour Fast Charge Safety Timer
Ideal for Low-Dropout Charger Designs for
Single-Cell Li-Ion or Li-Pol Packs in
Space-Limited Portable Applications
Small 3-mm × 3-mm SON Package
The device charges the battery in three phases:
conditioning, constant current, and constant voltage.
Charge is terminated based on minimum current. An
internal charge timer provides a backup safety for
charge termination. The device automatically restarts
the charge if the battery voltage falls below an
internal threshold. The device automatically enters
sleep mode when the ac adapter is removed.
2 Applications
•
•
•
•
Linear Chargers for Automotive
E-Call/ Back Up Call battery
Automotive Infotainment
Key FOB in Automotive
Device Information(1)
PART NUMBER
bq24080-Q1(2)
bq24081-Q1
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Product Preview
Simplified Schematic
AC
Adapter
VDC
GND
C1
0.1 mF
PACK+
bq24080-Q1
1
IN
C2
0.1 µF
OUT 10
PACK–
2
NC
CE
9
3
STAT1
PG
8
4
STAT2 VBSEL 7
5
VSS
Battery Pack
+
System
System
Interface
RSET
ISET
6
1.13 kW
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq24080-Q1, bq24081-Q1
SLUSCB6B – MAY 2015 – REVISED JUNE 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagram ....................................... 10
Feature Description................................................. 11
Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations ........................................ 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision A (August 2016) to Revision B
•
Page
Changed the RθJC(top) value From: 5034 °C/W To: 50.4 °C/W in the Thermal Information table ........................................... 4
Changes from Original (May 2016) to Revision A
Page
•
Recommended Operating Conditions, Changed The TJ MIN value From: 0 To: –40°C........................................................ 4
•
Electrical Characteristics, Changed the conditions statement From: 0°C ≤ TJ ≤ 125°C To: –40°C ≤ TJ ≤ 125°C ................ 5
2
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SLUSCB6B – MAY 2015 – REVISED JUNE 2017
5 Pin Configuration and Functions
bq24080-Q1 DRC Package
10 Pin VSON
Top View
VSS
5
STAT2 STAT1 GND
IN
3
1
VSS
4
6
bq24081-Q1 DRC Package
10 Pin VSON
Top View
7
ISET GND
2
8
9
10
PG
CE
OUT
STAT2 STAT1 GND
IN
5
4
3
2
1
6
7
8
9
10
TE
TS
OUT
ISET GND
Pin Functions
PIN
NAME
CE
NO.
bq24080-Q1
I/O
DESCRIPTION
bq24081-Q1
9
–
I
Charge enable input (active-low)
2, 7
2, 7
–
Ground
IN
1
1
I
Adapter dc voltage. Connect minimum 0.1-μF capacitor to VSS.
ISET
6
6
I
Charge current. External resistor to VSS sets precharge and fast-charge current, and also the
termination current value. Can be used to monitor the charge current.
OUT
10
10
O
Charge current output. Connect minimum 0.1-μF capacitor to VSS.
PG
8
–
O
Power-good status output (open-drain)
STAT1
3
3
O
STAT2
4
4
O
TE
–
8
I
TS
–
9
I/O
VSS
5
5
–
Ground
Thermal pad
–
–
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the
device. The exposed thermal pad must be connected to the same potential as the VSS pin on the
printed-circuit board. Do not use the thermal pad as the primary ground input for the device. The
VSS pin must be connected to ground at all times.
GND
Charge status outputs (open-drain)
Timer-enable input (active-low)
Temperature sense; connect to NTC in battery pack.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
bq24080-Q1, bq24081-Q1
MIN
UNIT
MAX
Input voltage (2)
IN, CE, ISET, OUT, PG, STAT1, STAT2, TE, TS
7
V
Output sink/source current
STAT1, STAT2, PG
15
mA
Output current
OUT
1.5
A
–0.3
Operating free-air temperature range, TA
Junction temperature range, TJ
Storage temperature, Tstg
(1)
(2)
–40
125
–65
150
°C
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to VSS.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
4.5
6.5
UNIT
V
TJ
Operating junction temperature range
–40
125
°C
6.4 Thermal Information
bq24080-Q1,
bq24081-Q1
THERMAL METRIC (1)
UNIT
DRC (10 PINS)
RθJA
Junction-to-ambient thermal resistance
44.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.4
°C/W
RθJB
Junction-to-board thermal resistance
19.7
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
19.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLUSCB6B – MAY 2015 – REVISED JUNE 2017
6.5 Electrical Characteristics
over –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2
2
2
5
UNIT
INPUT CURRENT
ICC(VCC)
VCC current
VCC > VCC(min)
ICC(SLP)
Sleep current
Sum of currents into OUT pin,
VCC < V(SLP)
ICC(STBY)
Standby current
CE = High, 0°C ≤ TJ ≤ 85°C
IIB(OUT)
Input current on OUT pin
Charge DONE, VCC > VCC(MIN)
150
1
mA
μA
5
VOLTAGE REGULATION VO(REG) + V(DO−MAX) ≤ VCC, I(TERM) < IO(OUT) ≤ 1 A
VO(REG)
Output voltage
4.2
TA = 25°C
Voltage regulation accuracy
V(DO)
0.35%
−1%
1%
VO(OUT) = VO(REG), IO(OUT) = 1 A
VO(REG) + V(DO)) ≤ VCC
Dropout voltage (V(IN) − V(OUT))
V
−0.35%
350
500
mV
1000
mA
V
CURRENT REGULATION
IO(OUT)
Output current range (1)
VI(OUT) > V(LOWV),
VI(IN) − VI(OUT) > V(DO),
VCC ≥ 4.5 V
V(SET)
Output current set voltage
Voltage on ISET pin, VCC ≥ 4.5 V,
VI ≥ 4.5 V, VI(OUT) > V(LOWV),
VI − VI(OUT) > V(DO)
K(SET)
Output current set factor
20
2.463
2.5
2.538
50 mA ≤ IO(OUT) ≤ 1 A
307
322
337
10 mA ≤ IO(OUT) < 50 mA
296
320
346
1 mA ≤ IO(OUT) < 10 mA
246
320
416
2.8
3
3.2
V
100
mA
270
mV
100
mA
mV
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
V(LOWV)
Precharge to fast-charge transition
threshold
Voltage on OUT pin
IO(PRECHG)
Precharge range (2)
0 V < VI(OUT) < V(LOWV), t < t(PRECHG)
2
Precharge set voltage
Voltage on ISET pin,
VO(REG) = 4.2 V,
0 V < VI(OUT) > V(LOWV), t < t(PRECHG)
240
V(PRECHG)
255
TERMINATION DETECTION
I(TERM)
Charge termination detection
range (3)
VI(OUT) > V(RCH), t < t(TRMDET)
2
V(TERM)
Charge termination detection set
voltage
Voltage on ISET pin,
VO(REG) = 4.2 V,
VI(OUT) > V(RCH), t < t(TRMDET)
235
250
265
VO(REG)
– 0.115
VO(REG)
− 0.10
VO(REG)
− 0.085
V
0.25
V
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold
STAT1, STAT2, and PG OUTPUTS
VOL
Low-level output saturation voltage
IO = 5 mA
CE and TE INPUTS
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
IIL
Low-level input current
–1
IIH
High-level input current
0.4
1
V
μA
TIMERS
I(FAULT)
(1)
(2)
(3)
Timer fault recovery current
200
μA
See Equation 2.
See Equation 1.
See Equation 4.
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Electrical Characteristics (continued)
over –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SLEEP COMPARATOR
V(SLP)
Sleep-mode entry threshold voltage
V(SLPEXIT)
Sleep-mode exit threshold voltage
2.3 V ≤ VI(OUT) ≤ VO(REG)
VCC ≤ VI(OUT)
+ 80 mV
VCC ≥ VI(OUT)
+ 190
V
THERMAL SHUTDOWN THRESHOLDS
T(SHTDWN)
Thermal trip threshold
165
TJ increasing
Thermal hysteresis
°C
15
UNDERVOLTAGE LOCKOUT
Undervoltage lockout
UVLO
Decreasing VCC
2.4
Hysteresis
2.5
2.6
27
V
mV
TEMPERATURE SENSE COMPARATOR (bq24081-Q1)
V(TS1)
High-voltage threshold
2.475
2.5
2.525
V(TS2)
Low-voltage threshold
0.485
0.5
0.515
I(TS)
TS pin current source
96
102
108
V
μA
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns,
10-mV overdrive,
VI(OUT) decreasing below threshold
250
375
500
ms
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
charging current decreasing below
10-mV overdrive
250
375
500
ms
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
decreasing below or increasing
above threshold, 10-mV overdrive
250
375
500
ms
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
Deglitch time for fast-charge to
precharge transition
TERMINATION DETECTION
tTRMDET
Deglitch time for termination
detection
BATTERY RECHARGE THRESHOLD
t(DEGL)
Deglitch time for recharge detect
TIMERS
t(PRECHG)
Precharge time
t(CHG)
Charge time
1,584
1,800
2,016
s
22,176
25,200
28,224
s
250
375
500
ms
250
375
500
ms
SLEEP COMPARATOR
V(IN) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
Sleep-mode entry deglitch time
TEMPERATURE SENSE COMPARATOR (bq24081-Q1)
t(DEGL)
6
Deglitch time for temperature fault
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SLUSCB6B – MAY 2015 – REVISED JUNE 2017
6.7 Typical Characteristics
450
IO(OUT) = 1000 mA
400
Dropout Voltage - mV
350
IO(OUT) = 750 mA
300
250
IO(OUT) = 500 mA
200
150
IO(OUT) = 250 mA
100
50
0
0
50
100
o
TJ - Junction Temperature - C
150
Figure 1. Dropout Voltage vs Junction Temperature
Figure 2. VIN Hot-Plug Power-Up Sequence
Figure 3. Charge Enable Power-Up Sequence
(CE = High-to-Low)
Figure 4. Battery Hot-Plug During Charging Phase
No battery – In termination deglitch prior to STAT1 going high. VOUT (VBAT) cycling between charge and done prior to screen capture
Stat1 goes high – In done state
2-V battery is inserted during the charge done state.
Charging is initiated – STAT1 goes low and charge current is applied.
Battery is removed – VOUT goes into regulation, IOUT goes to zero, and termination deglitch timer starts running (same as state 1).
Deglitch timer expires – charge done is declared.
Figure 5. Battery Hot-Plug and Removal Power Sequence
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7 Detailed Description
7.1 Overview
The device supports a precision Li-Ion, Li-Pol charging system suitable for single cells. Figure 6 shows a typical
charge profile, and Figure 7 shows an operational flow chart.
Preconditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Minimum
Charge
Voltage
PreConditioning
and Term
Detect
Charge
Voltage
Charge
Complete
Charge
Current
Safety Timer
M0066-01
Figure 6. Typical Charging Profile
8
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Overview (continued)
POR
SLEEP MODE
VCC > VI(OUT)
checked at all
times?
No
Indicate SLEEP
MODE
Yes
VI(OUT)<V(LOWV)
?
Yes
Regulate
IO(PRECHG)
and
Indicate ChargeIn-Progress
Reset and Start
t(PRECHG) Timer
No
Reset All Timers,
Start t(CHG) Timer
Regulate Current
or Voltage
and
Indicate ChargeIn-Progress
No
VI(OUT)<V(LOWV)
?
Yes
Yes
t(CHG) Expired?
t(PRECHG)
Expired?
No
No
Yes
Yes
Fault Condition
Yes
VI(OUT)<V(LOWV)
?
Indicate Fault
No
No
Yes
Iterm
Detection
?
VI(OUT) >V(RCH)
?
No
Yes
Enable I(FAULT)
Current
Turn Off Charge
Indicate DONE
VI(OUT) >V(RCH)
?
No
Yes
VI(OUT) <V(RCH)
?
No
Disable I(FAULT)
Current
Yes
F0018-01
Figure 7. Operational Flow Chart
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7.2 Functional Block Diagram
(3)
IN
OUT
ISET
V(PRECHG)
V(SET)
VO(REG)
V(RCH)
V(LOWV)
(3)
(3)
(3)
V(TERM)
V(IN)
ITS
VI(OUT) + V(SLP)
(3)
V(TS1)
V(UVLO)
(2)
Charge
Control,
Timers,
and
Status
TS
(3)
V(TS2)
STAT1
CE
(1)
STAT2
(2)
TE
(1)
PG
VSS
10
(1)
bq24080-Q1 only
(2)
bq24081-Q1 only
(3)
Signal deglitched
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7.3 Feature Description
7.3.1 Battery Preconditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold, the device applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. Resistor RSET, connected
between the ISET and VSS, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in
the Electrical Characteristics table.
K(SET) x V(PRECHG)
IO(PRECHG) =
RSET
(1)
The device activates a safety timer, t(PRECHG), during the conditioning phase. If the V(LOWV) threshold is not
reached within the timer period, the device turns off the charger and enunciates FAULT on the STATx pins. See
the Timer Fault and Recovery section for additional details.
7.3.2 Battery Fast-Charge Constant Current
The device offers on-chip current regulation with programmable set point. Resistor RSET, connected between the
ISET and VSS, determines the charge rate. The V(SET) and K(SET) parameters are specified in the specifications
table.
K(SET) x V(SET)
IO(OUT) =
RSET
(2)
7.3.3 Charge-Current Monitor
When the charge function is enabled internal circuits generate a current proportional to the charge current at the
ISET pin. This current, when applied to the external charge current programming resistor RISET generates an
analog voltage that can be monitored by an external host to calculate the current sourced from the OUT pin.
R(ISET)
V(ISET) = I(OUT) x
K(ISET)
(3)
7.3.4 Battery Fast-Charge Voltage Regulation
The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the
battery pack. The device monitors the battery-pack voltage between the OUT and VSS pins. When the battery
voltage rises to the VO(REG) threshold, the voltage regulation phase begins and the charging current begins to
taper down.
As a safety backup, the device also monitors the charge time in the charge mode. If charge is not terminated
within this time period, t(CHG), the charger is turned off and FAULT is set on the STATx pins. See the Timer Fault
and Recovery section for additional details.
7.3.5 Charge Termination Detection and Recharge
The device monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, charge is terminated. The V(TERM) and K(SET) parameters are specified in the Electrical
Characteristics table.
K
x V(TERM)
IO(TERM) = (SET)
RSET
(4)
After charge termination, the device restarts the charge once the voltage on the OUT pin falls below the V(RCH)
threshold. This feature keeps the battery at full capacity at all times.
The device monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, the charge is terminated immediately.
Resistor RSET, connected between the ISET and VSS, determines the current level at the termination threshold.
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Feature Description (continued)
7.3.6 Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 1. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the opendrain transistor is turned off.
Table 1. Status Pin Summary
CHANGE STATE
STAT1
Precharge in progress
ON
STAT2
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
OFF
OFF
Charge suspend (temperature)
Timer fault
Sleep mode
7.3.7
PG Output (bq24080-Q1)
The open-drain power-good (PG) output pulls low when a valid input voltage is present. This output is turned off
(high-impedance) in sleep mode. The PG pin can be used to drive an LED or communicate to the host
processor.
7.3.8 Charge-Enabled (CE) Input (bq24080-Q1)
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge and a high-level signal disables the charge and places the device in a low-power mode. A high-to-low
transition on this pin also resets all timers and timer fault conditions.
7.3.9 Timer Enabled (TE) Input (bq24081-Q1)
The TE digital input is used to disable or enable the fast-charge timer. A low-level signal on this pin enables the
fast-charge timer, and a high-level signal disables this feature.
7.3.10 Temperature Qualification (bq24081-Q1)
The bq24081-Q1 continuously monitors battery temperature by measuring the voltage between the TS and VSS
pins. An internal current source provides the bias for common 10-kΩ negative-temperature-coefficient thermistors
(NTC) (see the functional block diagram). The device compares the voltage on the TS pin with the internal V(TS1)
and V(TS2) thresholds to determine if charging is allowed. If a temperature outside the V(TS1) and V(TS2) thresholds
is detected, the device immediately suspends the charge by turning off the power FET and holding the timer
value (i.e., timers are not reset). Charge is resumed when the temperature returns within the normal range.
The allowed temperature range with a 103AT-type thermistor is 0°C to 45°C. However, the user may modify
these thresholds by adding external resistors (see Figure 8 and Figure 9).
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SLUSCB6B – MAY 2015 – REVISED JUNE 2017
bq24081-Q1
ITS
VHTF
PACK+
TS
NTC
VLTF
PACK–
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Default Temperature Thresholds
bq24081-Q1
ITS
VHTF
PACK+
RT1
TS
NTC
RT2
VLTF
PACK–
Copyright © 2016, Texas Instruments Incorporated
Figure 9. Temperature Thresholds Modified by External Resistors
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7.3.11 Timer Fault and Recovery
As shown in Figure 7, the device provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
7.3.11.1 Condition Number 1
OUT pin voltage is above the recharge threshold (V(RCH)), and a timeout fault occurs.
Recovery method: the device waits for the OUT pin voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the OUT pin voltage falls
below the recharge threshold, the device clears the fault and starts a new charge cycle. A POR, TE, or CE toggle
also clears the fault.
7.3.11.2 Condition Number 2
OUT pin voltage is below the recharge threshold (V(RCH)), and a timeout fault occurs
Recovery method: Under this scenario, the device applies the I(FAULT) current. This small current is used to detect
a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If
the OUT pin voltage goes above the recharge threshold, then the device disables the I(FAULT) current and
executes the recovery method described for condition number 1. Once the OUT pin voltage falls below the
recharge threshold, the bq24080-Q1 clears the fault and starts a new charge cycle. A POR, TE, or CE toggle
also clears the fault.
7.4 Device Functional Modes
7.4.1 Sleep Mode
The device enters the low-power sleep mode if the input power (IN) is removed from the circuit. This feature
prevents draining the battery during the absence of input supply.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq2408X-Q1 device is Lithium chemistry (Lithium Ion and Lithium Polymer) charger that is intended for
automotive applications. The allows the designer to pick an automotive qualified charger for applications where
the Li chemistry is needed. Such applications may involve E-Call (back up safety call) or infotainment systems
within the automotive space. The device comes completely ready with an integrated charge current monitor and
safety timers. The LDO based charger design allows for a cost optimized safe charging algorithm.
8.2 Typical Application
1.5 kW
SOURCE
INPUT
VDC
bq24080-Q1
C1
0.1 mF
1
IN
OUT
C2
0.1 mF
1.5 kW
GND
1.5 kW
PACK+
10
2
GND
CE
9
3
STAT1
PG
8
4
STAT2
GND
7
5
VSS
ISET
6
+
PACK–
1.13 kW
RSET
Charge Current
Translator Output
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Typical Application Circuit
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
Supply voltage
5V
Fast-charge current
≈ 750 mA
Battery-Temperature sense (bq24081-Q1)
–2°C to 44.5°C (default setting)
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8.2.2 Detailed Design Procedure
8.2.2.1 Calculations
Program the charge current for 750 mA:
RISET = [V(SET) × K(SET) / I(OUT)]
(5)
From Electrical Characteristics table, V(SET) = 2.5 V.
From Electrical Characteristics table, K(SET) = 322.
RISET = [2.5 V × 322 / 0.75 A] = 1.073 kΩ
(6)
Selecting the closest standard value, use a 1.07-kΩ resistor connected between ISET (pin 6) and ground.
8.2.2.2 Battery Temperature Sense (bq24081-Q1):
Use a Semitec 103AT-4 NTC thermistor connected between TS (pin 9) and ground.
RTHERM-cold = [V(TS1) / I(TS) ] = 2.5V / 100 μA = 25 kΩ
RTHERM-hot = [V(TS2) / I(TS) ] = 0.5V / 100 μA = 5 kΩ
(7)
(8)
Look up the corresponding temperature value in the manufacturer's resistance-temperature table for the
thermistor selected. For a 103AT-4 Semitec thermistor:
5 kΩ = 44.5°C
25 kΩ = 2°C
8.2.2.3 STAT Pins (All Devices) and PG Pin (bq24080-Q1):
Status pins Monitored by Processor:
Select a pullup resistor that can source more than the input bias (leakage) current of both the processor and
status pins and still provide a logic high.
RPULLUP ≤ [V(cc-pullup) – V(logic hi-min) / (I(µP-monitor) + I(STAT-OpenDrain)) ] = (3.3 V – 1.9 V) / (1 μA + 1 μA) ≤ 700 kΩ;
(9)
Connect a 100-kΩ pullup between each status pin and the VCC of the processor. Connect each status pin to
a μP monitor pin.
Status viewed by LED:
Select an LED with a current rating less than 10 mA and select a resistor to place in series with the LED to
limit the current to the desired current value (brightness).
RLED = [(V(IN) – V(LED-on)) / I(LED)] = (5 V – 2 V) / 1.5 mA = 2 kΩ.
(10)
Place an LED and resistor in series between the input and each status pin.
8.2.2.4 Selecting Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 0.1-μF
ceramic capacitor, placed in close proximity to the IN pin and GND pad works well. In some applications, it may
be necessary to protect against a hot plug input voltage overshoot. This is done in three ways:
1. The best way is to add an input zener, 6.2 V, between the IN pin and VSS.
2. A low-power zener is adequate for the single event transient. Increasing the input capacitance lowers the characteristic
impedance which makes the input resistance move effective at damping the overshoot, but risks damaging the input
contacts by the high inrush current.
3. Placing a resistor in series with the input dampens the overshoot, but causes excess power dissipation.
The device only requires a small capacitor for loop stability. A 0.1-μF ceramic capacitor placed between the OUT
and GND pad is typically sufficient.
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8.2.3 Application Curves
No battery – In termination deglitch prior to STAT1 going high.
VOUT (VBAT) cycling between charge and done prior to screen
capture
Stat1 goes high – In done state
2-V battery is inserted during the charge done state.
Charging is initiated – STAT1 goes low and charge current is
applied.
Battery is removed – VOUT goes into regulation, IOUT goes to
zero, and termination deglitch timer starts running (same as
state 1).
Deglitch timer expires – charge done is declared.
Figure 11. Charge Enable Power-Up Sequence
(CE = High-to-Low)
Figure 12. Battery Hot-Plug and Removal Power Sequence
9 Power Supply Recommendations
The devices are intended to operate withing the ranges shown in Recommended Operating Conditions. Because
the input of the device on pin IN is subject to a power source that is external, care muse be taken to not exercise
the pin above the Absolute Maximum Rating of the Pin shown in the Absolute Maximum Ratings table.
Copyright © 2015–2017, Texas Instruments Incorporated
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10 Layout
10.1 Layout Guidelines
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from VCC to V(IN) and the output filter capacitors from
OUT to VSS should be placed as close as possible to the device, with short trace runs to both signal and VSS
pins. The VSS pin should have short trace runs to the GND pin.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths from
the battery. Use a single-point ground technique incorporating both the small-signal ground path and the
power ground path.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
• The device is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment
(TI Literature Number SLUA271).
10.2 Layout Example
Device U1 GND Pad
For thermal improvement
Place VIA to GND plane if the plane is on a different layer
Low resistance path for
current flow
Low resistance path for
current flow
Device U1 bq24080-Q1, bq24081-Q1
Input Capacitor C1
Close to U1 pin IN
Output Capacitor C2
Resistor R3 to set ISET
Figure 13. Board Layout
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SLUSCB6B – MAY 2015 – REVISED JUNE 2017
10.3 Thermal Considerations
The bq24080-Q1 and bq24081-Q1 are packaged in a thermally enhanced MLP package. The package includes
a thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB).
Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB
Attachment (TI Literature Number SLUA271).
The most common measure of package thermal performance is thermal impedance (RθJA) measured (or
modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical
expression for RθJA is:
RqJA =
TJ - T A
P
(11)
Where:
• TJ = device junction temperature
• TA = ambient temperature
• P = device power dissipation
Factors that can greatly influence the measurement and calculation of RθJA include:
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
• Use multiple 10–13 mil vias in the PowerPAD™ to copper ground plane.
• Avoid cutting the ground plane with a signal trace near the power IC.
• The PCB must be sized to have adequate surface area for heat dissipation.
• FR4 (figerglass) thickness should be minimized.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power
FET. It can be calculated from the following equation:
P = (V(IN) - V(OUT)) x IO(OUT)
(12)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 6.
Copyright © 2015–2017, Texas Instruments Incorporated
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11 Device and Documentation Support
11.1 Device Support
11.2 Documentation Support
QFN/SON PCB Attachment , (SLUA271).
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq24080-Q1
Click here
Click here
Click here
Click here
Click here
bq24081-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24081QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
BQ24081QDRCTQ1
PREVIEW
VSON
DRC
10
250
TBD
Call TI
Call TI
-40 to 125
ZACQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2017
OTHER QUALIFIED VERSIONS OF BQ24081-Q1 :
• Catalog: BQ24081
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ24081QDRCRQ1
Package Package Pins
Type Drawing
VSON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24081QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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