Texas Instruments | CSD95482RWJ Synchronous Buck NexFET Smart Power Stage | Datasheet | Texas Instruments CSD95482RWJ Synchronous Buck NexFET Smart Power Stage Datasheet

Texas Instruments CSD95482RWJ Synchronous Buck NexFET Smart Power Stage Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
CSD95482RWJ
SLPS688 – JUNE 2017
CSD95482RWJ Synchronous Buck NexFET™ Smart Power Stage
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
40-A Continuous Operating Current Capability
Over 93.5% System Efficiency at 20 A
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Function
Temperature Compensated Bi-Directional Current
Sense
Analog Temperature Output
Fault Monitoring
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Switch
Optimized Dead Time for Shoot-Through
Protection
High-Density QFN 5-mm × 6-mm Footprint
Ultra-Low Inductance Package
System Optimized PCB Footprint
Thermally Enhanced Topside Cooling
RoHS Compliant – Lead-Free Terminal Plating
Halogen Free
Multiphase Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
POL DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR12.x / VR13.x V-Core
Synchronous Buck Converters
•
•
•
3 Description
The CSD95482RWJ NexFET™ power stage is a
highly optimized design for use in a high-power, highdensity synchronous buck converter. This product
integrates the driver IC and power MOSFETs to
complete the power stage switching function. This
combination produces high-current, high-efficiency,
and high-speed switching capability in a small 5-mm
× 6-mm outline package. It also integrates the
accurate current sensing and temperature sensing
functionality to simplify system design and improve
accuracy. In addition, the PCB footprint has been
optimized to help reduce design time and simplify the
completion of the overall system design.
Device Information(1)
Application Diagram
P12V
AVSP
AVSN
TPS53679
BOOT
VIN
PWM
PWM1
ASKIP#
P5V
MEDIA
QTY
PACKAGE
SHIP
13-Inch Reel
2500
CSD95482RWJT
7-Inch Reel
250
QFN
5.00-mm × 6.00-mm
Package
Tape
and
Reel
BOOT_R
CSD95482RWJ
EN/FCCM
VOS
VSW
VDD
PVDD
LSET
DEVICE
CSD95482RWJ
LOAD
TAO
PGND
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
IOUT REFIN
Typical Power Stage Efficiency and Power Loss
ACSP1
TSEN
P12V
P5V
VREF
ADDR
EN/FCCM
80
VSW
VDD
Efficiency (%)
TAO
PGND
IOUT REFIN
V3P3
ACSP6
VREF
VIN_CSNIN
CSPIN
VCCIO
BEN_VCCIO
SCLK
SDIO
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VR_FAULT#
RESET#
6
VOS
3.3V
P12V
90
BOOT_R
CSD95482RWJ
PVDD
LSET
7
BVSN
5
VDD = 5 V
VIN = 12 V
VOUT = 1.2 V
LOUT = 220 nH
fSW = 500 kHz
TA = 25qC
70
60
50
BVSP
4
3
Power Loss (W)
BOOT
VIN
PWM
APWM6
100
2
P12V
BOOT
VIN
PWM
BPWM1
BSKIP#
P5V
40
BOOT_R
CSD95492QVM
EN/FCCM
VDD
PVDD
LSET
1
VOS
VSW
TAO
PGND
LOAD
IOUT REFIN
30
0
5
10
15
20
25
Output Current (A)
30
35
0
40
D000
BCSP1
AGND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD95482RWJ
SLPS688 – JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
8
8.1
8.2
8.3
8.4
8.5
9
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
7
Device and Documentation Support.................... 6
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
6
6
6
6
6
Mechanical, Packaging, and Orderable
Information ............................................................. 7
9.1 Mechanical Drawing.................................................. 7
9.2 Recommended PCB Land Pattern............................ 8
9.3 Recommended Stencil Opening ............................... 9
Application Schematic .......................................... 5
4 Revision History
2
DATE
REVISION
NOTES
June 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
CSD95482RWJ
www.ti.com
SLPS688 – JUNE 2017
5 Pin Configuration and Functions
VOS
1
AGND
2
VDD
3
PVDD
4
PGND
5
NC
6
NC
35
VIN
36
BOOTR
EN/FCCM
37
PWM
TAO/FLT
38
BOOT
IOUT
39
LSET
REFIN
Top View
34
33
32
31
30
VIN
40
29
VIN
28
VIN
27
VIN
26
VIN
25
VIN
24 PGND
41
23 PGND
21 PGND
13
14
15
16
17
18
19
SW
12
SW
11
SW
10
SW
20 PGND
SW
9
SW
PGND
22 PGND
SW
8
SW
PGND
PGND
SW
7
SW
PGND
Pin Functions
PIN
NAME
DESCRIPTION
NO.
VOS
1
Output voltage sensing pin for the internal current sensing circuitry.
AGND
2
This pin is internally connected to PGND.
VDD
3
Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2.
PVDD
4
Supply voltage for gate drivers. This pin should be bypassed to PGND.
PGND
5
Power ground.
NC
6
Not connected. This pin needs to be left floating in application.
PGND
7-9
Power ground.
VSW
10-19
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
PGND
20-24
Power ground.
VIN
25-30
Input voltage pin. Connect input capacitors close to this pin.
NC
31
Not connected. This pin needs to be left floating in application.
BOOTR
32
Return path for HS gate driver. It is connected to VSW internally.
BOOT
33
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to
BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is
integrated.
PWM
34
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for
greater than the tri-state shutdown hold-off time (T3HT).
35
This dual function pin either enables the diode emulation function or can be used as a simple enable for the
device. When this pin is driven into the tri-state window and held there for more than the tri-state hold-off time,
Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous
Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left
floating.
TAO/FLT
36
Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated
in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs.
Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or HSS
detection circuit is tripped.
LSET
37
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.
IOUT
38
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
REFIN
39
External reference voltage input for current sensing amplifier.
PGND
40
Power ground.
NC
41
Not connected. This pin needs to be left floating in application.
EN/FCCM
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
3
CSD95482RWJ
SLPS688 – JUNE 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise stated) (1)
MIN
MAX
UNIT
VIN to PGND
–0.3
20
V
VIN to VSW
–0.3
20
V
23
V
–0.3
20
V
VIN to VSW (10 ns)
VSW to PGND
VSW to PGND (10 ns)
–7
23
V
VDD to PGND
–0.3
7
V
PVDD to PGND
–0.3
7
V
EN/FCCM, TAO/FLT, LSET to PGND
–0.3
VDD + 0.3
V
IOUT, VOS, PWM to PGND
–0.3
7
V
REFIN
–0.3
3.6
V
BOOT to BOOTR (2)
–0.3
VDD + 0.3
V
BOOT to PGND
–0.3
30
V
TJ
Operating junction temperature
–55
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied in the Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Should not exceed 7 V.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise stated)
MIN
MAX
UNIT
VDD
Driver supply voltage
4.5
5.5
V
PVDD
Gate drive voltage
4.5
5.5
V
VIN
Input supply voltage (1)
4.5
16
V
VOUT
Output voltage
5.5
V
PWM to PGND
VDD
V
40
A
IOUT
Continuous output current
(3)
VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz (2)
IOUT-PK
Peak output current
ƒSW
Switching frequency
CBST = 0.1 µF (min), VOUT = 2.5 V (max)
On-time duty cycle
ƒSW = 1 MHz
Minimum PWM on-time
(2)
(3)
4
A
kHz
85%
20
Operating junction temperature
(1)
60
1250
–40
ns
125
°C
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.
System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
CSD95482RWJ
www.ti.com
SLPS688 – JUNE 2017
7 Application Schematic
P12V
AVSP
TPS53679
AVSN
BOOT
VIN
PWM
ASKIP#
EN/FCCM
P5V
BOOT_R
CSD95482RWJ
PWM1
VOS
VSW
VDD
LOAD
TAO
PVDD
LSET
PGND
IOUT REFIN
ACSP1
TSEN
P12V
BOOT
VIN
PWM
APWM6
P5V
VREF
ADDR
BOOT_R
CSD95482RWJ
EN/FCCM
VOS
VSW
VDD
TAO
PVDD
LSET
PGND
IOUT REFIN
3.3V
V3P3
ACSP6
VREF
P12V
VIN_CSNIN
CSPIN
VCCIO
BEN_VCCIO
SCLK
SDIO
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VR_FAULT#
RESET#
BVSN
BVSP
P12V
BOOT
VIN
PWM
BPWM1
BSKIP#
P5V
BOOT_R
CSD95492QVM
EN/FCCM
VOS
VSW
VDD
PVDD
LSET
TAO
PGND
LOAD
IOUT REFIN
BCSP1
AGND
Copyright © 2017, Texas Instruments Incorporated
Figure 1. Application Schematic
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
5
CSD95482RWJ
SLPS688 – JUNE 2017
www.ti.com
8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
6
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
CSD95482RWJ
www.ti.com
SLPS688 – JUNE 2017
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
5.1
4.9
B
A
PIN 1 INDEX AREA
6.1
5.9
C
1.05 MAX
10
2.225 0.1
TYP
9
0.3
0.2
13X
20
1.95
0.8 0.1
0.4 0.1
0.1 0.1
19
2.05
1.3 0.1
0.9 0.1
2.6 0.1
2.2 0.1
(0.203) TYP
0.05
0.00
0.3
10X
0.2
9X 0.45
0.13 TYP
2.025
0.000
PKG
1.75 0.1
SEATING PLANE
0.08
7
10X 0.45
R0.05
TYP
41
24
0.000
PKG
6
0.3 0.1
25
16X
2.25 0.1
30
39
14X 0.45
0.4 0.1
PIN 1 ID
(45 X0.3)
2.175
29
1
16X
2.05
2.275
0.45
0.35
40
0.3
0.2
0.1
0.05
C A B
4221590/C 01/2017
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical
performance.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
7
CSD95482RWJ
SLPS688 – JUNE 2017
www.ti.com
16X (0.6)
39
(2.7) TYP
(2.22) TYP
2X (2.11)
3X (1.15)
(0.4)
(0.2)
0.000
3X (0.875)
(1.75)
(1.55)
(2)
(2.4)
9.2 Recommended PCB Land Pattern
METAL UNDER
SOLDER MASK
TYP
30
(2.9)
16X (0.25)
1
(2.25)
29
(2.25)
(2.175)
(2.05)
SOLDER MASK
OPENING, TYP
(1.275)
40
14X (0.45)
(0.5)
25
(0.3)
(0.025)
(0.1)
(0.4)
(0.3)
0.000 PKG
6
24
41
(0.3)
(R0.05) TYP
(0.8)
7
(1.05)
5X (1.15)
19X (0.45)
( 0.2) VIA
TYP
9
20
(2.2)
(0.05) MIN
TYP
5X (2)
(2.05)
(2.6)
(2.75) TYP
(3.2) TYP
19
10
(2.225) TYP
20X (0.25)
3X (2)
(2.025)
3X (1)
(0.9)
2X (1)
(1.3)
(1.75)
2X (2)
(2.225) TYP
(2.7) TYP
PKG
LAND PATTERN EXAMPLE
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
8
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
CSD95482RWJ
www.ti.com
SLPS688 – JUNE 2017
29X (0.6)
(2.4) TYP
2X (1.9)
2X (1.05)
2X (1.25)
2X (0.42)
2X (0.085)
0.000
PKG
2X (0.775)
2X (0.975)
2X (1.665)
(2)
(2.4) TYP
9.3 Recommended Stencil Opening
30
39
29X (0.25)
EXPOSED
METAL
1
29
24X (0.45)
4X (1.375)
4X (1.175)
40
EXPOSED
METAL
SOLDER MASK
OPENING
TYP
(0.025)
25
6
(0.1)
(0.4)
41
(0.84)
24
7
(R0.05) TYP
(0.375)
4X (0.305)
0.000 PKG
3X (0.13)
(0.25)
3X (1.05)
3X (1.25)
(1.3)
(1.75)
(1.05)
4X (2.245)
9
20
EXPOSED
METAL
4X (2.17)
(2.6)
(2.75) TYP
METAL UNDER
SOLDER MASK
TYP
10
(3.2) TYP
19
(2.025)
2X (1.9)
2X (0.9)
2X (1.1)
2X (0.1)
2X (0.1)
9X (0.45)
(1.1)
2X (0.9)
(1.9)
10X (0.25)
SOLDER PAST EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CSD95482RWJ
9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD95482RWJ
ACTIVE
VQFN-CLIP
RWJ
41
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95482RWJ
CSD95482RWJT
ACTIVE
VQFN-CLIP
RWJ
41
250
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95482RWJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CSD95482RWJ
VQFNCLIP
RWJ
41
2500
330.0
12.4
5.3
6.3
1.2
8.0
12.0
Q1
CSD95482RWJT
VQFNCLIP
RWJ
41
250
180.0
12.4
5.3
6.3
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD95482RWJ
VQFN-CLIP
RWJ
41
2500
370.0
355.0
55.0
CSD95482RWJT
VQFN-CLIP
RWJ
41
250
195.0
200.0
45.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising