Texas Instruments | TPS7A85A 4-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS), LDO Regulator | Datasheet | Texas Instruments TPS7A85A 4-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS), LDO Regulator Datasheet

Texas Instruments TPS7A85A 4-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS), LDO Regulator Datasheet
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TPS7A85A
SBVS313 – JUNE 2017
TPS7A85A 4-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS), LDO Regulator
1 Features
3 Description
•
•
The TPS7A85A is a low-noise (4.4 μVRMS), low
dropout linear regulator (LDO) capable of sourcing 4
A with only 240 mV of maximum dropout. The device
output voltage is pin-programmable from 0.8 V to
3.95 V and adjustable from 0.8 V to 5.1 V using an
external resistor divider.
1
•
•
•
•
•
•
•
•
•
•
•
Low Dropout: 150 mV (Typical) at 4 A
0.75% (Maximum) Accuracy Over Line, Load, and
Temperature With BIAS
Output Voltage Noise:
– 4.4 μVRMS at 0.8-V Output
– 7.7 μVRMS at 5.1-V Output
Input Voltage Range:
– Without BIAS: 1.4 V to 6.5 V
– With BIAS: 1.1 V to 6.5 V
ANY-OUT™ Operation:
– Output Voltage Range: 0.8 V to 3.95 V
Adjustable Operation:
– Output Voltage Range: 0.8 V to 5.1 V
Power-Supply Ripple Rejection:
– 40 dB at 500 kHz
Excellent Load Transient Response
Adjustable Soft-Start In-Rush Control
Open-Drain Power-Good (PG) Output
Stable with a 47-μF or Larger Ceramic Output
Capacitor
θJC = 3.4°C/W
3.5-mm × 3.5-mm, 20-Pin VQFN
2 Applications
•
•
•
•
•
Digital Loads: SerDes, FPGAs, and DSPs
Instrumentation, Medical, and Audio
High-Speed Analog Circuits:
– VCO, ADC, DAC, and LVDS
Imaging: CMOS Sensors and Video ASICs
Test and Measurement
The combination of low-noise (4.4 μVRMS), highPSRR, and high output current capability makes the
TPS7A85A
ideal
to
power
noise-sensitive
components such as those found in high-speed
communications, video, medical, or test and
measurement applications. The high performance of
the TPS7A85A limits power-supply-generated phase
noise and clock jitter, making this device ideal for
powering high-performance serializer and deserializer
(SerDes), analog-to-digital converters (ADCs), digitalto-analog converters (DACs), and RF components.
Specifically, RF amplifiers benefit from the highperformance and 5.1-V output capability of the
device.
For digital loads (such as application-specific
integrated circuits (ASICs), field-programmable gate
arrays (FPGAs), and digital signal processors
(DSPs)) requiring low-input voltage, low-output (LILO)
voltage operation, the exceptional accuracy (0.75%
over load and temperature), remote sensing,
excellent transient performance, and soft-start
capabilities of the TPS7A85A ensure optimal system
performance.
The versatility of the TPS7A8500A makes the device
a component of choice for many demanding
applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS7A85A
VQFN (20)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Powering RF Components
Powering Digital Loads
TPS7A85A
CBIAS
Bias
Supply
Input Supply
OUT
IN
PG
1.4 VIN
VCC
BIAS
IN
CIN
PG
EN
VCC
RPG
NR/SS
EN
IQ Modulators
IQ Demodulators
TRF372017
TRF3722
TRF371125
TRF371135
OUT
COUT
CNR/SS
TPS7A85A
SNS
1.6 V
CFF
800 mV
FB
400 mV
Copyright © 2017, Texas Instruments Incorporated
200 mV
100 mV
50 mV
0.9 VOUT
To Digital
Load
GND
ANYOUT
Used to set
voltage
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A85A
SBVS313 – JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
20
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 38
9 Power-Supply Recommendations...................... 39
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Example .................................................... 40
4 Revision History
2
DATE
REVISION
NOTES
June 2017
*
Initial release.
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5 Pin Configuration and Functions
OUT
OUT
GND
IN
IN
RGR Package
20-Pin VQFN
Top View
20
19
18
17
16
15 IN
OUT
1
SNS
2
FB
3
PG
4
12 BIAS
50mV
5
11 1.6V
14 EN
13 NR/SS
6
7
8
9
10
100mV
200mV
GND
400mV
800mV
Thermal Pad
Pin Functions
PIN
I/O
DESCRIPTION
I
ANY-OUT voltage setting pins. These pins connect to an internal feedback network. Connect these pins to ground,
SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins
to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins may
be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open)
when not in use. See ANY-OUT Programmable Output Voltage for additional details.
12
I
BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN =
1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac
performance for VIN ≤ 2.2 V. A 10-µF capacitor (5-µF capacitance) or larger must be connected between this pin and
ground if BIAS pin is used. If not used, this pin must be left floating or tied to ground and a capacitor is not required.
EN
14
I
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable
functionality is not required, this pin must be connected to IN or BIAS.
FB
3
I
Feedback pin connected to the error amplifier. Although not required, TI recommends a 10-nF feed-forward capacitor
from FB to OUT (as close to the device as possible) to maximize ac performance. The use of a feed-forward
capacitor may disrupt power-good (PG) functionality. See ANY-OUT Programmable Output Voltage and Adjustable
Operation for more details.
8, 18
—
15, 16, 17
I
13
—
Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference
voltage noise and enables the soft-start function. Although not required, TI recommends a 10-nF or larger capacitor
be connected from NR/SS to GND (as close as possible to the pin) to maximize ac performance. See Input and
Output Capacitor Requirements (CIN and COUT) for more details.
1, 19, 20
O
Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF of capacitance or greater) from OUT to ground is
required for stability and must be placed as close as possible to the output. Minimize the impedance from the OUT
pin to the load. See Input and Output Capacitor Requirements (CIN and COUT) for more details.
PG
4
O
Active-high, PG pin. An open-drain output indicates when the output voltage reaches VIT(PG) of the target. The use of
a feed-forward capacitor may disrupt PG functionality. See Input and Output Capacitor Requirements (CIN and COUT)
for more details.
SNS
2
I
Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load
side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin
floating. See ANY-OUT Programmable Output Voltage and Adjustable Operation for more details.
NAME
NO.
50mV
5
100mV
6
200mV
7
400mV
9
800mV
10
1.6V
11
BIAS
GND
IN
NR/SS
OUT
Thermal pad
—
Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance
connection.
Input supply voltage pin. A 10-μF or larger ceramic capacitor (5 μF of capacitance or greater) from IN to ground is
required to reduce the impedance of the input supply. Place the input capacitor as close as possible to the input. See
Input and Output Capacitor Requirements (CIN and COUT) for more details.
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
IN, BIAS, PG, EN
–0.3
7
V
IN, BIAS, PG, EN (5% duty cycle, pulse
duration = 200 μs)
–0.3
7.5
V
SNS, OUT
–0.3
VIN + 0.3
V
NR/SS, FB
–0.3
3.6
V
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V
–0.3
VOUT + 0.3
V
Internally
limited
Internally
limited
A
5
mA
Operating junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
Voltage
OUT
Current
PG (sink current into device)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
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6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input supply voltage range
VBIAS
Bias supply voltage range (1)
VOUT
Output voltage range (2)
VEN
Enable voltage range
IOUT
Output current
0
CIN
Input capacitor
10
COUT
Output capacitor
47
CBIAS
BIAS Capacitor
10
RPG
Power-good pullup resistance
10
CNR/SS
NR/SS capacitor
10
nF
CFF
Feed-forward capacitor
10
nF
R1
Top resistor value in feedback network for adjustable
operation
(4)
kΩ
R2
Bottom resistor value in feedback network for
adjustable operation
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
1.1
6.5
V
3
6.5
V
0.8
5.1
V
0
VIN
V
4
47
47 || 10 || 10
μF
(3)
μF
100
12.1
kΩ
(5)
kΩ
125
°C
160
–40
A
μF
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
This output voltage range does not include device accuracy or accuracy of the feedback resistors.
The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency
range is a typical value for dc-dc supplies.
The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R1 value.
The upper limit for the R2 resistor is to ensure accuracy by making the current through the feedback network much larger than the
leakage current into the feedback node.
6.4 Thermal Information
TPS7A85A
THERMAL METRIC (1)
RGR (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
43.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
°C/W
RθJB
Junction-to-board thermal resistance
17.6
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
17.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V (1), OUT connected to 50 Ω to GND (2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS
= 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
(3)
MIN
TYP
VIN
Input supply voltage range
VBIAS
Bias supply voltage range (3)
VFB
Feedback voltage
0.8
VNR/SS
NR/SS pin voltage
0.8
VUVLO1(IN)
Input supply UVLO with BIAS
VIN rising with VBIAS = 3 V
VHYS1(IN)
VUVLO1(IN) hysteresis
VBIAS = 3 V
320
VUVLO2(IN)
Input supply UVLO without BIAS
VIN rising
1.31
VHYS2(IN)
VUVLO2(IN) hysteresis
VUVLO(BIAS)
Bias supply UVLO
VBIAS rising
VIN = 1.1 V
VHYS(BIAS)
VUVLO(BIAS) hysteresis
VIN = 1.1 V
VOUT
Accuracy (4)
(5)
Accuracy with
BIAS
ΔVOUT / ΔVIN
ΔVOUT / ΔIOUT
VDO
Line regulation
Load regulation
Dropout voltage
6.5
V
3
6.5
V
1.02
2.83
V
mV
0.8 – 1%
5.1 + 1%
–1%
1%
–0.75%
0.75%
V
(6)
1.1V ≤ VIN ≤ 2.2 V
0.8 V ≤ VOUT ≤ 1.9 V
5 mA ≤ IOUT ≤ 4 A
3 V ≤ VBIAS ≤ 6.5 V
IOUT = 5 mA
1.4 V ≤ VIN ≤ 6.5 V
0.0035
5 mA ≤ IOUT ≤ 4 A
3 V ≤ VBIAS ≤ 6.5 V
VIN = 1.1 V
0.07
5 mA ≤ IOUT ≤ 4 A
0.08
5 mA ≤ IOUT ≤ 4 A
VOUT = 5.1 V
0.4
VIN = 1.4 V
IOUT = 4 A
VFB = 0.8 V – 3%
215
320
VIN = 5.5 V
IOUT = 4 A
VFB = 0.8 V – 3%
325
500
Short-circuit current limit
RLOAD = 20 mΩ
mV/V
mV/A
mV
VIN = 1.1 V
VBIAS = 5 V
IOUT = 4 A
VFB = 0.8 V – 3%
ISC
6
2.9
Using external resistors (4)
VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V
(6)
V
mV
3.95 + 1%
Output current limit
(4)
(5)
V
mV
1.39
290
ILIM
(2)
(3)
1.085
0.8 – 1%
150
VIN = 5.7 V
IOUT = 4 A
VFB = 0.8 V – 3%
(1)
V
Using the ANY-OUT pins
0.8 V ≤ VOUT ≤ 5.1 V
5 mA ≤ IOUT ≤ 4 A
1.4 V ≤ VIN ≤ 6.5 V
UNIT
1.1
253
Range
Output
voltage
VIN = 1.1 V
MAX
240
600
4.7
5.2
1
5.7
A
A
VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the
expected VOUT value set by the external feedback resistors.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The device is not tested under conditions where VIN > VOUT + 1.25 V and IOUT = 4 A because the power dissipation is higher than the
maximum rating of the package.
For VOUT ≤ 5 V, VIN = VOUT + 0.5 V. For VOUT > 5 V, VIN = VOUT + 0.6 V.
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Electrical Characteristics (continued)
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS
= 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
IGND
GND pin current
TYP
MAX
VIN = 6.5 V
IOUT = 5 mA
TEST CONDITIONS
MIN
2.8
4
VIN = 1.4 V
IOUT = 4 A
4.8
6
mA
Shutdown, PG = open, VIN = 6.5 V
VEN = 0.5 V
IEN
EN pin current
VIN = 6.5 V
VEN = 0 V and 6.5 V
IBIAS
BIAS pin current
VIN = 1.1 V
VBIAS = 6.5 V
VOUT(nom) = 0.8 V
IOUT = 4 A
VIL(EN)
EN pin low-level input voltage
(disable device)
VIH(EN)
EN pin high-level input voltage
(enable device)
VIT(PG)
PG pin threshold
For falling VOUT
VHYS(PG)
PG pin hysteresis
For rising VOUT
VOL(PG)
PG pin low-level output voltage
VOUT < VIT(PG)
IPG = –1 mA (current into device)
Ilkg(PG)
PG pin leakage current
VOUT > VIT(PG)
VPG = 6.5 V
INR/SS
NR/SS pin charging current
VNR/SS = GND
VIN = 6.5 V
IFB
FB pin leakage current
VIN = 6.5 V
PSRR
Vn
Power-supply ripple rejection
Output noise voltage
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
25
µA
0.1
µA
3.5
mA
0
0.5
V
1.1
6.5
V
93% × VOUT
V
–0.1
2.3
82% × VOUT
88.3% ×
VOUT
1% × VOUT
4
6.2
–100
f = 10 kHz
VOUT = 0.8 V
VBIAS = 5 V
42
f = 500 kHz
VOUT = 0.8 V
VBIAS = 5 V
39
f = 10 kHz
VOUT = 5 V
40
f = 500 kHz
VOUT = 5 V
25
Bandwidth = 10 Hz to 100 kHz, VIN = 1.1 V
VOUT = 0.8 V
VBIAS = 5 V
IOUT = 4 A
CNR/SS = 100 nF
CFF = 10 nF
COUT = 47 μF || 10 μF || 10 μF
4.4
Bandwidth = 10 Hz to 100 kHz
VOUT = 5 V
IOUT = 4 A
CNR/SS = 100 nF
CFF = 10 nF
COUT = 47 μF || 10 μF || 10 μF
8.4
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
VIN – VO UT = 0.5 V
IOUT = 4 A
CNR/SS = 100 nF
CFF = 10 nF
COUT =
47 μF || 10 μF || 10 μF
UNIT
V
0.4
V
1
µA
9
µA
100
nA
dB
μVRMS
–40
°C
125
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6.6 Typical Characteristics
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
100
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
IOUT = 3.5 A
IOUT = 4.0 A
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Power Supply-Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
80
60
40
20
0
10
10M
VIN = 1.2 V, VBIAS = 5 V,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
10k
100k
Frequency (Hz)
1M
10M
80
60
40
20
100
1k
10k
100k
Frequency (Hz)
1M
Power-Supply Rejection Ratio (dB)
100
VBIAS = 0 V
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
0
10
80
60
40
20
0
10
10M
VIN = 1.4 V, IOUT = 1 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
VIN = 1.1 V, VBIAS = 5 V
VIN = 1.2 V, VBIAS = 5 V
VIN = 1.4 V, VBIAS = 0 V
VIN = 2.5 V, VBIAS = 0 V
VIN = 5.0 V, VBIAS = 0 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
IOUT = 1 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 3. PSRR vs Frequency and VBIAS
Figure 4. PSRR vs Frequency and VIN
100
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = VOUT + 0.4 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 5. PSRR vs Frequency and VOUT With Bias
Power-Supply Rejection Ratio (dB)
100
Power-Supply Rejection Ratio (dB)
1k
Figure 2. PSRR vs Frequency and VIN With Bias
100
8
100
IOUT = 4 A, VBIAS = 5 V,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 1. PSRR vs Frequency and IOUT
Power-Supply Rejection Ratio (dB)
VIN = 1.10 V
VIN = 1.15 V
VIN = 1.20 V
VIN = 1.25 V
VIN = 1.30 V
VIN = 1.35 V
VIN = 1.40 V
VIN = 3.60 V
VIN = 3.65 V
VIN = 3.70 V
VIN = 3.75 V
VIN = 3.80 V
VIN = 3.85 V
VIN = 3.90 V
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF
Figure 6. PSRR vs Frequency and VIN for VOUT = 3.3 V
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
100
COUT = 47 PF||10 PF||10 PF
COUT = 47 PF
COUT = 100 PF
COUT = 200 PF
COUT = 500 PF
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
Figure 7. PSRR vs Frequency and COUT
40
20
60
40
20
100
1k
10k
100k
Frequency (Hz)
1M
10M
60
40
20
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
Figure 9. PSRR vs Frequency and VIN for VOUT = 5 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 10. VBIAS PSRR vs Frequency
2
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
IOUT = 4.0 A
VOUT = 0.8 V, 4.5 PVRMS
VOUT = 1.5 V, 5.4 PVRMS
VOUT = 3.3 V, 8.5 PVRMS
VOUT = 5.0 V, 12.4 PVRMS
1
Output Voltage Noise (PV/—Hz)
Output Voltage Noise (PVRMS)
1M
VIN = VOUT + 0.4 V, VOUT = 1 V, IOUT = 4 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
15
10.5
9
7.5
6
4.5
3
0.6
10k
100k
Frequency (Hz)
80
0
10
10M
IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF
12
1k
Figure 8. PSRR vs Frequency and IOUT for VOUT = 5 V
VIN = 5.35 V
VIN = 5.4 V
VIN = 5.45 V
VIN = 5.5 V
VIN = 5.55 V
VIN = 5.60 V
VIN = 5.65 V
80
13.5
100
100
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
60
VIN = VOUT + 0.6 V, IOUT = 4 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
100
0
10
80
0
10
10M
VIN = 5.6 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, CFF = 10 nF
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
IOUT = 4.0 A
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
1.2
1.8
2.4
3
3.6
Output Voltage (V)
4.2
4.8
5.4
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 11. Output Voltage Noise vs Output Voltage
0.001
10
100
1k
10k
Frequency (Hz)
100k
1M
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 4 A,
RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 12. Output Noise vs Frequency and VOUT
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
2
2
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PVRMS
VIN = 1.4 V, 6.0 PVRMS
VIN = 1.5 V, 4.5 PVRMS
VIN = 1.8 V, 4.5 PVRMS
VIN = 2.5 V, 4.6 PVRMS
VIN = 5.0 V, 5.15 PVRMS
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
Frequency (Hz)
100k
0.001
10
1M
IOUT = 1 A, RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
100k
1M
2
CFF = 0 nF, 6.2 PVRMS
CFF = 0.1 nF, 5.8 PVRMS
CFF = 1 nF, 4.9 PVRMS
CFF = 10 nF, 4.5PVRMS
CFF = 100 nF, 4.4 PVRMS
0.5
0.2
CNR/SS = 10 nF, 12.3 PVRMS
CNR/SS = 100 nF, 8.4 PVRMS
CFF = CNR/SS = 100 nF, 6.6 PVRMS
1
Output Voltage Noise (PV/—Hz)
1
0.1
0.05
0.02
0.01
0.005
0.002
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
Frequency (Hz)
100k
0.001
10
1M
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A,
RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF
100
1k
10k
Frequency (Hz)
100k
1M
VIN = 5.6 V, IOUT = 4 A, RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF
Figure 15. Output Noise vs Frequency and CFF
Figure 16. Output Noise at 5.0-V Output vs CNR/SS and CFF
1.2
10
50
Output Current
VOUT = 0.9 V
VOUT = 1.2 V
VOUT = 1.8 V
1
0.6
0.4
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0.2
0
-0.2
Output Current (A)
7.5
0.8
25
5
0
2.5
-25
0
0
5
10
15
20
25
30
Time (ms)
35
40
45
50
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF
Figure 17. Start-Up Waveform vs Time and CNR/SS
AC-Coupled Output Voltage (mV)
Output Voltage Noise (PV/—Hz)
1k
10k
Frequency (Hz)
Figure 14. Output Noise vs Frequency and CNR/SS
2
Voltage (V)
100
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A,
RMS Noise BW = 10 Hz to 100 kHz,
COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF
Figure 13. Output Noise vs Frequency and VIN
10
CNR/SS = 0 nF, 6.2 PVRMS
CNR/SS = 1 nF, 4.9 PVRMS
CNR/SS = 10 nF, 4.5 PVRMS
CNR/SS = 100 nF, 4.4 PVRMS
1
Output Voltage Noise (PV/—Hz)
Output Voltage Noise (PV/—Hz)
1
-50
0
0.5
1
Time (ms)
1.5
2
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate =
1 A/μs, CNR/SS = CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF
Figure 18. Load Transient Waveform vs Time and
VOUT With Bias
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
50
Output Current (A)
7.5
25
5
0
2.5
-25
0
AC-Coupled Output Voltage (mV)
50
Output Current
VOUT = 3.3 V
VOUT = 5.0 V
AC-Coupled Output Voltage (mV)
10
0.4
0.8
1.2
Time (ms)
1.6
25
0
-25
-50
-50
0
Slew Rate = 2 A/Ps
Slew Rate = 1 A/Ps
Slew Rate = 0.5 A/Ps
0
2
IOUT, DC = 100 mA, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
1.6
2
Figure 20. Load Transient Waveform vs
Time and Slew Rate
50
AC-Coupled Output Voltage (mV)
50
AC-Coupled Output Voltage (mV)
0.8
1.2
Time (ms)
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 4 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF
Figure 19. Load Transient Waveform vs
Time and VOUT Without Bias
25
0
-25
COUT = 100 PF
COUT = 200 PF
COUT = 500 PF
COUT = 500 PF || 1 mF Oscon
-50
IOUT = 100 mA to 4 A
IOUT = 500 mA to 4 A
IOUT = 1 A to 4 A
25
0
-25
-50
0
0.4
0.8
1.2
Time (ms)
1.6
2
VIN = 1.2 V, VBIAS = 5.0 V, IOUT = 100 mA to 4 A,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
0
0.4
0.8
1.2
Time (ms)
1.6
2
VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
Figure 21. Load Transient Waveform vs Time and COUT
(VOUT = 0.9 V)
Figure 22. Load Transient Waveform vs Time and DC Load
(VOUT = 0.9 V)
450
450
-40°C
0°C
25°C
85°C
125°C
350
-40°C
0°C
25°C
85°C
125°C
400
Dropout Voltage (mV)
400
Dropout Voltage (mV)
0.4
300
250
200
350
300
250
200
150
150
1
2
3
4
Input Voltage (V)
5
6
1
IOUT = 4 A, VBIAS = 0 V
2
3
4
Input Voltage (V)
5
6
IOUT = 4 A, VBIAS = 6.5 V
Figure 23. Dropout Voltage vs Input Voltage Without Bias
Figure 24. Dropout Voltage vs Input Voltage With Bias
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
300
0.2
-40°C
0°C
25°C
85°C
125°C
200
-40°C
0°C
25°C
85°C
125°C
0.175
Dropout Voltage (mV)
Dropout Voltage (mV)
250
150
100
50
0.15
0.125
0.1
0.075
0.05
0.025
0
0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
VIN = 1.4 V, VBIAS = 0 V
3.5
4
0.2
-40°C
0°C
25°C
85°C
125°C
250
-40°C
0°C
25°C
85°C
125°C
0.15
Change in VOUT (%)
300
200
150
100
0.1
0.05
0
-0.05
50
-0.1
0.5
0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
1
1.5
VIN = 5.5 V
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
IOUT = 100 mA to 4 A
Figure 27. Dropout Voltage vs Output Current (High VIN)
Figure 28. Load Regulation vs Output Voltage
0.025
0.15
-40°C
0°C
25°C
85°C
125°C
0
Change in VOUT (%)
0.1
Change in VOUT (%)
3
Figure 26. Dropout Voltage vs Output Current With Bias
350
0.05
0
-0.025
-0.05
-40°C
0°C
25°C
85°C
125°C
-0.075
-0.05
-0.1
-0.1
0
0.8
1.6
2.4
Output Current (A)
3.2
Figure 29. Load Regulation (0.8-V Output)
12
1.5
2
2.5
Output Current (A)
VIN = 1.1 V, VBIAS = 3 V
Figure 25. Dropout Voltage vs Output Current Without Bias
Dropout Voltage (mV)
1
4
0
0.8
1.6
2.4
Output Current (A)
3.2
4
Figure 30. Load Regulation (3.3-V Output)
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Typical Characteristics (continued)
0.025
0
0
-0.025
Change in VOUT (%)
Change in VOUT (%)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
-0.025
-0.05
-40°C
0°C
25°C
85°C
125°C
-0.075
-0.05
-0.075
-40°C
0°C
25°C
85°C
125°C
-0.1
-0.1
-0.125
0
0.8
1.6
2.4
Output Current (A)
3.2
4
1
1.5
2
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
6.5
IOUT = 5 mA
Figure 31. Load Regulation (5-V Output)
Figure 32. Line Regulation Without Bias
0
25
Change in VOUT (ppm)
Change in VOUT (ppm)
0
-25
-50
-40°C
0°C
25°C
85°C
125°C
-75
3.5
4
4.5
5
Bias Voltage (V)
5.5
6
-40
-40°C
0°C
25°C
85°C
125°C
-60
5.25
-100
3
-20
6.5
5.5
5.75
6
Input Voltage (V)
VIN = 1.1 V, IOUT = 5 mA
6.25
6.5
IOUT = 5 mA
Figure 33. Line Regulation vs Bias Voltage
Figure 34. Line Regulation (5-V Output)
3.3
2.4
Bias Pin Current (mA)
Ground Pin Current (mA)
3
2.7
2.4
2.1
-40°C
0°C
25°C
85°C
125°C
1.8
1.5
2
1.6
-40°C
0°C
25°C
85°C
125°C
1.2
0.8
1
2
3
4
5
Input Voltage (V)
6
7
3
3.5
IOUT = 5 mA
4
4.5
5
Bias Voltage (V)
5.5
6
6.5
VIN = 1.1 V, IOUT = 5 mA
Figure 35. Ground Pin Current vs Input Voltage
Figure 36. Bias Pin Current vs Bias Voltage
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
6
5
-40°C
0°C
25°C
85°C
125°C
Shutdown Current (PA)
Shutdown Current (PA)
4
-40°C
0°C
25°C
85°C
125°C
5
3
2
1
4
3
2
1
0
0
1
1.5
2
2.5
3
3.5 4 4.5
Input Voltage (V)
5
5.5
6
6.5
3
3.5
4
4.5
5
Bias Voltage (V)
5.5
6
6.5
VIN = 1.1 V
Figure 38. Shutdown Current vs Bias Voltage
1.4
7
1.2
6.5
6
5.5
-40°C
0°C
25°C
85°C
125°C
5
Input Voltage (V)
NR/SS Charging Current (PA)
Figure 37. Shutdown Current vs Input Voltage
7.5
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0.8
0.6
VUVLO2(IN), Rising
VUVLO2(IN), Falling
VUVLO1(IN), Rising
VUVLO1(IN), Falling
0.4
0.2
-40
4.5
1
1
6.5
-20
Figure 39. NR/SS Charging Current vs Input Voltage
40
60
80
Temperature (°C)
100
120
140
0.85
VUVLO(BIAS), Rising
VUVLO(BIAS), Falling
0.8
Enable Voltage (V)
2.9
Bias Voltage (V)
20
Figure 40. VIN UVLO vs Temperature
3
2.8
2.7
2.6
2.5
-60
0
0.75
0.7
0.65
VIH(EN), VIN = 1.4 V
VIH(EN), VIN = 6.5 V
VIL(EN), VIN = 1.4 V
VIL(EN), VIN = 6.5 V
0.6
-30
0
30
60
Temperature (°C)
90
120
150
0.55
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
VIN = 1.1 V
Figure 41. VBIAS UVLO vs Temperature
14
Figure 42. Enable Threshold vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
0.75
0.4
-40°C
0°C
25°C
85°C
125°C
0.32
PG Voltage (V)
PG Voltage (V)
0.6
-40°C
0°C
25°C
85°C
125°C
0.45
0.3
0.15
0.24
0.16
0.08
0
0
0
0.5
1
1.5
2
PG Current Sink (mA)
2.5
3
0
0.5
1
1.5
2
PG Current Sink (mA)
2.5
3
VIN = 6.5 V
Figure 43. PG Voltage vs PG Current Sink
Figure 44. PG Voltage vs PG Current Sink
90.25
PG Threshold (% VOUT(NOM))
90
89.75
VIT(PG) Rising, VIN = 1.4 V
VIT(PG) Rising, VIN = 6.5 V
VIT(PG) Falling, VIN = 1.4V
VIT(PG) Falling, VIN = 6.5 V
89.5
89.25
89
88.75
88.5
88.25
88
87.75
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 45. PG Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A85A is a high-current (4 A), low-noise (4.4 µVRMS), high accuracy (0.75%) low-dropout linear voltage
regulator (LDO). These features make the device a robust solution to solve many challenging problems in
generating a clean, accurate power supply.
The TPS7A85A has several features that makes the device useful in a variety of applications. See Table 1 for a
categorization of the functions shown in the Functional Block Diagram.
Table 1. Features
VOLTAGE REGULATION
SYSTEM START-UP
INTERNAL PROTECTION
High accuracy
Programmable soft-start
Foldback current limit
Low-noise, high-PSRR output
No sequencing requirement between BIAS,
IN and EN
Thermal shutdown
Power-good output
Fast transient response
Start-up with negative bias on OUT
Overall, these features make the TPS7A85A the component of choice due to its versatility and ability to generate
a supply for most applications.
7.2 Functional Block Diagram
PSRR
Boost
IN
Current
Limit
OUT
Charge
Pump
BIAS
0.8-V
VREF
Active
Discharge
RNR/SS = 250 k:
+
Error
Amp
±
INR/SS
SNS
NR/SS
200 pF
R1 = 2×R = 12.1 k:
FB
1×R = 6.05 k:
1.6 V
UVLO
Circuits
2×R = 12.1 k:
Internal
Controller
800 mV
4×R = 24.2 k:
400 mV
8×R = 48.4 k:
200 mV
16×R = 96.8 k:
100 mV
32×R = 193.6 k:
50 mV
ANY-OUT Network
Thermal
Shutdown
±
0.88 x VREF
EN
GND
PG
+
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NOTE: For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual
resistance may vary significantly from the numbers listed.
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7.3 Feature Description
7.3.1 Voltage Regulation Features
7.3.1.1 DC Regulation
An LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (VREF), as
shown in Figure 46. VREF is designed to have a very low bandwidth at the input to the error amplifier through the
use of a low-pass filter (VNR/SS).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes
from the combination of the output capacitor and pass element. The pass element presents a high input
impedance to the source voltage when operating as a current source. A positive LDO can only source current
because of the class-B architecture.
This device achieves a maximum of 0.75% output voltage accuracy primarily because of the high-precision bandgap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation
required by the device to regulate the output voltage at a given current level, which improves system efficiency.
These features combine to make this device a good approximation of an ideal voltage source.
VIN
To Load
±
+
R1
VREF
R2
GND
NOTE: VOUT = VREF × (1 + R1 / R2).
Figure 46. Simplified Regulation Circuit
7.3.1.2 AC and Transient Response
The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output
current (load transient) resulting from the LDO high-input impedance and low output-impedance across
frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and,
when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (smallsignal) and large-signal conditions.
The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor
(CNR/SS) and feed-forward capacitor (CFF) reduce the device noise floor and improve PSRR; see Optimizing
Noise and PSRR for more information on optimizing the noise and PSRR performance.
7.3.2 System Start-Up Features
In many different applications, the power-supply output must turn on within a specific window of time to either
ensure proper operation of the load or to minimize the loading on the input supply or other sequencing
requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements
faced by many power-supply design engineers in a simple fashion.
7.3.2.1 Programmable Soft Start (NR/SS)
Soft start directly controls the output start-up time and indirectly controls the output current during start-up (inrush
current).
The external capacitor at the NR/SS pin (CNR/SS) sets the output start-up time by setting the rise time of the
internal reference (VNR/SS), as shown in Figure 47.
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Feature Description (continued)
SW
INR/SS
RNR
VREF
+
CNR/SS
VFB
±
GND
Figure 47. Simplified Soft-Start Circuit
7.3.2.2 Internal Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of
the high power levels inherent in a PDN, and the variations between all of the supplies. The LDO turnon and
turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO1,2(IN) and UVLOBIAS), as
shown in Figure 48 and Table 2.
EN
UVLOBIAS
UVLO1,2(IN)
Internal Enable
Control
Figure 48. Simplified Turnon Control
Table 2. Internal Sequencing Functionality Table
INPUT VOLTAGE
BIAS VOLTAGE
VBIAS ≥ VUVLO(BIAS)
VIN ≥ VUVLO_1,2(IN)
ENABLE
STATUS
LDO STATUS
ACTIVE
DISCHARGE
POWER GOOD
EN = 1
On
Off
PG = 1 when VOUT ≥ VIT(PG)
EN = 0
Off
On
VBIAS < VUVLO(BIAS) +
VHYS(BIAS)
(1)
Off
EN = don't
care
VIN < VUVLO_1,2(IN) –
VHYS1,2(IN)
BIAS = don't care
IN = don't care
VBIAS ≥ VUVLO(BIAS)
Off
On
(1)
PG = 0
Off
The active discharge remains on as long as VIN or VBIAS provides enough headroom for the discharge circuit to function.
7.3.2.2.1 Enable (EN)
The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the
rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN
≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. Connect EN
to VIN if enable functionality is not desired.
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7.3.2.2.2 Undervoltage Lockout (UVLO) Control
The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if
either of these rails collapse.
The local input capacitance prevents severe brownouts in most applications; see Undervoltage Lockout (UVLO)
for more details.
7.3.2.2.3 Active Discharge
When EN or UVLO is low, the device connects a resistor of several hundred ohms from VOUT to GND,
discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUT > VIN,
which can cause damage to the device (when VOUT > VIN + 0.3 V); see Reverse Current for more details.
7.3.2.3 Power-Good Output (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals
when the output nears its nominal value. PG can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUT(nom)). A simplified schematic is shown in Figure 49.
The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high.
The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the FB
pin, the PG signal can indicate a false positive. A simple solution to this scenario is to use an external voltage
detector device, such as the TPS3890; see Feed-Forward Capacitor (CFF) for more information.
VPG
VBG
VIN
VFB
±
+
GND
UVLOBIAS
UVLOIN
GND
EN
GND
Figure 49. Simplified PG Circuit
7.3.3 Internal Protection Features
In many applications, fault events can occur that damage devices in the system. Short circuits and excessive
heat are the most common fault events for power supplies. The TPS7A85A implements circuitry to protect the
device and the load during these events. Continuously operating in these fault conditions or above a junction
temperature of 125°C is not recommended because the long-term reliability of the device is reduced.
7.3.3.1 Foldback Current Limit (ICL)
The internal current limit circuit protects the LDO against high load-current faults or shorting events. During a
current-limit event, the LDO sources constant current. As a result, the output voltage falls with decreased load
impedance. Thermal shutdown can activate during a current limit event because of the high power dissipation
typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to
the input and load. Continuous operation in current limit is not recommended.
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7.3.3.2 Thermal Protection (Tsd)
The thermal shutdown circuit protects the LDO against excessive heat in the system, resulting from current limit
or high ambient temperature.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal
shutdown temperature. The output turns on again after TJ decreases below the falling thermal shutdown
temperature.
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be
greater than or equal to Tsd, which triggers the thermal shutdown and causing the output to fall to 0 V. The LDO
can cycle on and off when thermal shutdown is reached under these conditions.
7.4 Device Functional Modes
Table 3 lists a comparison between the regulation and disabled operation.
Table 3. Device Functional Modes Comparison
OPERATING
MODE
PARAMETER
VIN
VBIAS
EN
IOUT
TJ
Regulation (1)
VIN > VOUT(nom) +
VDO
VBIAS ≥ VUVLO(BIAS) (2)
VEN > VIH(EN)
IOUT < ICL
TJ ≤ TJ(maximum)
Disabled (3)
VIN < VUVLO_1,2(IN)
VBIAS < VUVLO(BIAS)
VEN < VIL(EN)
Current limit
operation
(1)
(2)
(3)
TJ > Tsd
IOUT ≥ ICL
All table conditions must be met.
VBIAS only required for VIN < 1.4 V.
The device is disabled when any condition is met.
7.4.1 Regulation
The device regulates the output to the nominal output voltage when all the conditions in Table 3 are met.
7.4.2 Disabled
When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is
actively discharged to ground by an internal resistor from the output to ground. See Active Discharge for
additional information.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 External Component Selection
8.1.1.1 Adjustable Operation
The TPS7A85A can be used with the internal ANY-OUT network or by using external resistors. Using the ANYOUT network allows the TPS7A85A to be programmed from 0.8 V to 3.95 V. For output voltage range greater
than 3.95 V and up to 5.1 V, external resistors must be used. This configuration is referred to as the adjustable
configuration of the TPS7A85A throughout the data sheet. The output voltage is set by two resistors, as shown in
Figure 50. 0.75% accuracy can be achieved with an external BIAS for VIN lower than 2.2 V.
CBIAS
Optional
Bias
Supply
Input
Supply
BIAS
IN
CIN
PG
EN
RPG
NR/SS
To Load
OUT
COUT
CNR/SS
TPS7A85A
SNS
1.6 V
R1
800 mV
CFF
FB
400 mV
200 mV
R2
100 mV
50 mV
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 50. Adjustable Operation
R1 and R2 can be calculated for any output voltage range using . This resistive network must provide a current
equal to or greater than 5 μA for dc accuracy. TI recommends using an R1 approximately 12 kΩ to optimize the
noise and PSRR.
VOUT = VNR/SS ´ (1 + R1 / R2 )
(1)
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Application Information (continued)
Table 4 lists the resistor combinations required to achieve several common rails using standard 1%-tolerance
resistors.
Table 4. Recommended Feedback-Resistor Values (1)
(1)
TARGETED OUTPUT
VOLTAGE
(V)
FEEDBACK RESISTOR VALUES
R1 (kΩ)
R2 (kΩ)
CALCULATED OUTPUT
VOLTAGE
(V)
0.9
12.4
100
0.899
0.95
12.4
66.5
0.949
1
12.4
49.9
0.999
1.1
12.4
33.2
1.099
1.2
12.4
24.9
1.198
1.5
12.4
14.3
1.494
1.8
12.4
10
1.798
1.9
12.1
8.87
1.89
2.5
12.4
5.9
2.48
2.85
12.1
4.75
2.838
3
12.1
4.42
2.990
3.3
11.8
3.74
3.324
3.6
12.1
3.48
3.582
4.5
11.8
2.55
4.502
5
12.4
2.37
4.985
R1 is connected from OUT to FB; R2 is connected from FB to GND.
8.1.1.2 ANY-OUT Programmable Output Voltage
The TPS7A85A can use external resistors or the internally-matched ANY-OUT feedback resistor network to set
output voltage. The ANY-OUT resistors are accessible through pin 2 and pins 5 to 11 and program the regulated
output voltage. Each pin can be connected to ground (active), left open (floating), or connected to SNS. ANYOUT programming is set by as the sum of the internal reference voltage (VNR/SS = 0.8 V) plus the accumulated
sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7),
400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 5 lists the voltage values associated with each active pin
setting for reference. By leaving all program pins open or floating, the output is programmed to the minimum
possible output voltage equal to VFB.
VOUT = VNR/SS + ( å ANY - OUT Pins to Ground)
(2)
Table 5. ANY-OUT Programmable Output Voltage (RGR Package)
ANY-OUT PROGRAM PINS (ACTIVE LOW)
22
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
50 mV
Pin 6 (100mV)
100 mV
Pin 7 (200mV)
200 mV
Pin 9 (400mV)
400 mV
Pin 10 (800mV)
800 mV
Pin 11 (1.6V)
1.6 V
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Table 6 lists target output voltages and corresponding pin settings when the ANY-OUT pins are only tied to
ground or left floating. The voltage setting pins have a binary weight, so the output voltage can be programmed
to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are several alternative
ways to set the output voltage. The program pins can be driven using external general-purpose input or output
pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the given layout of the
printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the output voltage is
set according to except that R1 and R2 are internally integrated and matched for higher accuracy. Tying any of
the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by decreasing the value
of R1. See Increasing ANY-OUT Resolution for LILO Conditions for additional information.
VOUT = VNR/SS ´ (1 + R1 / R2 )
(3)
NOTE
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see
Adjustable Operation).
Table 6. User-Configurable Output Voltage Settings
VOUT(NOM)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
VOUT(NOM)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
0.8
Open
Open
Open
Open
Open
Open
2.4
Open
Open
Open
Open
Open
GND
0.85
GND
Open
Open
Open
Open
Open
2.45
GND
Open
Open
Open
Open
GND
0.9
Open
GND
Open
Open
Open
Open
2.5
Open
GND
Open
Open
Open
GND
0.95
GND
GND
Open
Open
Open
Open
2.55
GND
GND
Open
Open
Open
GND
1
Open
Open
GND
Open
Open
Open
2.6
Open
Open
GND
Open
Open
GND
1.05
GND
Open
GND
Open
Open
Open
2.65
GND
Open
GND
Open
Open
GND
1.1
Open
GND
GND
Open
Open
Open
2.7
Open
GND
GND
Open
Open
GND
1.15
GND
GND
GND
Open
Open
Open
2.75
GND
GND
GND
Open
Open
GND
1.2
Open
Open
Open
GND
Open
Open
2.8
Open
Open
Open
GND
Open
GND
1.25
GND
Open
Open
GND
Open
Open
2.85
GND
Open
Open
GND
Open
GND
1.3
Open
GND
Open
GND
Open
Open
2.9
Open
GND
Open
GND
Open
GND
1.35
GND
GND
Open
GND
Open
Open
2.95
GND
GND
Open
GND
Open
GND
1.4
Open
Open
GND
GND
Open
Open
3
Open
Open
GND
GND
Open
GND
1.45
GND
Open
GND
GND
Open
Open
3.05
GND
Open
GND
GND
Open
GND
1.5
Open
GND
GND
GND
Open
Open
3.1
Open
GND
GND
GND
Open
GND
1.55
GND
GND
GND
GND
Open
Open
3.15
GND
GND
GND
GND
Open
GND
1.6
Open
Open
Open
Open
GND
Open
3.2
Open
Open
Open
Open
GND
GND
1.65
GND
Open
Open
Open
GND
Open
3.25
GND
Open
Open
Open
GND
GND
1.7
Open
GND
Open
Open
GND
Open
3.3
Open
GND
Open
Open
GND
GND
1.75
GND
GND
Open
Open
GND
Open
3.35
GND
GND
Open
Open
GND
GND
1.8
Open
Open
GND
Open
GND
Open
3.4
Open
Open
GND
Open
GND
GND
1.85
GND
Open
GND
Open
GND
Open
3.45
GND
Open
GND
Open
GND
GND
1.9
Open
GND
GND
Open
GND
Open
3.5
Open
GND
GND
Open
GND
GND
1.95
GND
GND
GND
Open
GND
Open
3.55
GND
GND
GND
Open
GND
GND
2
Open
Open
Open
GND
GND
Open
3.6
Open
Open
Open
GND
GND
GND
2.05
GND
Open
Open
GND
GND
Open
3.65
GND
Open
Open
GND
GND
GND
2.10
Open
GND
Open
GND
GND
Open
3.7
Open
GND
Open
GND
GND
GND
2.15
GND
GND
Open
GND
GND
Open
3.75
GND
GND
Open
GND
GND
GND
2.2
Open
Open
GND
GND
GND
Open
3.8
Open
Open
GND
GND
GND
GND
2.25
GND
Open
GND
GND
GND
Open
3.85
GND
Open
GND
GND
GND
GND
2.3
Open
GND
GND
GND
GND
Open
3.9
Open
GND
GND
GND
GND
GND
2.35
GND
GND
GND
GND
GND
Open
3.95
GND
GND
GND
GND
GND
GND
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8.1.1.3 ANY-OUT Operation
Considering the use of the ANY-OUT internal network where the unit resistance of 1R, as shown in () is equal to
6.05 kΩ, the output voltage is set by grounding the appropriate control pins as shown in Figure 51. When
grounded, all control pins add a specific voltage on top of the internal reference voltage (VNR/SS = 0.8 V). The
output voltage can be calculated by and . Figure 51 and Figure 52 show a 0.9-V output voltage (respectively) that
show an example of the circuit usage with and without bias voltage.
CBIAS
Bias
Supply
VIN
EN
IN
BIAS
CIN
PG
RPG
NR/SS
3.3 VOUT
To Load
OUT
COUT
CNR/SS
TPS7A85A
SNS
1.6 V
CFF
800 mV
FB
400 mV
200 mV
100 mV
50 mV
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 51. ANY-OUT Configuration Circuit
(3.3-V Output, No External Bias)
VOUT(nom) = VNR/SS + 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V
(4)
CBIAS
Bias
Supply
1.4 VIN
BIAS
IN
CIN
PG
EN
RPG
NR/SS
OUT
COUT
CNR/SS
TPS7A85A
SNS
1.6 V
CFF
800 mV
FB
400 mV
200 mV
100 mV
50 mV
0.9 VOUT
To Digital
Load
GND
ANYOUT
Used to set
voltage
Copyright © 2017, Texas Instruments Incorporated
Figure 52. ANY-OUT Configuration Circuit
(0.9-V Output with Bias)
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VOUT(nom) = VNR / SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
(5)
8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
As with the adjustable operation, the output voltage is set according to Equation 5. However, R1 and R2 are
internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the
resolution of the internal feedback network by decreasing the value of R1. One of the more useful pin
combinations is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range.
The new ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. Table 7 lists the new additive output
voltage levels.
Table 7. ANY-OUT Programmable Output Voltage With 800 mV Tied to SNS (RGR Package)
ANY-OUT PROGRAM PINS (ACTIVE LOW)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
25 mV
Pin 6 (100mV)
50 mV
Pin 7 (200mV)
100 mV
Pin 9 (400mV)
200 mV
Pin 11 (1.6V)
800 V
8.1.1.5 Current Sharing
Current sharing is possible through the use of external operational amplifiers. For more details, see 6A CurrentSharing Dual LDO.
8.1.1.6 Recommended Capacitor Types
The TPS7A85A is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input, output, and noise-reduction pin (NR/SS). Multilayer ceramic capacitors are the industry standard for these
types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that use
X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature,
whereas the use of Y5V-rated capacitors is not recommended because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature; derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein
account for a capacitance derating of approximately 50%, but at high VIN and VOUT conditions (for example, VIN =
5.6 V to VOUT = 5.1 V) the derating can be greater than 50% and must be taken into consideration.
8.1.1.7 Input and Output Capacitor Requirements (CIN and COUT)
The TPS7A85A is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or
greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. TI
recommends using a capacitor with a value of at least 47 µF at the input to minimize input impedance. Place the
input and output capacitors as close as possible to the respective input and output pins to minimize trace
parasitic. If the trace inductance from the input supply to the TPS7A85A is high, a fast current transient can
cause VIN to ring above the absolute maximum voltage rating and damage the device. This situation can be
mitigated by additional input capacitors to dampen the ringing and to keep it below the device absolute maximum
ratings.
A combination of multiple output capacitors boosts the high-frequency PSRR as shown in several of the PSRR
curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,
10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes
PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency. This
47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage
configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a
voltage derating of approximately 60% to 80% at 5.15 V, so the addition of the two 10-µF capacitors ensures that
the capacitance is at or above 25 µF.
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8.1.1.8 Feed-Forward Capacitor (CFF)
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher
capacitance CFF can be used; however, the start-up time is longer, and the PG signal can incorrectly indicate that
the output voltage is settled. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor
with a Low Dropout Regulator.
8.1.1.9 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
The TPS7A85A features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CNR/SS).The use of an external CNR/SS is highly recommended, especially to minimize inrush current
into the output capacitors. This soft-start eliminates power-up initialization problems when powering fieldprogrammable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the
input power bus.
To achieve a monotonic start-up, the TPS7A85A error amplifier tracks the voltage ramp of the external soft-start
capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start
charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Soft-start ramp
time can be calculated with Equation 6:
t SS = (VNR/SS ´ CNR/SS ) / I NR/SS
(6)
INR/SS is shown in Electrical Characteristics.
The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that
minimizes the noise from the reference. The reference and noise are amplified by the error amplifier and so the
CNR/SS reduces the overall noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated
with Equation 7. The typical value of RNR/SS is 250 kΩ. Increasing the CNR/SS capacitor has a dominant effect on
the output noise at higher output voltages because of the larger gain that is present on the error amplifier. For
low-noise applications, TI recommends using a 10-nF to 1-µF CNR/SS . A larger CNR/SS has a higher leakage
current and as a result, the start-up time may be higher than the expected soft-start time calculated with
Equation 6.
f cutoff = 1/ (2 ´ p ´ R NR/SS ´ CNR/SS )
(7)
8.1.2 Start-Up
8.1.2.1 Circuit Soft-Start Control (NR/SS)
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an
external capacitor (CNR/SS). This soft-start eliminates power-up initialization problems when powering fieldprogrammable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the
input power bus.
The output voltage (VOUT) rises proportionally to VNR/SS during start-up as the LDO regulates so that the feedback
voltage equals the NR/SS voltage (VFB = VNR/SS). The time required for VNR/SS to reach the nominal value
determines the rise time of VOUT (start-up time).
Not using a noise-reduction capacitor on the NR/SS pin may result in an output voltage overshoot of
approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.
lists the soft-start charging current values.
8.1.2.1.1 Inrush Current
Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current consists of the
sum of load current and the current that charges the output capacitor. This current is difficult to measure because
the input capacitor must be removed, which is not recommended. This soft-start current can be estimated by
Equation 8:
u dVOUT (t) · § VOUT (t) ·
§C
IOUT (t) = ¨ OUT
¸
¸ + ¨
dt
©
¹ © RLOAD ¹
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where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(8)
8.1.2.2 Undervoltage Lockout (UVLO)
The UVLO circuits ensure that the device stays disabled before the input or bias supplies reach the minimum
operational voltage range, and ensures that the device properly shuts down when the input or bias supply
collapses.
Figure 53 and Table 8 show one of the UVLO circuits triggered by various input voltage events, assuming that
VEN ≥ VIH(EN).
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 53. Typical UVLO Operation
Table 8. Typical UVLO Operation Description
REGION
EVENT
VOUT STATUS
A
Turnon, VIN ≥ VUVLO_1, 2(IN) and
VBIAS ≥ VUVLO(BIAS)
COMMENT
Off
Start-up
B
Regulation
On
Regulates to target VOUT
C
Brownout, VIN ≥ VUVLO_1, 2(IN) –
VHYS_1, 2(IN)
or VBIAS ≥ VUVLO(BIAS) – VHYS(BIAS)
On
The output can fall out of regulation but the device is still enabled.
D
Regulation
On
Regulates to target VOUT
E
Brownout, VIN < VUVLO_1, 2(IN) –
VHYS_1, 2(IN)
or VBIAS ≥ VUVLO(BIAS) – VHYS(BIAS)
Off
The device is disabled and the output falls because of the load and
active discharge circuit. The device is reenabled when the UVLO
fault is removed when either the IN or BIAS UVLO rising threshold
is reached by the input or bias voltage and a normal start-up then
follows.
F
Regulation
On
Regulates to target VOUT
G
Turnoff, VIN < VUVLO_1, 2(IN) –
VHYS_1, 2(IN)
or VBIAS < VUVLO(BIAS) – VHYS(BIAS)
Off
The output falls because of the load and active discharge circuit.
Similar to many other LDOs with this feature, the UVLO circuits take a few microseconds to fully assert. During
this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time;
however, the UVLO circuits do not have enough stored energy to fully discharge the internal circuits inside of the
device. When the UVLO circuits are not given enough time to fully discharge the internal nodes, the outputs are
not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall
time of the input supply when operating near the minimum VIN.
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8.1.2.3 Power-Good (PG) Function
The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG
circuit asserts whenever FB, VIN, or EN are below the thresholds. The PG operation versus the output voltage is
shown in Figure 54, which is listed in Table 9.
PG Rising Threshold
PG Falling Threshold
VOUT
E
C
PG
tAt
tBt
tDt
tFt
tGt
Figure 54. Typical PG Operation
Table 9. Typical PG Operation Description
REGION
EVENT
PG STATUS
FB VOLTAGE
VFB < VIT(PG) + VHYS(PG)
A
Turnon
0
B
Regulation
Hi-Z
C
Output voltage dip
Hi-Z
D
Regulation
Hi-Z
E
Output voltage dip
0
F
Regulation
Hi-Z
VFB ≥ VIT(PG)
G
Turnoff
0
VFB < VIT(PG)
VFB ≥ VIT(PG)
VFB < VIT(PG)
The PG pin is open-drain and connects a pullup resistor to an external supply, enabling other devices to receive
power good as a logic signal that can be used for sequencing. Take care to ensure that the external pullup
supply voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The
lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100
kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then
the PG signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the PG signal to incorrectly indicate that the output voltage has
settled during turnon. The CFF time constant must be greater than the soft-start time constant to ensure proper
operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward
Capacitor with a Low Dropout Regulator.
The state of PG is only valid when the device operates above the minimum supply voltage. During short
brownout events and at light loads, PG does not assert because the output voltage (and as a result, VFB) is
sustained by the output capacitance.
8.1.3 AC and Transient Performance
LDO ac performance includes power-supply-rejection ratio, output-current transient response, and output noise.
These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closedloop input and output impedance of the LDO. The output noise is primarily a result of the reference and error
amplifier noise.
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Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control loop rejects signals from VIN to VOUT across the frequency
spectrum (usually 10 Hz to 10 MHz). Equation 9 gives the PSRR calculation as a function of frequency for the
input signal (VIN(f)) and output signal (VOUT(f)).
PSRR dB
§ V ¦ ·
20Log10 ¨ IN
¸¸
¨V
© OUT ¦ ¹
(9)
Although PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.
A simplified diagram of PSRR versus frequency is shown in Figure 55.
Power-Supply Rejection Ratio (dB)
PSRR Boost Circuit Improves PSRR in This Region
Band Gap
Band-Gap
RC Filter
Error Amplifier,
Flat-Gain Region
Error Amplifier,
Gain Roll-Off
Output Capacitor
|ZCOUT| Decreasing
Output Capacitor
|ZCOUT| Increasing
10 Hz±1 MHz
Sub 10 Hz
100 kHz +
Frequency (Hz)
Figure 55. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a dc-dc regulator, but provides exceptionally clean power-supply voltages
that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the
TPS7A85A.
The TPS7A85A features an innovative circuit to boost the PSRR from 200 kHz to 1 MHz; see . To achieve the
maximum benefit of this PSRR boost circuit, TI recommends using a capacitor with a minimum impedance in the
100-kHz to 1-MHz band.
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8.1.3.2 Output Voltage Noise
The TPS7A85A is designed for system applications where minimizing noise on the power-supply rail is critical to
system performance. For example, the TPS7A85A can be used in a phase-locked loop (PLL)-based clocking
circuit can be used for minimum phase noise, or in test and measurement systems where small power-supply
noise fluctuations reduce system dynamic range.
Charge Pump Spurs
fN
1/
oi
se
Wide-Band Noise
N
oi
se
ai
G
Integrated Noise
From Band-Gap and Error Amplifier
n
R
ol
ff
l-O
Output Voltage Noise Density (nV/¥+])
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower
frequencies as a function of 1/f). Figure 56 shows a simplified output voltage noise density plot versus frequency.
Measurement Noise Floor
Frequency (Hz)
Figure 56. Output Voltage Noise Diagram
For further details, see the How to Measure LDO Noise white paper.
8.1.3.3 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved in several ways, as listed in Table 10.
Table 10. Effect of Various Parameters on AC Performance (1) (2)
NOISE
(1)
(2)
PSRR
PARAMETER
LOWFREQUENCY
MIDFREQUENCY
HIGHFREQUENCY
LOWFREQUENCY
CNR/SS
+++
No effect
No effect
CFF
++
+++
+
MIDFREQUENCY
HIGHFREQUENCY
+++
+
No effect
++
+++
+
+++
COUT
No effect
+
+++
No effect
+
VIN – VOUT
+
+
+
+++
+++
++
PCB layout
++
++
+
+
+++
+++
The number of + symbols indicate the improvement in noise or PSRR performance by increasing the parameter value.
Shaded cells indicate the simplest improvement to noise or PSRR performance.
The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, which minimizes the
output voltage noise floor. The LPF is a single-pole filter, and the cutoff frequency can be calculated with
Equation 10. The typical value of RNR/SS is 250 kΩ. The effect of the CNR/SS capacitor increases when VOUT(nom)
increases because the noise from the reference is gained up when the output voltage increases. For low-noise
applications, TI recommends a 10-nF to 10-µF CNR/SS.
f cutoff = 1/ (2 ´ p ´ R NR/SS ´ CNR/SS )
(10)
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feedforward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing
out the loop bandwidth, which improves mid-band PSRR.
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A larger COUT or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing
the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the
internal circuits. However, a high power dissipation across the die increases the output noise because of the
increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and
isolating VOUT at high frequencies.
Table 11 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions
with an input voltage of 5.5 V and a load current of 4 A. The 5-V output is selected as a worst-case nominal
operation for output voltage noise.
Table 11. Output Noise Voltage at a 5-V Output
OUTPUT VOLTAGE NOISE
(µVRMS)
CNR/SS (nF)
CFF (nF)
COUT (µF)
11.7
10
10
47 || 10 || 10
7.7
100
10
47 || 10 || 10
6
100
100
47 || 10 || 10
7.4
100
10
1000
5.8
100
100
1000
8.1.3.3.1 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise, as shown in Figure 57.
Using a bias rail minimizes the internal charge-pump noise when the internal voltage is clamped, which reduces
the overall output noise floor.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter, which further reduces the high-frequency noise contribution.
0.5
VIN = 1.5 V, 4.5 PV RMS
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PV RMS
0.3
0.2
Noise (PV/—Hz)
0.1
0.07
0.05
0.03
0.02
0.01
0.007
0.005
0.003
0.002
0.001
1000000
2000000
3000000
4000000
5000000
6000000
Frequency (Hz)
7000000
8000000
9000000
1E+7
Figure 57. Charge Pump Noise
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8.1.3.4
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Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, where
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in
Figure 58 are further described in this section and are listed in Table 12. Regions A, E, and H are where the
output voltage is in steady-state.
VOUTx
B
A
F
C
D
E
G
H
IOUTx
Figure 58. Load Transient Waveform
Table 12. Load Transient Waveform Description
32
REGION
DESCRIPTION
A
Regulation
COMMENT
B
Output current ramping
C
LDO responding to transient
Recovery from the dip results from the LDO increasing its sourcing current, and leads
to output voltage regulation.
D
Reaching thermal equilibrium
At high load currents the LDO takes some time to heat up. During this time the output
voltage changes slightly.
E
Regulation
F
Output current ramping
G
LDO responding to transient
H
Regulation
Regulation
Initial voltage dip is a result of the depletion of the output capacitor charge.
Regulation
Initial voltage rise results from the LDO sourcing a large current, and leads to the
output capacitor charge to increase.
Recovery from the rise results from the LDO decreasing its sourcing current in
combination with the load discharging the output capacitor.
Regulation
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The transient response peaks (VOUT(max) and VOUT(min)) are improved by using more output capacitance; however,
using more output capacitance slows down the recovery time (Wrise and Wfall). Figure 59 shows these parameters
during a load transient with a given pulse duration (PW) and current levels (IOUT(LO) and IOUT(HI)).
VOUT(max)
Wrise
VOUT
Wfall
VOUT(min)
IOUT(HI)
PW
IOUT
IOUT(LO)
IOUT(LO)
tfall
trise
Figure 59. Simplified Load Transient Waveform
8.1.4 DC Performance
8.1.4.1 Output Voltage Accuracy (VOUT)
The device features an output voltage accuracy of 0.75% maximum with BIAS that includes the errors introduced
by the internal reference, load regulation, line regulation, and operating temperature as shown in the . Output
voltage accuracy specifies minimum and maximum output voltage error relative to the expected nominal output
voltage stated as a percent.
8.1.4.2
Dropout Voltage (VDO)
Generally, the dropout voltage refers to the minimum voltage difference between the input and output voltage
(VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for the given load
current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is
proportional to the output current because the device is operating as a resistive switch, as shown in Figure 60.
VDO
IOUT
Figure 60. Dropout Voltage versus Output Current
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VIN on this device because of the internal charge pump. Dropout voltage increases exponentially when the
input voltage approaches the maximum operating voltage.
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8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
Some applications can have transients that place the LDO into dropout, such as slower ramps on VIN for start-up
or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in
the right range, as shown in Figure 61. This condition is simply avoided by using an enable signal or by
increasing the soft-start time with CSS/NR.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Voltage
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 61. Start-Up Into Dropout
8.1.5 Sequencing Requirements
There is no sequencing requirement between the BIAS, IN, and EN pins in the TPS7A85A.
8.1.6 Negatively Biased Output
The TPS7A85A output can be negatively biased to the absolute maximum rating without effecting start-up
condition.
8.1.7 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current is current that flows through the body diode on the pass element instead of the normal
conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device
resulting from risks of electromigration and excess heat being dissipated across the device. If the current flow
gets high enough, a latch-up condition can be entered.
This section outlines conditions where excessive current can occur, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses quickly with little or no load current,
• The output is biased when the input supply is not established, or
• The output is biased above the input supply.
If excessive reverse current flow is expected in the application, then external protection must be used to protect
the device. Figure 62 shows one approach of protecting the device.
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Schottky Diode
IN
CIN
Internal Body Diode
OUT
TI Device
COUT
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 62. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.8 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be approximated using Equation 11:
PD = (VIN – VOUT ) ´ I OUT
(11)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. The minimum input to output voltage differential is obtained by properly selecting the system
voltage rails. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device is through the thermal pad on the package. As a result, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to
Equation 12. The equation is rearranged for output current in Equation 13.
TJ = TA + R qJA ´ PD
(12)
I OUT = (TJ - TA ) / RqJA ´ (VIN – VOUT )
(13)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, which varies according to the total copper area, copper weight, and location of the planes.
The RθJA recorded in the v table is determined by the JEDEC standard, PCB, and copper-spreading area, and is
only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is the
sum of the VQFN package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance
contribution by the PCB copper.
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8.1.8.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not referencing thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are shown in and are used in accordance with Equation 14.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(14)
8.1.8.2 Recommended Area for Continuous Operation (RACO)
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator can be separated into the
following parts, as shown in Figure 63:
•
•
•
Output Current (A)
•
Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VIN – VOUT) at a given output current level; see Dropout Voltage (VDO) for more details.
Limited by rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
Limited by thermals: The shape of the slope is calculated by Equation 14. The slope is nonlinear because the
junction temperature of the LDO is controlled by the power dissipation across the LDO. As a result, when
VIN – VOUT increases, the output current must decrease to ensure that the rated junction temperature of the
device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces
long-term reliability.
Limited by VIN range: The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited by Thermals
Limited by
Minimum VIN
Limited by
Maximum VIN
VIN ± VOUT (V)
Figure 63. Continuous Operation Slope Region Description
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Figure 64 to Figure 69 show the recommended area of operation curves for this device on a JEDEC-standard,
high-K board with a RθJA = 43.4°C/W, as shown in .
6
6
TA = +40°C
TA = +55°C
TA = +70°C
4
3
2
1
4
3
2
0
0
0.2
0.4
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
0
0.2
0.4
D001
fig5
Figure 64. Recommended Area for Continuous Operation
for VOUT = 0.9 V
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
D001
fig6
Figure 65. Recommended Area for Continuous Operation
for VOUT = 1.2 V
6
6
TA = +40°C
TA = +55°C
TA = +70°C
TA = +85°C
RACO at TA = +85°C
TA = +40°C
TA = +55°C
TA = +70°C
5
Output Current (A)
5
Output Current (A)
TA = +85°C
RACO at TA = +85°C
1
0
4
3
2
1
TA = +85°C
RACO at TA = +85°C
4
3
2
1
0
0
0
0.2
0.4
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
0
0.2
0.4
D001
fig6
Figure 66. Recommended Area for Continuous Operation
for VOUT = 1.8 V
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
D001
fig6
Figure 67. Recommended Area for Continuous Operation
for VOUT = 2.5 V
6
6
TA = +40°C
TA = +55°C
TA = +70°C
TA = +85°C
RACO at TA = +85°C
TA = +40°C
TA = +55°C
TA = +70°C
5
Output Current (A)
5
Output Current (A)
TA = +40°C
TA = +55°C
TA = +70°C
5
Output Current (A)
Output Current (A)
5
TA = +85°C
RACO at TA = +85°C
4
3
2
1
TA = +85°C
RACO at TA = +85°C
4
3
2
1
0
0
0
0.2
0.4
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
0
0.2
D001
fig6
Figure 68. Recommended Area for Continuous Operation
for VOUT = 3.3 V
0.4
0.6
0.8
1
VIN - VOUT (V)
1.2
1.4
1.6
D001
fig6
Figure 69. Recommended Area for Continuous Operation
for VOUT = 5 V
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8.2 Typical Applications
8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
The TPS7A85A device uses the ANY-OUT configuration to regulate a 4-A load requiring good PSRR at high
frequency with low-noise at 0.9 V using a 1.2-V input voltage and a 5-V bias supply. The schematic for this
typical application circuit is shown in Figure 70.
CBIAS
Bias
Supply
1.4 VIN
BIAS
IN
CIN
PG
EN
RPG
NR/SS
OUT
COUT
CNR/SS
TPS7A85A
SNS
1.6 V
CFF
800 mV
FB
400 mV
200 mV
100 mV
50 mV
0.9 VOUT
To Digital
Load
GND
ANYOUT
Used to set
voltage
Copyright © 2017, Texas Instruments Incorporated
Figure 70. TPS7A85A Typical Application
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 13 as the input parameters.
Table 13. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.4 V, ±3%, provided by the dc-dc converter switching at 500 kHz
Bias voltage
5 V, ±5%
Output voltage
0.9 V, ±1%
Output current
4 A (maximum), 100 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 10 µVRMS
PSRR at 500 kHz
> 40 dB
Start-up time
< 25 ms
8.2.1.2 Detailed Design Procedure
At 4 A, the dropout of the TPS7A85A has 240-mV maximum dropout over temperature, and a result, a 400-mV
headroom is sufficient for operation over input and output voltage accuracy. The bias rail is provided for better
performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, and noise is less than
10 µVRMS, as listed in Table 13.
The ANY-OUT internal resistor network is used for maximum accuracy.
The 100mV pin is grounded to achieve 0.9 V on the output. The voltage value of 100 mV is added to the 0.8-V
internal reference voltage for VOUT(nom) equal to 0.9 V, as shown in Equation 15.
VOUT(nom) = VNR / SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
(15)
38
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Input and output capacitors are selected in accordance with External Component Selection. Ceramic
capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output
are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This
value is calculated with Equation 16.
t SS = (VNR/SS ´ CNR/SS ) / INR/SS
(16)
At the 4-A maximum load, the internal power dissipation is 2 W and corresponds to a 7°C junction temperature
rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the
junction temperature is at 62°C. To further minimize noise, a feed-forward capacitance (CFF) of 10 nF is selected.
8.2.1.3 Application Curves
25
5
0
2.5
-25
0
-50
0
0.5
1
Time (ms)
1.5
2
1
0.8
Voltage (V)
7.5
Output Current (A)
1.2
50
Output Current
VOUT = 0.9 V
VOUT = 1.2 V
VOUT = 1.8 V
AC-Coupled Output Voltage (mV)
10
0.6
0.4
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0.2
0
-0.2
0
Figure 71. Output Load Transient Response
5
10
15
20
25
30
Time (ms)
35
40
45
50
Figure 72. Output Start-Up Response
9 Power-Supply Recommendations
The TPS7A85A device is designed to operate from an input voltage supply range from 1.1 V to 6.5 V. If the input
supply is less than 1.4 V, then a bias rail of at least 3 V must be used. The input voltage range provides
adequate headroom for the device to have a regulated output. This input supply must be well-regulated. If the
input supply is noisy, additional input capacitors with low ESR may help improve output noise performance.
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. The grounding and layout scheme shown in Figure 73 minimizes
inductive parasitics, and as a result, reduces load-current transients, minimizes noise, and increases circuit
stability.
TI recommends a ground reference plane embedded in the PCB itself or located on the bottom side of the PCB
opposite the components. This reference plane serves to ensure accuracy of the output voltage, shield noise,
and behaves similarly to a thermal plane to spread (or sink) heat from the LDO device when connected to the
thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.
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10.2 Layout Example
CBIAS
To Bias Supply
1.6V
800mV
400mV
GND
200mV
100mv
Ground Plane for Thermal Relief and Signal
Ground
10
9
8
7
6
11
5
RPG
BIAS
12
4
PG Output
PG
R2
Thermal Pad
To Signal Ground
To PG Pullup Supply
50mV
NR/SS
13
3
FB
EN
14
2
SNS
To Signal Ground
CNR/SS
Enable Signal
To Load
CFF R1
1
17
18
19
20
IN
GND
OUT
OUT
Input Power Plane
16
IN
15
IN
CIN
OUT
Output Power Plane
COUT
Power Ground Plane
Vias used for application purposes.
Figure 73. Example Layout
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A8500ARGRR
ACTIVE
VQFN
RGR
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8500A
TPS7A8500ARGRT
ACTIVE
VQFN
RGR
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8500A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7A8500ARGRR
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
TPS7A8500ARGRT
VQFN
RGR
20
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A8500ARGRR
VQFN
RGR
20
3000
367.0
367.0
35.0
TPS7A8500ARGRT
VQFN
RGR
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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