Texas Instruments | TPS65150-Q1 Automotive LCD Power Supply for Source and Gate Drivers with Gate Voltage Shaping and VCOM Buffer (Rev. C) | Datasheet | Texas Instruments TPS65150-Q1 Automotive LCD Power Supply for Source and Gate Drivers with Gate Voltage Shaping and VCOM Buffer (Rev. C) Datasheet

Texas Instruments TPS65150-Q1 Automotive LCD Power Supply for Source and Gate Drivers with Gate Voltage Shaping and VCOM Buffer (Rev. C) Datasheet
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TPS65150-Q1
SLVSBX4C – JUNE 2013 – REVISED MAY 2017
TPS65150-Q1 Automotive LCD Power Supply for Source and Gate Drivers with Gate
Voltage Shaping and VCOM Buffer
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
AEC-Q100 Qualified:
– Device Temperature Grade 1: –40°C to 125°C
Junction Temperature
– Device HBM ESD Classification According to
AEC - Q100-002
– Device CDM ESD Classification According to
AEC - Q100-011
Input Voltage Range: 1.8 V to 6 V
V(VS) Boost Converter
– Up to 15 V Output Voltage
– < 1% Output Voltage Accuracy
– 2-A Switch Current Limit
V(VGH) Positive Regulated Charge Pump Driver
– Up to 30 V Output Voltage
– Gate Voltage Shaping
V(VGL) Negative Regulated Charge Pump Driver
– Down to –15 V Output Voltage
Integrated VCOM Buffer
Adjustable Power On Sequencing
– Gate Drive Signal for External Isolation
MOSFET for V(VS)
Protection Features
– Out-of-Regulation Protection
– Over-voltage Protection
– Adjustable Fault Detection Timing
– Thermal Shutdown
24-Pin TSSOP Package with Exposed Thermal
Pad
LCD Displays ranging approx. from 4" to 17"
– Automotive Infotainment & Cluster
– Automotive Navigation Systems
– Rear Seat Entertainment
– Smart Mirror
3 Description
The TPS65150-Q1 is an integrated power-supply for
automotive LCD applications. The device integrates a
boost converter for the source voltage and two
regulated adjustable charge pump drivers for the gate
voltages. For reduced external cost, improved picture
quality and reduced image sticking, the device
includes a VCOM buffer and a gate-voltage shaping
function.
The device is designed to operate from a supply
voltage of 1.8 V to 6 V making it ideal for automotive
LCD applications using a fixed 3.3 V or 5 V inputvoltage rail.
Adjustable power-on sequencing for VGL and VGH
allow the device to be optimized for a variety of
displays.
For protection from system malfunction, the
TPS65150-Q1 integrates an adjustable shutdown
latch feature. The device monitors the outputs (V(VS),
V(VGL), V(VGH)); and, as soon as one of the outputs
falls below its power-good threshold for longer than
the adjustable fault delay time, the device enters
shutdown.
Device Information(1)
PART NUMBER
TPS65150-Q1
PACKAGE
TSSOP (24)
BODY SIZE (NOM)
6.40 mm × 7.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VI
1.8 V to 6.0 V
Boost
Converter
Negative
Charge Pump
Positive
Charge Pump
Gate-Voltage
Shaping
VCOM
Buffer
V(VS)
Up to 15 V / 300 mA
V(VGL)
Down to ±15 V / 50 mA
V(CPI)
V(VGH)
Up to 30 V / 50 mA
V(VCCM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65150-Q1
SLVSBX4C – JUNE 2013 – REVISED MAY 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
8.3 System Examples ................................................... 30
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2016) to Revision C
Page
•
Moved "AEC-Q100 Qualified" to the top of Features list........................................................................................................ 1
•
Changed the Electrical Characteristics conditions From: TA = –40°C to 85°C To: TA = –40°C to 125°C .............................. 6
Changes from Revision A (September 2013) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added specifications to the Absolute Maximum Ratings table............................................................................................... 5
•
Added Switching Characteristics ........................................................................................................................................... 7
•
Changed typical characteristics graphs ................................................................................................................................. 8
•
Changed Functional Block Diagram for clarity .................................................................................................................... 11
Changes from Original (June 2013) to Revision A
•
2
Page
Changed document status from Product Preview to Production Data .................................................................................. 1
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5 Pin Configuration and Functions
PWP Package
24-Pin TSSOP
Top View
1
24
FDLY
2
23
GD
DLY2
3
22
COMP
VIN
4
21
FBN
SW
5
20
REF
SW
6
19
GND
PGND
7
18
DRVN
PGND
8
17
DRVP
SUP
9
16
CPI
VCOM
10
15
IN
11
14
VGH
ADJ
FBP
12
13
CTRL
Thermal Pad
FB
DLY1
Pin Functions
PIN
NAME
HTSSOP
I/O
DESCRIPTION
ADJ
14
I/O
Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the
positive gate voltage V(VGH).
COMP
22
O
This is the compensation pin for the main boost converter. A small capacitor and if
required a series resistor is connected to this pin.
CPI
16
I
Input of the VGH isolation switch and gate voltage shaping circuit.
CTRL
13
I
Control signal for the gate voltage shaping signal. Apply the control signal for the gate
voltage control. Usually the timing controller of the LCD panel generates this signal. If this
function is not required, this pin must be connected to VI. By doing this, the internal switch
between CPI and VGH provides isolation for the positive charge pump output V(VGH).
DLY2 sets the delay time for V(VGH) to come up.
DLY1
2
I/O
Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set
the delay time between the boost converter output V(VS) and the negative charge pump
V(VGL) during start-up.
DLY2
3
I/O
Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set
the delay time between the negative charge pump V(VGL) and the positive charge pump
during start-up. Note that Q5 in the gate voltage shaping block only turns on when the
positive charge pump is within regulation. (This provides input-output isolation of V(VGH)).
DRVN
18
I/O
Negative charge pump driver.
DRVP
17
I/O
Positive charge pump driver.
FB
1
I
Boost converter feedback sense input.
FBN
21
I
Negative charge pump feedback sense input.
FBP
12
I
Positive charge pump feedback sense input.
FDLY
24
I/O
GD
23
I
GND
19
IN
11
PGND
7, 8
REF
20
O
Internal reference output, typically 1.213 V.
SUP
9
I/O
Supply pin of the positive, negative charge pump and boost converter gate drive circuit.
This pin must be connected to the output of the main boost converter and cannot be
connected to any other voltage rail.
Fault delay. Connecting a capacitor from this pin to VI sets the delay time from the point
when one or more of the of the outputs V(VS), V(VGH), V(VGL) drops below its power good
threshold until the device shuts down. To restart the device, the input voltage must be
cycled to ground. This feature can be disabled by connecting the FDLY pin to VI.
Active-low, open-drain output. This output is latched low when the boost converter output
is in regulation. This signal can be used to drive an external MOSFET to provide isolation
for V(VS).
Analog ground.
I
Input of the VCOM buffer. If this pin is connected to ground, the VCOM buffer is disabled.
Power ground.
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Pin Functions (continued)
PIN
NAME
HTSSOP
I/O
DESCRIPTION
SW
5, 6
I
Switch pin of the boost converter.
VCOM
10
O
VCOM buffer output. Typically a 1-µF output capacitor is required on this pin.
VGH
15
O
Positive output voltage to drive the TFT gates with an adjustable fall time. This pin is
internally connected with a MOSFET switch to the positive charge pump input CPI.
VIN
4
I
This is the input voltage pin of the device.
Thermal Pad
—
4
The thermal pad must to be soldered to GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN, CTRL
–0.3
7
V
ADJ
–0.3
22
V
VCOM, IN, DRVP, DRVN
–0.3
15
V
FBN, COMP, FBP, FB, DLY1, DLY2
–0.3
5.5
V
REF
–0.3
4
V
VGH
–0.3
30
V
FDLY
–0.3
6
V
GD, SUP
–0.3
15.5
V
SW
–0.3
20
V
CPI
–0.3
32
V
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Voltages on pin
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC-Q100-02
±2000
Charged-device model (CDM), per AEC-Q100-011
±500
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VI
Input voltage range
V(VS)
Output voltage range of the boost converter V(VS)
(1)
L
Inductor
TA
Operating ambient temperature
(1)
NOM
MAX
1.8
UNIT
6
V
15
V
4.7
µH
–40
125
°C
See Typical Application for further information.
6.4 Thermal Information
TPS65150-Q1
THERMAL METRIC (1)
PWP (TSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
40.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.8
°C/W
RθJB
Junction-to-board thermal resistance
18.4
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
18.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VI = 3.3 V, V(VS) = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
V
14
25
µA
SUPPLY CURRENT
VI
Input voltage (VIN)
1.8
Supply current (VIN)
Device not switching
Supply current (SUP)
Device not switching
1.9
3
mA
750
1500
µA
–40 °C < TA < 85 °C
1.6
1.8
–40 °C < TA < 125 °C
1.6
1.85
–40 °C < TA < 85 °C
1.7
1.9
–40 °C < TA < 125 °C
1.7
1.95
Supply current (VCOM buffer)
VIT–
Undervoltage lockout threshold (VIN)
VI falling
VIT+
Undervoltage lockout threshold (VIN)
VI rising
Thermal shutdown temperature threshold
TJ rising
Thermal shutdown temperature hysteresis
V
V
155
°C
10
°C
LOGIC SIGNALS
VIH
High-level input voltage (CTRL)
VIL
Low-level input voltage (CTRL)
IIH, IIL
Input current (CTRL)
1.6
CTRL = VI or GND
V
0.4
V
0.01
0.2
µA
15
V
BOOST CONVERTER
VO
Output voltage
Vref
Boost converter reference voltage (FB)
IIB
Input bias current (FB)
–40 °C < TA < 85 °C
1.136
1.146
1.154
–40 °C < TA < 125 °C
1.132
1.146
1.160
V
10
100
VO = 10 V
200
300
VO = 5 V
305
450
VO = 10 V
8
15
VO = 5 V
12
22
2.5
3.4
A
1
10
µA
rDS(on)
Drain-source on-state resistance (Q1)
IDS = 500 mA
rDS(on)
Drain-source on-state resistance (Q2)
IDS = 500 mA
IDS
Drain-source current rating (Q2)
1
Current limit (Q1)
2
I(SW)(off)
Off-state current (SW)
V(SW) = 15 V
VIT+
Overvoltage protection threshold (SUP)
V(SUP) rising
ΔVO(ΔVI)
Line regulation
VI = 1.8 V to 5 V
IO = 1 mA
ΔVO(ΔIO)
Load regulation
VI = 5 V
IO = 0 A to 400 mA
VIT+
Gate drive threshold (FB) (1)
nA
mΩ
Ω
A
16
20
V
0.007
%/V
0.16
%/A
–12% of
Vref
–4% of
Vref
V
–2
V
NEGATIVE CHARGE PUMP
VO
Output voltage
–40 °C < TA < 85 °C
1.205
1.213
1.219
–40 °C < TA < 125 °C
1.203
1.213
1.223
V(REF)
Reference output voltage (REF)
Vref
Feedback regulation voltage (FBN)
IIB
Input bias current (FBN)
rDS(on)
Drain-source on-state resistance (Q4)
IDS = 20 mA
4.4
V(DRVN)
Current sink voltage drop (2)
V(FBN) = 5% above nominal I(DRVN) = 50 mA
voltage
I(DRVN) = 100 mA
130
300
280
450
ΔVO(ΔIO)
Load regulation
VO = –5 V
(1)
(2)
6
–36
IO = 0 mA to 20 mA
V
0
36
mV
10
100
nA
0.016
Ω
mV
%/mA
The GD signal is latched low when the main boost converter output is within regulation. The GD signal is reset when the voltage on the
VIN pin goes below the UVLO threshold voltage.
The maximum charge pump output current is half the drive current of the internal current source or sink.
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Electrical Characteristics (continued)
VI = 3.3 V, V(VS) = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.187
1.214
1.238
V
10
100
nA
POSITIVE CHARGE PUMP
VO
Output voltage
CTRL = GND
VGH = open
Vref
Feedback regulation voltage (FBP)
CTRL = GND
VGH = open
IIB
Input bias current (FBP)
CTRL = GND
VGH = open
rDS(on)
Drain-source on-state resistance (Q3)
IDS = 20 mA
30
V
Ω
1.1
V(SUP) –
V(DRVP)
Current sink voltage drop (2)
V(FBP) = 5% below nominal
voltage
I(DRVP) = 50 mA
420
650
I(DRVP)= 100 mA
900
1400
ΔVO(ΔIO)
Load regulation
VO = 24 V
IO = 0 mA to 20 mA
0.07
mV
%/mA
GATE-VOLTAGE SHAPING
rDS(on)
Drain-source on-state resistance (Q5)
IO = –20 mA
I(ADJ)
Capacitor charge current
V(ADJ) = 20 V
V(CPI) = 30 V
VOmin
Minimum output voltage
V(ADJ) = 0 V
IO = –10 mA
IOM
Maximum output current
160
12
30
Ω
200
240
µA
2
V
20
mA
TIMING CIRCUITS DLY1, DLY2, FDLY
I(DLY1)
Drive current into delay capacitor (DLY1)
V(DLY1) = 1.213 V
3
5
7
µA
I(DLY2)
Drive current into delay capacitor (DLY2)
V(DLY2) = 1.213 V
3
5
7
µA
R(FDLY)
Fault time delay resistor
250
450
650
kΩ
GATE DRIVE (GD)
V(GD_VS)
Gate Drive Threshold
V(VS) rising
VOL
Low-level output voltage (GD)
IOL = 500 µA
IOH
Off-state current (GD)
VOH = 15 V
–12% of
V(SUP)
–4% of
V(SUP)
0.5
V
1
µA
2.25
V(SUP) –
2V
V
IO = 0 mA
–25
25
IO = ±25 mA
–37
37
IO = ±50 mA
–77
55
IO = ±100 mA
–85
85
IO = ±150 mA
–110
110
0.001
VCOM BUFFER
VISR
Single-ended input voltage (IN)
VIO
Input offset voltage (IN)
ΔVO(ΔIO)
IIB
IOM
Load regulation
Input bias current (IN)
Maximum output current (VCOM)
–300
V(SUP) = 15 V
1.2
V(SUP) = 10 V
0.65
V(SUP) = 5 V
0.15
–30
mV
mV
300
nA
A
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Oscillator frequency
MIN
1.02
TYP
MAX
UNIT
1.2
1.38
MHz
Duty cycle (DRVN)
50%
Duty cycle (DRVP)
50%
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6.7 Typical Characteristics
The typical characteristics are measured at 3.3 V
Table 1. Table Of Graphs
FIGURE
Boost converter switch (Q1) current limit
vs temperature
Figure 1
Boost converter switch (Q1) rDS(on)
vs temperature
Figure 2
Boost converter rectifier (Q2) rDS(on)
vs temperature
Figure 3
Boost converter reference Voltage
vs temperature
Figure 4
Positive charge pump reference voltage
vs temperature
Figure 5
REF pin voltage
vs temperature
Figure 6
Oscillator frequency
vs temperature
Figure 7
3.4
0.30
3.2
0.25
Resistance (Ω)
Current (A)
3.0
2.8
2.6
2.4
−20
0
20
40
60
80
Junction Temperature (°C)
100
0
20
40
60
80
Junction Temperature (°C)
100
120
G000
Figure 2. Boost Converter Switch (Q1) rDS(on) vs
Temperature
1.155
20
1.150
Voltage (V)
Resistance (Ω)
−20
G000
25
15
10
1.145
1.140
5
−20
0
20
40
60
80
Junction Temperature (°C)
100
120
1.135
−40
G000
Figure 3. Boost Converter Rectifier (Q2) rDS(on) vs
Temperature
8
0.10
0.00
−40
120
Figure 1. Boost Converter Switch (Q1) Current Limit vs
Temperature
0
−40
0.15
0.05
2.2
2.0
−40
0.20
−20
0
20
40
60
80
Junction Temperature (°C)
100
120
G000
Figure 4. Boost Converter Reference Voltage vs
Temperature
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1.24
1.220
1.23
Voltage (V)
Voltage (V)
1.215
1.22
1.21
1.210
1.20
1.205
1.19
1.18
−40
−20
0
20
40
60
80
Junction Temperature (°C)
100
120
1.200
−40
−20
0
G000
Figure 5. Positive Charge Pump Reference Voltage vs
Temperature
20
40
60
80
Junction Temperature (°C)
100
120
G000
Figure 6. REF Pin Voltage vs Temperature
1.40
1.35
Frequency (MHz)
1.30
1.25
1.20
1.15
1.10
1.05
1.00
−40
−20
0
20
40
60
80
Junction Temperature (°C)
100
120
G000
Figure 7. Oscillator Frequency vs Temperature
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7 Detailed Description
7.1 Overview
The TPS65150-Q1 device is a complete bias supply for LCD displays. The device generates supply voltages for
the source driver and gate driver ICs in the display as well as generating the common plane voltage of the
display (VCOM). The device also features a gate-voltage shaping function that can be used to reduce image
sticking and improve picture quality. The use of external components to control power-up sequencing, fault
detection time, and boost converter compensation allows the device to be optimized for a variety of displays.
The device has been designed to work from input supply voltages as low as 1.8 V and is therefore ideal for use
in applications where it is supplied from fixed 2.5-V, 3.3-V, or 5-V supplies.
10
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7.2 Functional Block Diagram
SW
SUP
FB
±
1.146 V
+
Sawtooth
Generator
Q2
V(VIN)
COMP
Control
Logic
&
Gate
Drivers
1.2 MHz
FBP
V(SUP)
DRVP
Q3
+
Current
Control
&
Soft
Start
Q1
±
I(DRVP)
Current
Limit
&
Soft
Start
1.214 V
PGND
1.2 MHz
CPI
Q5
Control
Logic
FBN
Q7
VGH
V(SUP)
I(DRVN)
Q6
+
DRVN
±
Current
Control
&
Soft
Start
Q4
V(FBP) power good
UVLO
&
200 µA
1.2 MHz
ADJ
CTRL
Boost converter soft start completed
VIN
&
GD
V(FB) power good
5 µA
1.213 V
delay 1
DLY1
5 µA
1.213 V
delay 2
DLY2
References,
Control Logic,
Oscillator,
Sequencing,
Fault Detection &
Thermal Shutdown
REF
1.213 V
1.146 V
1.2 MHz
Soft Start
GND
V(SUP)
Q11
0.69 V(VIN)
fault
±
FDLY
VCOM
+
450 k
Disable
IN
Q12
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7.3 Feature Description
7.3.1 Boost Converter
Figure 8 shows a simplified block diagram of the boost converter.
L
VI
VO
CI
CO
VIN
SW
SUP
Q2
Feed-forward
signal
Current Limit
& Soft Start
I(SW)
To charge
pumps,
VCOM
buffer, etc.
Q1
1.2 MHz
Sawtooth
Generator
Gate
Drive
R1
CFF
FB
±
+
Vref = 1.146 V
R2
COMP
RCOMP
CCOMP
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Boost Converter Block Diagram
The boost converter uses a unique fast-response voltage-mode controller scheme with input feedforward to
achieve excellent line and load regulation, while still allowing the use of small external components. The use of
external compensation adds flexibility and allows the response of the boost converter to be optimized for a wide
range of external components.
The TPS65150-Q1 device uses a virtual-synchronous topology that allows the boost converter to operate in
continuous conduction mode (CCM) even at light loads. This is achieved by including a small MOSFET (Q2) in
parallel with the external rectifier diode. Under light-load conditions, Q2 allows the inductor current to become
negative, maintaining operation in CCM. By operating always in CCM, boost converter compensation is
simplified, ringing on the SW pin at low loads is avoided, and additional charge pump stages can be driven by
the SW pin. The boost converter duty cycle is given by Equation 1.
VI
D=1±
VO
where
•
•
•
12
η is the boost converter efficiency (either taken from data in Application Curves or a worst-case assumption of
75%),
VI is the boost converter input supply voltage, and
VO is the boost converter output voltage.
(1)
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Feature Description (continued)
Use Equation 2 to calculate the boost converter peak switch current.
DVI
IO
I:SW;M =
+
2fL 1 ± D
where
•
•
•
f = 1.2 MHz (the boost converter switching frequency),
IO is the boost converter output current, and
L is the boost converter inductance.
(2)
7.3.1.1 Setting the Boost Converter Output Voltage
The boost converter output voltage is set by the R1/R2 resistor divider, and is calculated using Equation 3.
R1
VO = l1 +
pV
R2 ref
where
•
Vref = 1.146 V (the boost converter internal reference voltage).
(3)
To minimize quiescent current consumption, the value of R1 should be in the range of 100 kΩ to 1 MΩ.
7.3.1.2 Boost Converter Rectifier Diode
The reverse voltage rating of the diode must be higher than the maximum output voltage of the converter, and its
average forward current rating must be higher than the output current of the boost converter. Use Equation 4 to
calculate the rectifier diode repetitive peak forward current.
IFRM = I:SW;M
(4)
Use Equation 5 to calculate the power dissipated in the rectifier diode.
PD = VF IO
where
•
VF is the rectifier diode forward voltage.
(5)
The main diode parameters affecting converter efficiency are its forward voltage and reverse leakage current,
and both should be as low as possible.
7.3.1.3 Choosing the Boost Converter Output Capacitance
The output capacitance of the boost converter smooths the output voltage and supplies transient output current
demands that are outside the loop bandwidth of the converter. Generally speaking, larger output currents or
smaller input supply voltages require larger output capacitances. Use Equation 6 to calculate the output voltage
ripple of the boost converter.
DIO
VO:PP; =
fCO
where
•
CO is the boost converter output capacitance.
(6)
7.3.1.4 Compensation
The boost converter requires a series R-C network connected between the COMP pin and ground to
compensate its feedback loop. The COMP pin is the output of the boost converter's error amplifier, and the
compensation capacitor determines the amplifier's low-frequency gain and the resistor its high-frequency gain.
Because the converter gain changes with the input voltage, different compensation capacitors may be required:
lower input voltages require a higher gain, and therefore a smaller compensation capacitor value. If an input
supply voltage of the application changes (for example, if the TPS65150-Q1 device is supplied from a battery),
choose compensation components suitable for a supply voltage midway between the minimum and maximum
values. In all cases, verify that the values selected are suitable by performing transient tests over the full range of
operating conditions.
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Feature Description (continued)
Table 2. Recommended Compensation Components for Different Input Supply Voltages
VI
CCOMP
RCOMP
FEED-FORWARD ZERO
CUT-OFF FREQUENCY
2.5 V
470 pF
68 kΩ
8.8 kHz
3.3 V
470 pF
33 kΩ
7.8 kHz
5V
2.2 nF
0 kΩ
11.2 kHz
A feed-forward capacitor CFF in parallel with the upper feedback resistor R1 adds an additional zero to the loop
response, which improves transient performance. Table 2 suggests suitable values for the cut-off frequency of
the feedforward zero; however, these are only guidelines. In any application, variations in input supply voltage,
inductance, and output capacitance all affect circuit operation, and the optimum value must be verified with
transient tests before being finalized.
The cut-off frequency of the feed-forward zero is determined using Equation 7.
1
fco =
Œ:R1;CFF
where
•
fco is the cutoff frequency of the feedforward zero formed by R1 and CFF.
(7)
7.3.1.5 Soft Start
The boost converter features a soft-start function that limits the current drawn from the input supply during startup. During the first 2048 switching cycles, the switch current of the boost converter is limited to 40% of its
maximum value; during the next 2048 cycles, it is limited to 60% of its maximum value; and after that it is as high
as it must be to regulate the output voltage (up to 100% of the maximum). In typical applications, this results in a
start-up time of about 5 ms (see Figure 9).
Switch Current Limit
100%
60%
40%
0%
t2048 cyclest
t2048 cyclest
t
Figure 9. Boost Converter Switch Current Limit During Soft-Start
7.3.1.6 Gate Drive Signal
The GD pin provides a signal to control an external P-channel enhancement MOSFET, allowing the output of the
boost converter to be isolated from its input when disabled (see Figure 36). The GD pin is an open-drain type
whose output is latched low as soon as the output voltage of the boost converter reaches its power-good
threshold. The GD pin goes high impedance whenever the input voltage falls below the undervoltage lockout
threshold or the device shuts down as the result of a fault condition (see Adjustable Fault Delay).
7.3.2 Negative Charge Pump
Figure 10 shows a simplified block diagram of the negative charge pump.
14
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SUP
1.2 MHz
Q4
Current
Control
&
Soft
Start
DRVN
CFLY
D1
VO
D2
CO
I(DRVN)
R1
FBN
+
±
R2
REF
1.213 V
+
±
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Negative Charge Pump Block Diagram
The negative charge pump operates with a fixed frequency of 1.2 MHz and a 50% duty cycle in two distinct
phases. During the charge phase, transistor Q4 is turned on, controlled current source I(DRVN) is turned off, and
flying capacitance CFLY charges up to approximately V(SUP). During the discharge phase, Q4 is turned off, I(DRVN)
is turned on, and a negative current of I(DRVN) flows through D1 to the output. The output voltage is fed back
through R1 and R2 to an error amplifier that controls I(DRVN) so that the output voltage is regulated at the correct
value.
7.3.2.1 Negative Charge Pump Output Voltage
The negative charge pump output voltage is set by resistors R1 and R2 and is given by Equation 8.
R1
VO = ± l p V(REF)
R2
where
•
V(REF) = 1.213 V (the voltage on the REF pin).
(8)
Resistor R2 should be in the range 39 kΩ to 150 kΩ. Smaller values load the REF pin too heavily and larger
values may cause stability problems.
7.3.2.2 Negative Charge Pump Flying Capacitance
The flying capacitance transfers charge from the SUP pin to the negative charge pump output. TI recommends a
flying capacitor of at least 100 nF for output currents up to 20 mA. Smaller values can be used with smaller
output currents.
7.3.2.3 Negative Charge Pump Output Capacitance
The output capacitor smooths the discontinuous current delivered by the flying capacitor to generate a DC output
voltage. In general, higher output currents require larger output capacitances. Use Equation 9 to calculate the
negative charge pump output voltage ripple.
IO
VO(PP) =
2fCO
where
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•
•
•
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IO is the negative charge pump output current,
CO is the negative charge pump output capacitance, and
f = 1.2 MHz (the negative charge pump switching frequency).
(9)
7.3.2.4 Negative Charge Pump Diodes
The average forward current of both diodes is equal to the negative charge pump output current. If the
recommended flying capacitor (or larger) is used, the repetitive peak forward current in D1 and D2 is equal to
twice the output current.
7.3.3 Positive Charge Pump
Figure 11 shows a simplified block diagram of the positive charge pump, which works in a similar way to the
negative charge pump except that the positions of the current source IDRVP and the MOSFET Q3 are reversed.
SUP
V(VS)
I(DRVP)
1.2 MHz
Current
Control
&
Soft
Start
DRVP
CFLY
D2
VO
D1
CO
Q3
R1
FBP
±
+
Vref = 1.214 V
R2
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Figure 11. Positive Charge Pump Block Diagram
If higher output voltages are required another charge pump stage can be added to the output, as shown in
Figure 34 at the end of the data sheet.
7.3.3.1 Positive Charge Pump Output Voltage
The positive charge pump output voltage is set by resistors R1 and R2 and is calculated using Equation 10.
R1
VO = l1 +
pV
R2 ref
where
•
Vref = 1.214 V (the positive charge pump reference voltage).
(10)
TI recommends choosing a value for R2 not greater than 1 MΩ.
7.3.3.2 Positive Charge Pump Flying Capacitance
The flying capacitance transfers charge from the SUP pin to the charge pump output. TI recommends a flying
capacitor of at least 330 nF (1) for output currents up to 20 mA. Smaller values can be used with smaller output
currents.
(1)
16
The minimum recommended flying capacitance for the positive charge pump is larger than for the negative charge pump because the
rDS(on) of Q3 is smaller than the rDS(on) of Q4.
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7.3.3.3 Positive Charge Pump Output Capacitance
The output voltage ripple of the positive charge pump is given by Equation 11.
IO
VO(PP) =
2fCO
where
•
•
•
IO is the output current of the positive charge pump,
CO is the output capacitance of the positive charge pump, and
f = 1.2 MHz (the switching frequency of the positive charge pump).
(11)
7.3.3.4 Positive Charge Pump Diodes
The average forward current of both diodes is equal to the positive charge pump output current. If the
recommended flying capacitance (or larger) is used, the repetitive peak forward current in D1 and D2 equal to
twice the output current.
7.3.4 Power-On Sequencing, DLY1, DLY2
The boost converter starts as soon as the input supply voltage exceeds the rising UVLO threshold. The negative
charge pump starts td(DLY1) seconds after the boost converter output voltage has reached its final value, and the
positive charge pump starts td(DLY2) seconds after the output of the negative charge pump has reached its final
value. The VCOM buffer starts up as soon as the output voltage of the positive charge pump (V(CPI)) has reached
its final value.
VI
VIT+
VIT±
V(VS)
ttd(DLY1)t
V(VGL)
See note 1
V(CPI)
ttd(DLY2)t
V(VCOM)
V(GD)
Notes
1. The fall times of V(VS), V(VGL), V(CPI) depend on their respective load currents and feedback resistances.
Figure 12. Start-Up Sequencing With CTRL = High
The delay times td(DLY1) and td(DLY2) are set by the capacitors connected to the DLY1 and DLY2 pins respectively.
Each of these pins is connected to its own 5-µA current source (I(DLY1) and I(DLY2)) that causes the voltage on the
external capacitor to ramp up linearly. The delay time is defined by how long it takes the voltage on the external
capacitor to reach the reference voltage, and is given by Equation 12.
CDLY2 Vref
CDLY1 Vref
td(DLY1) =
and td(DLY2) =
I(DLY1)
I(DLY2)
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where
•
•
•
Vref = 1.213 V (the internal reference voltage),
I(DLY1) = 5 µA (the DLY1 pin output current), and
I(DLY2) = 5 µA (the DLY2 pin output current).
(12)
7.3.5 Gate Voltage Shaping
The gate voltage shaping function can be used to reduce crosstalk between LCD pixels by reducing the gate
drivers’ input supply voltage between lines. Figure 13 shows a simplified block diagram of the gate voltage
shaping function. Gate voltage shaping is controlled by a logic-level signal applied to the CTRL pin. When CTRL
is high, Q5 and Q7 are on and Q6 is off, and the output of the positive charge pump is connected to the VGH
pin. When CTRL is low, Q5 and Q7 are off and Q6 is on. Q6 operates as a source follower and tracks the
voltage on the ADJ pin, which ramps down linearly as the current sink I(ADJ) discharges the external capacitor
CADJ (see Figure 14). The peak-to-peak voltage on the VGH pin is determined by the value of CADJ and the
duration of the low level applied to the CTRL pin, and is calculated using Equation 13.
I(ADJ) tw(CTRL)
V(VGH)(PP) =
CADJ
where
•
•
•
I(ADJ) = 200 µA (ADJ pin output current),
tw(CTRL) is the duration of the low-level signal connected to the CTRL pin, and
CADJ is the capacitance connected to the ADJ pin.
(13)
When the input supply voltage is below the UVLO threshold or the device enters a shutdown condition because
of a fault on one or more of its outputs, Q5 and Q6 turn off and the VGH pin is high impedance.
CPI
Q5
Q7
VGH
Control
Logic
I(ADJ) = 200 µA
V(VIN) > VIT
V(FBP) power good
Q6
&
CTRL
ADJ
CADJ
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Figure 13. Gate Voltage Shaping Block Diagram
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ttw(CTRL)t
CTRL
V(CPI)
V(VGH)
V(VGH)(PP)
Figure 14. Gate Voltage Shaping Timing
7.3.6 VCOM Buffer
The VCOM Buffer is a transconductance amplifier designed to drive capacitive loads. The IN pin is the input of
the VCOM buffer. The VCOM buffer features a soft-start function that reduces the current drawn from the SUP
pin when the amplifier starts up.
If the VCOM buffer is not required for certain applications, it is possible to shut down the VCOM buffer by
connecting IN to ground, reducing the overall quiescent current. The IN pin cannot be pulled dynamically to
ground during operation.
7.3.7 Protection
7.3.7.1 Boost Converter Overvoltage Protection
The boost converter features an overvoltage protection function that monitors the voltage on the SUP pin and
forces the TPS65150-Q1 device to enter fault mode if the boost converter output voltage exceeds the
overvoltage threshold.
7.3.7.2 Adjustable Fault Delay
The TPS65150-Q1 device detects a fault condition and shuts down if the boost converter output or either of the
charge pump outputs falls out of regulation for longer than the fault delay time td(FDLY). Fault conditions are
detected by comparing the voltage on the feedback pins with the internal power-good thresholds. Outputs that
fall below their power-good threshold but recover within less than td(FDLY) seconds are not detected as faults and
the device does not shut down in such cases. The output fault detection function is active during start-up, so the
device shuts down if any of its outputs fails to reach its power-good threshold during start-up. Shut-down
following an output voltage fault is a latched condition, and the input supply voltage must be cycled to recover
normal operation after it occurs.
The fault detection delay time is set by the capacitor connected between the FDLY and VIN pins and is given by
Equation 14.
td(FDLY) = R(FDLY) CFDLY
where
•
•
R(FDLY) = 450 kΩ (the internal resistance connected to the FDLY pin) and
CFDLY is the external capacitance connected to the FDLY pin.
(14)
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Fault Delay Time (s)
1
100m
10m
1m
100u
Minimum
Typical
Maximum
1n
10n
100n
Capacitance Connected to FDLY Pin (F)
1u
G000
Figure 15. Adjustable Fault Delay Time
7.3.7.3 Thermal Shutdown
A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation.
Typically, the thermal shutdown threshold is 155°C. When this threshold is reached, the device enters shutdown.
The device can be enabled again by cycling the input supply voltage.
7.3.7.4 Undervoltage Lockout
The TPS65150-Q1 device has an undervoltage lockout (UVLO) function. The UVLO function stops device
operation if the voltage on the VIN pin is less than the UVLO threshold voltage. This makes sure that the device
only operates when the supply voltage is high enough for correct operation.
7.4 Device Functional Modes
Figure 16 shows the functional modes of the TPS65150-Q1.
7.4.1 VI > VIT+
When the input supply voltage is above the undervoltage lockout threshold, the device is on and all its functions
are enabled. Note that full performance may not be available until the input supply voltage exceeds the minimum
value specified in Recommended Operating Conditions.
7.4.2 VI < VIT–
When the input supply voltage is below the undervoltage lockout threshold, the TPS65150-Q1 device is off and
all its functions are disabled.
7.4.3 Fault Mode
The TPS65150-Q1 device immediately enters fault mode when any of the following is detected:
• boost converter overvoltage
• overtemperature
The TPS65150-Q1 device also enters fault mode if any of the following conditions is detected and persists for
longer than td(FDLY):
• boost converter output out of regulation
• negative charge pump output out of regulation
• positive charge pump output out of regulation
The TPS65150-Q1 device does not function during fault mode. Cycle the input supply voltage to exit fault mode
and recover normal operation.
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Device Functional Modes (continued)
OFF
VI < VIT±
ANY
STATE
VI > VIT+
ON
Thermal shutdown
Boost converter over-voltage
Boost converter out of regulation
Negative charge pump out of regulation
Positive charge pump out of regulation
Fault condition duration
longer than td(FDLY)
FAULT
Fault condition duration
less than td(FDLY)
FAULT
DETECTION
Figure 16. Functional Modes
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65150-Q1 device has been designed to provide the input supply voltages for the source drivers and
gate drivers plus the voltage for the common plane in LCD display applications. In addition, the device provides a
gate voltage shaping function that can be used to modulate the gate drivers' positive supply to reduce image
sticking.
8.2 Typical Application
Figure 17 shows a typical application circuit for a monitor display powered from a 5-V supply. It generates up to
450 mA at 13.5 V to power the source drivers, and 20 mA at 23 V and –5 V to power the gate drivers.
L1
3.9 µH
VI
5V
C2
22 µF
D1
C15
22 pF
V(VS)
13.5 V, 450 mA
C1
22 µF
VIN
R1
820 k
SW
SUP
FB
C7
330 nF
D2
V(VGL)
±5 V, 20 mA
C3
330 nF
C14
1 µF
DRVN
R2
75 k
D3
C16
330 nF
R3
620 k
D4
DRVP
FBN
D5
C4
330 nF
R4
150 k
REF
C8
220 nF
VI
C13
100 nF
C9
2.2 nF
C10
22 pF
C11
10 nF
C12
10 nF
FLK
FBP
FDLY
R6
56 k
COMP
CPI
ADJ
DLY1
DLY2
GD
CTRL
VGH
V(VGH)
23 V, 20 mA
R7
500 k
IN
V(VS)
R8
500 k
C6
1 nF
R5
1M
VCOM
PGND
GND
V(VCOM)
C5
1 µF
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Figure 17. Monitor LCD Supply Powered from a 5-V Rail
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Typical Application (continued)
8.2.1 Design Requirements
Table 3 shows the parameters for this example.
Table 3. Design Parameters
PARAMETER
VALUE
VI
Input supply voltage
V(VS)
Boost converter output voltage and current
5V
V(VS)(PP)
Boost converter peak-to-peak output voltage ripple
V(CPI)
Positive charge pump output voltage and current
V(VGH)(PP)
Positive charge pump peak-to-peak output voltage ripple
V(VGL)
Negative charge pump output voltage and current
V(VGL)(PP)
Negative charge pump peak-to-peak output voltage ripple
td1
Negative charge pump start-up delay time
td2
Positive charge pump start-up delay time
1 ms
td(fault)
Fault delay time
45 ms
13.5 V at 450 mA
10 mV
23 V at 20 mA
100 mV
–5 V at 20 mA
100 mV
1 ms
Gate voltage shaping slope
10 V/µs
8.2.2 Detailed Design Procedure
8.2.2.1 Boost Converter Design Procedure
8.2.2.1.1 Inductor Selection
Several inductors work with the TPS65150-Q1, and with external compensation the performance can be adjusted
to the specific application requirements.
The main parameter for the inductor selection is the inductor saturation current, which must be higher than the
peak switch current as calculated in Equation 2 with additional margin to cover for heavy load transients. The
alternative, more conservative approach, is to choose the inductor with a saturation current at least as high as
the maximum switch current limit of 3.4 A.
The second important parameter is the inductor DC resistance. Usually, the lower the DC resistance the higher
the efficiency. It is important to note that the inductor DC resistance is not the only parameter determining the
efficiency. For a boost converter, where the inductor is the energy storage element, the type and material of the
inductor influences the efficiency as well. Especially at a switching frequency of 1.2 MHz, inductor core losses,
proximity effects, and skin effects become more important. Usually, an inductor with a larger form factor gives
higher efficiency. The efficiency difference between different inductors can vary from 2% to 10%. For the
TPS65150-Q1, inductor values from 3.3 µH and 6.8 µH are a good choice, but other values can be used as well.
Possible inductors are shown in Table 4. Equivalent parts can also be used.
Table 4. Inductor Selection (1)
INDUCTANCE
ISAT
DCR
MANUFACTURER
PART NUMBER
DIMENSIONS
4.7 µH
2.6 A
54 mΩ
Coilcraft
DO1813P-472HC
8.89 mm × 6.1 mm × 5 mm
4.2 µH
2.2 A
23 mΩ
Sumida
CDRH5D28-4R2
5.7 mm × 5.7 mm × 3 mm
4.7 µH
1.6 A
48 mΩ
Sumida
CDC5D23-4R7
6 mm × 6 mm × 2.5 mm
4.2 µH
1.8 A
60 mΩ
Sumida
CDRH6D12-4R2
6.5 mm × 6.5 mm × 1.5 mm
3.9 µH
2.6 A
20 mΩ
Sumida
CDRH6D28-3R9
7 mm × 7 mm × 3 mm
3.3 µH
1.9 A
50 mΩ
Sumida
CDRH6D12-3R3
6.5 mm × 6.5 mm × 1.5 mm
(1)
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The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. A simple approach is to estimate the converter
efficiency, by taking the efficiency numbers from the provided efficiency curves, or use a worst case assumption
for the expected efficiency, for example, 75%.
From Figure 19, it can be seen that the boost converter efficiency is about 85% when operating under the target
application conditions. Inserting these values into Equation 1 yields Equation 15.
:0.85;:5 V;
D=1±
= 0.69
13.5 V
(15)
and from Equation 2, the peak switch current can be calculated as Equation 16.
:0.69;:5 V;
:0.45 A;
I(SW)M =
+
= 1.8 A
2:1.2 MHz;:
H;
1 ± 0.69
(16)
The peak switch current is the peak current that the integrated switch, inductor, and rectifier diode must be able
to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest.
For the calculation of the maximum current delivered by the boost converter, it must be considered that the
positive and negative charge pumps as well as the VCOM buffer run from the output of the boost converter as
well.
8.2.2.2 Rectifier Diode Selection
The rectifier diode reverse voltage rating must be higher than the maximum output voltage of the converter
(13.5 V in this application); its average forward current rating must be higher than the maximum boost converter
output current of 450 mA, and its repetitive peak forward current must be greater than or equal to the peak
switch current of 1.8 A. Not all diode manufacturers specify repetitive peak forward current; however, a diode
with an average forward current rating of 1 A or higher is suitable for most practical applications.
From Equation 5, the power dissipated in the rectifier diode is calculated with Equation 17.
PD = IO VF = :0.45 A;:0.5 V; = 0.225 W
(17)
Table 5 lists a number of suitable rectifier diodes, any of which would be suitable for this application. Equivalent
parts can also be used.
Table 5. Rectifier Diode Selection (1)
(1)
IF(AV)
VR
VF
MANUFACTURER
PART NUMBER
2A
20 V
0.44 V at 2 A
Vishay Semiconductor
SL22
2A
20 V
0.5 V at 2 A
Fairchild Semiconductor
SS22
1A
30 V
0.44 V at 2 A
Fairchild Semiconductor
MBRS130L
1A
20 V
0.45 V at 1 A
Microsemi
UPS120
1A
20 V
0.45 V at 1 A
ON Semiconductor
MBRM120
See Third-party Products disclaimer.
8.2.2.3 Setting the Output Voltage
Rearranging Equation 3 and inserting the application parameters yields Equation 18.
13.5 V
R1
=
± 1 = 10.78
R2 1.146 V
(18)
Standard values of R1 = 820 kΩ and R2 = 75 kΩ result in a nominal output voltage of 13.68 V and satisfy the
recommendation that the value R1 be lower than 1 MΩ.
8.2.2.4 Output Capacitor Selection
For best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low
ESR value, but tantalum capacitors can be used as well, depending on the application. A 22-µF ceramic output
capacitor works for most applications. Higher capacitor values can be used to improve the load transient
regulation. See Table 6 for the selection of the output capacitor.
24
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Rearranging Equation 6 and inserting the application parameters, the minimum value of output capacitance is
given by Equation 19.
CO =
1 ± 0.69
13.5 V ± 5 V 1 ± 0.69
m1.8 A ± 0.45 A ± l
pl
pq = 20.3 F
:1.2 MHz;:10 mV;
H
1.2 MHz
(19)
The closest standard value is 22 µF. In practice, TI recommends connecting an additional 1-µF capacitor directly
to the SUP pin to ensure a clean supply to the internal circuitry that runs from this supply voltage.
8.2.2.5 Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. A 22-µF ceramic input capacitor
is sufficient for most applications. For better input voltage filtering, this value can be increased. See Table 6 for
input capacitor recommendations. Equivalent parts can also be used.
Table 6. Input and Output Capacitance Selection
CAPACITANCE
VOLTAGE RATING
MANUFACTURER
PART NUMBER
SIZE
22 µF
16 V
Taiyo Yuden
EMK325BY226MM
1206
22 µF
6.3 V
Taiyo Yuden
JMK316BJ226
1206
8.2.2.6 Compensation
From Table 2, it can be seen that the recommended values for C9 and R9 when VI = 5 V are 2.2 nF and 0 Ω
respectively, and that a feedforward zero at 11.2 kHz must be added.
Rearranging Equation 7 yields Equation 20.
1
C15 =
Œfco :R1;
(20)
Inserting fco = 11.2 kHz and R1 = 820 kΩ yields .
1
C15 =
= 17 pF
Œ:11.2 kHz;:820 k ;
In this case, a standard value of 22 pF was used.
8.2.2.7 Negative Charge Pump
8.2.2.7.1 Choosing the Output Capacitance
Rearranging Equation 9 and inserting the application parameters, the minimum recommended value of C3 is
given by Equation 21.
IO
20 mA
C3 =
=
= 83 nF
2fVO:PP; 2:1.2 MHz;:100 mV;
(21)
In this application, a capacitor of 330 nF was used to allow the same value to be used for all charge pump
capacitors.
8.2.2.7.2 Choosing the Flying Capacitance
A minimum flying capacitance of 100 nF is recommended. In this application, a capacitor of 330 nF was used to
allow the same value to be used for all charge pump capacitors.
8.2.2.7.3 Choosing the Feedback Resistors
The ratio of R3 to R4 required to generate an output voltage of –5 V is given by Equation 22.
VO
±5 V
R3 = ± F
G R4 = ± l
p R4 = :4.122;R4
V(REF)
1.213 V
(22)
Values of R3 = 620 kΩ and R4 = 150 kΩ generate a nominal output voltage of –5.014 V and load the REF pin
with only 8 µA.
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8.2.2.7.4 Choosing the Diodes
The average forward current in D2 and D3 is equal to the output current and therefore a maximum of 20 mA. The
peak repetitive forward current in D2 and D3 is equal to twice the output current and therefore less than 40 mA.
The BAT54S comprises two Schottky diodes in a small SOT-23 package and easily meets the current
requirements of this application.
8.2.2.8 Positive Charge Pump
8.2.2.8.1 Choosing the Flying Capacitance
A minimum flying capacitor of 330 nF is recommended.
8.2.2.8.2 Choosing the Output Capacitance
Rearranging Equation 10 and inserting the application parameters yields Equation 23.
:20 mA;
C4 =
= 83 nF
2:1.2 MHz;:100 mV;
(23)
In this application, a nominal value of 330 nF was used to allow the same value to be used for all charge pump
capacitors.
8.2.2.8.3 Choosing the Feedback Resistors
Rearranging Equation 8 and inserting the application parameters yields Equation 24.
R5
23 V
=
± 1 = 17.95
R6 1.214 V
(24)
Standard values of 1 MΩ and 56 kΩ result in a nominal output voltage of 22.89 V.
8.2.2.8.4 Choosing the Diodes
The average forward current in D4 and D5 is equal to the output current and therefore a maximum of 20 mA. The
peak repetitive forward current in D4 and D5 is equal to twice the output current and therefore less than 40 mA.
8.2.2.9 Gate Voltage Shaping
Rearranging Equation 13 and inserting I(ADJ) = 200 µA and slope = 10 V/µs yields Equation 25.
I:ADJ;
A
C10 =
=
= 20 pF
slope 10 V/ s
(25)
The closest standard value for C10 is 22 pF.
8.2.2.10 Power-On Sequencing
Rearranging Equation 12 and inserting td1 = td2 = 1 ms and Vref2 = 1.213 V, yields Equation 26.
: A;:2.5 ms;
C11 = C12 =
= 10.31 nF
1.213 V
(26)
10 nF is the closest standard value.
8.2.2.11 Fault Delay
Rearranging Equation 14 and inserting td(FDLY) = 45 ms yields Equation 27.
45 ms
CFDLY =
= 100 nF
450 k
(27)
100 nF is a standard value.
26
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8.2.3 Application Curves
100
100
V(VS) = 10 V
80
80
70
70
60
50
40
30
60
50
40
30
VI = 2.5 V
VI = 3.3 V
VI = 5 V
20
10
0
V(VS) = 13.5 V
90
Efficiency (%)
Efficiency (%)
90
0
100m
I(VGH) = 0 mA
200m
300m 400m 500m
Output Current (A)
600m
VI = 2.5 V
VI = 3.3 V
VI = 5 V
20
10
0
700m
0
100m
G000
I(VGL) = 0 mA
I(VGH) = 0 mA
Figure 18. Boost Converter Efficiency (V(VS) = 10 V, I(VGH) =
I(VGL) = 0 mA)
200m
300m
Output Current (A)
400m
500m
G000
I(VGL) = 0 mA
Figure 19. Boost Converter Efficiency (V(VS) = 13.5 V, I(VGH)
= I(VGL) = 0 mA)
1.155M
100
V(VS) = 13.5 V
V(VS) = 15 V
90
1.15M
70
Frequency (Hz)
Efficiency (%)
80
60
50
40
30
1.14M
1.135M
1.13M
VI = 2.5 V
VI = 3.3 V
VI = 5 V
20
10
0
1.145M
0
50m
I(VGH) = 0 mA
100m
150m
200m
Output Current (A)
250m
1.125M
300m
VI = 1.8 V
VI = 3.6 V
1.12M
−40
G000
−20
0
20
40
60
80
Free−Air Temperature (°C)
100
120
G000
I(VGL) = 0 mA
Figure 20. Boost Converter Efficiency (V(VS) = 15 V, I(VGH) =
I(VGL) = 0 mA)
V(SW)
10 V/div
Figure 21. Boost Converter Switching Frequency
V(SW)
10 V/div
V(VS)
50 mV/div
V(VS)
50 mV/div
VI = 5 V
V(VS) = 13.5 V / 10 mA
IL
1 A/div
IL
1 A/div
VI = 5 V
V(VS) = 13.5 V / 300 mA
250 ns/div
250 ns/div
Figure 22. Boost Converter Operation (Nominal Load)
Figure 23. Boost Converter Operation (Light Load)
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V(VS)
100 mV/div
VI
5 V/div
VI = 3.3 V
V(VS) = 10 V, CO = 22 µF
V(VS)
5 V/div
I(VS)
30 mA to 330 mA
VI = 5 V
V(VS) = 13.5 V
I(VS) = 200 mA
IIN
500 mA/div
100 µs/div
2.5 ms/div
Figure 24. Boost Converter Load Transient Response
Figure 25. Boost Converter Soft Start
V(VS)
5 V/div
V(VS)
5 V/div
V(VGH)
10 V/div
V(VGH)
10 V/div
V(VGL)
5 V/div
V(VGL)
5 V/div
V(VCOM)
2 V/div
VI = 5 V
V(VS) = 13.6 V / 300 mA
C(IN) = 1 nF
V(VCOM)
5 V/div
1 ms/div
2.5 ms/div
Figure 26. Power-On Sequencing
Figure 27. Power-On Sequencing With External Isolation
MOSFET
V(VS)
5 V/div
V(VGH)
10 V/div
CTRL
2 V/div
td(FDLY)
V(VGH)
10 V/div
Fault
(Heavy load on V(VS))
CADJ = 68 pF
I(VGH) = No Load
V(VGL)
5 V/div
CFDLY = 10 nF
2.5 µs/div
10 ms/div
Figure 28. Gate Voltage Shaping
28
Figure 29. Adjustable Fault Detection Time
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−4.86
25.0
V(VS) = 10 V
V(VGL) = –5 V
24.0
−4.90
−4.92
−4.94
−4.96
−4.98
TA = –40°C
TA = 25°C
TA = 85°C
−5.00
−5.02
0
20m
40m
60m
Output Current (A)
80m
23.0
22.5
22.0
21.5
TA = –40°C
TA = 25°C
TA = 85°C
20.5
20.0
100m
0
20m
G000
40m
60m
Output Current (A)
80m
100m
G000
Figure 31. Positive Charge Pump Load Regulation (×2)
80m
25.0
V(VS) = 10 V
V(VGH) = 24 V
24.5
60m
V(VCOM) − V(IN) (V)
24.0
Output Voltage (V)
23.5
21.0
Figure 30. Negative Charge Pump Load Regulation
23.5
23.0
22.5
22.0
21.5
20.5
0
20m
V(VS) = 10 V
V(VCOM) = 5 V
40m
20m
0
−20m
−40m
TA = –40°C
TA = 25°C
TA = 85°C
21.0
20.0
V(VS) = 15 V
V(VGH) = 24 V
24.5
Output Voltage (V)
Output Voltage (V)
−4.88
−60m
40m
60m
Output Current (A)
80m
100m
G000
Figure 32. Positive Charge Pump Load Regulation (×3)
−80m
−160m −120m −80m −40m
0
40m
Output Current (A)
80m
120m 160m
G000
Figure 33. VCOM Buffer Load Regulation
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8.3 System Examples
V(SW)
L1
3.9 µH
VI
2.5 V
C1
22 µF
VIN
C2
22 µF
D1
C15
47 pF
V(VS)
10 V, 280 mA
R1
430 k
SW
SUP
FB
C7
330 nF
D2
V(VGL)
±5 V, 20 mA
C3
330 nF
C14
1 µF
R2
56 k
DRVN
D3
C16
330 nF
R3
620 k
D4
DRVP
FBN
D5
R9 VI
68 k
C13
100 nF
C9
470 pF
C10
22 pF
C11
10 nF
C12
10 nF
FLK
C6
1 nF
R5
1M
FDLY
R6
56 k
COMP
CPI
ADJ
DLY1
DLY2
GD
CTRL
VGH
IN
R8
500 k
C4
330 nF
FBP
V(VGH)
23 V, 20 mA
R7
500 k
V(VS)
D7
C18
330 nF
V(SW)
REF
C8
220 nF
D6
C17
330 nF
R4
150 k
VCOM
PGND
GND
V(VCOM)
C5
1 µF
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Figure 34. Notebook LCD Supply Powered from a 2.5-V Rail
30
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System Examples (continued)
L1
3.9 µH
VI
5V
C2
22 µF
D1
C15
22 pF
V(VS)
13.5 V, 450 mA
C1
22 µF
VIN
R1
820 k
SW
SUP
FB
C7
330 nF
D2
V(VGL)
±5 V, 20 mA
C3
330 nF
C14
1 µF
DRVN
R2
75 k
D3
C16
330 nF
R3
620 k
D4
DRVP
FBN
D5
C4
330 nF
R4
150 k
REF
C8
220 nF
VI
C13
100 nF
C9
2.2 nF
C10
22 pF
C11
10 nF
C12
10 nF
FLK
FBP
FDLY
R6
56 k
COMP
CPI
ADJ
DLY1
DLY2
GD
CTRL
VGH
V(VGH)
23 V, 20 mA
R7
500 k
IN
V(VS)
R8
500 k
C6
1 nF
R5
1M
VCOM
PGND
GND
V(VCOM)
C5
1 µF
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Figure 35. Monitor LCD Supply Powered from a 5-V Rail
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System Examples (continued)
L1
3.9 µH
VI
5V
C1
22 µF
VIN
C2
22 µF
D1
C15
22 pF
C13
1 µF
V(VS)
13.5 V, 450 mA
R7
510 k
R1
820 k
SW
Q1
Si2343
C17
220 nF
SUP
FB
C7
330 nF
D2
V(VGL)
±5 V, 20 mA
C3
330 nF
C14
1 µF
DRVN
R8
100 k
R2
75 k
D3
C16
330 nF
R3
620 k
D4
DRVP
FBN
D5
C4
330 nF
R4
150 k
REF
C8
220 nF
VI
C13
100 nF
C9
2.2 nF
C10
22 pF
C11
10 nF
C12
10 nF
FLK
FBP
FDLY
R6
56 k
COMP
CPI
ADJ
DLY1
DLY2
GD
CTRL
VGH
V(VGH)
23 V, 20 mA
R7
500 k
IN
V(VS)
R8
500 k
C6
1 nF
R5
1M
VCOM
PGND
GND
V(VCOM)
C5
1 µF
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Figure 36. Typical Isolation and Short Circuit Protection Switch for V(VS) Using Q1 and Gate Drive Signal
(GD)
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9 Power Supply Recommendations
The TPS65150-Q1 device is designed to operate with input supplies from 1.8 V to 6 V. Like most integrated
circuits, the input supply must be stable and free of noise if the full performance of the device is to be achieved. If
the input is placed more than a few centimeters away from the device, additional bulk capacitance may be
required. The input capacitance shown in the application schematics in this data sheet is sufficient for typical
applications.
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step in the power supply design. An incorrect layout could cause converter
instability, load regulation problems, noise, and EMI issues. Especially with a switching DC-DC converter at high
load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding is also important. If
possible, TI recommends using a common ground plane to minimize ground shifts between analog ground
(GND) and power ground (PGND). Additionally, the following PCB design layout guidelines are recommended for
the TPS65150-Q1 device:
1. Boost converter output capacitor, input capacitor and Power ground (PGND) must form a star ground or must
be directly connected together on a common power ground plane.
2. Place the input capacitor directly from the input pin (VIN) to ground.
3. Use a bold PCB trace to connect SUP to the output Vs.
4. Place a small bypass capacitor from the SUP pin to ground.
5. Use short traces for the charge-pump drive pins (DRVN, DRVP) of VGH and VGL because these traces
carry switching currents.
6. Place the charge pump flying capacitors as close as possible to the DRVP and DRVN pin, avoiding a high
voltage spikes at these pins.
7. Place the Schottky diodes as close as possible to the device and to the flying capacitors connected to DRVP
and DRVN.
8. Carefully route the charge pump traces to avoid interference with other circuits because they carry high
voltage switching currents .
9. Place the output capacitor of the VCOM buffer as close as possible to the output pin (VCOM).
10. The thermal pad must be soldered to the PCB for correct thermal performance.
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10.2 Layout Example
VI
GND
FB
GD
DLY2
COMP
VIN
FBN
SW
REF
SW
GND
PGND
DRVN
PGND
DRVP
SUP
GND
FDLY
DLY1
CPI
VCOM
VGH
IN
ADJ
FBP
V(VGL)
V(VGH)
CTRL
V(CPI)
V(VCOM)
V(VS)
GND
Via to inner / bottom signal layer
Thermal via to copper pour on inner / bottom signal layer
Figure 37. PCB Layout Example
34
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65150QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
24
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TPS65150Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2017
OTHER QUALIFIED VERSIONS OF TPS65150-Q1 :
• Catalog: TPS65150
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65150QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65150QPWPRQ1
HTSSOP
PWP
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
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