Texas Instruments | TPS564201 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23 (Rev. B) | Datasheet | Texas Instruments TPS564201 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23 (Rev. B) Datasheet

Texas Instruments TPS564201 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23 (Rev. B) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
TPS564201 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23
1 Features
3 Description
•
The TPS564201 is a simple, easy-to-use, 4-A
synchronous step-down converter in SOT-23
package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
TPS564201 4-A Converter Integrated 50-mΩ and
22-mΩ FETs
D-CAP2™ Mode Control with Fast Transient
Response
Input Voltage Range: 4.5 V to 17 V
Output Voltage Range: 0.76 V to 7 V
Pulse Skip Mode
560-kHz Switching Frequency
Low Shutdown Current Less than 5 µA
1.6% Feedback Voltage Accuracy (25ºC)
Startup from Pre-Biased Output Voltage
Cycle-by-Cycle Overcurrent Limit
Hiccup-mode Overcurrent Protection
Non-Latch UVP and TSD Protections
Fixed Soft Start: 1.0 ms
Create a Custom Design Using the TPS564201
With the WEBENCH® Power Designer
These switch mode power supply (SMPS) devices
employ D-CAP2 mode control providing a fast
transient response and supporting both lowequivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
The TPS564201 operates in pulse skip mode,
maintaining high efficiency during light load operation.
The TPS564201 is available in a 6-pin 1.6-mm × 2.9mm SOT (DDC) package, and specified from a –40°C
to 125°C junction temperature.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
The device is optimized to operate with minimum
external component count and also optimized to
achieve low standby current.
TPS564201
Digital TV Power Supply
High Definition Blu-ray™ Disc Players
Networking Home Terminal
Digital Set Top Box (STB)
Surveillance
PACKAGE
DDC (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Simplified Schematic
TPS564201 Efficiency
CBST
100%
TPS564201
LO
CO
70%
5
SW
EN
VIN
VFB
3
VIN
80%
VBST
2
VOUT
90%
6
GND
EN
4
VOUT
RFB2 RFB1
CIN
Copyright © 2016, Texas Instruments Incorporated
Efficiency
1
60%
50%
40%
VOUT = 1.05 V
30%
VOUT = 1.5 V
20%
VOUT = 1.8 V
VOUT = 3.3 V
10%
0%
0.001
VOUT = 5 V
0.01
0.1
Output Current (A)
1
4
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Development Support ...........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2016) to Revision B
Page
•
Added WEBENCH® Designer link to Features ...................................................................................................................... 1
•
Changed VFBTH spec MIN from 739 to 745, TYP from 759 to 760, and MAX from 779 to 775.............................................. 5
•
Changed equation Equation 2 ............................................................................................................................................. 13
•
Added Custom Design With WEBENCH® Tools ................................................................................................................ 20
Changes from Original (May 2016) to Revision A
•
2
Page
Full specification release ....................................................................................................................................................... 1
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
6
VBST
SW
2
5
EN
VIN
3
4
VFB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
1
—
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
3
I
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
4
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
VBST
6
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
3
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
VBST
–0.3
25
V
VBST (10 ns transient)
–0.3
27
V
VBST (vs SW)
–0.3
6.5
V
VFB
–0.3
6.5
V
SW
–2
19
V
–3.5
21
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Input voltage
SW (10 ns transient)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
VI
Input voltage range
TJ
NOM
MAX
4.5
17
VBST
–0.1
23
VBST (10 ns transient)
–0.1
26
VBST (vs SW)
–0.1
6.0
EN
–0.1
17
VFB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Operating junction temperature
UNIT
V
V
°C
6.4 Thermal Information
TPS564201
THERMAL METRIC (1)
DDC (SOT)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
86.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.4
°C/W
RθJB
Junction-to-board thermal resistance
13.3
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
13.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
510
µA
0.9
5
µA
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 1 V
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
TPS564201
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
1.6
REN
EN pin resistance to GND
VEN = 12 V
V
0.8
V
900
kΩ
225
425
745
760
775
mV
0
±0.1
µA
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
VO = 1.05 V, continuous mode operation
IVFB
VFB input current
VFB = 0.8 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
50
mΩ
RDS(on)l
Low-side switch resistance
TA = 25°C
22
mΩ
MOSFET
CURRENT LIMIT
Current limit (1)
Iocl
DC current, VOUT = 1.05 V, L1 = 1.5 µH
4.2
6
7.7
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
172
Hysteresis
°C
38
ON-TIME TIMER CONTROL
tOFF(MIN)
Minimum off time
VFB = 0.68 V
220
280
ns
Soft-start time
Internal soft-start time
1.0
ms
Switching frequency
VIN = 12 V, VO = 1.05 V, FCCM mode
560
kHz
SOFT START
tSS
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
THICCUP_WAIT
Hiccup on time
THICCUP_RE
Hiccup time before restart
Hiccup detect (H > L)
65%
1.9
ms
15.5
ms
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage (1)
(1)
4.0
3.3
4.3
3.6
V
0.4
Not production tested.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
5
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.762
0.45
FB Voltage (V)
Buck Quiescent Curr4ent (mA)
0.50
0.40
0.761
0.760
0.35
0.30
0.759
0
±50
50
100
±50
Temperature (ƒC)
±20
10
40
70
100
Temperrature (ƒC)
C002
Figure 1. TPS56420 Supply Current vs Junction
Temperature
130
C003
Figure 2. VFB Voltage vs Junction Temperature
1.23
1.45
EN Pin UVLO-High (V)
EN Pin UVLO-Low (V)
1.20
1.17
1.14
1.11
1.08
1.42
1.39
1.36
1.33
1.05
1.02
1.30
±50
±20
10
40
70
100
130
Temperrature (ƒC)
±50
Figure 3. EN Pin UVLO Low Voltage vs Junction
Temperature
40
70
100
130
C004
Figure 4. TPS564201 EN Pin UVLO High Voltage vs Junction
Temperature
32
Low Side Rds_on (mŸ)
70
High Side Rds_on (mŸ)
10
Temperrature (ƒC)
80
60
50
40
30
20
28
24
20
16
12
±50
±30
±10
10
30
50
70
Temperrature (ƒC)
90
110
130
±50
±30
±10
10
30
50
70
Temperrature (ƒC)
C006
Figure 5. TPS564201 High-Side Rds-On vs Junction
Temperature
6
±20
C005
90
110
130
C006
Figure 6. Low-Side Rds-On vs Junction Temperature
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
580
620
VOUT = 1.05 V
600
VOUT = 3.3 V
Switching Frequency (KHz)
Switching Frequency (KHz)
VOUT = 1.8 V
VOUT = 5 V
580
560
540
520
500
4
6
8
10
12
14
16
VOUT = 5 V
380
280
180
80
0
0.001
18
Input Voltage (V)
VOUT = 3.3 V
480
1
4
C009
Figure 8. TPS564201 Switching Frequency
vs Output Current
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
Efficiency
0.1
Output Current (A)
Figure 7. TPS564201 Switching Frequency
vs Input Voltage
50%
40%
30%
50%
40%
30%
20%
10%
20%
VIN = 5 V
VIN =9 V
VIN =12 V
VIN =15 V
10%
0%
0.001
0.01
0.1
1
0%
0.001
4
Output Current (A)
L = 2.2 µH
90%
80%
80%
70%
70%
60%
60%
Efficiency
90%
30%
VIN = 15 V
0.1
1
4
C011
L = 2.2 µH
Figure 10. TPS564201 Efficiency vs Output Current
100%
40%
VIN = 9 V
VIN = 12 V
VOUT = 1.5 V
Figure 9. TPS564201 Efficiency vs Output Current
50%
VIN = 5 V
Output Current (A)
100%
50%
40%
30%
20%
10%
0%
0.001
0.01
C010
VOUT = 1.05 V
Efficiency
0.01
C008
0.01
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.1
Output Current (A)
VOUT = 1.8 V
1
20%
10%
4
0%
0.001
Figure 11. TPS564201 Efficiency vs Output Current
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.1
1
4
Output Current (A)
C012
L = 2.2 µH
0.01
VIN = 5 V
VOUT = 3.3 V
C012
L = 2.2 µH
Figure 12. TPS564201 Efficiency vs Output Current
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
7
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
20%
VIN = 9 V
10%
VIN = 12 V
VIN = 15 V
0%
0.001
0.01
0.1
1
Output Current (A)
VOUT = 5 V
4
C014
L = 3.3 µH
Figure 13. TPS564201 Efficiency vs Output Current
8
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
7 Detailed Description
7.1 Overview
The TPS564201 is a 4-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports
low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without
complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the
output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
VUVP
+
UVP
±
Hiccup
Control Logic
3
VIN
6
VBST
2
SW
1
GND
VREG5
Regulator
UVLO
VFB
4
Voltage
Reference
Ref
Soft Start
SS
PWM
±
+
+
HS
Turn-On
One Shot
XCON
VREG5
TSD
OCL
Threshold
LS
±
OCL
+
+
ZC
±
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
9
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS564201 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN,
and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference
voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode
control.
7.3.2 Pulse Skip Mode
The TPS564201 is designed with Advanced Eco-mode™ to maintain high light load efficiency. As the output
current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point
that its rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases the converter runs into discontinuous conduction mode. The ontime is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition
point to the light load operation IOUT(LL) current can be calculated in Equation 1.
(V - VOUT ) ´ VOUT
1
IOUT(LL) =
´ IN
2 ´ L ´ ¦ SW
VIN
(1)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS564201 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converter ramps up smoothly into regulation point.
10
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
Feature Description (continued)
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-starts after the hiccup time (typically 15.5 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS564201 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS564201 operates at a quasi-fixed frequency of 560
kHz.
7.4.2 Eco-mode™ Operation
When the TPS564201 is in the normal CCM operating mode and the switch current falls to 0A, the TPS564201
begins operating in pulse skipping eco-mode. Each switching cycle is followed by a period of energy saving sleep
time. The sleep time ends when the VFB voltage falls below the eco-mode threshold voltage. As the output
current decreases, the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS564201 is operating in either normal CCM or Eco-mode™, it may be placed in standby by
asserting the EN pin low.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
11
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with
a maximum available output current of 4 A. The following design procedure can be used to select component
values for the TPS564201. Alternately, the WEBENCH® software may be used to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic in Figure 14 shows the TPS564201 4.5-V to 17-V input, 1.05-V output converter
design meeting the requirements for 4-A output. This circuit is available as the evaluation module (EVM). The
sections provide the design procedure.
C7 0.1 F
TPS564201
1
L1
VOUT = 1.05 V / 4A
2
VOUT
GND
VBST
SW
EN
VIN
VFB
6
R3 10 k
5
EN
2.2 H
C9
22 F
C8
22 F
3
4
VOUT
R1 3.09 k
R2
10 k
1
C1
10 F
C2
10 F
C3
0.1 F
Not Installed
C4
1
VIN
VIN = 4.5 V to 17 V
1
Copyright © 2016, Texas Instruments Incorporated
Figure 14. TPS564201 1.05-V, 4-A Reference Design
12
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 17 V
Output voltage
1.05 V
Transient response, 2-A load step
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
4A
Operating frequency
560 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS564201 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of
resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will
be more noticeable.
R1 ö
æ
VOUT = 0.760 ´ ç 1 +
R2 ÷ø
è
(2)
8.2.2.3 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
2S LOUT u COUT
(3)
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
13
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
C8 + C9 (µF)
1
3.09
10.0
1.5
2.2
4.7
20 to 68
1.05
3.74
10.0
1.5
2.2
4.7
20 to 68
1.2
5.76
10.0
1.5
2.2
4.7
20 to 68
1.5
9.53
10.0
1.5
2.2
4.7
20 to 68
1.8
13.7
10.0
1.5
2.2
4.7
20 to 68
2.5
22.6
10.0
2.2
2.2
4.7
20 to 68
3.3
33.2
10.0
2.2
2.2
4.7
20 to 68
5
54.9
10.0
3.3
3.3
4.7
20 to 68
6.5
75
10.0
3.3
3.3
4.7
20 to 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 560 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 7.
VIN(MAX) VOUT
VOUT
IlP P
u
VIN(MAX)
LO u fSW
(4)
IlPEAK
ILO(RMS)
IO
IlP P
2
IO2
(5)
1
IlP
12
2
P
(6)
For this design example, the calculated peak current is 4.4 A and the calculated RMS current is 4 A. The
inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS564201 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7
to determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.4 Input Capacitor Selection
The TPS564201 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
14
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
8.2.2.5 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
15
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
3.00%
3.00%
2.00%
2.00%
Output Voltage (V)
Output Voltage (V)
8.2.3 Application Curves
1.00%
0.00%
-1.00%
-2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-3.00%
0
1
2
3
4
Output Current (A)
0
1
VIN = 5 V
2
3
4
Output Current (A)
C016
VOUT = 1.05 V
VIN = 12 V
Figure 15. Load Regulation, VIN = 5 V
C015
VOUT = 1.05 V
Figure 16. Load Regulation, VIN = 12 V
1.062
100%
90%
80%
70%
1.060
Efficiency
Output Voltage (V)
1.061
1.059
60%
50%
40%
30%
1.058
20%
10%
1.057
VIN = 5 V
VIN =9 V
VIN =12 V
VIN =15 V
0%
4
6
8
10
12
14
16
Input Voltage (V)
18
0.001
0.01
0.1
1
Output Current (A)
C017
4
C010
VOUT = 1.05 V
Figure 17. Line Regulation
Figure 18. Efficiency vs Output Current
VOUT = 100 mV/div
VIN = 100 mV/div
LX = 5 V/div
LX = 5 V/div
IOUT = 2 A/div
IOUT = 500 mA/div
1 µs/div
1 µs/div
Figure 19. TPS564201 Input Voltage Ripple
16
Figure 20. TPS564201 Output Voltage Ripple, No Load
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
VOUT = 20 mV/div
VOUT = 20 mV/div
LX = 5 V/div
LX = 5 V/div
IOUT = 2 A/div
IOUT = 5 A/div
1 µs/div
1 µs/div
Figure 21. TPS564201 Output Voltage Ripple, IOUT 2 A
Figure 22. TPS564201 Output Voltage Ripple, IOUT 4 A
VOUT = 10 mV/div
VOUT = 25 mV/div
IOUT = 1 A/div
IOUT = 1 A/div
100 µs/div
100 µs/div
Figure 23. TPS564201 Transient Response 0.1 to 2 A
Figure 24. TPS564201 Transient Response, 1 to 3 A
VOUT = 20 mV/div
VEN = 5 V/div
VIN = 5 V/div
IOUT = 2 A/div
VOUT = 500 mV/div
100 µs/div
2 ms/div
Figure 25. TPS564201 Transient Response, 2 to 4 A
Figure 26. TPS564201 Startup Relative to VIN
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
17
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
VOUT = 500 mV/div
400 µs/div
Figure 27. TPS564201 Startup Relative to EN
Figure 28. TPS564201 Shutdown Relative to VIN
VIN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
Figure 29. TPS564201 Shutdown Relative to EN
9 Power Supply Recommendations
The TPS564201 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO / 0.75.
18
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
GND
Output
Capacitor
Vias to the
Internal SW
Node Copper
Additional
Vias to the
GND Plane
BOOST
CAPACITOR
Output
Inductor
GND
SW
Vias to the
Internal SW
Node Copper
Input Bypass
Capacitor
VIN
VIN
VBST
EN
To Enable
Control
Feedback
Resistors
VFB
SW Node Copper
Pour Area on
Internal
or Bottom Layer
Figure 30. TPS564201 Layout Example
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
19
TPS564201
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
www.ti.com
11 Device and Documentation Support
11.1 Development Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS564201 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
TPS564201
www.ti.com
SLVSDJ7B – MAY 2016 – REVISED AUGUST 2017
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS564201
21
PACKAGE OPTION ADDENDUM
www.ti.com
25-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS564201DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
4201
TPS564201DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
4201
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-May-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS564201DDCR
SOT23-THIN
DDC
6
3000
180.0
9.5
TPS564201DDCT
SOT23-THIN
DDC
6
250
180.0
9.5
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.17
3.1
1.1
4.0
8.0
Q3
3.17
3.1
1.1
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS564201DDCR
SOT-23-THIN
DDC
6
3000
184.0
184.0
19.0
TPS564201DDCT
SOT-23-THIN
DDC
6
250
184.0
184.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
SCALE 4.000
SOT
3.05
2.55
1.75
1.45
PIN 1
INDEX AREA
1.1 MAX
B
1
0.1 C
A
6
4X 0.95
3.05
2.75
1.9
4
3
0.5
0.3
0.2
0.1
TYP
0.0
6X
0 -8 TYP
0.20
TYP
0.12
C A B
C
SEATING PLANE
0.6
TYP
0.3
0.25
GAGE PLANE
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising