Texas Instruments | CSD19502Q5B 80 V N-Channel NexFET™ Power MOSFET (Rev. B) | Datasheet | Texas Instruments CSD19502Q5B 80 V N-Channel NexFET™ Power MOSFET (Rev. B) Datasheet

Texas Instruments CSD19502Q5B 80 V N-Channel NexFET™ Power MOSFET (Rev. B) Datasheet
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CSD19502Q5B
SLPS413B – DECEMBER 2013 – REVISED MAY 2017
CSD19502Q5B 80 V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Logic Level
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
TA = 25°C
UNIT
Drain-to-Source Voltage
80
V
Qg
Gate Charge Total (10 V)
48
nC
Qgd
Gate Charge Gate to Drain
8.6
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
nC
VGS = 6 V
3.8
mΩ
VGS = 10 V
3.4
mΩ
2.7
V
.
Ordering Information(1)
2 Applications
•
•
TYPICAL VALUE
VDS
Secondary Side Synchronous Rectifier
Motor Control
Device
Media
Qty
Package
Ship
CSD19502Q5B
13-Inch Reel
2500
CSD19502Q5BT
13-Inch Reel
250
SON 5 x 6 mm
Plastic Package
Tape and
Reel
3 Description
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
This 3.4 mΩ, 80 V, SON 5 mm × 6 mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
TA = 25°C
Top View
S
8
1
Absolute Maximum Ratings
VALUE
UNIT
VDS
Drain-to-Source Voltage
80
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
100
Continuous Drain Current (Silicon limited),
TC = 25°C
157
D
ID
S
7
2
(1)
Continuous Drain Current
17
Pulsed Drain Current(2)
400
Power Dissipation(1)
3.1
Power Dissipation, TC = 25°C
195
TJ,
Tstg
Operating Junction and
Storage Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 74 A, L = 0.1 mH, RG = 25 Ω
274
mJ
D
IDM
S
6
3
D
PD
D
G
5
4
D
P0093-01
SPACE
A
W
(1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB.
(2) Max RθJC = 0.8°C/W, pulse duration ≤100 µs, duty cycle ≤1%
SPACE
RDS(on) vs VGS
Gate Charge
20
10
TC = 25°C, I D = 19A
TC = 125°C, I D = 19A
18
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
A
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 19A
VDS = 40V
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
40
45
50
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19502Q5B
SLPS413B – DECEMBER 2013 – REVISED MAY 2017
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Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
6.2
6.3
6.4
6.5
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q5B Package Dimensions ........................................ 8
Recommended PCB Pattern..................................... 9
Recommended Stencil Pattern ................................. 9
Q5B Tape and Reel Information ............................. 10
4 Revision History
Changes from Revision A (June 2014) to Revision B
Page
•
Added the Receiving Notification of Documentation Updates and Community Resources sections to Device and
Documentation Support. ........................................................................................................................................................ 7
•
Changed the dimension between pads 3 and 4 from 0.028 inches: to 0.050 inches in the Recommended PCB
Pattern section diagram ......................................................................................................................................................... 9
Changes from Original (December 2013) to Revision A
Page
•
Added small reel option to ordering information table. .......................................................................................................... 1
•
Increased silicon limit for continuous drain current to 157 A. ................................................................................................ 1
•
Increased max pulsed current to 400 A. ............................................................................................................................... 1
•
Added max power rating when the case temperature is held to 25°C. ................................................................................. 1
•
Updated pulsed current conditions to specify duty cycle ≤ 1%, pulse duration ≤ 100 µs, and Max RθJC = 0.8ºC/W. ........... 1
•
Updated Figure 10. ................................................................................................................................................................ 6
•
Updated mechanical drawing. ............................................................................................................................................... 8
2
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5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = 64 V
1
μA
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-Source On Resistance
gfs
Transconductance
80
2.2
V
2.7
3.3
V
VGS = 6 V, ID = 19 A
3.8
4.8
mΩ
VGS = 10 V, ID = 19 A
3.4
4.1
mΩ
VDS = 8 V, ID = 19 A
88
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Series Gate Resistance
Qg
Gate Charge Total (10 V)
48
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0 V, VDS = 40 V, ƒ = 1 MHz
VDS = 40 V, ID = 19 A
VDS = 40 V, VGS = 0 V
VDS = 40 V, VGS = 10 V,
IDS = 19 A, RG = 0 Ω
3750
4870
pF
925
1202
pF
17
22
pF
1.2
2.4
Ω
62
nC
8.6
nC
14
nC
10
nC
130
nC
8
ns
6
ns
22
ns
7
ns
DIODE CHARACTERISTICS
VSD
Diode Forward Voltage
ISD = 19 A, VGS = 0 V
0.8
1
V
Qrr
Reverse Recovery Charge
nC
Reverse Recovery Time
VDS= 40 V, IF = 19 A,
di/dt = 300 A/μs
275
trr
72
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
RθJC
Junction-to-Case Thermal Resistance (1)
RθJA
Junction-to-Ambient Thermal Resistance
(1)
(2)
MIN
TYP
MAX
0.8
(1) (2)
50
UNIT
°C/W
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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CSD19502Q5B
SLPS413B – DECEMBER 2013 – REVISED MAY 2017
GATE
www.ti.com
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Source
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
200
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
(TA = 25°C unless otherwise stated)
160
140
120
100
80
60
VGS = 10V
VGS = 8V
VGS = 6V
40
20
0
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
1
VDS = 5V
0
0.5
Figure 2. Saturation Characteristics
5.5
6
G001
ID = 19A
VDS = 40V
9
8
7
6
5
4
3
1000
100
10
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
40
45
1
50
0
10
20
30
40
50
60
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
70
80
G001
Figure 5. Capacitance
3.3
20
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
5
10000
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
1.5 2 2.5 3 3.5 4 4.5
VGS - Gate-to-Source Voltage (V)
Figure 3. Transfer Characteristics
10
0
1
G001
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs Temperature
175
TC = 25°C, I D = 19A
TC = 125°C, I D = 19A
18
16
14
12
10
8
6
4
2
0
0
2
G001
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
2
100
VGS = 6V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
ID =19A
−25
25
75
125
TC - Case Temperature (ºC)
175
0.0001
0
Figure 8. Normalized On-State Resistance vs Temperature
G001
Figure 9. Typical Diode Forward Voltage
10us
100us
1ms
10ms
DC
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1
100
10000
1000
100
10
1
Single Pulse Width
Max RthetaJC = 0.8ºC/W
0.1
0.1
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS413B – DECEMBER 2013 – REVISED MAY 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD19502Q5B
SLPS413B – DECEMBER 2013 – REVISED MAY 2017
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q5B Package Dimensions
K
H
D3
6
D1
4
5
e
6
4
3
3
5
D2
7
2
E
2
7
•
1
8
1
8
L
b (8x)
c1
E1
d1
Top View
d2
Bottom View
Side View
•
Front View
DIM
MILLIMETERS
MIN
NOM
MAX
A
0.80
1.00
1.05
b
0.36
0.41
0.46
c
0.15
0.20
0.25
c1
0.15
0.20
0.25
c2
0.20
0.25
0.30
D1
4.90
5.00
5.10
D2
4.12
4.22
4.32
D3
3.90
4.00
4.10
d
0.20
0.25
0.30
d1
0.085 TYP
d2
0.319
0.369
0.419
E
4.90
5.00
5.10
E1
5.90
6.00
6.10
E2
3.48
3.58
3.68
e
H
0.36
0.46
0.56
L
0.46
0.56
0.66
L1
0.57
0.67
0.77
θ
0°
—
—
K
8
1.27 TYP
1.40 TYP
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SLPS413B – DECEMBER 2013 – REVISED MAY 2017
7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Pattern
(0.020)
0.508
x4
(0.011)
0.286
(0.014)
0.350
(0.022)
0.562 x 4
(0.029)
0.746 x 8
2.186 (0.086)
4.318 (0.170)
0.300
(0.012)
1.270 (0.050)
(0.030)
0.766
(0.051)
1.294
x8
(0.060)
1.525
1.270 (0.050)
(0.042)
1.072
(0.259)
6.586
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SLPS413B – DECEMBER 2013 – REVISED MAY 2017
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K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
7.4 Q5B Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.
10
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PACKAGE OPTION ADDENDUM
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19-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD19502Q5B
ACTIVE
VSON-CLIP
DNK
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD19502
CSD19502Q5BT
ACTIVE
VSON-CLIP
DNK
8
250
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD19502
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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19-May-2017
Addendum-Page 2
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