Texas Instruments | TPS6218x 4-V to 15-V, 6-A, 2-Phase Step-Down Converters with AEE (Rev. B) | Datasheet | Texas Instruments TPS6218x 4-V to 15-V, 6-A, 2-Phase Step-Down Converters with AEE (Rev. B) Datasheet

Texas Instruments TPS6218x 4-V to 15-V, 6-A, 2-Phase Step-Down Converters with AEE (Rev. B) Datasheet
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TPS62180, TPS62182
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TPS6218x 4-V to 15-V, 6-A, 2-Phase Step-Down Converters with AEE™
1 Features
3 Description
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The TPS6218x is a synchronous dual-phase stepdown DC-DC converter for low profile power rails. It
operates with two identical, current balanced phases
that are peak current controlled enabling use in
height limited applications.
1
•
Dual Phase Balanced Peak Current Mode
Input Voltage Range: 4 V to 15 V
Output Voltage Range: 0.9 V to 6 V
Output Current up to 6 A
Typical Quiescent Current of 28 µA
Output Voltage Accuracy of ±1% (PWM Mode)
Automatic Efficiency Enhancement (AEE™)
Phase Shifted Operation
Automatic Power Save Mode
Adjustable Soft Start
Power Good Output
Undervoltage Lockout
HICCUP Over Current Protection
Pin-to-Pin Compatible with TPS62184
Over Temperature Protection
NanoFree™ 2.10 mm x 3.10 mm DSBGA
Package
Create a Custom Design Using the TPS62180
With the WEBENCH® Power Designer
2 Applications
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Low Profile POL Supply
NVDC Powered Systems
Dual/Triple Cell Li-ion Battery
Ultra Portable/Embedded/Tablet PC
Computing Network Solutions
Micro Server, SSD
With a wide operating input voltage range of 4 V to
15 V, the device is ideally suited for systems powered
from multi-cell Li-Ion batteries or 12-V rails. The
output current of 6 A is continuously provided by two
phases of 3 A each, allowing the use of low profile
external components. The phases operate out of
phase, reducing switching noise significantly.
The TPS6218x automatically enters Power Save
Mode to maintain high efficiency down to very light
loads. It also incorporates an Automatic Efficiency
Enhancement (AEE™) for the entire duty cycle range.
The device features a Power Good signal, as well as
an adjustable soft start. The quiescent current is
typically 28 µA, it is able to run in 100% mode, and it
has no duty cycle limitation even at lowest output
voltage.
The TPS6218x, available in adjustable and fixed
output voltage options, is packaged in a small 24bump, 0.5 mm pitch DSBGA package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS62180
DSBGA (24)
2.10 mm x 3.10 mm
TPS62182
DSBGA (24)
2.10 mm x 3.10 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
spacing
Simplified Schematic
Efficiency vs Output Current
space
22µF
1µH
4 to 15 V
VIN1
SW1
VIN2
SW2
3.3V/6A
1µH
VO
22µF
470k
TPS62182
PG
EN
2x
47µF
FB
SS/TR
GND
3.3nF
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62180, TPS62182
SLVSBB8B – AUGUST 2014 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
9.3 TPS62180 Output Voltage Application Examples... 28
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2014) to Revision B
Page
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Added Feature: Pin-to-Pin Compatible with TPS62184 ......................................................................................................... 1
•
Added WEBENCH® information to Features, Detailed Design Procedures, and Development Support sections................. 1
•
Changed the BODY SIZE value From: 2.14 mm x 3.14 mm To: 2.10 mm x 3.10 mm in the Device Information table ........ 1
•
Added SW1, SW2, (AC, less than 10ns) and Note (3) to the Pin voltage range in the Absolute Maximum Ratings table ... 4
•
Changed Handling Ratings To: ESD Ratings table................................................................................................................ 4
•
Added Table 1 ....................................................................................................................................................................... 9
•
Added the application note .................................................................................................................................................. 14
•
Changed the Design Requirements paragraph .................................................................................................................... 14
•
Added Note (2) to Table 6 ................................................................................................................................................... 17
•
Added Figure 31 and Figure 32............................................................................................................................................ 21
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Added Figure 37 .................................................................................................................................................................. 22
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Changed the Design Requirements paragraph .................................................................................................................... 24
•
Added Figure 38 and Figure 39 to the Inductor section ....................................................................................................... 24
•
Changed Figure 55 .............................................................................................................................................................. 31
Changes from Original (August 2014) to Revision A
•
2
Page
Released to Production ......................................................................................................................................................... 1
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5 Device Comparison Table
PART NUMBER
OUTPUT VOLTAGE
TJ
TPS62180
Adjustable
-40°C to 125°C
TPS62182
3.3 V
-40°C to 125°C
Spacer
6 Pin Configuration and Functions
24-Pin DSBGA
YZF Package
(Top View - Left, Bottom View - Right)
1
2
3
4
F
E
D
C
B
A
A
B
C
D
E
F
Pin Functions
PIN (1)
DESCRIPTION
NAME
NUMBER
AGND
C4
Analog Ground. Connect on PCB directly with PGND.
EN
E4
Enable input (High = enabled, Low = disabled)
FB
B4
Output voltage feedback. Connect resistive voltage divider to this pin and AGND. On TPS62182,
connect to AGND.
PG
F4
Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain
(requires pull-up resistor)
PGND
A3, B3, C3, D3,
E3, F3
SS/TR
D4
Common power ground.
Soft-Start and Tracking Pin. An external capacitor connected to this pin sets the internal voltage
reference rise time.
SW1
A2, B2, C2
Switch node for Phase 1 (master), connected to the internal MOSFET switches. Connect inductor 1
between SW1 and output capacitor.
SW2
D2, E2, F2
Switch node for Phase 2 (follower), connected to the internal MOSFET switches. Connect inductor 2
between SW2 and output capacitor.
VIN1
A1, B1, C1
Supply voltage for Phase 1.
VIN2
D1, E1, F1
Supply voltage for Phase 2.
A4
Output Voltage Connection
VO
(1)
For more information about connecting pins, see Detailed Description and Application Information sections.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Pin voltage range (2)
MIN
MAX
UNIT
VIN1, VIN2
–0.3
17
V
EN, PG
–0.3
VIN + 0.3
V
SW1, SW2, (DC)
–0.3
VIN + 0.3
–2
24.5
SS/TR
–0.3
VIN + 0.3,
but ≤ 7
V
FB, VO
–0.3
7
V
10
mA
SW1, SW2, (AC, less than 10ns) (3)
V
Power good sink
current
PG
Operating junction
temperature range
TJ
–40
150
°C
Storage Temperature
Range
Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground pin.
While switching.
7.2 ESD Ratings
VESD (1)
(1)
(2)
MIN
MAX
Human Body Model (HBM) ESD stress voltage (2)
–1
1
Charge device model (CDM) ESD stress voltage
–0.5
0.5
UNIT
kV
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Supply voltage range, VIN
Output voltage range, VOUT
Maximum Output current,
IOUT(max)
0.9V ≤ VOUT ≤ 3.3V
TYP
MAX
UNIT
4
15
V
0.9
6
V
6
3.3V < VOUT
A
6
Operating junction temperature, TJ
–40
125
°C
7.4 Thermal Information
TPS6218x
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
YZF (24 PINS)
UNIT
61.5
°C/W
Junction-to-case (top) thermal resistance
0.3
°C/W
Junction-to-board thermal resistance
10.1
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
10.1
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +125°C) and VIN = 4 V to 15 V.
Typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
4
IQ
Operating quiescent current
EN = High, IOUT = 0 mA, Device not switching,
(TJ = –40°C to +85°C)
ISD
Shutdown current
EN = Low (≤ 0.3 V), (TJ = –40°C to +85°C)
VUVLO
TSD
Undervoltage lockout threshold
(1)
Thermal shutdown
Falling input voltage
3.5
15
V
28
55
µA
2.8
15
µA
3.6
3.7
Hysteresis
300
Rising junction temperature
160
Hysteresis
V
mV
°C
20
CONTROL (EN, SS/TR, PG)
VH_EN
High-level input threshold voltage (EN)
VL_EN
Low-level input threshold voltage (EN)
ILKG_EN
Input leakage current (EN)
ISS/TR
SS/TR pin source current
VTH_PG
Power good threshold voltage
VOL_PG
Power good output low voltage
ILKG_PG
Input leakage current (PG)
0.97
0.87
EN = VIN or GND
1
1.03
V
0.9
0.93
V
0.01
1.2
µA
µA
4.5
5
5.5
Rising (%VOUT)
94%
96%
98%
Falling (%VOUT)
90%
92%
94%
0.3
V
1
100
nA
27
65
mΩ
21
45
mΩ
4.7
5.5
IPG= -2 mA
POWER SWITCH
Phase 1
High-side MOSFET ON-resistance
RDS(ON)
VIN = 7.5 V
Low-side MOSFET ON-resistance
Phase 2
Phase 1
Phase 2
ILIM
High-side MOSFET current limit
Each phase, VIN = 7.5 V
TPSD
Phase shift delay time
Phase 2 after Phase 1, PWM mode
4.0
250
A
ns
OUTPUT
VREF
Internal reference voltage
ILKG_FB
Input leakage current (FB)
VFB = 0.8 V
0.792
RDISCHARGE
Output discharge resistance
EN = Low
Output voltage range (TPS62180)
VIN ≥ VOUT
V
100
nA
60
Ω
6
3.3
PWM Mode, VIN ≥ VOUT + 1 V
1%
–1%
2%
Power Save Mode, VOUT = 0.9 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)
–1%
3%
PWM Mode, VIN ≥ VOUT + 1 V
–1%
1%
Power Save Mode, Iload ≥ 1 mA, L = 1 µH,
COUT = 2 x 47 µF, (TJ = –40°C to +85°C)
–1%
2%
Power Save Mode, VOUT = 1.8 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)
VOUT
Output voltage accuracy
(TPS62182) (2)
V
V
–1%
Power Save Mode, VOUT = 3.3 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 2 x 47 µF, (TJ = –40°C to +85°C)
Feedback voltage accuracy
(TPS62180) (2)
(1)
(2)
0.808
1
0.9
Output voltage (TPS62182)
tHICCUP
0.8
Load regulation
VOUT = 3.3 V, PWM Mode operation
0.04
%/A
Line regulation
4 V ≤ VIN ≤ 15 V, VOUT = 3.3 V, IOUT = 4 A
0.01
%/V
Hiccup on time
0.9
Hiccup off time
5
ms
The minimum VIN value of 4 V is not violated by UVLO threshold and hysteresis variations.
The accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.
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7.6 Typical Characteristics
6
Figure 1. Quiescent Current
Figure 2. Shutdown Current
Figure 3. High-Side Switch Resistance
Figure 4. Low-Side Switch Resistance
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8 Detailed Description
8.1 Overview
The TPS6218x is a high efficiency synchronous switched mode step-down converter based on a peak current
control topology. It is designed for smallest solution size low-profile applications, converting multi-cell Li-Ion
supply voltages to output voltages of 0.9 V to 6 V. While an outer voltage loop sets the regulation threshold for
the current loop based on the actual VOUT level, the inner current loop adapts the peak inductor current for every
switching cycle. The regulation network is internally compensated. The switching frequency is set by an OFFtime control and features Power Save Mode (PSM) and AEE™ (Automatic Efficiency Enhancement) to keep the
efficiency high over the whole load current and duty cycle range. The switching frequency is set depending on
VIN and VOUT and remains unchanged for steady state operating conditions.
The TPS6218x is a dual phase converter, sharing the load current among the phases. Identical in construction,
the follower control loop is connected with a fixed delay to the master control loop. Both the phases use the
same regulation threshold and cycle-by-cycle peak current setpoint. This ensures a phase-shifted as well as
current-balanced operation. Using the advantages of the dual phase topology, a 6-A continuous output current is
provided with high performance and smallest system solution size.
While the TPS62180 offers an adjustable output voltage, the TPS62182 supports a fixed 3.3-V output voltage,
saving external components.
8.2 Functional Block Diagram
Thermal
Shutdown
PG
VIN1
VIN2
1
3
3
Power Save
Mode
PG control
VIN1
HS1
EN*
1
power
control
control logic
SS/TR
VIN
SW2
1
FB
HS2
HICCUP
follower
VO
3
HS2
phase shift
UVLO
SW1
VIN2
gate
drive
1
3
tf
1
gmout
delay
60
gm
VREF
master
EN
VIN
AEETM
tm
off-timer
HS1
VIN
7
GND
*Pin is connected to a pull down resistor internally
(see Feature Description section)
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Figure 5. TPS62180 (Adjustable output voltage)
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Functional Block Diagram (continued)
Thermal
Shutdown
PG
VIN1
VIN2
1
3
3
Power Save
Mode
PG control
VIN1
HS1
EN*
1
SS/TR
phase shift
VIN
VREF
gmout
delay
60
master
VIN
AEETM
1
FB*
VO
tf
1
EN
SW2
HS2
HICCUP
follower
VO
3
HS2
1
UVLO
SW1
VIN2
gate
drive
power
control
control logic
3
gm
tm
off-timer
R1
R2
HS1
VIN
7
GND
*Pin is connected to a pull down resistor internally
(see Feature Description section)
Copyright © 2017, Texas Instruments Incorporated
Figure 6. TPS62182 (Fixed output voltage)
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
The device starts operation, when VIN is present and Enable (EN) is set High. The EN threshold is 1 V for rising
and 0.9 V for falling voltages, providing a threshold accuracy of ±3%. That makes it suitable for precise switching
on and off in accurate power sequencing arrangements as well as for slowly rising EN control voltage signals
(see Using the Accurate EN Threshold for more details).
The device is disabled by pulling EN Low. A discharge resistor of about 60 Ω is then connected to the output. At
the EN pin, an internal pull down resistor of about 350 kΩ keeps the Low state, if EN gets high impedance or
floating afterwards.
The EN pin can be connected to VIN to always enable the device. A delay of 1 ms, after VIN exceeds VUVLO,
ensures safe operating conditions before the device starts switching. If VIN is already present, a soft start
sequence is initiated about 100 µs after EN is pulled High.
8.3.2 Soft Start / Tracking (SS/TR)
The soft start circuit controls the output voltage slope during startup. This avoids excessive inrush current and
ensures a controlled output voltage rise time. It also prevents unwanted voltage drop from high impedance power
sources or batteries. When EN is set to start device operation, the device starts switching and VOUT rises with a
slope, controlled by the external capacitor connected to the SS/TR pin. There is no theoretical limit for the
longest startup time. It is not recommended to leave the SS/TR pin floating, because VOUT may overshoot.
Typical startup operation is shown in Application Performance Curves.
8
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Feature Description (continued)
The device can track an external voltage (see Tracking). The device can monotonically start into a pre-biased
output.
8.3.3 Power Good (PG)
The TPS6218x has a built in power good (PG) function. The PG pin goes High, when the output voltage has
reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low. The
PG pin is an open drain output that requires a pull-up resistor and can sink typically 2 mA. If not used, the PG pin
can be left floating or grounded.
space
Table 1. Power Good Pin Logic Table
PG Logic Status
Device Information
Enable (EN=High)
High Z
VFB ≥ VTH_PG
Low
√
VFB ≤ VTH_PG
√
√
Shutdown (EN=Low)
UVLO
0.7V < VIN < VUVLO
Thermal Shutdown
TJ > TSD
Power Supply Removal
VIN < 0.7V
√
√
√
space
8.3.4 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) prevents misoperation of the device, if the input voltage drops below the UVLO
threshold. It is set to 3.6 V typically with a hysteresis of typically 300mV. (See also Device Functional Modes).
8.3.5 Thermal Shutdown
The junction temperature TJ of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. Both the power FETs are turned
off, the discharge resistor is connected to the output and the PG pin goes Low. Once TJ has decreased enough,
the device resumes normal operation with Soft Start.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPS6218x is based on a predictive OFF-time peak current control topology, operating with PWM in
continuous conduction mode for heavier loads. Since the OFF-time is automatically adjusted according to the
actual VIN and VOUT, it provides highest efficiency over the entire input and output voltage range. The OFF-time is
calculated as:
spacing
é V
ù
tOFF = ê IN 500ns ú + 50ns
ë 5VOUT
û
(1)
spacing
While the OFF-time is predicted, the ON-time is set depending on the converter's duty cycle and calculated as:
spacing
t ON =
t OFF × VOUT
V IN - VOUT
(2)
spacing
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Device Functional Modes (continued)
Thereby the switching frequency is fixed for a given input and output voltage and is calculated as:
spacing
f SW =
1- D
1
=
tOFF
tOFF
æ VOUT
çç1 VIN
è
ö
÷÷
ø
(3)
spacing
Both the master and follower phases regulate to the same level of VOUT with separate current loops, using the
same peak current setpoint, cycle by cycle. This provides excellent peak current balancing, independent of
inductor dc resistance matching. Since the follower phase operates with a fixed delay to the master phase, also
cycle by cycle, phase shifted operation is obtained.
The device features an automatic transition into Power Save Mode, entered at light loads, running in
discontinuous conduction mode (DCM).
8.4.2 Power Save Mode (PSM) Operation
As the load current decreases, the converter enters Power Save Mode operation. During PSM, the converter
operates with a reduced switching frequency maintaining highest efficiency due to minimum quiescent current.
Power Save Mode is based on a fixed peak current architecture, where the peak current (IPEAK) is set depending
on VIN, VOUT, and L. After each single pulse, a pause time until the internal VOUT_Low level threshold is reached
completes the switching cycle in PSM.
The switching frequency for PSM in one phase operation is calculated as :
spacing
f PSM =
2 I OUT × VOUT (VIN - VOUT )
2
L × I PEAK
× VIN
(4)
spacing
Equation 4 shows the linear relationship of output current and switching frequency. Typical values of the fixed
peak current are shown in Figure 7.
space
Figure 7. Typical Fixed Peak Current (IPEAK) in Power Save Mode
space
If the load decreases to very light loads and only one phase is needed, either phase (master or follower) might
be active. The load current level at which Power Save Mode is entered is calculated as follows:
spacing
10
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Device Functional Modes (continued)
I load ( PSM ) = DI L
(5)
spacing
Equation 7 is used to calculate ΔIL.
8.4.3 Minimum Duty Cycle and 100% Mode Operation
When the input voltage comes close to the output voltage, the device enters 100% mode and both high-side
FETs are continuously switched on as long as VOUT remains below its setpoint. The minimum VIN to maintain
output voltage regulation is calculated as:
spacing
éR
ù
VIN (min) = VOUT (min) + I OUT ê DS (ON ) + DCRL1 // DCRL 2 ú
ë 2
û
(6)
spacing
This allows the conversion of small input to output voltage differences, for example for the longest operation time
in battery powered applications. In 100% duty cycle mode, the low-side FET is switched off.
While the maximum ON-time is not limited, the AEE feature, explained in the next section, secures a minimum
ON-time of about 100 ns.
8.4.4 Automatic Efficiency Enhancement (AEE™)
AEE™ provides highest efficiency over the entire input voltage and output voltage range by automatically
adjusting the converter's switching frequency. This is achieved by setting the predictive off-time of the converter.
The efficiency of a switched mode converter is determined by the power losses during the conversion. The
efficiency decreases, if VOUT decreases and/or VIN increases. In order to keep the efficiency high over the entire
duty cycle range (VOUT/VIN ratio), the switching frequency is adjusted while maintaining the ripple current. The
following equation shows the relation between the inductor ripple current, switching frequency and duty cycle.
spacing
æ 1- D
DI L = VOUT × çç
è L × f SW
ö
÷÷ = VOUT
ø
æ VOUT
ç1VIN
×ç
ç L × f SW
ç
è
ö
÷
÷
÷
÷
ø
(7)
spacing
Efficiency increases by decreasing switching losses, preserving high efficiency for varying duty cycles, while the
ripple current amplitude remains low enough to deliver the full output current without reaching current limit. The
AEE™ feature provides an efficiency enhancement for various duty cycles, especially for lower Vout values,
where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates
for the very small duty cycles of high VIN to low VOUT conversion, which limits the control range in other
topologies.
Figure 8 shows the typical switching frequency over the input voltage range.
space
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Device Functional Modes (continued)
Figure 8. Typical Switching Frequency vs Input Voltage
space
8.4.5 Phase-Shifted Operation
While, for a buck converter, the input current source provides the average current that is needed to support the
output current, an input capacitance is needed to support pulse currents. One of the natural benefits of a two- (or
multi-) phase converter is the possibility to operate out of phase, which decreases the pulse currents and
switching noise. In PWM mode, the TPS6218x devices run with a fixed delay of typically 250 ns between the
phases. This ensures that the phases run phase-delayed, limiting input RMS current and corresponding noise. If
in PSM, both phases run, the phase delay is about 100 ns.
8.4.6 Current Limit, Current Balancing, and Short Circuit Protection
Each phase has a separate integrated peak current limit. While its minimum value limits the output current of the
phase, the maximum number gives the current that must be considered to flow in any operating case. If the
current limit of a phase is reached, the peak current setpoint is unable to increase further. The device provides its
maximum output current. Detecting this heavy load or short circuit condition for about 0.9 ms, the device
switches off for about 5 ms and then restarts again with a soft start cycle. As long as the overload condition is
present, the device hiccups that way, limiting the output power.
The two phases are peak current balanced with a variation within about ±10% at 6-A output current (see
Figure 9). Since the control topology does not depend on inductor or output current measurements, the current
balancing accuracy is independent of inductor matching (binning) and does not need matched power routing.
space
12
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Device Functional Modes (continued)
Figure 9. Typical Current Balancing vs Load Current
space
8.4.7 Tracking
VOUT can track a voltage that is applied at the SS/TR pin. The tracking range at the SS/TR pin is 50 mV to 1.2 V
and the FB pin voltage tracks this as given in Equation 8:
spacing
VFB » 0.64 × VSS / TR
(8)
spacing
Due to the factor of about 0.64, the minimum output voltage for tracking is 1.25 V. Once the SS/TR pin voltage
reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage and the device goes to
normal regulation. This works for falling tracking voltage as well. If, in this case, the SS/TR voltage decreases,
the device does not sink current from the output. Thus, the resulting decrease of the output voltage may be
slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3 V.
Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a
wider tolerance than specified.
8.4.8 Operation with Fixed VOUT
The TPS62182 provides a fixed output voltage of 3.3 V (±1%). In this case, the feedback divider is integrated
and the FB pin is internally connected to GND with a resistor of about 350 kΩ. It is recommended to connect the
FB pin to PCB ground to improve thermal behavior.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS62180/2 are switched mode step-down converters, able to convert a 4-V to 15-V input voltage into a
lower 0.9-V to 6-V output voltage, providing up to 6 A. It needs a minimum amount of external components. Apart
from the LC output filter and the input capacitors only an optional pull-up resistor for Power Good (PG) and a
small capacitor for adjustable soft start are used. The TPS62180 with an adjustable output voltage needs an
additional resistive divider to set the output voltage level.
9.2 Typical Applications
9.2.1 Typical TPS62180 Application
C1
L1
VIN1
4 to 15 V
VOUT/6A
SW1
L2
VIN2
SW2
VO
C2
470k
TPS62180
C3
PG
EN
FB
SS/TR
GND
C5
C4
R1
VFB
R2
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Figure 10. Typical 4-V to 15-V Input, 6A Converter
spacing
9.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. The component selection is given in Table 2 and gives a total solution size of about 99 mm2 with a
maximum height of 2.1 mm:
spacing
Table 2. Components Used for Application Characteristics
REFERENCE NAME
DESCRIPTION / VALUE
MANUFACTURER
TPS62180YZF
2 phase step down converter, 2 x 3 mm WCSP
Texas Instruments
L1, L2
Inductor XFL4020-102ME, 1 µH ±20%, 4 x 4 x 2.1 mm
Coilcraft
C1, C2
Ceramic capacitor GRM21BR61E226ME44, 2 x 22 µF, 25 V, X5R, 0805
muRata
C3, C4
Ceramic capacitor GRM21BR60J476ME15, 2 x 47 µF, 6.3 V, X5R, 0805
muRata
C5
Ceramic capacitor, 3.3 nF
Standard
R1
Chip resistor, value depending on VOUT
Standard
R2
Chip resistor, value depending on VOUT
Standard
R3
Chip resistor, 470 kΩ, 0603, 1/16 W, 1%
Standard
14
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62180 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Programming the Output Voltage
The output voltage of the TPS62180 is programmed using an external resistive divider. While the voltage at the
FB pin is regulated to 0.8 V, the output voltage range is specified from 0.9 up to 6 V. The value of the output
voltage is set by selection of the resistive divider (from VOUT to FB to AGND) from Equation 9.
spacing
R1 VOUT
=
-1
R2 VFB
(9)
spacing
The current through those resistors contributes to the light load efficiency, which makes larger resistor values
beneficial. However, to get sufficient noise immunity these values should not be oversized. Using this, the
resistor values are calculated by converting Equation 9 as follows:
spacing
R2 =
VFB 0.8V
=
= 160kW
I FB 5mA
(10)
spacing
Inserting the R2 value in Equation 11, R1 can be obtained.
spacing
æV
ö
R1 = R2 × çç OUT - 1÷÷
è VFB
ø
(11)
spacing
Calculating for VOUT = 3.3 V gives R1 = 500 kΩ. Using standard resistor values R1 = 470 kΩ and R2 = 150 kΩ are
chosen.
For applications requiring lowest current consumption, the use of fixed output voltage options is recommended.
Using the TPS62182, the FB pin can be left floating, but it is recommended to connect it to AGND which
decreases thermal resistance.
In case the FB pin of the adjustable output voltage version gets opened or an over voltage appears at the output,
an internal clamp limits the output voltage to about 7.4 V.
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9.2.1.2.3 Output Filter Selection
Since the TPS6218x is compensated internally, it is optimized for a range of external component values, which is
specified below. Table 3 and Table 4 are used to simplify the output filter component selection. Checked cells
represent combinations that are proven for stability by simulation and lab test. Further combinations should be
checked for each individual application.
Table 3. Recommended LC Output Filter Combinations for VOUT ≥ 1.8 V (1)
2 x 47 µF
4 x 47 µF
6 x 47 µF
8 x 47 µF
√
√
√
√
0.47 µH
1.0 µH
1.5 µH
(1)
The values in the table are the nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and
–60%.
Table 4. Recommended LC Output Filter Combinations for VOUT < 1.8 V (1)
2 x 47 µF
4 x 47 µF
6 x 47 µF
√
√
8 x 47 µF
0.68 µH
1.0 µH
1.5 µH
(1)
The values in the table are nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and –40%.
For the output capacitors, a voltage rating of 6.3 V and an X5R dielectric are chosen. If space allows for higher
voltage rated capacitors in larger case sizes, the dc bias effect is lowered and the effective capacitance value
increases.
9.2.1.2.4 Inductor Selection
The TPS6218x is designed to work with two inductors of 1 µH nominal. They have to be selected for adequate
saturation current and a low dc resistance (DCR). The minimum inductor current rating IL(min) that is needed
under static load conditions is calculated using Equation 12 and Equation 13. A current imbalance of 10% at
most is incorporated.
spacing
I peak (max) = I L (min) =
1.1× I OUT (max)
2
+
DI L (max)
2
(12)
spacing
spacing
DI L (max)
V
æ
ç 1 - OUT
VIN (max)
= VOUT × ç
ç L(min) × f SW
ç
è
ö
÷
÷
÷
÷
ø
(13)
spacing
This calculation gives the minimum saturation current of the inductor needed and an additional margin of about
20% is recommended to cover dynamic overshoot due to load transients. For low profile solutions, the physical
inductor size and the power losses have to be traded off. Smallest solution size (for example with chip inductors)
are less efficient than bigger inductors with lower losses due to lower DCR and/or core losses. The following
inductors have been tested with the TPS6218x:
16
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Table 5. List of Inductors
TYPE
INDUCTANCE
[µH]
CURRENT RATING
MIN/TYP [A] (1)
DCR MAX
[mΩ]
DIMENSIONS (LxBxH) [mm]
MANUFACTURER
DFE201612E-1R0M
1 ±20%
4.0/4.4
48
2.0 x 1.6 x 1.2
TOKO
TOKO
DFE252012F-1R0M
1 ±20%
4.7/5.3
40
2.5 x 2.0 x 1.2
DFE252012P-1R0M
1 ±20%
3.8/4.5
42
2.5 x 2.0 x 1.2
TOKO
PIFE32251B-1R0MS
1 ±20%
4.2/4.7
42
3.2 x 2.5 x 1.2
CYNTEC
PIME031B-1R0MS
1 ±20%
4.5/5.4
55
3.7 x 3.3 x 1.2
CYNTEC
PISB25201T-1R0MS
1 ±20%
3.6/3.9
62
2.5 x 2.0 x 1.0
CYNTEC
IHLP1212AB-11
1 ±20%
/5.0
37.5
3.6 x 3.0 x 1.2
VISHAY
(1)
IHLP1212AE-11
1 ±20%
/5.3
33
3.6 x 3.0 x 1.5
VISHAY
XFL4015-122ME_
1.2±20%
/4.5
20.7
4.0 x 4.0 x 1.5
COILCRAFT
XFL4020-102ME_
1 ±20%
/5.4
11.9
4.0 x 4.0 x 2.1
COILCRAFT
TFM201610-GHM
1 ±20%
3.6/3.8
60
2.0 x 1.6 x 1.0
TDK
TFM252010-GHM
1 ±20%
3.5/4.0
56
2.5 x 2.0 x 1.0
TDK
ISAT at 30% drop of inductance (ΔIL/IL).
The TPS6218x is not designed to operate with only one inductor.
9.2.1.2.5 Output Capacitor Selection
The TPS6218x provides a wide output voltage range of 0.9 V to 6 V. While stability is a critical criteria for the
output filter selection, the output capacitor value also determines transient response behavior, ripple and
accuracy of VOUT. Table 6 gives recommendations to achieve various transient design targets using 1-µH
inductors and small sized output capacitors (see Table 2).
Table 6. Recommended Output Capacitor Values
OUTPUT
VOLTAGE [V]
0.9 (2)
1.8
3.3
(1)
(2)
(3)
LOAD STEP [A]
(NOMINAL) CAPACITOR VALUE (1)
2-6-2 (3)
2-6-2
2-6-2
(3)
(3)
TYPICAL TRANSIENT RESPONSE ACCURACY
±mV
±%
4 x 47 µF
90
10
6 x 47 µF
70
8
2 x 47 µF
150
8
4 x 47 µF
120
7
8 x 47 µF
90
5
2 x 47 µF
170
5
4 x 47 µF
135
4
8 x 47 µF
100
3
Ceramic capacitors have a dc bias effect where the effective capacitance differs significantly from the nominal value, depending on
package size, voltage rating and dielectric material.
For output voltages < 1.8V an additional feedforward capacitor of 82pF, parallel to R1 is recommended to increase stability margin at
heavy load steps.
The transient load step is tested with 1-µs/step rising/falling slopes.
spacing
The architecture of the TPS6218x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to
use X7R or X5R dielectrics. Using even higher values than demanded for stability and transient response has
further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.
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9.2.1.2.6 Input Capacitor Selection
The input current of a buck converter is pulsating. Therefore, a low ESR input capacitor is required to prevent
large voltage transients and provide peak currents. The recommended value for most applications is 2 x 22 µF,
split between the VIN1 and VIN2 inputs and placed as close as possible to these pins and PGND pins. If
additional capacitance is needed, it can be added as bulk capacitance. To ensure proper operation, the effective
capacitance at the VIN pins must not fall below 2 x 2 µF (close) + 10 µF bulk (effective capacitances).
Low ESR multilayer ceramic capacitors are recommended for best filtering. Increasing with input voltage, the dc
bias effect reduces the nominal capacitance value significantly. To decrease input ripple current further, larger
values of input capacitors can be used.
9.2.1.2.7 Soft Start Capacitor Selection
The TPS6218x provides a user programmable soft start time. A constant current source of 5 µA, internally
connected to the SS/TR pin, allows control of the startup slope by connecting a capacitor to this pin. The current
source charges the capacitor and the soft start time is given by:
spacing
CSS = t SS ×
5mA
1.25V
(14)
spacing
where CSS is the soft-start capacitance required at the SS/TR pin and tss is the resulting soft-start ramp time.
spacing
The SS/TR pin should not be left floating and a minimum capacitance of 220 pF is recommended. Using
Equation 14, and inserting tSS = 750 µs, a value of 3 nF is calculated. 3.3 nF is chosen as a standard value for
this example.
18
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9.2.1.3 Application Performance Curves
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
VOUT = 6 V
VOUT = 6 V
Figure 11. Efficiency vs Load Current
VOUT = 3.3 V
Figure 12. Efficiency vs Input Voltage
VOUT = 3.3 V
Figure 13. Efficiency vs Load Current
VOUT = 1.8 V
Figure 14. Efficiency vs Input Voltage
VOUT = 1.8 V
Figure 15. Efficiency vs Load Current
Figure 16. Efficiency vs Input Voltage
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VOUT = 0.9 V
20
VOUT = 0.9 V
Figure 17. Efficiency vs Load Current
Figure 18. Efficiency vs Input Voltage
Figure 19. Output Voltage vs Output Current (Load
regulation)
Figure 20. Output Voltage vs Input Voltage (Line
regulation)
Figure 21. Maximum Output Current vs Input Voltage
Figure 22. Switching Frequency vs Output Current
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Figure 23. Startup into 33 Ω (100 mA)
Figure 24. Startup into 1 Ω (3.3 A)
Figure 25. Startup into 0.5 Ω (6.6 A)
Figure 26. Output Discharge (No load)
IOUT = 3 A
IOUT = 100 mA
Figure 27. Typical Operation (PWM)
Figure 28. Typical Operation (PSM)
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Figure 29. Load Transient Response (PSM-PWM)
VOUT = 1.8 V
COUT = 6x47 µF
VOUT = 1.8 V
Figure 31. Transient Response to a load step of 1-6A
(1A/µs)
RLOAD = 0.33 Ω
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COUT = 6x47 µF
additional CFF = 82
pF
Figure 32. Transient Response to a load step of 1-6A
(1A/µs)
RLOAD = 0.33 Ω
Figure 33. HICCUP at Overload Condition
22
Figure 30. Load Transient Response (PWM-PWM)
Figure 34. HICCUP at Overload Condition
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Figure 35. HICCUP at Short Circuit
Figure 36. HICCUP at Short Circuit
Figure 37. Maximum Ambient Temperature
space
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9.2.2 TPS62180 Low Profile Solution
This design example is based on Figure 10 again, providing a very small (see Figure 38) and low profile solution,
using low profile inductors.
9.2.2.1 Design Requirements
The input parameters used for this design are given in Table 7 and give a total solution size of about 72mm2,
using inductors with a maximum height of 1.2 mm:
space
Table 7. Components Used for Application Characteristics
REFERENCE NAME
DESCRIPTION / VALUE
MANUFACTURER
TPS62180YZF
2 phase step down converter, 2 x 3 mm WCSP
Texas Instruments
L1, L2
Inductor DFE252012P, 1 µH ±20%, 2.5 x 2 x 1.2 mm
Toko
CIN
Ceramic capacitor GRM21BR61E226ME44, 2 x 22 µF, 25 V, X5R, 0805
muRata
COUT
Ceramic capacitor GRM21BR60J476ME15, 2 x 47 µF, 6.3 V, X5R, 0805
muRata
CSS
Ceramic capacitor, 10 nF
Standard
R1
Chip resistor, value depending on VOUT
Standard
R2
Chip resistor, value depending on VOUT
Standard
R3
Chip resistor, 470 kΩ, 0603, 1/16 W, 1%
Standard
space
9.2.2.2 Detailed Design Procedure
As opposed to the previous example, the solution size, including height, is limited and the soft start time is
longer. This is achieved by using smaller inductors, as well as using a different soft start capacitor.
9.2.2.2.1 Inductor
Using Table 5, the 1-µH DFE252012P is chosen with dimensions of 2.5 x 2.0 x 1.2 mm. The larger DCR of 42
mΩ maximum causes some efficiency drop (see comparison below).
space
Figure 38. Ultra Small Solution Size
Figure 39. Efficiency vs Inductor Size/Type
space
24
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9.2.2.2.2 Input and Output Capacitors
Since electrical design parameters are unchanged, the same values as chosen in the previous example are used
for these capacitors.
9.2.2.2.3 Soft Start Capacitor
Using Equation 14 again, and inserting tSS = 2.5 ms gives a capacitance of 10 nF, which is chosen.
9.2.2.2.4 Using the Accurate EN Threshold
The TPS6218x provides a very accurate EN threshold voltage. This can be used to switch on the device
according to a VIN or another voltage level by using a resistive divider as shown below.
space
VIN
VIN
REN1
EN
REN2
Figure 40. Resistive Divider for Controlled EN Threshold
space
The values of REN1 and REN2, needed to set EN = High at a specific VIN can be calculated according to
Kirchhoff's laws, shown in Equation 15 and used in the following example:
space
VIN = VEN _ threshold ×
REN 1 + REN 2
REN 2
(15)
space
For a typical 8-V input rail, the device turn on target value is set to 5.5 V. The current through the resistive divider
is set to 10 µA, which indicates a total resistance of about 800 kΩ. Appropriate standard resistor values, fitting
Equation 15, are REN1 = 680 kΩ and REN2 = 150 kΩ. As a result, the device switches on, when VIN has reached
5.5 V and the current through the divider is 9.6 µA. The device switches off at a threshold of 0.9 V. Using
Equation 15 again, this case gives a level of VIN = 5.0 V.
Figure 47 to Figure 50 show thresholds and appropriate device behavior with a startup time of about 800 µs.
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9.2.2.3 Application Performance Curves
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
Figure 41. Efficiency vs Load Current
VIN = 8 V, IOUT = 4 A
26
Figure 42. Efficiency vs Input Voltage
CSS = 10 nF
Figure 43. Typical Operation (PWM)
Figure 44. Startup into 1 Ω (3.3 A)
Figure 45. Load Transient Response (PSM-PWM)
Figure 46. Load Transient Response (PWM-PWM)
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VIN = 5.5 V (Rising), VIN = 5.0 V (Falling)
Figure 47. Accurate EN Threshold
VIN = 5.5 V (Rising)
Figure 48. Accurate EN Threshold Showing VOUT
VIN = 5.0 V (Falling)
Figure 49. Accurate EN Threshold
Figure 50. Accurate EN Threshold
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9.3 TPS62180 Output Voltage Application Examples
This section provides typical schematics for commonly used output voltage values.
9.3.1 Application Schematic Examples
space
22µF
1µH
VIN1
4 to 15 V
SW1
0.9V/6A
1µH
VIN2
SW2
VO
22µF
470k
TPS62180
PG
EN
20k
FB
SS/TR
GND
3.3nF
4x
47µF
160k
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Figure 51. 0.9-V/6-A Power Supply
space
22µF
1µH
VIN1
4 to 15 V
SW1
1.8V/6A
1µH
VIN2
SW2
VO
22µF
470k
TPS62180
PG
EN
2x
47µF
FB
SS/TR
3.3nF
200k
GND
160k
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Figure 52. 1.8-V/6-A Power Supply
space
28
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Product Folder Links: TPS62180 TPS62182
TPS62180, TPS62182
www.ti.com
SLVSBB8B – AUGUST 2014 – REVISED MAY 2017
TPS62180 Output Voltage Application Examples (continued)
22µF
1µH
VIN1
4 to 15 V
SW1
3.3V/6A
1µH
VIN2
SW2
VO
22µF
470k
TPS62180
PG
EN
470k
2x
47µF
FB
SS/TR
GND
3.3nF
150k
Copyright © 2017, Texas Instruments Incorporated
Figure 53. 3.3-V/6-A Power Supply
space
22µF
1µH
VIN1
(4) to 15 V
SW1
5V/6A
1µH
VIN2
SW2
VO
22µF
470k
TPS62180
PG
EN
430k
FB
SS/TR
GND
3.3nF
4x
47µF
82k
Copyright © 2017, Texas Instruments Incorporated
Figure 54. 5-V/6-A Power Supply
9.3.2 Design Requirements
Based on Figure 10, the schematics shown in Figure 51 through Figure 54 show different output voltage divider
values to get different VOUT. Another design target is to have about 5-µA current through the divider.
9.3.3 External Component Selection
The values for the voltage divider are derived using the procedure given in Programming the Output Voltage.
While Equation 10 and Equation 11 are used to calculate R2 and R1, the values are aligned with standard
resistor values.
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS62180 TPS62182
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TPS62180, TPS62182
SLVSBB8B – AUGUST 2014 – REVISED MAY 2017
www.ti.com
10 Power Supply Recommendations
The TPS6218x are designed to operate from a 4-V to 15-V input voltage supply. The input power supply's output
current needs to be rated according to the output voltage and the output current of the power rail application.
30
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Product Folder Links: TPS62180 TPS62182
TPS62180, TPS62182
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SLVSBB8B – AUGUST 2014 – REVISED MAY 2017
11 Layout
11.1 Layout Guidelines
The PCB layout of the TPS6218x demands careful attention to ensure proper operation, thermal profile, low
noise emission and to achieve best performance. A poor layout can lead to issues like poor regulation, stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity. While the TPS6218x provides very high
power density, the PCB layout also contributes significantly to the thermal performance.
11.1.1 PCB Layout
A recommended PCB layout for the TPS62180 dual phase solution is shown below. It ensures best electrical and
optimized thermal performance considering the following important topics:
• The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides
low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN
connection, to avoid interference between the input lines.
• The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can
be designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal
behavior.
• The VOUT regulation loop is closed with COUT and its ground connection. If a ground layer or plane is used, a
direct connection by vias, as shown, is recommended. Otherwise the connection of COUT to GND must be
short for good load regulation.
• The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB pin,
avoiding long trace distance. Using the TPS62182 (fixed output voltage version), the FB pin can be left
floating, but it is good practice and recommended to connect it to AGND for best thermal characteristics.
11.2 Layout Example
space
L1
VOUT
C3
VIN
C1
C2
R1
C5 R2
GND
C4
VOUT
L2
Figure 55. TPS62180 Board Layout
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS62180 TPS62182
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TPS62180, TPS62182
SLVSBB8B – AUGUST 2014 – REVISED MAY 2017
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62180
Click here
Click here
Click here
Click here
Click here
TPS62182
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
AEE, NanoFree are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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Product Folder Links: TPS62180 TPS62182
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS62180YZFR
ACTIVE
DSBGA
YZF
24
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
ELC180
TPS62180YZFT
ACTIVE
DSBGA
YZF
24
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
ELC180
TPS62182YZFR
ACTIVE
DSBGA
YZF
24
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
ELC182
TPS62182YZFT
ACTIVE
DSBGA
YZF
24
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
ELC182
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS62180YZFR
DSBGA
YZF
24
3000
330.0
12.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.25
3.25
0.81
4.0
12.0
Q1
TPS62180YZFT
DSBGA
YZF
24
250
330.0
12.4
2.25
3.25
0.81
4.0
12.0
Q1
TPS62182YZFR
DSBGA
YZF
24
3000
330.0
12.4
2.25
3.25
0.81
4.0
12.0
Q1
TPS62182YZFT
DSBGA
YZF
24
250
330.0
12.4
2.25
3.25
0.81
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62180YZFR
DSBGA
YZF
24
3000
367.0
367.0
35.0
TPS62180YZFT
DSBGA
YZF
24
250
367.0
367.0
35.0
TPS62182YZFR
DSBGA
YZF
24
3000
367.0
367.0
35.0
TPS62182YZFT
DSBGA
YZF
24
250
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0024
DSBGA - 0.625 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.35
0.15
BALL TYP
0.05 C
1.5 TYP
SYMM
F
E
D
2.5
TYP
SYMM
D: Max = 3.13 mm, Min = 3.07 mm
C
E: Max = 2.13 mm, Min = 2.07 mm
0.5
TYP
B
A
1
24X
0.015
0.35
0.25
C A B
2
4
3
0.5 TYP
4219412/A 01/2019
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
24X ( 0.245)
2
1
3
4
A
(0.5) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:28X
0.05 MAX
( 0.245)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
0.05 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.245)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219412/A 01/2019
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
24X ( 0.25)
1
2
3
4
A
(0.5)
TYP
B
METAL
TYP
C
SYMM
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219412/A 01/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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