Texas Instruments | CSD19538Q3A 100-V N-Channel NexFET™ Power MOSFET (Rev. A) | Datasheet | Texas Instruments CSD19538Q3A 100-V N-Channel NexFET™ Power MOSFET (Rev. A) Datasheet

Texas Instruments CSD19538Q3A 100-V N-Channel NexFET™ Power MOSFET (Rev. A) Datasheet
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CSD19538Q3A
SLPS583A – MAY 2016 – REVISED MARCH 2017
CSD19538Q3A 100-V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low-Thermal Resistance
Avalanche Rated
Lead Free
RoHS Compliant
Halogen Free
SON 3.3-mm × 3.3-mm Plastic Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
100
V
Qg
Gate Charge Total (10 V)
4.3
nC
Qgd
Gate Charge Gate to Drain
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
This 100-V, 49-mΩ, SON 3.3-mm × 3.3-mm
NexFET™ power MOSFET is designed to minimize
conduction losses and reduce board footprint in PoE
applications.
49
mΩ
3.2
V
DEVICE
MEDIA
QTY
PACKAGE
SHIP
13-Inch Reel
3000
CSD19538Q3AT
7-Inch Reel
250
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
100
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package Limited)
15
Continuous Drain Current (Silicon Limited),
TC = 25°C
14
Continuous Drain Current(1)
4.9
ID
8
1
7
2
D
IDM
D
PD
6
3
D
D
G
VGS = 10 V
CSD19538Q3A
Top View
S
58
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
S
nC
VGS = 6 V
Device Information(1)
Power Over Ethernet (PoE)
Power Sourcing Equipment (PSE)
Motor Control
S
0.8
RDS(on)
2 Applications
•
•
•
UNIT
VDS
5
4
Pulsed Drain Current(2)
37
Power Dissipation(1)
2.8
Power Dissipation, TC = 25°C
23
TJ,
Tstg
Operating Junction Temperature,
Storage Temperature
EAS
Avalanche Energy, Single Pulse
ID = 12.7 A, L = 0.1 mH, RG = 25 Ω
D
P0093-01
A
A
W
–55 to 150
°C
8.1
mJ
(1) Typical RθJA = 45°C/W on a 1-in2, 2-oz Cu pad on a 0.06 in
thick FR4 PCB.
(2) Max RθJC = 5.5°C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
RDS(on) vs VGS
Gate Charge
10
TC = 25qC, ID = 5 A
TC = 125qC, ID = 5 A
180
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
200
160
140
120
100
80
60
40
20
0
ID = 5 A
9 VDS = 50 V
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
0
0.5
1
1.5
2
2.5
3
3.5
Qg - Gate Charge (nC)
4
4.5
5
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19538Q3A
SLPS583A – MAY 2016 – REVISED MARCH 2017
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Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
6.2
6.3
6.4
6.5
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q3A Package Dimensions ........................................ 8
Q3A Recommended PCB Pattern ............................ 9
Q3A Recommended Stencil Pattern ......................... 9
Q3A Tape and Reel Information ............................. 10
4 Revision History
Changes from Original (May 2016) to Revision A
Page
•
Changed the test voltage VDS in Gate Charge curve from 100 V : to 50 V............................................................................ 1
•
Changed the test voltage VDS in Figure 4 from 100 V : to 50 V ............................................................................................. 5
•
Added Receiving Notification of Documentation Updates section to Device and Documentation Support section............... 7
2
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 80 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
V
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
100
2.8
V
3.2
3.8
VGS = 6 V, ID = 5 A
58
72
VGS = 10 V, ID = 5 A
49
59
VDS = 10 V, ID = 5 A
6.1
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (10 V)
4.3
nC
Qgd
Gate charge gate-to-drain
0.8
nC
Qgs
Gate charge gate-to-source
1.6
nC
Qg(th)
Gate charge at Vth
1
nC
Qoss
Output charge
12.3
nC
td(on)
Turnon delay time
5
ns
tr
Rise time
3
ns
td(off)
Turnoff delay time
7
ns
tf
Fall time
2
ns
VGS = 0 V, VDS = 50 V, ƒ = 1 MHz
VDS = 50 V, ID = 5 A
VDS = 50 V, VGS = 0 V
VDS = 50 V, VGS = 10 V,
IDS = 5 A, RG = 0 Ω
349
454
pF
69
90
pF
12.6
16.4
pF
4.6
9.2
Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
ISD = 5 A, VGS = 0 V
0.85
1
V
Qrr
Reverse recovery charge
nC
Reverse recovery time
VDS= 50 V, IF = 5 A,
di/dt = 300 A/μs
94
trr
32
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance (1)
THERMAL METRIC
5.5
°C/W
RθJA
Junction-to-ambient thermal resistance (1) (2)
55
°C/W
(1)
(2)
MIN
TYP
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
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GATE
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GATE
Source
Source
Max RθJA = 195°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 55°C/W
when mounted on 1-in2
(6.45-cm2) of 2-oz
(0.071-mm) thick Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
30
30
27
27
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C (unless otherwise stated)
24
21
18
15
12
9
6
VGS = 6 V
VGS = 8 V
VGS = 10 V
3
TC = 125° C
TC = 25° C
TC = -55° C
24
21
18
15
12
9
6
3
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
VDS - Drain-to-Source Voltage (V)
4.5
5
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
D002
6
7
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
9
8
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
10
2
1
1
0
0
0.5
1
ID = 5 A
1.5
2
2.5
3
3.5
Qg - Gate Charge (nC)
4
4.5
0
5
10
20
D004
100
D005
Figure 5. Capacitance
200
RDS(on) - On-State Resistance (m:)
3.8
VGS(th) - Threshold Voltage (V)
90
VDS = 50 V
Figure 4. Gate Charge
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
-75
30
40
50
60
70
80
VDS - Drain-to-Source Voltage (V)
TC = 25qC, ID = 5 A
TC = 125qC, ID = 5 A
180
160
140
120
100
80
60
40
20
0
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
0
2
D006
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
2
VGS = 6 V
VGS = 10 V
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
-75
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
175
0
0.2
D008
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
1.2
D009
ID = 5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
100
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
0.1
0.01
0.1
DC
10 ms
1 ms
100 µs
10 µs
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
TC = 25q C
TC = 125q C
10
1
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single pulse, max RθJC = 5.5°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
18
15
12
9
6
3
0
-50
-25
0
25
50
75
100 125
TC - Case Temperature (qC)
150
175
D012
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS583A – MAY 2016 – REVISED MARCH 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
8
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SLPS583A – MAY 2016 – REVISED MARCH 2017
7.2 Q3A Recommended PCB Pattern
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Q3A Recommended Stencil Pattern
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1.75 ±0.10
7.4 Q3A Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF-reflow compatible.
10
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PACKAGE OPTION ADDENDUM
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12-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD19538Q3A
ACTIVE
VSONP
DNH
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
19538
CSD19538Q3AT
ACTIVE
VSONP
DNH
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
19538
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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12-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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