Texas Instruments | CSD95378BQ5MC Synchronous Buck NexFET™ Smart Power Stage (Rev. C) | Datasheet | Texas Instruments CSD95378BQ5MC Synchronous Buck NexFET™ Smart Power Stage (Rev. C) Datasheet

Texas Instruments CSD95378BQ5MC Synchronous Buck NexFET™ Smart Power Stage (Rev. C) Datasheet
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CSD95378BQ5MC
SLPS463C – APRIL 2014 – REVISED MARCH 2017
CSD95378BQ5MC Synchronous Buck NexFET™ Smart Power Stage
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
60-A Continuous Operating Current Capability
93.4% System Efficiency at 30 A
Low-Power Loss of 2.8 W at 30 A
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Mode With FCCM
Temperature Compensated Bidirectional Current
Sense
Analog Temperature Output (400 mV at 0°C)
Fault Monitoring
– High-Side Short, Overcurrent, and
Overtemperature Protection
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Diode
Optimized Dead Time for Shoot-Through
Protection
High-Density SON 5-mm × 6-mm Footprint
Ultra-Low-Inductance Package
System-Optimized PCB Footprint
DualCool™ Packaging
RoHS Compliant – Lead-Free Terminal Plating
Halogen-Free
Multiphase Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty-Cycle Applications
POL DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR11.x / VR12.x V-core and
Memory Synchronous Converters
•
•
•
3 Description
The CSD95378BQ5MC NexFET™ smart power
stage is a highly-optimized design for use in a highpower, high-density synchronous buck converter.
This product integrates the driver IC and power
MOSFETs to complete the power stage switching
function. This combination produces high-current,
high-efficiency, and high-speed switching capability in
a small 5-mm × 6-mm outline package. It also
integrates the accurate current sensing and
temperature sensing functionality to simplify system
design and improve accuracy. In addition, the PCB
footprint is optimized to help reduce design time and
simplify the completion of the overall system design.
Device Information(1)
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD95378BQ5MC
13-Inch Reel
2500
CSD95378BQ5MCT
7-Inch Reel
250
SON
5.00-mm × 6.00-mm
DualCool Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
Typical Power Stage Efficiency and Power Loss
VIN
100
14
90
12
80
10
VCC
VCC
VOUT
60
30
+Is2
-Is2
PWM2
RT
6
4
2
40
TSEN
SS
8
VDD = 5V
VIN = 12V
VOUT = 1.2V
LOUT = .225µH
fSW = 500kHz
TA = 25ºC
50
PWM1
+Is1
-Is2
VOUT
70
Power Loss (W)
VOUT
Efficiency (%)
CSD95378B
0
10
20
30
40
Output Current (A)
50
60
0
G001
PGND
Multiphase
Controller
CSD95378B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD95378BQ5MC
SLPS463C – APRIL 2014 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Application Schematic .......................................... 6
8
Device and Documentation Support.................... 7
8.1
8.2
8.3
8.4
8.5
9
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
9.1 Mechanical Drawing.................................................. 8
9.2 Recommended PCB Land Pattern............................ 9
9.3 Recommended Stencil Opening ............................... 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2015) to Revision C
Page
•
Changed the CSD95378B parts in the Application Schematic section .................................................................................. 6
•
Added Receiving Notification of Documentation Updates section to the Device and Documentation Support section......... 7
Changes from Revision A (June 2014) to Revision B
•
Corrected MAX A dimensions in Mechanical Drawing table to 1.050 mm (0.041 inch). ....................................................... 8
Changes from Original (April 2014) to Revision A
•
2
Page
Page
Updated the controller IC in the Application Schematic to the TPS40428. ........................................................................... 6
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
5 Pin Configuration and Functions
13-Pin SON
Top View
IOUT
1
12
PWM
REFIN
2
11
TAO/FAULT
ENABLE
3
10
FCCM
PGND
4
9
BOOT
VDD
5
8
BOOT_R
VSW
6
7
VIN
13
PGND
Pin Functions
PIN
DESCRIPTION
NAME
NUMBER
BOOT
9
Bootstrap capacitor connection. Connect a minimum of 0.1-µF, 16-V, X7R ceramic capacitor from BOOT to
BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is
integrated.
BOOT_R
8
Return path for HS gate driver, connected to VSW internally.
ENABLE
3
Enables device operation. If ENABLE = logic high, turns on device. If ENABLE = logic low, the device is turned
off and both MOSFET gates are actively pulled low. An internal 100-kΩ pulldown resistor will pull the ENABLE
pin low if left floating.
FCCM
10
This pin enables the diode emulation function. When this pin is held low, diode emulation mode is enabled for
sync FET. When FCCM is high, the device is operated in Forced Continuous Conduction Mode. An internal 5-µA
current source will pull the FCCM pin to 3.3 V if left floating.
IOUT
1
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
PGND
4
Power ground, connected directly to pin 13.
PGND
13
Power ground.
PWM
12
Pulse width modulated tri-state input from external controller. Logic low sets control FET gate low and sync FET
gate high. Logic high sets control FET gate high and sync FET gate low. Open or Hi-Z sets both MOSFET gates
low if greater than the tri-state shutdown hold-off time (t3HT).
REFIN
2
External reference voltage input for current sensing amplifier.
TAO/
FAULT
11
Temperature Analog Output. Reports a voltage proportional to the die temperature. An ORing diode is integrated
in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs.
Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO
should be bypassed to PGND with a 1-nF, 16-V, X7R ceramic capacitor.
VDD
5
Supply voltage to gate driver and internal circuitry.
VIN
7
Input voltage pin. Connect input capacitors close to this pin.
VSW
6
Phase node connecting the HS MOSFET source and LS MOSFET drain-pin connection to the output inductor.
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN to PGND
–0.3
25
V
VIN to VSW
–0.3
25
V
–7
27
V
–0.3
20
V
VIN to VSW (10 ns)
VSW to PGND
VSW to PGND (10 ns)
–7
23
V
VDD to PGND
–0.3
7
V
ENABLE, PWM, FCCM, TAO, IOUT, REFIN to PGND
–0.3
VDD + 0.3 V
V
–0.3
VDD + 0.3 V
V
12
W
BOOT to BOOT_R
(2)
PD
Power dissipation
TJ
Operating junction
–55
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Should not exceed 7 V.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
MIN
MAX
4.5
5.5
V
Input supply voltage (1)
16
V
VOUT
Output voltage
5.5
V
IOUT
Continuous output current
A
Peak output current (3)
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz, LOUT = 0.225 µH (2)
60
IOUT-PK
ƒSW
Switching frequency
CBST = 0.1 µF (min)
On-time duty cycle
ƒSW = 1 MHz
VDD
Gate drive voltage
VIN
(1)
(2)
(3)
4
90
1250
UNIT
A
kHz
85%
Minimum PWM on time
40
Operating temperature
–40
ns
125
°C
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 1. Peak output current is applied for tp = 50 µs.
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
RθJC
Junction-to-case (top of package) thermal resistance
RθJB
Junction-to-board thermal resistance (2)
(1)
(2)
2
MIN
(1)
TYP
MAX
UNIT
5
°C/W
1.5
°C/W
2
RθJC is determined with the device mounted on a 1-in (6.45-cm ), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm)
thick FR4 board.
RθJB value based on hottest board temperature within 1 mm of the package.
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
www.ti.com
7 Application Schematic
12V
VDD
BP3
BP5
VIN
PWM
PWM2
BOOT
CSD95378B
FCCM
TPS40428
FLT2
FLT1
ISH1
ISH2
ISH1
VSNS1
GSNS1
CS2N
DIFFO1
ENABLE
FB2
FB2
COMP2
LOAD
PGND IOUT REFIN
BP5
COMP1
12V
FB1
PG1
CNTL1
VOUT
CS2P
PG2
PG2
CNTL2
COMP1
VSW
PGND
VDD
5V
FLT1
BOOT_R
TAO/FAULT
VIN
PWM1
RT
BOOT
PWM
FCCM
5V
VDD
ENABLE
BOOT_R
TAO/FAULT
CSD95378B
VSW
PGND
PGND IOUT REFIN
SYNC
PHSET
CS1P
CS1N
VSNS2
GSNS2
PMBDATA
PMBCLK
PMBUS I/F
SMBALERT
ADDR0
ADDR1
AGND
TSNS1
SVID1
TSNS2
AVSDATA1
AVSCLK1
VIO
High-Speed
AVSBUS
Copyright © 2017, Texas Instruments Incorporated
6
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Product Folder Links: CSD95378BQ5MC
CSD95378BQ5MC
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
DualCool, NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
www.ti.com
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
Exposed tie clip may vary
c2
A
E1
E2
c1
!
K
d2
d1
L1
b3
b1
b2
E
D2
b
e
a1
L
d
MILLIMETERS
DIM
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
0.950
1.000
1.050
0.037
0.039
0.041
a1
0.000
0.000
0.050
0.000
0.000
0.002
b
0.200
0.250
0.320
0.008
0.010
0.013
b1
b2
2.750 TYP
0.200
b3
8
0.300 x 45°
0.250
0.108 TYP
0.320
0.008
0.250 TYP
0.010
0.013
0.010 TYP
c1
0.150
0.200
0.250
0.006
0.008
0.010
c2
0.200
0.250
0.300
0.008
0.010
0.012
D2
5.300
5.400
5.500
0.209
0.213
0.217
d
0.200
0.250
0.300
0.008
0.010
0.012
d1
0.350
0.400
0.450
0.014
0.016
0.018
d2
1.900
2.000
2.100
0.075
0.079
0.083
E
5.900
6.000
6.100
0.232
0.236
0.240
E1
4.900
5.000
5.100
0.193
0.197
0.201
E2
3.200
3.300
3.400
0.126
0.130
0.134
e
0.500 TYP
K
0.350 TYP
0.020 TYP
0.014 TYP
L
0.400
0.500
0.600
0.016
0.020
0.024
L1
0.210
0.310
0.410
0.008
0.012
0.016
θ
0.000
—
—
0.000
—
—
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SLPS463C – APRIL 2014 – REVISED MARCH 2017
9.2 Recommended PCB Land Pattern
0.331(0.013)
0.370 (0.015)
0.410 (0.016)
1.000 (0.039)
0.550 (0.022)
0.300 (0.012)
2.800
(0.110)
5.300
(0.209)
6.300
(0.248)
0.500
(0.020)
5.639
(0.222)
0.300
(0.012)
R0.127 (R0.005)
3.400
(0.134)
5.900
(0.232)
1. Dimensions are in mm (in).
9.3 Recommended Stencil Opening
0.350(0.014)
2.750
(0.108)
0.250
(0.010)
1. Dimensions are in mm (in).
2. Stencil thickness is 100 µm.
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9
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD95378BQ5MC
ACTIVE
VSON-CLIP
DMC
12
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95378BMC
CSD95378BQ5MCT
ACTIVE
VSON-CLIP
DMC
12
250
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 150
95378BMC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CSD95378BQ5MC
VSONCLIP
DMC
12
2500
330.0
15.4
5.3
6.3
1.2
8.0
12.0
Q1
CSD95378BQ5MCT
VSONCLIP
DMC
12
250
178.0
12.4
5.3
6.3
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD95378BQ5MC
VSON-CLIP
DMC
12
2500
336.6
336.6
41.3
CSD95378BQ5MCT
VSON-CLIP
DMC
12
250
210.0
210.0
52.0
Pack Materials-Page 2
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