Texas Instruments | CSD19531KCS 100-V N-Channel NexFET Power MOSFET (Rev. C) | Datasheet | Texas Instruments CSD19531KCS 100-V N-Channel NexFET Power MOSFET (Rev. C) Datasheet

Texas Instruments CSD19531KCS 100-V N-Channel NexFET Power MOSFET (Rev. C) Datasheet
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CSD19531KCS
SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
CSD19531KCS 100-V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
TO-220 Plastic Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
100
V
Qg
Gate Charge Total (10 V)
37
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
7.5
nC
VGS = 6 V
7.3
VGS = 10 V
6.4
2.7
mΩ
V
Device Information(1)
2 Applications
•
•
•
UNIT
VDS
Secondary Side Synchronous Rectifier
Hot Swap Telecom
Motor Control
DEVICE
PACKAGE
MEDIA
QTY
SHIP
CSD19531KCS
TO-220 Plastic Package
Tube
50
Tube
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
3 Description
This 100-V, 6.4-mΩ, TO-220 NexFET™ power
MOSFET is designed to minimize losses in power
conversion applications.
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
100
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package Limited)
100
Continuous Drain Current (Silicon Limited),
TC = 25°C
110
Continuous Drain Current (Silicon Limited),
TC = 100°C
78
IDM
Pulsed Drain Current(1)
285
A
PD
Power Dissipation
214
W
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 175
°C
EAS
Avalanche Energy, Single Pulse
ID = 60 A, L = 0.1 mH, RG = 25 Ω
180
mJ
.
Drain (Pin 2)
ID
Gate
(Pin 1)
Source (Pin 3)
A
(1) Max RθJC = 0.7º C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
.
RDS(on) vs VGS
Gate Charge
10
TC = 25°C, I D = 60A
TC = 125°C, I D = 60A
18
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
20
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 60A
VDS = 50V
9
8
7
6
5
4
3
2
1
0
0
4
8
12
16
20
24
28
Qg - Gate Charge (nC)
32
36
40
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19531KCS
SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
6.5
7
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 KCS Package Dimensions........................................ 8
4 Revision History
Changes from Revision B (June 2014) to Revision C
Page
•
Added Receiving Notification of Documentation Updates section and Community Resources section to the Device
and Documentation Support section ...................................................................................................................................... 7
•
Changed package drawing in KCS Package Dimensions section ......................................................................................... 8
Changes from Revision A (May 2014) to Revision B
•
Page
Added value for max Qg ......................................................................................................................................................... 3
Changes from Original (September 2013) to Revision A
Page
•
Updated the silicon limited currents to reflect increase in device operating temperature range ........................................... 1
•
Increased pulsed current to reflect new conditions ............................................................................................................... 1
•
Increased max power dissipation to reflect new conditions .................................................................................................. 1
•
Increased operating and junction temperature range to 175ºC ............................................................................................. 1
•
Updated the pulsed drain current conditions.......................................................................................................................... 1
•
Changed Figure 1 from a normalized RθJA curve to a normalized RθJC curve ....................................................................... 4
•
Updated Figure 6 to reflect increase in device operating temperature range ....................................................................... 5
•
Updated Figure 8 to reflect increase in device operating temperature range ....................................................................... 5
•
Updated Figure 10 to reflect measured SOA data ................................................................................................................ 6
•
Updated Figure 12 to reflect increase in device operating temperature range ..................................................................... 6
2
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SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 80 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
V
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
100
2.2
V
2.7
3.3
VGS = 6 V, ID = 60 A
7.3
8.8
VGS = 10 V, ID = 60 A
6.4
7.7
VDS = 10 V, ID = 60 A
137
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (10 V)
38
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turnon delay time
tr
Rise Time
7.2
ns
td(off)
Turnoff delay time
16
ns
tf
Fall time
4.1
ns
VGS = 0 V, VDS = 50 V, ƒ = 1 MHz
VDS = 50 V, ID = 60 A
VDS = 50 V, VGS = 0 V
VDS = 50 V, VGS = 10 V,
IDS = 60 A, RG = 0 Ω
2980
3870
pF
560
728
pF
13
17
pF
1.3
2.6
Ω
49
nC
7.5
nC
11.9
nC
7.3
nC
98
nC
8.4
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
ISD = 60 A, VGS = 0 V
0.9
1
V
Qrr
Reverse recovery charge
nC
Reverse recovery time
VDS= 50 V, IF = 60 A,
di/dt = 300 A/μs
270
trr
83
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance
THERMAL METRIC
MIN
TYP
0.7
°C/W
RθJA
Junction-to-ambient thermal resistance
62
°C/W
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SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
200
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
Figure 1. Transient Thermal Impedance
160
140
120
100
80
60
VGS =10V
VGS =8V
VGS =6V
40
20
0
0
0.4
0.8
1.2
1.6
VDS - Drain-to-Source Voltage (V)
2
VDS = 5V
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
0
G001
Figure 2. Saturation Characteristics
4
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1
2
3
4
5
6
VGS - Gate-to-Source Voltage (V)
7
8
G001
Figure 3. Transfer Characteristics
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Product Folder Links: CSD19531KCS
CSD19531KCS
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SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 60A
VDS = 50V
9
8
10000
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
10
2
1
0
0
4
8
12
16
20
24
28
Qg - Gate Charge (nC)
32
36
1
40
0
10
20
G001
Figure 4. Gate Charge
ID = 250uA
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.3
−75 −50 −25
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
100
G001
20
1.5
Figure 6. Threshold Voltage vs Temperature
TC = 25°C, I D = 60A
TC = 125°C, I D = 60A
18
16
14
12
10
8
6
4
2
0
0
25 50 75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
Figure 7. On-State Resistance vs Gate-to-Source Voltage
100
2.4
VGS = 6V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
90
Figure 5. Capacitance
3.3
2.2
30
40
50
60
70
80
VDS - Drain-to-Source Voltage (V)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75 −50 −25
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
ID = 60A
0
25 50 75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 8. Normalized On-State Resistance vs Temperature
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
1
G001
Figure 9. Typical Diode Forward Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
1000
100
10us
100us
1ms
10ms
DC
100
10
1
Single Pulse
Max RthetaJC = 0.7ºC/W
0.1
0.1
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
5000
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
10
0.01
G001
Figure 10. Maximum Safe Operating Area
0.1
TAV - Time in Avalanche (mS)
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
125
100
75
50
25
0
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
6
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CSD19531KCS
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SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS407C – SEPTEMBER 2013 – REVISED MARCH 2017
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KCS Package Dimensions
4.7
4.4
10.36
9.96
1.32
1.22
2.9
2.6
6.5
6.1
8.55
8.15
(6.3)
( 3.84)
12.5
12.1
19.65 MAX
9.25
9.05
3X
3.9 MAX
13.12
12.70
3
1
3X
0.47
0.34
0.90
0.77
2.79
2.59
2X 2.54
1.36
3X
1.23
5.08
4222214/A 10/2015
Notes:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in
brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-220.
Table 1. Pin Configuration
POSITION
8
DESIGNATION
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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PACKAGE OPTION ADDENDUM
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5-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD19531KCS
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TO-220
KCS
3
50
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU SN
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
-55 to 175
CSD19531KCS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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