Texas Instruments | TPS61240-Q1 3.5-MHz High Efficiency Step-Up Converter (Rev. B) | Datasheet | Texas Instruments TPS61240-Q1 3.5-MHz High Efficiency Step-Up Converter (Rev. B) Datasheet

Texas Instruments TPS61240-Q1 3.5-MHz High Efficiency Step-Up Converter (Rev. B) Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
TPS61240-Q1 3.5-MHz High Efficiency Step-Up Converter
1 Features
3 Description
•
•
The TPS61240-Q1 device is a high efficient
synchronous step up DC-DC converter optimized for
products powered by either a three-cell alkaline, NiCd
or NiMH, or one-cell Li-Ion or Li-Polymer battery. The
TPS61240-Q1 supports output currents up to 450
mA. The TPS61240-Q1 has an input valley current
limit of 500 mA.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade
– TPS61240IDRVRQ1: Grade 3, –40°C to
+85°C Ambient Operating Temperature
– TPS61240TDRVRQ1: Grade 2, –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Efficiency > 90% at Nominal Operating Conditions
Total DC Output Voltage Accuracy 5 V ±2%
Typical 30 μA Quiescent Current
Best in Class Line and Load Transient
Wide VIN Range From 2.3 V to 5.5 V
Output current up to 450 mA
Automatic PFM/PWM Mode transition
Low Ripple Power Save Mode for Improved
Efficiency at Light Loads
Internal Softstart, 250 μs typical Start-Up time
3.5 MHz Typical Operating Frequency
Load Disconnect During Shutdown
Current Overload and Thermal Shutdown
Protection
Only Three Surface-Mount External Components
Required (One MLCC Inductor, Two Ceramic
Capacitors)
Total Solution Size < 13 mm2
Available in a 2 mm × 2 mm WSON Package
TPS61240-Q1 device provides fixed output voltage of
5V-typ with an input voltage range of 2.3 V to 5.5 V
and the device supports batteries with extended
voltage range. During shutdown, the load is
completely disconnected from the battery. The
TPS61240-Q1 boost converter is based on a quasiconstant on-time valley current mode control scheme.
The TPS61240-Q1 presents a high impedance at the
VOUT pin when shut down. This allows for use in
applications that require the regulated output bus to
be driven by another supply while the TPS61240-Q1
is shut down.
During light loads the device will automatically pulse
skip allowing maximum efficiency at lowest quiescent
currents. In the shutdown mode, the current
consumption is reduced to less than 1 μA.
TPS61240-Q1 allows the use of a small inductor and
capacitors to achieve a small solution size. The
TPS61240-Q1 is available in a 2 mm × 2 mm WSON
package.
Device Information(1)
PART NUMBER
•
•
•
Advanced Driver Assistance Systems (ADAS)
– Front Camera
– Surround View System ECU
– Radar and LIDAR
Automotive Infotainment and Cluster
– Head Unit
– HMI and Display
Body Electronics and Lighting
Factory Automation and Control
BODY SIZE (NOM)
WSON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
TPS61240-Q1
Simplified Schematic
TPS61240-Q1
L
1 µH
VIN
VOUT
L
VIN
FB
EN
GND
VOUT 5 V
COUT
4.7 µF
CIN
2.2 µF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
8.3 System Example .................................................... 17
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example ................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2016) to Revision B
Page
•
Added the AEC-Q100 qualified information to the Features section...................................................................................... 1
•
Added operating ambient temperature for T version of device (TPS61240TDRVRQ1) in the Recommended
Operating Conditions table ..................................................................................................................................................... 5
•
Added shutdown current for T version of device (TPS61240TDRVRQ1) in the Electrical Characteristics table................... 6
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 18
Changes from Original (December 2010) to Revision A
Page
•
Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Changed TPS6124x to TPS61240-Q1 throughout document ............................................................................................... 1
•
Changed Description section ................................................................................................................................................. 1
•
Deleted Ordering Information table ........................................................................................................................................ 1
•
Changed Pin Functions figure and table ............................................................................................................................... 4
•
Deleted Dissipation Ratings table........................................................................................................................................... 5
•
Added Inductance and Output capacitance values and table note to Recommended Operating Conditions ...................... 5
•
Added Thermal Information table ........................................................................................................................................... 5
•
Changed reference to Typical Applications section .............................................................................................................. 6
•
Changed VOUT test condition to 2.3 V to ≤ VIN ≤ VOUT ........................................................................................................... 6
•
Added equals before 2.3 V in Output current test condition ................................................................................................. 6
•
Removed ISW from all rows except Switch valley current limit .............................................................................................. 6
•
Changed Operating quiescent current test condition by adding device not switching .......................................................... 6
•
Added equals before 600 mVp-p in Line transient response test condition .......................................................................... 6
•
Moved figures 8 through 16 to Application Curves section ................................................................................................... 7
•
Updated titles of figures 2 through 7 for better clarity Figure 2 ............................................................................................. 7
2
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
•
Deleted Parameter Measurement Information section .......................................................................................................... 9
•
Changed Updated Overview section for more clarity ............................................................................................................ 9
•
Changed Figure 8 Inductor/Rectifier Currents in Current Limit Operation waveform........................................................... 10
•
Added Under no load conditions to Soft Start section.......................................................................................................... 11
•
Deleted HDMI / USB-OTG Application title ......................................................................................................................... 12
•
Updated Inductor Selection section...................................................................................................................................... 13
•
Deleted List of Inductors table and listed one example inductor in description ................................................................... 13
•
Changed 2.7 µF to 2.3 µF in Output Capacitor section ....................................................................................................... 14
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
3
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
5 Pin Configuration and Functions
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
GND
V
OUT
FB
1
6
V
2 Thermal 5
Pad
L
3
EN
4
IN
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
GND
GND
2
VOUT
O
Output Supply pin. Connected to the load
3
FB
I
Feedback for regulation.
4
EN
I
Positive polarity. Low = IC shutdown.
5
L
I
Inductor connection to FETs
6
VIN
I
Supply from battery
—
PAD
—
4
Power ground and IC ground
For good thermal performance, this pad must be soldered to the land pattern on the PCB
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Input voltage, VI (on VIN, L, and EN)
MIN
MAX
UNIT
–0.3
7
V
Voltage on VOUT
–2
7
V
Voltage on FB
–2
14
V
Peak output current
Internally limited
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage at VIN
NOM
MAX
UNIT
2.3
5.5
V
L
Inductance
1
2.2
µH
Cout
Output capacitance
1
20
µF
TA
Operating ambient temperature (1)
(1)
TPS61240IDRVRQ1
–40
85
°C
TPS61240TDRVRQ1
–40
105
°C
In applications where high power dissipation, poor package thermal resistance, or both are present, the maximum ambient temperature
may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature
(TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the
device or package in the application (RθJA), as given by the following equation: TA(max)= TJ(max) – (RθJA × PD(max))
6.4 Thermal Information
TPS61240-Q1
THERMAL METRIC (1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
67.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.4
°C/W
RθJB
Junction-to-board thermal resistance
37.5
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
37.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
5
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
6.5 Electrical Characteristics
Over full operating ambient temperature range with typical values at TA = 25°C. Specifications apply for condition VIN = EN =
3.6 V (unless otherwise noted). External components CIN = 2.2 μF, COUT = 4.7 μF (0603), and L = 1μH (refer to Typical
Applications section).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC/DC STAGE
VIN
Input voltage range
VOUT
Fixed output voltage range
2.3 V ≤ VIN ≤ VOUT, 0 mA ≤ IOUT ≤ 200 mA
VO_Ripple
Ripple voltage, PWM mode
ILOAD = 150 mA
Output current
VIN = 2.3 V to 5.5 V
200
Switch valley current limit
VOUT = VGS = 5 V
500
600
mA
Short circuit current
VOUT = VGS = 5 V
200
350
mApk
High side MOSFET
on-resistance (1)
VIN = VGS = 5 V, TA = 25°C (1)
290
mΩ
Low Side MOSFET
on-resistance (1)
VIN = VGS = 5 V, TA = 25°C (1)
250
mΩ
Operating quiescent current
IOUT = 0 mA, power save mode, device not
switching
ISW
5
V
5.1
V
20
mVpp
mA
30
40
μA
1.5
TPS61240TDRVRQ1, EN = GND
2.5
Reverse leakage current VOUT
EN = 0 V, VOUT = 5 V
2.5
μA
Leakage current from battery
to VOUT
EN = GND
2.5
μA
Line transient response
VIN = 600 mVp-p AC square wave, 200 Hz,
12.5% DC at 50 mA or 200 mA load
±25
±50
mVpk
0 mA to 50 mA, 50 mA to 0 mA, VIN = 3.6 V,
TRise = TFall = 0.1 μs
50
Load transient response
Input bias current, EN
VUVLO
4.9
5.5
TPS61240IDRVRQ1, EN = GND
Shutdown current
IIN
2.3
Undervoltage lockout threshold
μA
mVpk
50 mA to 200 mA, 200 mA to 50 mA, VIN = 3.6 V,
TRise = TFall = 0.1 μs
150
EN = GND or VIN
0.01
1.0
μA
Falling
2.0
2.1
V
Rising
2.1
2.2
V
1.0
V
CONTROL STAGE
VIH
High level input voltage, EN
2.3 V ≤ VIN ≤ 5.5 V
VIL
Low level input voltage, EN
2.3 V ≤ VIN ≤ 5.5 V
OVC
Input over-voltage threshold
tStart
Start-up time
0.4
V
Falling
5.9
Rising
6
Time from active EN to start switching, no-load until
VOUT is stable 5 V
V
300
μs
DC/DC STAGE
Freq
TSD
(1)
6
See Figure 7
3.5
MHz
Thermal shutdown
Increasing junction temperature
140
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
DRV package has an increased RDSon of about 40 mΩ due to bond wire resistance.
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
6.6 Typical Characteristics
Table 1. Table of Graphs
Figure
Maximum output current
Efficiency
Input current
Output voltage
Frequency
vs Input voltage
Figure 1
vs Output current, VOUT = 5 V, VIN = [2.3 V, 3 V, 3.6 V, 4.2 V]
Figure 2
vs Input voltage, VOUT = 5 V, IOUT = [100 µA, 1 mA, 10 mA, 100 mA, 200 mA]
Figure 3
at No output load (PFM Mode)
Figure 4
vs Output current, VOUT = 5 V, VIN = [2.3 V, 3 V, 3.6 V, 4.2 V]
Figure 5
vs Input voltage
Figure 6
vs Output load, VOUT = 5 V, VIN = [3 V, 4 V, 5 V]
Figure 7
100
0.8
VI = 3.6 V
90
0.7
VI = 4.2 V
80
IO - Output Current - A
0.6
VI = 3 V
70
0.4
Efficiency - %
0.5
25°C
-40°C
0.3
VI = 2.3 V
60
50
40
30
0.2
85°C
20
0.1
10
0
0.00001
0
2
2.5
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
6
Figure 1. Maximum Output Current vs Input Voltage
0.0001
0.001
0.01
0.1
IO - Output Current - A
1
Figure 2. Efficiency vs Output Current for Different VIN (VI)
100
0.070
IO = 200 mA
90
-40°C
0.060
25°C
II - Input Current - mA
Efficiency - %
80
70
IO = 100 mA
60
50
40
IO = 10 mA
IO = 1 mA
IO = 100 mA
30
85°C
0.050
0.040
0.030
0.020
20
0.010
10
0
2.3
0
2.8
3.3
3.8
4.3
VIN - Input Voltage - V
4.8
5.3
Figure 3. Efficiency vs Input Voltage for Different Output
Current (IO)
2
2.5
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
6
Figure 4. Input Current at No Output Load (PFM Mode) for
Different TA
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
7
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
5.10
5.10
5.08
VI = 4.2 V
VO - Output Voltage - V
VO - Output Voltage DC - V
5.06
IO = 100 mA
IO = 1 mA
5.05
5
VI = 3.6 V
VI = 3 V
VI = 2.3 V
4.95
IO = 10 mA
5.04
5.02
5
4.98
IO = 100 mA
IO = 200 mA
4.96
4.94
4.92
4.90
0.01
0.1
1
10
100
IO - Output Current - mA
4.90
2.3
1000
Figure 5. Output Voltage vs Output Current for Different VIN
(VI)
2.8
3.3
3.8
4.3
4.8
VI - Input Voltage - V
5.3
Figure 6. Output Voltage vs Input Voltage for Different
Output Current (IO)
5.5
f - Frequency - MHz
5
4.5
5V
4
4V
3V
3.5
3
100
150
200
250 300 350 400
IO - Output Current - mA
450
500
Figure 7. Frequency vs Output Load for Different VIN
8
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
7 Detailed Description
7.1 Overview
The TPS61240-Q1 boost converter operates with typically a 3.5-MHz fixed-frequency pulse width modulation
(PWM) at moderate to heavy load currents. At light load currents, the converter automatically enters Power Save
Mode and then operates in pulse frequency modulation (PFM) mode.
During PWM operation the converter uses a unique fast response quasi-constant on-time valley current mode
controller scheme, which allows best in class line and load regulation allowing the use of small ceramic input and
output capacitors and a small inductor. During shutdown, the load is completely disconnected from the battery.
Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching
cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined
by the on-time and the inductance. In the second phase, once the peak current is reached, the current
comparator trips and the on-timer is reset and this turns off N-MOS switch. Now rectifier switch (P-MOS) is
turned on and the inductor current decays to an internally set valley current threshold. Finally, the switching cycle
repeats by setting the on timer again and activating the low-side N-MOS switch.
In general, a DC-to-DC step-up converter can only operate in true boost mode, that is, the output is boosted by a
certain amount above the input voltage. The TPS61240-Q1 device operates differently as it can smoothly
transition in and out of zero duty-cycle operation. Therefore, the output can be kept as close as possible to its
regulation limits even though the converter is subject to an input voltage that tends to be excessive.
7.2 Functional Block Diagram
L
VOUT
Gate Drive
VIN
FB
Current
Sense
Error Amp.
R1
Softstart
Internal
Resistor
Network
R2
+
Thermal
Shutdown
EN
+
_
Control
Logic
VREF
GND
Undervoltage
Lockout
GND
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
9
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
7.3 Feature Description
7.3.1 Current Limit Operation
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier.
During the current limit operation, the output voltage is reduced as the power stage of the device operates in a
constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit operation,
can be defined by Equation 1.
IOUT(CL) = (1 - D) ´ (IVALLEY +
1
DIL )
2
with DIL =
V
- VIN
VIN
D
´
and D » OUT
L
f
VOUT
(1)
Figure 8 illustrates the inductor and rectifier current waveforms during current limit operation. The output current,
IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such that the
lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this
threshold before the next on-time begins (so called frequency fold-back mechanism).
IL
Current Limit
Threshold
Rectifier
Current
IPEAK
IVALLEY = ILIM
IOUT(CL)
DIL
IOUT(DC)
Increased
Load Current
IIN(DC)
f
Inductor
Current
IIN(DC)
DIL
ΔI L =
V IN D
×
L f
Figure 8. Inductor/Rectifier Currents in Current Limit Operation
7.3.2 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
undervoltage lockout threshold VUVLO. The undervoltage lockout threshold VUVLO for falling VIN is 2 V (typical).
The device starts operation once the rising VIN trips undervoltage lockout threshold VUVLO again at 2.1 V
(typical).
7.3.3 Input Overvoltage Protection
In the event of an overvoltage condition on the input rail, the output voltage will also experience the overvoltage
due to being in dropout condition. An input overvoltage protection feature has been implemented into the
TPS61240-Q1, which has an input overvoltage threshold of 6 V. Once this level is triggered, the device will go
into shutdown mode to protect itself. If the voltage drops to 5.9 V or below, the device will startup once more into
normal operation.
10
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
Feature Description (continued)
7.3.4 Enable
Setting EN pin to high, enables the device. At first, the internal reference is activated and the internal analog
circuits are settled. Afterwards, the soft start activates and the output voltage ramps up. The output voltages
reach nominal values in typically 250 μs after the device has been enabled.
The EN input can control power sequencing in a system with various DC/DC converters. The EN pin can be
connected to the output of another converter, to drive the EN pin high and get a sequencing of supply rails. With
EN = GND, the device enters shutdown mode.
7.3.5 Soft Start
The TPS61240-Q1 has an internal soft start circuit that controls the ramp up of the output voltage. Under no load
conditions, the output voltage reaches nominal values within tStart of typically 250 μs after EN pin has been pulled
to a high level.
This limits the inrush current in the converter during start up and prevents possible input voltage drops when a
battery or high impedance power source is used.
During soft start, the switch current limit is reduced to 300 mA until the output voltage reaches VIN. Once the
output voltage trips this threshold, the device operates with its nominal current limit ILIMF.
7.3.6 Load Disconnect
Load disconnect electrically removes the output from the input of the power supply when the supply is disabled.
This is especially important during shutdown. In shutdown of a boost converter, the load is still connected to the
input through the inductor and catch diode. Since the input voltage is still connected to the output, a small current
continues to flow, even when the supply is disabled. Even small leakage currents significantly reduce battery life
during extended periods of off time.
The benefit of this implemented feature for a system design is that the battery is not depleted during shutdown of
the converter. No additional components must be added to the design to make sure that the battery is
disconnected from the output of the converter.
7.3.7 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typical) the device goes into thermal shutdown. In this
mode, the High Side and Low Side MOSFETs are turned off. When the junction temperature falls below the
thermal shutdown hysteresis, the device continues operation.
7.4 Device Functional Modes
7.4.1 Power-Save Mode
The TPS61240-Q1 family of devices integrates a power save mode to improve efficiency at light load. In power
save mode, the converter only operates when the output voltage trips below a set threshold voltage. It ramps up
the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set
threshold voltage.
Output
Voltage
PFM mode at light load
PFM ripple about 0.015 x VOUT
1.006 x VOUT NOM.
VOUT NOM.
PWM mode at heavy load
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
11
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61240-Q1 boost regulator has fixed output voltage of 5 V typical with an input voltage range of 2.3 V to
5.5 V. TPS61240-Q1 allows the use of small inductors and capacitors to achieve a small solution size and
supports output currents up to 450 mA. When shut down, the TPS61240-Q1 presents a high impedance at the
VOUT pin and the load is disconnected completely from the battery. This allows for use in applications that require
the regulated output bus to be driven by another supply while the TPS61240-Q1 is shut down.
8.2 Typical Applications
TPS61240-Q1
L
1 µH
VIN
VOUT
L
VIN
FB
EN
GND
VOUT 5 V
COUT
4.7 µF
CIN
2.2 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 9. TPS61240-Q1 Fixed 5 V Output from VIN = 3 V to 4.2 V
8.2.1 Design Requirements
Table 2 lists the design parameters for this application example.
Table 2. TPS61240-Q1 5V Output Design Requirements
PARAMETERS
VALUE
Input voltage
3 V to 4.2 V
Output voltage
5V
Output current
200 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Programming the Output Voltage
The output voltage is set by an internal resistor divider. The FB pin is used to sense the output voltage. To
configure the output properly, the FB pin has to be connected directly to the output.
12
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
8.2.2.2 Inductor Selection
For correct operation of TPS61240-Q1 device, an inductor must be connected between pin VIN and pin L. A
boost converter requires two main passive components for storing energy during the conversion. A boost
inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to
keep the possible peak inductor current below the current limit threshold of the power switch in the chosen
configuration. The highest peak current through the inductor and the switch depends on the output load, the input
(VIN), and the output voltage (VOUT). Estimation of the maximum average inductor current can be done using
Equation 2.
IL_MAX » IOUT ´
VOUT
η ´ VIN
where
•
η is the efficiency of the switching regulator
(2)
For example, for an output current of 200 mA at 5 V VOUT, with efficiency of 85%, at least 392 mA of average
current flows through the inductor at a minimum input voltage of 3 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple (or larger
inductor value) reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI.
But with larger inductor, regulation time during load transients rises. In addition, a larger inductor increases the
total system size and cost. With these parameters, it is possible to calculate the value of the minimum inductance
by using Equation 3.
VIN ´
LMIN »
(VOUT - VIN )
DIL ´ f ´ VOUT
where
•
•
f is the switching frequency
ΔIL is the ripple current in the inductor
(3)
With VIN = 4.2 V, VOUT = 5 V, assuming inductor ripple current = 30% of minimum current limit of 0.5 A, the
resulting inductor value = 1.28 μH. In typical applications, a 1.0 μH inductance is recommended. The device has
been optimized to operate with inductance values between 1.0 μH and 2.2 μH. It is recommended that
inductance values of at least 1.0 μH is used, even if Equation 3 yields something lower. Care has to be taken
that load transients and losses in the circuit can lead to higher currents as estimated in Equation 3. Also, the
losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total
circuit efficiency.
With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated.
Equation 4 shows how to calculate the peak current I.
IL(peak) =
VIN ´ D
2 ´ f ´ L
+
IOUT
(1 - D) ´ η
V
- VIN
with D = OUT
VOUT
(4)
This would be the critical value for the current rating for selecting the inductor. It also needs to be taken into
account that load transients and error conditions may cause higher inductor currents. Inductor with part number,
LQM21PN1R0MC0 is one example of an inductor that can be used with this device. Customers need to verify
and validate whether it is suitable for their application.
8.2.2.3 Input Capacitor
At least 2.2-μF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. It is recommended to place a ceramic capacitor as close as possible to the VIN
and GND pins
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
13
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
8.2.2.4 Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended.
This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC. To get an
estimate of the recommended minimum output capacitance, Equation 5 can be used.
I
´ (VOUT - VIN )
C min = OUT
f ´ D V ´ VOUT
where
•
ΔV is the maximum allowed ripple
(5)
With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 2.3 μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
ΔVESR = IOUT × RESR
A capacitor with a value equal to or higher than the calculated minimum should be used. This is required to
maintain control loop stability. There are no additional requirements regarding minimum ESR. There is no upper
limit for the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output
voltage drop during load transients.
Note that ceramic capacitors have a DC bias effect, which will have a strong influence on the final effective
capacitance. Therefore the correct capacitor value has to be chosen carefully. Package size and voltage rating in
combination with material are responsible for differences between the rated capacitor value and the effective
capacitance.
8.2.2.5 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. Time between the
load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current
required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the effective
series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the
regulator to return VO to its steady-state value. The results are very easily interpreted when the device operates
in PWM mode. During recovery time, VO can be monitored for settling time, overshoot or ringing to judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET rDS(on))
that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load
current range, and temperature range.
14
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
8.2.3 Application Curves
Table 3. Table of Application Curves
Figure
Waveforms
Output voltage ripple, PFM mode, IOUT = 10 mA
Figure 10
Output voltage ripple, PWM mode, IOUT = 150 mA
Figure 11
Load transient response, VIN, 3.6 V, 0 mA to 50 mA
Figure 12
Load transient response, VIN, 3.6 V, 50 mA to 200 mA
Figure 13
Line transient response, VIN, 3.6 V to 4.2 V, IOUT = 50 mA
Figure 14
Line transient response, VIN, 3.6 V to 4.2 V, IOUT = 200 mA
Figure 15
Startup after enable, VIN, 3.6 V, VOUT = 5 V, Load = 5 kΩ
Figure 16
Startup after enable, VIN, 3.6 V, VOUT = 5 V, Load = 16.5 kΩ
Figure 17
Startup and shutdown, VIN, 3.6 V, VOUT = 5 V, Load = 16.5 kΩ
Figure 18
VIN = 3.6 V, VOUT = 5 V, IOUT = 150 mA
VIN = 3.6 V, VOUT = 5 V, IOUT = 10 mA
VOUT = 20 mV/div
VOUT = 10 mV/div
SW = 5 V/div
SW = 5 V/div
ICOIL = 200 mA/div
ICOIL = 200 mA/div
t - Time Base - 20 ms/div
t - Time Base - 1 ms/div
Figure 10. Output Voltage Ripple – PFM Mode
Figure 11. Output Voltage Ripple – PWM Mode
VOUT = 200 mV/div
VOUT = 100 mV/dIV
VIN = 3.6 V
VOUT = 5 V
IOUT = 0 - 50 mA
ICOIL = 100 mA/dIV
VIN = 3.6 V
VOUT = 5 V
IOUT = 50 - 200 mA
ICOIL = 200 mA/div
200 mA
50 mA
50 mA
0 mA
IOUT = 100 mA/div
IOUT = 200 mA/div
t - Time Base - 20 ms/div
t - Time Base - 20 ms/div
Figure 12. Load Transient Response
0 mA to 50 mA and 50 mA to 0 mA
Figure 13. Load Transient Response
0 mA to 200 mA and 200 mA to 0 mA
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
15
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
VIN = 1 V/div
VIN = 1 V/div
VOUT = 50 mv/div
VOUT = 50 mv/div
VIN = 3.6 V - 4.2 V
VOUT = 5 V
IOUT = 200 mA
VIN = 3.6 V - 4.2 V
VOUT = 5 V
IOUT = 50 mA
ICOIL = 200 mA/div
ICOIL = 200 mA/div
t - Time Base - 100 ms/div
t - Time Base - 100 ms/div
Figure 14. Line Transient Response
3.6 V to 4.2 V at 50 mA Load
Figure 15. Line Transient Response
3.6 V to 4.2 V at 200 mA Load
EN = 5 V/div
EN = 5 V/div
VOUT = 1 V/div
VIN = 3.6 V
VOUT = 5 V
IOUT = 150 mA
VIN = 3.6 V
VOUT = 5 V
IOUT = 10 mA
VOUT = 2 V/div
ICOIL = 200 mA/div
ICOIL = 200 mA/div
t - Time Base - 100 ms/div
t - Time Base - 50 ms/div
Figure 17. Startup After Enable – With Load
Figure 16. Startup After Enable – No Load
EN = 5 V/div
VOUT = 1 V/div
VIN = 3.6 V
VOUT = 5 V
IOUT = 150 mA
VIN = 1 V/div
ICOIL = 200 mA/div
t - Time Base - 200 ms/div
Figure 18. Startup and Shutdown
16
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
TPS61240-Q1
www.ti.com
8.3
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
System Example
Figure 19 is another example for using the TPS61240-Q1 with fixed 5 V and a Schottky diode for output
overvoltage protection.
TPS61240-Q1
L
1 µH
VIN
L
VIN
FB
VOUT 5 V
VOUT
COUT
CIN
EN
2.2 µF
GND
4.7 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 19. TPS61240-Q1 Fixed 5 V With Schottky Diode for Output Overvoltage Protection
9 Power Supply Recommendations
The input supply should be in the range from 2.3 V to 5.5 V. The input supply can be a regulated supply voltage
or a three-cell alkaline, NiCd or NiMH, or one-cell Li-Ion or Li-Polymer battery. If the input supply is located more
than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic or tantalum capacitor with a value of 47 μF is a typical choice for the bulk capacitance.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. The following are some guidelines for good layout design.
Figure 20 provides an example of layout design with the TPS61240-Q1 device. Follow the guidelines for a good
layout.
• Use wide and short traces for the main current path and for the power ground tracks.
• The input and output capacitor, as well as the inductor, should be placed as close as possible to the IC.
• Connect the exposed thermal pad to the GND plane and place multiple thermal vias below the thermal pad to
enhance the thermal performance.
10.2 Layout Example
Figure 20. PCB Layout Example
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
17
TPS61240-Q1
SLVSAO4B – DECEMBER 2010 – REVISED MARCH 2017
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• QFN/SON PCB Attachment
• Performing Accurate PFM Mode Efficiency Measurements
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS61240-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS61240IDRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QVL
TPS61240TDRVRQ1
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
14T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS61240-Q1 :
• Catalog: TPS61240
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS61240IDRVRQ1
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS61240TDRVRQ1
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61240IDRVRQ1
WSON
DRV
6
3000
195.0
200.0
45.0
TPS61240TDRVRQ1
WSON
DRV
6
3000
195.0
200.0
45.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A B
C
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising