Texas Instruments | TPS249x Positive High-Voltage Power-Limiting Hot Swap Controller (Rev. E) | Datasheet | Texas Instruments TPS249x Positive High-Voltage Power-Limiting Hot Swap Controller (Rev. E) Datasheet

Texas Instruments TPS249x Positive High-Voltage Power-Limiting Hot Swap Controller (Rev. E) Datasheet
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TPS2490, TPS2491
SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
TPS249x Positive High-Voltage Power-Limiting Hot Swap Controller
1 Features
3 Description
•
The TPS249x are easy-to-use, positive high voltage,
10-pin Hot Swap Power Manager devices that safely
drive an external N-channel MOSFET switch. The
power limit and current limit (both are adjustable and
independent of each other) ensure that the external
MOSFET operates inside a selected safe operating
area (SOA) under the harshest operating conditions.
Applications include inrush current limiting, electronic
circuit breaker protection, controlled load turn-on,
interfacing to down-stream DC-to-DC converters, and
power feed protection. These devices are available in
a small, space-saving 10-pin VSSOP package and
significantly reduce the number of external devices,
saving precious board space. The TPS249x is
supported by application notes, an evaluation
module, and a design tool.
1
•
•
•
•
•
•
•
•
Programmable Power Limiting and Current
Limiting for Complete Safe Operating Area (SOA)
Protection
Wide Operating Range: 9 V to 80 V
Latched Operation (TPS2490) and Automatic
Retry (TPS2491)
High-Side Drive for Low-RDS(on) External Nchannel MOSFET
Programmable Fault Timer to Protect the
MOSFET and Eliminate Nuisance Shutdowns
Power Good Open-Drain Output for Downstream
DC/DC Coordination
Enable Can Be Used as a Programmable
Undervoltage Lockout or Logic Control
Small, Space-Saving 10-pin VSSOP Package
Calculator Tool Available (TPS2490/91 Design-in
Calculator, SLVC033)
Device Information(1)
PART NUMBER
TPS249x
VSSOP (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
Server Backplanes
Storage Area Networks (SAN)
Medical Systems
Plug-In Modules
Base Stations
Typical Application
VIN
RSNS
VOUT
Q1
CIN
Z1
D1
R5
SENSE
Only required when
using dv/dt start-up
GATE OUT
470 NŸ
R1
COUT
VCC
1 NŸ
PG
TPS2490/91
EN
Cdv/dt
VREF
R2
R3
PROG
TIMER
GND
CTIMER
R4
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2490, TPS2491
SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
13
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 19
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Development Support ...........................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2012) to Revision E
•
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision C (September 2011) to Revision D
Page
•
Added Operating voltage range to the RECOMMENDED OPERATING CONDITIONS table............................................... 5
•
Changed Supply Current Disabled Test Conditions From: VEN = Lo, VSENSE = VVCC = VOUT = 0 To: VEN = Lo, VSENSE =
VVCC = VOUT ............................................................................................................................................................................ 6
Changes from Revision B (March 2010) to Revision C
•
Page
Changed Figure 14, From: IIN = 5 A/div To: IIN = 0.5 A/div................................................................................................... 15
Changes from Revision A (March 2010) to Revision B
Page
•
Added Feature: Calculator Tool Available (SLVC033) ........................................................................................................... 1
•
Added the Gate Capacitor (dV/dt) Control section: Revised text and Equation 5................................................................ 17
2
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Changes from Original (November 2003) to Revision A
Page
•
Deleted Lead temperature spec. from Abs Max Ratings table............................................................................................... 5
•
Changed VPROG MIN voltage spec. from: 0 to: 0.4; added footnote (1) to the RECOMMENDED OPERATING
CONDITIONS table ............................................................................................................................................................... 5
•
Deleted footnote - Not tested in production from tF_TRIP ......................................................................................................... 7
•
Added clarification sentence to the GATE pin description, regarding adding capacitance. ................................................ 11
•
Changed V(VCC-OUT). to V(SENSE-OUT) in the OUT pin description. ........................................................................................... 11
•
Changed from: (0–4 V) to: (0.4 – 4 V) in the PROG pin description ................................................................................... 12
•
Changed from: 2.5 V to: 2.7 V in the PG pin description. .................................................................................................... 13
•
Added text to the PG pin description.................................................................................................................................... 13
•
Changed from: V(VCC–OUT) to: V(SENSE–OUT) ............................................................................................................................. 14
•
Added text to the Gate Capacitor (dV/dt) Control section description.................................................................................. 17
•
Added text to the High Gate Capacitance Applications section description......................................................................... 18
•
Added The Input Bypass section description. ...................................................................................................................... 18
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SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
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5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
EN
VREF
PROG
TIMER
GND
1
10
2
9
3
8
4
7
5
6
VCC
SENSE
GATE
OUT
PG
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
EN
I
Device enable
2
VREF
O
Reference voltage output, used to set power threshold on PROG pin
Power-limit setting input
3
PROG
I
4
TIMER
I/O
Fault timing capacitor
5
GND
—
Ground
6
PG
O
Power good reporting output, open-drain
7
OUT
I
Output voltage feedback
8
GATE
O
Gate output
9
SENSE
I
Current-limit sense input
10
VCC
I
Supply input
4
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6
SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC, SENSE, EN
Input voltage
OUT
Output voltage
Sink current
Source current
(2)
MIN
MAX
UNIT
–0.3
100
V
–1
100
V
PROG
–0.3
6
V
GATE, PG
–0.3
100
V
TIMER, VREF
–0.3
6
V
PG
10
mA
PROG
2
mA
VREF
0
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
2
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
OUT will withstand transients to –2 V for 1 ms or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VVCC
Input voltage
9
80
V
VPROG
Input voltage
0.4 (1)
4
V
VOUT
Operating voltage
0
80
V
IVREF
Operating current range (sourcing), VREF
0
1
mA
TJ
Operating junction temperature
–40
125
°C
TA
Operating free-air temperature
–40
85
°C
(1)
VPROG may be set below this minimum with reduced accuracy.
6.4 Thermal Information
THERMAL METRIC
(1)
TPS2490
TPS2491
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
164.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.7
°C/W
RθJB
Junction-to-board thermal resistance
85.5
°C/W
ψJT
Junction-to-top characterization parameter
5.6
°C/W
ψJB
Junction-to-board characterization parameter
84.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and
voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and
all outputs unloaded; positive currents are into pins.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT (VCC)
Enabled
VEN = Hi, VSENSE = VOUT = VVCC
450
1000
µA
Disabled
VEN = Lo, VSENSE = VVCC = VOUT
90
250
µA
VSENSE = VVCC, VOUT = VVCC
7.5
20
µA
4
4.1
V
5
µA
375
600
Ω
CURRENT SENSE INPUT (SENSE)
ISENSE
Input bias current
REFERENCE VOLTAGE OUTPUT (VREF)
VREF
Reference voltage
0 < IVREF < 1 mA
3.9
POWER LIMITING INPUT (PROG)
IPROG
Input bias current, device enabled,
sourcing or sinking
RPROG
Pulldown resistance, device disabled IPROG = 200 µA, VEN = 0 V
0 < VPROG < 4 V, VEN = 48 V
POWER LIMITING AND CURRENT LIMITING (SENSE)
VCL
VSENSE
Current sense threshold V(VCCSENSE) with power limiting trip
VPROG = 2.4 V, VOUT = 0 V or
VPROG = 0.9 V, VOUT = 30 V, VVCC =
48 V
17
25
33
mV
Current sense threshold V(VCCSENSE) without power limiting trip
VPROG = 4 V, VSENSE = VOUT
45
50
55
mV
VTIMER = 0 V
15
25
34
µA
TIMER OPERATION (TIMER)
Charge current (sourcing)
Discharge current (sinking)
VTIMER = 0 V, TJ = 25°C
20
25
30
µA
VTIMER = 5 V
1.5
2.5
3.7
µA
VTIMER = 5 V, TJ = 25°C
2.1
2.5
3.1
µA
3.9
4
4.1
V
V
TIMER upper threshold voltage
TIMER lower reset threshold voltage TPS2491 only
DRETRY
Fault retry duty cycle
0.96
1
1.04
0.5%
0.75%
1%
VSENSE = VVCC, V(GATE-OUT) = 7 V,
VEN = Hi
15
22
35
µA
VEN = Lo, VGATE = VVCC
1.8
2.4
2.8
mA
VEN = Hi, VGATE = VVCC,
V(VCC-SENSE) ≥ 200 mV
75
125
250
mA
16
V
TPS2491 only
GATE DRIVE OUTPUT (GATE)
IGATE
GATE sourcing current
GATE sinking current
GATE output voltage, V(GATE-OUT)
12
POWER GOOD OUTPUT (PG)
IPG = 2 mA
0.1
0.25
V
IPG = 4 mA
0.25
0.5
V
0.8
1.25
1.7
V
2.2
2.7
3.2
V
VPG_L
Low voltage (sinking)
VPGTL
PG threshold voltage, VOUT rising,
PG goes open drain
VSENSE = VVCC, measure V(VCC-OUT)
VPGTH
PG threshold voltage, VOUT falling,
PG goes low
VSENSE = VVCC, measure V(VCC-OUT)
PG threshold hysteresis voltage,
V(SENSE-OUT)
VSENSE = VVCC
ΔVPGT
1.4
Leakage current, PG false, open
drain
V
10
µA
8
20
µA
18
40
µA
OUTPUT VOLTAGE FEEDBACK INPUT (OUT)
IOUT
6
Bias current
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VOUT = VVCC, VEN = Hi, sinking
VOUT = GND, VEN = Lo, sourcing
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SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
Electrical Characteristics (continued)
unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and
voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and
all outputs unloaded; positive currents are into pins.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ENABLE INPUT (EN)
VEN_H
Threshold, VEN going high
1.32
1.35
1.38
VEN_L
Threshold, VEN going low
1.22
1.25
1.28
VEN hysteresis
V
100
Leakage current
VEN = 48 V
mV
1
µA
8.8
V
INPUT SUPPLY UVLO (VCC)
VVCC turn on
Rising
VVCC turn off
Falling
8.4
7.5
Hysteresis
8.3
V
75
mV
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER LIMITING AND CURRENT LIMITING (SENSE)
tF_TRIP
VPROG = 4 V, VOUT = VSENSE,
V(VCC-SENSE): 0 → 200 mV,
C(GATE-OUT) = 2 nF, V(GATE-OUT) = 1
V
Large overload response time to
GATE low
1.2
µs
25
40
µs
GATE DRIVE OUTPUT (GATE)
VEN = 0 → 2.5 V, 50% of VEN to
50% of VGATE, VOUT = VVCC, R(GATEOUT)= 1 MΩ
tD_ON
Propagation delay: EN going true to
GATE output high
tD_OFF
V = 2.5 V → 0, 50% of VEN to
Propagation delay: EN going false (0 EN
50% of VGATE, VOUT = VVCC,
V) to GATE output low
R(GATE-OUT)= 1 MΩ, tFALL < 0.1 µs
0.5
1
µs
V
: 0 → 5 V, tRISE < 0.1 µs, 50%
Propagation delay: TIMER expires to TIMER
of VTIMER to 50% of VGATE, VOUT =
GATE output low
VVCC, R(GATE-OUT) = 1 MΩ,
0.8
1
µs
9
15
ms
POWER GOOD OUTPUT (PG)
tDPG
PG deglitch delay, detection to
output, rising and falling edges
VSENSE = VVCC
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6.7 Typical Characteristics
55
600
I VCC− Supply Current − mA
− Current Limit Trip − mV
V(
VCC − Sense)
TJ = 1255C
550
500
TJ = 255C
450
400
TJ = −405C
350
300
250
200
53
52
TJ = −405C
51
50
TJ = 255C
49
48
TJ = 1255C
47
46
45
9
19
29
39
49
59
VCC − Supply Voltage − V
69
79
9
Figure 1. Supply Current vs Supply Voltage
19
29
39
49
59
VCC − Supply Voltage − V
69
79
Figure 2. Current Limit Trip vs Supply Voltage
2.6
I Gate − Gate Pullup Current (EN = OV) − mA
35
33
I Gate − Gate Pullup Current − mA
54
31
29
27
TJ = 1255C
25
23
TJ = 255C
21
19
TJ = −405C
17
TJ = 1255C
2.5
TJ = 255C
2.4
2.3
TJ = −405C
2.2
2.1
2
15
9
19
29
39
49
59
VCC − Supply Voltage − V
69
9
79
19
29
39
49
59
69
79
VCC − Supply Voltage − V
Figure 4. Gate Pulldown Current (EN = 0 V) vs Supply
Voltage
Figure 3. Gate Pullup Current vs Supply Voltage
215
1200
195
T − Current Limit Response Time − nS
I Gate − Gate Pulldown Current − mA
TJ = 1255C
TJ = −405C
175
TJ = 255C
155
135
115
TJ = 1255C
95
75 9
19
29
39
49
59
VCC − Supply Voltage − V
69
79
Figure 5. Gate Pulldown Current vs Supply Voltage (EN = 4
V, V(VCC – Sense) = 200 mV)
8
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1000
TJ = 255C
800
600
TJ = −405C
400
200
0
9
14
19
24
29
34
39
VCC − Supply Voltage − V
44
49
Figure 6. Current Limit Response Time vs Supply Voltage
(EN = 4 V, V(VCC – Sense) = 200 mV)
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Typical Characteristics (continued)
14.50
32
TJ = 1255C
I Timer − Timer Pullup Current − µ A
VGate − Gate Output Voltage − V
TJ = 1255C
14.25
TJ = 255C
14
TJ = −405C
13.75
28
TJ = 255C
26
24
TJ = −405C
22
20
18
13.50
9
19
29
39
49
59
VCC − Supply Voltage − V
69
9
79
29
19
39
49
59
69
79
VCC − Supply Voltage − V
Figure 8. Timer Pullup Current vs Supply Voltage
Figure 7. Gate Output Voltage vs Supply Voltage
9.80
1.255
VEN − EN Threshold Voltage (Falling) − V
ITimer − Charge/Discharge Ratio
30
9.75
TJ = 255C
TJ = −405C
9.70
TJ = 1255C
9.65
1.254
1.253
1.252
TJ = 1255C
1.251
TJ = 255C
1.250
1.249
TJ = −405C
1.248
1.247
1.246
9.60
9
19
29
39
49
59
VCC − Supply Voltage − V
69
1.245
79
Figure 9. Timer Charge/Discharge Ratio vs Supply Voltage
and Temperature
9
19
29
39
49
59
VCC − Supply Voltage − V
69
79
Figure 10. EN Threshold Voltage (Falling) vs Supply Voltage
VEN − EN Threshold Voltage (Rising) − V
1.351
TJ = 1255C
1.350
TJ = 255C
1.349
1.348
TJ = −405C
1.347
1.346
1.345
9
19
29
39
49
59
VCC − Supply Voltage − V
69
79
Figure 11. EN Threshold Voltage (Rising) vs Supply Voltage
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7 Detailed Description
7.1 Overview
The inline protection functionality of the TPS2490 is designed to control the inrush current to the load upon
insertion of a circuit card into a live backplane or other hot power source, thereby limiting the voltage sag on the
backplane's supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the
system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is
removed can also be implemented using the TPS2490.
In addition to a programmable current limit, the TPS2490 monitors and limits the maximum power dissipation in
the series pass device to maintain operating within the device Safe Operating Area (SOA). Either current limiting
or power limiting for an extended period of time results in the shutdown of the series pass device. In this event,
the TPS2490 will latch off while the TPS2491 will retry an infinite number of timer to recover after the fault is
removed. Programmable EN circuit shuts down the TPS2490 when the system input voltage falls below the
desired operating range.
7.2 Functional Block Diagram
4V
Reference
10
VCC
Enable
2
VREF
Charge
Pump
Constant
Power
Engine
22 mA
A
3
PROG
50 mV max
A
2B
V (DS)
Detector
+
B
+
_
Gate Control
Amplifier
8
GATE
14 V
−
2 mA
I (D)
Detector
+
Power/Current
Amplifier
−
9
SENSE
2.7 V and
1.25 V
8.4 V and
8.3 V
1
EN
1.35 V and
1.25 V
Inrush
Complete
+
_
+
_
7
OUT
6
PG
9 mS
Deglitch
Enable
25 mA
Fault
Logic
UVLO
+
_
4V
and
1V
+
_
Enable
Timer
2.5 mA
POR
For Autoretry Option with
Duty Cycle of 0.75%
5
GND
4
TIMER
10
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7.3 Feature Description
7.3.1
VCC
This pin is associated with three functions:
1. Biasing power to the integrated circuit
2. Input to power on reset (POR) and undervoltage lockout (UVLO) functions
3. Voltage sense at one terminal of RS for Q1 current measurement
The voltage must exceed the POR (about 6 V for approximately 400 µs) and the internal UVLO (about 8 V)
before normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RS
voltage sensing errors and to maximize the effect of C1 and Z1; place C1 at RS rather than at the IC pin to
eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR are
active.
7.3.2 SENSE
Monitors the voltage at the drain of Q1, and the downstream side of RS providing the constant power limit engine
with feedback of both Q1 current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE
and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses
VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The
current limit is set by Equation 1:
I LIM + 50 mV
RS
(1)
Design the connections to SENSE to minimize RS voltage sensing errors. Don't drive SENSE to a large voltage
difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by
connecting SENSE to VCC.
7.3.3 GATE
Provides the high side (above VCC) gate drive for Q1. It is controlled by the internal gate drive amplifier, which
provides a pull-up of 22 µA from an internal charge pump and a strong pulldown to ground of 75 mA (minimum).
The pulldown current is a nonlinear function of the amplifier overdrive; it provides small drive for small overloads,
but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut Q1 off when
EN or UVLO cause this to happen. An internal clamp protects the gate of Q1 (to OUT) and generally eliminates
the need for an external clamp in almost all cases for devices with 20-V VGS(MAX) ratings; an external Zener may
be required to protect the gate of devices with VGS(MAX) < 16 V. A small series resistance (R5) of 10 Ω must be
inserted in the gate lead if the CISS of Q1 > 200 pF, otherwise use 33 Ω for small MOSFETs.
A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile
without affecting the amplifier stability. Add a series resistor of about 1 kΩ to the gate capacitor to maintain the
gate clamping and current limit response time. Adding capacitance across Q1 gate to source requires some
series damping resistance to avoid high-frequency oscillations.
7.3.4 OUT
This input pin is used by the constant power engine and the PG comparator to measure VDS of Q1 as V(SENSEOUT). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can drive OUT
below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND (anode).
7.3.5 EN
The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds
have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by
R1/R2 in the Figure 17 circuit, or it can be tied to VCC to always enable the TPS249x. The hysteresis associated
with the internal comparator makes this a stable method of detecting a low input condition and shutting the
downstream circuits off. A TPS2490 that has latched off can be reset by cycling EN below its negative threshold
and back high.
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Feature Description (continued)
7.3.6 VREF
Provides a 4-V reference voltage for use in conjunction with R3/R4 of the typical application circuit to set the
voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds have
been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA is
drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be
placed on this pin.
7.3.7 PROG
The voltage applied to this pin (0.4 to 4 V) programs the power limit used by the constant power engine.
Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to
Equation 2:
P LIM
V PROG +
10 I LIM
where
•
•
PLIM is the desired power limit of Q1
ILIM is the current limit setpoint (see SENSE).
(2)
PLIM is determined by the desired thermal stress on Q1:
T J(MAX) * T S(MAX)
P LIM t
R qJC(MAX)
where
•
•
TJ(MAX) is the maximum desired transient junction temperature of Q1
TS(MAX) is the maximum case temperature prior to a start or restart.
(3)
VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine.
ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID <
ID_ALLOWED, the amplifier turns the gate of Q1 fully on because there is no overload condition; otherwise GATE is
regulated to maintain the ID = ID_ALLOWED relationship.
A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If
properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp.
PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off.
This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to
PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor.
7.3.8 TIMER
An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the fault-time for
both versions and the restart interval for the TPS2491. The timer charges at 25 µA whenever the TPS249x is in
power limit or current limit and discharges at 2.5 µA otherwise. The charge-to-discharge current ratio is constant
with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the
TPS2490 pulls GATE to ground, latch off, and discharge CT. The TPS2491 pulls GATE to ground and attempt a
restart (reenable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more
charge and discharge cycles. The TPS2490 can be reset by either cycling the EN pin or the UVLO (for example,
power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin should be tied to
ground if this feature is not used.
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Feature Description (continued)
7.3.9 PG
This open-drain output is intended to interface to downstream DC/DC converters or monitoring circuits. PG goes
open drain (high voltage with a pullup) after VDS of Q1 has fallen to about 1.25 V and a 9-ms deglitch time period
has elapsed. PG is false (low or low resistance to ground) whenever VDS of Q1 has not been less than 1.25 V,
VDS of Q1 is above 2.7 V, or UVLO is active. Both VDS rising and falling are deglitched while entering UVLO sets
PG low immediately. PG can also be viewed as having an input and output voltage monitor function. The 9-ms
deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary
overload or input voltage step. VPG voltage can be greater than VVCC because it’s ESD protection is only with
respect to ground.
7.3.10 GND
This pin is connected to system ground.
7.4 Device Functional Modes
The TPS249x devices provide all the features needed for a positive hot swap controller. These features include:
1. undervoltage lockout (UVLO)
2. adjustable (system-level) enable
3. turnon inrush limit
4. high-side gate drive for an external N-channel MOSFET
5. MOSFET protection (power limit and current limit)
6. adjustable overload timeout—also called an electronic circuit breaker
7. charge-complete indicator for downstream converter coordination
8. an optional automatic restart mode
The TPS249x devices feature superior power-limiting MOSFET protection that allows independent control of
current limit (to set maximum full-load current), power limit (to control junction temperature rise), and overload
time (to control case temperature rise).
The typical application circuit, and oscilloscope plots of Figure 12 through Figure 16 demonstrate many of the
functions described Device Functional Modes.
7.4.1 Board Plug-In (Figure 12)
Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in.
The TPS249x is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while internal
voltages stabilize. A start-up cycle is ready to take place after the stabilization.
GATE, PROG, TIMER, and PG are released after stabilization in this example because both the internal UVLO
threshold and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from
the GATE pin and Q1 begins to turn on while the voltage across it, V(SENSE–OUT), and current through it,
V(VCC–SENSE), are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM ÷ VVCC)
since the output capacitor was discharged.
7.4.2 TIMER and PG Operation (Figure 12)
The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when
limiting stops. If the voltage on CT reaches 4 V before the output is charged, Q1 is turned off and either a latchoff or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched
end-of-charge indication which is based on the voltage across Q1. PG is useful for preventing a downstream
DC/DC converter from starting while CO is still charging. PG goes active (open drain) about 9 ms after CO is
charged. This delay allows Q1 to fully turn on and any transients in the power circuits to end before the converter
starts up. The resistor pullup shown on pin PG in Typical Application only demonstrates operation; the actual
connection to the converter depends on the application. Timing can appear to terminate early in some designs if
operation transitions out of the power limit mode into a gate charge limited mode at low VDS values.
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Device Functional Modes (continued)
VCC
VCC
CH1
10 V/div
PG
10 V/div
IIN 1 A/div
Timer 1 V/div
OUT
10 V/div
t - Time - 2 ms/div
Figure 12. Basic Board Insertion
7.4.3 Action of the Constant Power Engine (Figure 13)
The calculated power dissipated in Q1, VDS ×ID, is computed under the same startup conditions as Figure 12 .
The current of Q1, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is
34 W ÷ 48 V = 0.7 A. The 34 W value is programmed into the engine by setting the PROG voltage using
Equation 2 given in the PROG. VDS of Q1, which is calculated as V(SENSE–OUT), falls as CO charges, thus allowing
the Q1 drain current to increase. This is the result of the internal constant power engine adjusting the current limit
reference to the GATE amplifier as CO charges and VDS falls. The calculated device power in Figure 13, labeled
FET PWR, is seen to be flat-topped and constant within the limitations of circuit tolerance and acquisition noise.
A fixed current limit is implemented by clamping the constant power engine’s output to 50 mV when VDS is low.
This protection technique can be viewed as a specialized form of foldback limiting; the benefit over linear
foldback is that it yields the maximum output current from a device over the full range of VDS and still protects the
device.
VCC − OUT
10 V/div
FET PWR 10 W/div
VOUT 10 V/div
IIN
1 A/div
M1 Power Measured 29.6 W,
Calculated 34.4 W
t - Time - 2 ms/div
Figure 13. Computation of Q1 Stress During Startup
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Device Functional Modes (continued)
7.4.4 Response to a Hard Output Short (Figure 14 and Figure 15)
Figure 14 shows the short circuit response over the full time-out period. The period begins when the output
voltage falls and ends when Q1 is turned off. Q1 current is actively controlled by the constant power engine and
gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold causing Q1 to be turned off. The
TPS2490 latches off after the threshold is reached until either the input voltage drops below the UVLO threshold
or EN cycles through the false (low) state. The TPS2491 goes through a timing sequence before attempting a
restart.
IIN
0.5 A/div
TIMER
1 V/div
GATE 10 V/div
OUT 10 V/div
t - Time - 2 ms/div
Figure 14. Current Limit Overview
The TPS249x responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result of
Q1 and CO currents through the short’s impedance at this time scale. The internal GATE clamp causes the
GATE voltage to follow the output voltage down and subsequently limits the negative VGS to 1 V to 2 V. The
rapidly rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn Q1 off by sinking
current to ground. Q1 slowly turns back on as the GATE amplifier recovers; Q1 then settles to an equilibrium
operating point determined by the power limiting circuit.
GATE 10 V/div
VCC 10 V/div
OUT 10 V/div
IIN
5A/div
t - Time - 500 ns/div
Figure 15. Current Limit Onset
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Device Functional Modes (continued)
Minimal input voltage overshoot appears in Figure 15 because a local 100-µF bypass capacitor and very short
input leads were used. The input voltage would overshoot as the input current abruptly drops in a typical
application due to the stored energy in the input distribution’s inductance. The exact waveforms seen in an
application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short
itself.
7.4.5 Automatic Restart (Figure 16)
The TPS2491 automatically initiates a restart after a fault has caused it to turn off Q1. Internal control circuits use
CT to count 16 cycles before re-enabling Q1. This sequence repeats if the fault persists. The TIMER has a 1:10
charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle specification
quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation to levels
associated with normal operation and eliminates special thermal considerations for surviving a prolonged output
short.
GATE 10 V/div
OUT 10 V/div
TIMER 1 V/div
IIN
.5 A/div
t - Time - 200 ms/div
Figure 16. TPS2491 Restart Cycle Timing
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS2490 is a hot swap controller that provides inrush current limiting, electronic circuit breaker protection,
controlled load turn-on, interfacing to down-stream dc-to-dc converters, and power feed protection. As a hot
swap it is used to manage inrush current and protect in case of faults. When designing a hot swap three key
scenarios should be considered:
• Start-up
• Output of a hot swap is shorted to ground when the hot swap is on. This is often referred to as a hot-short.
• Powering up a board when the output and ground are shorted. This is usually called a start-into-short.
All of these scenarios place a lot of stress on the hot swap MOSFET and thus special care is required when
designing the hot swap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the
following sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI
recommends using the TPS2490/91 Design-in Calculator (SLVC033), which is provided on the product page.
8.1.1 Alternative Inrush Designs
8.1.1.1 Gate Capacitor (dV/dt) Control
The TPS249x can be used with applications that require constant turn-on currents. The current is controlled by a
single capacitor from the GATE terminal to ground with a series resistor. Q1 appears to operate as a source
follower (following the gate voltage) in this implementation. Choose a time to charge, Δt, based on the output
capacitor, input voltage VI, and desired charge current, ICHARGE. Select ICHARGE to be less than PLIM ÷ VVCC if the
power limit feature is kept. See TPS2490/91 Design-in Calculator (SLVC033) for a calculation tool.
C
V VCC
Dt + O
I CHARGE
(4)
To select the gate capacitance:
æ
Δt ö
CG = ç IGATE ´
÷ - CRS
VVCC ø
è
where
•
IGATE is the nominal gate charge current.
(5)
This equation assumes that the MOSFET CGD is the controlling element as the gate and output voltage rise. CGD
is non-linear with applied VDG. An averaged estimate may be made using the MOSFET VGS vs QG curve. Divide
the charge accumulated during the plateau region by the plateau VGS to get CRS.
Because neither power nor current-limit faults are invoked during turnon, CTIMER can be chosen for fast transient
turnoff response using the Q1 SOA curve. Choose the single pulse time conservatively from the Q1 SOA curve
using maximum operating voltage and maximum trip current. A series resistor of about 1 kΩ should be used in
conjunction with CG.
8.1.1.2 PROG Inrush Control
A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12
based on the Typical Application circuit. This method maintains a relatively fast turn-on time without the
drawbacks of a gate-to-ground capacitor that include increased short circuit response time and less predictable
gate clamping.
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Application Information (continued)
8.1.2 Additional Design Considerations
8.1.2.1 Use of PG
Use the PG pin to control and coordinate a downstream dc/dc converter. A long time delay is needed to allow CO
to fully charge before the converter starts if this is not done. An undesirable latchup condition can be created
between the TPS2490 output characteristic and the DC/DC converter input characteristic if the converter starts
while CO is still charging; the PG pin is one way to avoid this.
8.1.2.2 Faults and Backplane Voltage Droop
A hard short at the output of the TPS249x during normal operation could result in activation of the enable or
UVLO circuit instead of the current limit if the input voltage droops sufficiently. The lower GATE drive in this
condition will cause a prolonged, larger over-current spike. This can be eliminated by filtering EN, or distributing
capacitance on the bus itself. Capacitance from adjacent plugged-in units may help with this as well.
8.1.2.3 Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current limit. The OUT pin ratings can be maintained with a diode, such as an D1, across TPS249x OUT to GND.
8.1.2.4 Gate Clamp Diode
The TPS249x has a relatively well-regulated gate voltage of 12 V to 16 V, even with low-supply voltages. A small
clamp Zener from gate to source of Q1, such as a BZX84C7V5, is recommended if VGS of Q1 is rated below this
range.
8.1.2.5 High Gate Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. TI
recommends an external gate clamp Zener diode to assist the internal Zener if the total gate capacitance of Q1
exceeds about 4000 pF. When gate capacitor dv/dt control is used, TI recommends a 1-kΩ resistor in series with
CG. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not
necessary.
8.1.2.6 Input Bypass
CIN should be present for control of external noise at VCC and as a low-impedance source for high-speed
circuits.
8.1.2.7 Output Short Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to obtaining different results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet—every setup differs.
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8.2 Typical Application
This section describes the design procedure for a 24-V, 10-A hot swap design.
VIN
RSNS
VOUT
Q1
CIN
Z1
COUT
D1
R5
Only required when
using dv/dt start-up
GATE OUT
SENSE
470 NŸ
R1
VCC
1 NŸ
PG
TPS2490/91
EN
Cdv/dt
VREF
R2
R3
PROG
TIMER
GND
CTIMER
R4
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Figure 17. Typical Application Schematic, TPS2490
8.2.1 Design Requirements
Table 1 summarizes the design parameters that must be known before designing a hot swap circuit. When
charging the output capacitor through the hot swap MOSFET, the FET’s total energy dissipation equals the total
energy stored in the output capacitor (1/2CV2). Thus both the input voltage and Output capacitance will
determine the stress experienced by the MOSFET. The maximum load current will drive the current limit and
sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and the thermal
properties of the PCB (RθCA) will drive the selection of the MOSFET RDSON and the number of MOSFETs used.
RθCA is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET.
Note that the drain is not electrically connected to the ground plane and thus the ground plane cannot be used to
help with heat dissipation. For this design example RθCA = 30°C/W is used, which is similar to the TPS2490 EVM.
It’s a good practice to measure the RθCA of a given design after the physical PCBs are available.
Finally, it is important to understand what test conditions the hot swap needs to pass. In general, a hot swap is
designed to pass both a Hot-Short and a Start into a Short, which are described in the previous section. Also, TI
recommends to keep the load OFF until the hot swap is fully powered up. Starting the load early causes
unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start-up.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
18 V - 30 V
Target UVLO Threshold
18 V
Maximum load current
10 A
Maximum Output Capacitance of the Hot
swap
330 µF
Maximum Ambient Temperature
55°C
MOSFET RθCA (function of layout)
30°C/W
Pass Hot-Short on Output?
Yes
Pass a Start into short?
Yes
Is the load off until PG asserted?
Yes
Can a hot board be plugged back in?
Yes
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8.2.2 Detailed Design Procedure
8.2.2.1 Select RSNS and CL setting
The TPS2490 monitors the current in the external MOSFET (Q1) by measuring the voltage across the sense
resistor (RS), connected from VIN to SENSE. When the voltage difference across the Vin and Sense pins (VCL)
is greater than 50 mV(typical), the LM5069 will begin regulating the MOSFET gate. Size RSNS for maximum or
minimum VCL for applications that require guaranteed shutoff or guaranteed conduction. In this design example,
RSNS is sized to exhibit minimum VCL across RSNS at maximum load current.
R SNS,CLC
V CL
45 mV
10 A
I LIM
4.5 m:
(6)
Typically sense resistors are only available in discrete values. If a precise current limit is desired, a sense
resistor along with a resistor divider can be used as shown in Figure 18.
RSNS
R2
R1
VCC
SENSE
Figure 18. SENSE Resistor Divider
If using a resistor divider, then the next larger available sense resistor should be chosen (1 mΩ for example).
The ratio of R1 and R2 can then be computed as follows:
R3
R SNS,CLC
R4
R SNS R SNS,CLC
4.5 m:
5 m: 4.5 m:
9
(7)
Note that the SENSE pin typically pulls 7.5 µA of current, which creates an offset across R2. TI recommends to
keep R2 below 10 Ω to reduce the offset that this introduces. In addition the 1% resistors add to the current
monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense
resistance (RSNS,EFF) using Equation 8 instead of RSNS in all equations.
R SNS,EFF
R SNS u R 3
R3
R4
(8)
Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the
next smaller available sense resistor. For this application, a resistive divider was not used, and a 4 mΩ resistor
was used for a 12.5 A (typical) current limit.
8.2.2.2 Selecting the Hot Swap FET(s)
It is critical to select the correct MOSFET for a hot swap design. The device must meet the following
requirements:
• The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by
transients. For most 12-V systems a 30-V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of
the FET. TI recommends to keep the steady state FET temperature below 125°C to allow margin to handle
transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current
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must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three
requirements also pass these two.
A VGS rating of ±20 V is required, because the TPS2490 can pull up the gate as high as 16 V above source.
For this design the CSD19532KTT was selected for its low RDSON and good SOA. After selecting the MOSFET,
the maximum steady state case temperature can be computed as follows:
T C,MAX
T A,MAX
2
R TCA u I LOAD,MAX
u R DSON TJ
(9)
Note that the RDSON is a strong function of junction temperature, which for most MOSFETs will be close to the
case temperature. A few iterations of the above equations may be necessary to converge on the final RDSON and
TC,MAX value. According to the CSD17552Q5B datasheet, its RDSON is approximately 1.4x at 78°C. The
Equation 10 uses this RDSON value to compute the TC,MAX.
T C,MAX
55 qC 30 q
C
u 10 A
W
2
u 1.4 u 5.6 m:
78.5 qC
(10)
This maximum steady state case temperature indicates that a second MOSFET is not needed to reduce and
distribute power dissipation during normal operation.
For reference, when using parallel MOSFETs, the maximum steady state case temperature can be computed as
follows:
2
T C,MAX
TA,MAX
R TCA
§ I LOAD,MAX ·
u ¨¨
¸¸ u R DSON TJ
© # of MOSFETs ¹
(11)
Iterate until the computed TC,MAX is using two parallel MOSFETs is less than to the junction temperature
assumed for RDSON. Then, no further iterations are necessary.
8.2.2.3 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the
TPS2490 is set to a very low power limit setting, it has to regulate the FET current and hence the voltage across
the sense resistor (VSNS) to a very low value. VSNS can be computed as shown in Equation 12:
PLIM u R SNS
V SNS
V DS
(12)
To avoid significant degradation of the power limiting accuracy, a VSNS of less than 5 mV is not recommended.
Based on this requirement the minimum allowed power limit can be computed as follows:
PLIM,MIN
V SNS,MIN u VIN,MAX
5 mV u 30 V
4 m:
R SNS
37.5 W
(13)
Because the VPROG pin, which programs the power limit of the device, has a minimum voltage of 0.4 V, the set
PLIM must also result in the voltage at VPROG being greater than 0.4 V. Based on this requirement the minimum
allowed power limit can be computed as follows:
PLIM,MIN
V PROG * I LIM MAX * 10
0.4 * 12.5 * 10
50 W
(14)
Because the power limit has to satisfy both the VSNS and VPROG, the greater PLIM,MIN value is used as the basis
for sizing the resistive divider. In this design example it is 50 W. The maximum ratio of the resistive divider can
be computed as follows:
R3
R4
V REF
V PROG
1
V REF
PLIM,MIN
10 * I LIM
1
4V
50 W
10 * 12.5
1 9
(15)
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In Equation 16 R3 is picked as 41.2 kΩ. R3 must be greater than 4 kΩ, but TI recommends that 10 kΩ or greater
be used. The resistive divider ratio is used to calculate R4, and next largest available resistor is chosen.
1
*R3
R3
R4
1
* 41.2 k:
9
4.58 k:
R4
(16)
We choose 4.64 kΩ for our final value of R4.
8.2.2.4 Set Fault Timer
The fault timer runs when the hot swap is in power limit or current limit, which is the case during start-up. Thus
the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current
limit (ILIM x VDS < PLIM) the maximum start time can be computed with Equation 17:
C OUT u V IN,MAX
t start,max
I LIM
(17)
For most designs (including this example) ILIM x VDS > PLIM so the hot swap will start in power limit and transition
into current limit. In that case the start time can be computed as follows:
C OUT
t start
2
ª V2
IN,MAX
u«
« PLIM,TYP
¬
PLIM,TYP º
»
2
»
I LIM
¼
330 PF ª (30 V) 2
u«
2
¬« 50 W
º
»
(12.5 A) ¼»
50 W
2
2.92 ms
(18)
The actual startup time is slightly longer, as the power limit is a function of VDS and decreases as the output
voltage increases. To ensure that the timer never times out during start-up, TI recommends to set the fault time
(tflt) to be 1.75 x tstart or 5.11ms. This accounts for the variation in power limit, timer current, and timer
capacitance. Thus CTIMER can be computed as follows:
C TIMER
t flt u i timer
v timer
5.11 ms u 25 PA
4V
32 nF
(19)
The next largest available CTIMER is chosen as 33 nF. Once the CTIMER is chosen the actual programmed fault
time can be computed as follows:
t flt
C TIMER u v timer
i timer
33 nF u 4 V
25 PA
5.28 ms
(20)
8.2.2.5 Check MOSFET SOA
Once the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all
test conditions. During a Hot-Short the circuit breaker trips and the TPS2490 restarts into power limit until the
timer runs out. In the worst case the MOSFET’s VDS will equal VIN,MAX, IDS will equal PLIM / VIN,MAX and the stress
event will last for tflt. For this design example the MOSFET has 30 V, 1.83 A across it for 5.28 ms.
Based on the SOA of the CSD19532KTT, it can handle 30 V, 2.4 A for 10 ms and it can handle 30 V, 11A for
1ms. The SOA for 5.28 ms can be extrapolated by approximating SOA vs time as a power function as shown in
Equation 21 through Equation 24:
I SOA t
m
22
autm
(21)
ln(I SOA t 1 / I SOA t 2
ln t 1 / t 2
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§ 12 A ·
ln ¨
¸
© 2.4 A ¹
§ 1 ms ·
ln ¨
¸
© 10 ms ¹
0.7
(22)
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a
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I SOA t 1
t 1m
I SOA 6.24 ms
2.3 A
0.7
10 ms
2.4 A u 10 ms
0.7
(23)
2.4 A u 10 ms
0.7
u 5.28 ms
0.7
3.75 A
(24)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using Equation 25 through
Equation 26:
I SOA 5.28 ms, T C,MAX
3.75 u
I SOA 5.28 ms,25 qC u
175 qC 78.5 qC
175 qC 25 qC
T J,ABSMAX
T C,MAX
T J,ABSMAX
25 qC
(25)
2.41 A
(26)
Based on this calculation the MOSFET can handle 2.41 A, 30 V for 5.28 ms at elevated case temperature, but is
required to handle 1.83 A during a hot-short. This means the MOSFET will not be at risk of getting damaged
during a hot-short. In general, TI recommends for the MOSFET to be able to handle a minimum of 1.3x more
power than what is required during a hot-short in order to provide margin to cover the variance of the power limit
and fault time.
8.2.2.6 Set Under-Voltage Threshold
For this design example, the following values are targeted: VUVH = 18 V, VUVL = 17 V. First, pick R2 to be a
common value such as 10 kΩ. R1 can be computed using the Equation 27:
§ V UV
·
R1 ¨¨
1¸¸ * R2
© 1.35 V
¹
§ 18
·
1¸ * 10 k:
¨
1.35
V
©
¹
123.3 k:
(27)
Nearest available 1% resistors should be chosen. Set R1 = 124 kΩ, R2 = 10 kΩ.
8.2.2.7 Choose R5, and CIN
R5 is intended to suppress high-frequency oscillations; a resistor of 10 Ω will serve for most applications but if
Q1 has a CISS below 200 pF, then use 33 Ω. Applications with larger MOSFETs and short wiring may not require
R5. CIN is a bypass capacitor to help with control of transient voltages, unit emissions, and local supply noise
while in the disabled state. Where acceptable, TI recommends a value in the range of 0.001 µF to 0.1 µF.
8.2.2.8 Input and Output Protection
Proper operation of the TPS2490 hot swap circuit requires a voltage clamping element present on the supply
side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in . The TVS is
necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current.
This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET
shuts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage during
hot-short events. For many high power applications, SMBJ30A-13-F is a good choice.
8.2.2.9 Final Schematic and Component Values
shows the schematic used to implement the requirements described in the previous section. In addition, Table 2
provides the final component values that were used to meet the design requirements for a 24-V, 10-A hot swap
design. The Application Curves are based on the component values in Table 2.
Table 2. Component Values
COMPONENT
VALUE
RSNS
4 mΩ
R1
124 kΩ
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Table 2. Component Values (continued)
COMPONENT
VALUE
R2
10 kΩ
R3
41.2 kΩ
R4
4.64 kΩ
Q1
CSD19532KTT
Z1
SMBJ30A-13-F
CTIMER
33 nF
8.2.3 Application Curves
24
Figure 19. Start-Up
Figure 20. Start-Up into Short Circuit
Figure 21. Under-Voltage
Figure 22. Gradual Over-Current
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Figure 23. Loadstep
Figure 24. Hotshort on Output
Figure 25. Hotshort (Zoomed-In)
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9 Power Supply Recommendations
In general, the TPS2490 behavior is more reliable if it is supplied from a very regulated power supply. However,
high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is
expected in the end system, TI recommends placing a 1-µF ceramic capacitor to ground close to the drain of the
hot swap MOSFET. This reduces the common mode voltage seen by VCC and SENSE. Additional filtering may
be necessary to avoid nuisance trips.
10 Layout
10.1 Layout Guidelines
10.1.1 PC Board Guidelines
The following guidelines must be followed when designing the PC board for the TPS2490:
• Place the TPS2490 close to the board's input connector to minimize trace inductance from the connector to
the FET.
• Note that special care must be taken when placing the bypass capacitor for the VCC pin. During hot shorts,
there is a very large dV/dt on input voltage after the MOSFET turns off. If the bypass capacitor is placed right
next to the pin and the trace from Rsns to the pin is long, an LC filter is formed. As a result, a large differential
voltage can develop between VCC and SENSE. To avoid this, place the bypass capacitor close to Rsns
instead of the VCC pin.
• The sense resistor (RS) must be close to the TPS2490, and connected to it using Kelvin techniques.
• The high current path from the board's input to the load (via Q1), and the return path, must be parallel and
close to each other to minimize loop inductance.
• The ground connection for the various components around the TPS2490 must be connected directly to each
other and to the TPS2490's GND pin, and then connected to the system ground at one point. Do not connect
the various component grounds to each other through the high current ground line.
• Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turnon and
turnoff.
• The board's edge connector can be designed to shut off the TPS2490 as the board is removed, before the
supply voltage is disconnected from the TPS2490. A shorter edge connector pin can be used for the EN
signal going to the TPS2490. In this case, when the board is inserted into the edge connector, the system
voltage is applied to the TPS2490's VCC pin before the EN voltage is taken high.
10.1.2 System Considerations
A) Continued proper operation of the LM5069 hot swap circuit requires capacitance be present on the supply
side of the connector into which the hot swap circuit is plugged in, as depicted in . The capacitor in the Live
Backplane section is necessary to absorb the transient generated whenever the hot swap circuit shuts off the
load current. If the capacitance is not present, inductance in the supply lines generate a voltage transient at shutoff which can exceed the absolute maximum rating of the TPS2490, resulting in its destruction.
B) If the load powered via the TPS2490 hot swap circuit has inductive characteristics, a diode is required across
the TPS2490’s output. The diode provides a recirculating path for the load’s current when the TPS2490 shuts off
that current. Adding the diode prevents possible damage to the TPS2490 as the OUT pin is taken below ground
by the inductive load at shutoff. See Figure 26.
26
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Layout Guidelines (continued)
RS
VSYS
VOUT
Q1
+48 V
LIVE
BACKPLANE
OUT
VCC
CL
Inductive
Load
TPS2490
GND
GND
PLUG-IN BOARD
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Output Diode Required for Inductive Loads
10.2 Layout Example
Rsns
R
R
R
Source
R
C
Hot Swap
C
Output Caps
C
IC GND
High Current GND
Figure 27. TPS249x Quiet IC Ground Layout
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TPS2490, TPS2491
SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
www.ti.com
11 Device and Documentation Support
11.1 Development Support
For the TPS2490, TPS2491 Design Calculator Tool see TPS2490/91 Design-in Calculator (SLVC033)
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Robust Hot Swap Design, (SLVA673)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2490
Click here
Click here
Click here
Click here
Click here
TPS2491
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
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SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA00165DGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIY
TPS2490DGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIY
TPS2490DGSG4
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIY
TPS2490DGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIY
TPS2490DGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIY
TPS2491DGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIX
TPS2491DGSG4
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIX
TPS2491DGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIX
TPS2491DGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BIX
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
12-Aug-2017
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS2490DGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPS2491DGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2490DGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
TPS2491DGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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