Texas Instruments | UCC27712-Q1 Automotive, 620-V, 1.8-A, 2.8-A High-Side Low-Side Gate Driver with Interlock | Datasheet | Texas Instruments UCC27712-Q1 Automotive, 620-V, 1.8-A, 2.8-A High-Side Low-Side Gate Driver with Interlock Datasheet

Texas Instruments UCC27712-Q1 Automotive, 620-V, 1.8-A, 2.8-A High-Side Low-Side Gate Driver with Interlock Datasheet
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UCC27712-Q1
SLUSCW3 – AUGUST 2017
UCC27712-Q1 Automotive, 620-V, 1.8-A, 2.8-A High-Side Low-Side Gate Driver
with Interlock
1 Features
3 Description
•
The UCC27712-Q1 is a 620-V high-side and low-side
gate driver with 1.8-A source, 2.8-A sink current,
targeted to drive power MOSFETs or IGBTs.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Application
– Device HBM Classification Level 1C
– Device CDM Classification Level C4B
High-Side and Low-Side Configuration
Dual Inputs With Output Interlock and 150-ns
Deadtime
Fully Operational up to 620-V, 700-V Absolute
Maximum on HB Pin
10-V to 20-V VDD Recommended Range
Peak Output Current 2.8-A Sink, 1.8-A Source
dv/dt Immunity of 50 V/ns
Logic Operational up to –11 V on HS Pin
Negative Voltage Tolerance On Inputs of –5 V
Large Negative Transient Safe Operating Area
UVLO Protection for Both Channels
Small Propagation Delay (100-ns Typical)
Delay Matching (12-ns Typical)
Low Quiescent Current
TTL and CMOS Compatible Inputs
Industry Standard SOIC-8 Package
All Parameters Specified Over Temperature
Range, –40 °C to +125 °C
2 Applications
•
•
•
Automotive Inverters
On-Board Chargers (PFC, Phase-Shifted Full
Bridge)
Motor Drive for Automotive Applications (Stepper
Motors, Fans)
The recommended VDD operating voltage is 10-V to
20-V for IGBT's and 10-V to 17-V for power
MOSFETs.
The UCC27712-Q1 includes protection features
where the outputs are held low when the inputs are
left open or when the minimum input pulse width
specification is not met. Interlock and deadtime
functions prevent both outputs from being turned on
simultaneously. In addition, the device accepts a wide
range bias supply range from 10 V to 22 V, and offers
UVLO protection for both the VDD and HB bias
supply.
Developed with TI's state of the art high-voltage
device technology, the device features robust drive
with excellent noise and transient immunity including
large negative voltage tolerance on its inputs, high
dV/dt tolerance, wide negative transient safe
operating area (NTSOA) on the switch node (HS),
and interlock.
The device consists of one ground-referenced
channel (LO) and one floating channel (HO) which is
designed for operating with bootstrap or isolated
power supplies. The device features fast propagation
delays and excellent delay matching between both
channels. On the UCC27712-Q1, each channel is
controlled by its respective input pins, HI and LI.
Device Information (1)
PART NUMBER
(1)
4
PACKAGE
UCC27712-Q1
BODY SIZE (NOM)
SOIC (8)
3.91 mm × 8.65 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Bias
Typical Propagation Delay Comparison
Up to 600 V
300
UCC27712-Q1
3 VDD
HB
8
2 HI
HO
7
HS
6
LO
5
COM
4
PWM
Controller
PWM1
PWM2
1
Load
LI
GND
Propagation Delay (ns)
250
Competitor
TI
200
150
100
50
Copyright © 2017, Texas Instruments Incorporated
0
-40
-20
0
20
40
60
Temperature (oC)
80
100
120
Typi
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27712-Q1
SLUSCW3 – AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
3
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Dynamic Electrical Characteristics ...........................
Typical Characteristics ..............................................
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application ................................................. 26
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
12.6
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2017
*
Initial release.
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6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
LI
1
8
HB
HI
2
7
HO
VDD
3
6
HS
COM
4
5
LO
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COM
4
–
Ground
HB
8
I
High-side floating supply. Bypass this pin to HS with a suitable capacitor to sustain boot-strap
circuit operation, typically 10 times bigger than the MOSFETs/IGBTs gate capacitance.
HI
2
I
Logic input for high-side driver. If HI is unbiased or floating, HO is held low
HO
7
O
High-side driver output.
HS
6
–
Return for high-side floating supply.
LI
1
I
Logic input for low-side driver. If LI is unbiased or floating, LO is held low
LO
5
O
Low-side driver output.
VDD
3
I
Bias supply input. Power supply for the input logic side of the device and also low-side driver
output. Bypass this pin to COM with a 0.1-µF or larger value ceramic capacitor.
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise
noted), currents are positive into and negative out of the specified terminal. (1)
PARAMETER
MIN
MAX
–5
22
VDD supply voltage
–0.3
22
HB
–0.3
700
HI, LI
Input voltage
(2)
HB–HS
HO
Output voltage
LO
–0.3
22
HS–0.3
HB+0.3
Transient, less than 100 ns (3)
HS–2
HB+0.3
DC
–0.3
VDD+0.3
–2
VDD+0.3
DC
Transient, less than 100 ns (3)
IOUT_PULSED (100 ns)
HO, LO
dVHS/dt
Allowable offset supply voltage transient
–50
50
TJ
Junction temperature
–40
150
Tstg
Storage temperature
–65
150
(2)
(3)
V
V
V
2.8/–1.8
Output current
(1)
UNIT
IOUT_DC
A
0.15
V/ns
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum voltage on the input pins is not restricted by the voltage on the VDD pin
Values are verified by characterization on bench.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±1500
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
All voltages are with respect to COM, over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
HB–HS
Driver bootstrap voltage
HS
Source terminal voltage (1)
HI, LI
Input voltage with respect to COM
TA
Ambient temperature
(1)
NOM
MAX
IGBT applications
10
20
MOSFET applications
10
17
IGBT applications
10
20
MOSFET applications
10
17
–11
600
–4
20
–40
125
UNIT
V
°C
Logic operational for HS of –11 V to +600 V at HB–HS = 15 V
7.4 Thermal Information
UCC27712-Q1
THERMAL METRIC
(1)
(SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
108.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.5
°C/W
RθJB
Junction-to-board thermal resistance
57.9
°C/W
ψJT
Junction-to-top characterization parameter
15.3
°C/W
ψJB
Junction-to-board characterization parameter
57.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY BLOCK
VVDD
ON
Turn-on threshold voltage of VDD
8.0
8.9
9.8
VVDD
OFF
Turn-off threshold voltage of VDD
7.5
8.4
9.3
HYS
Hysteresis of VDD
VVDD
0.5
VVHB ON
Turn-on threshold voltage of
VHB–VHS
7.2
8.2
9.2
VVHB OFF
Turn-off threshold voltage of
VHB–VHS
6.4
7.3
8.3
VVHB HYS
Hysteresis of VHB–VHS
IQ
Total quiescent supply current
IQVDD
Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state
IQBS
Quiescent HB-HS supply current
HI = 0 V or 5 V, HO in DC on/off
state
IBL
Bootstrap supply leakage current
HB = HS = 600 V
IOP
Dynamic operating current
HI = LI = 0 V or 5 V, f = 100 kHz,
duty = 50%, CL= 1 nF
(1)
4
HI = LI = 0 V or 5 V, DC on/off state
0.5
0.9
180
255
420
190
320
65
100
V
µA
20
3800 (1)
4500
Ensured by design, not tested in production
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Electrical Characteristics (continued)
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BLOCK
VINH
Input Pin (HI, LI) high threshold
1.6
2.0
2.4
VINL
Input Pin (HI, LI) low threshold
0.8
1.2
1.5
VINHYS
Input Pin (HI, LI) threshold
hysteresis
IINL
HI, LI input low bias current
HI, LI = 0 V
–5
IINH
HI, LI input high bias current
HI, LI = 5 V
1.7
V
0.8
0
5
µA
70
OUTPUT BLOCK
VDD-VLOH
LO output high voltage
LI = 5 V, ILO = –20 mA
60
136
VHB-VHOH
HO output high voltage
HI = 5 V, IHO = –20 mA
60
136
VLOL
LO output low voltage
LI = 0 V, ILO = 20 mA
30
80
VHOL
HO output low voltage
HI = 0 V, IHO = 20 mA
30
80
RLOL,
RHOL
LO, HO output pull-down resistance
ILO = IHO = 20 mA
1.5
4
RLOH,
RHOH
LO, HO output pull-up resistance
ILO = IHO = –20 mA
3.0
6.8
IGPK- (1)
HO, LO output low short circuit
pulsed current
HI = LI = 0 V, HO = LO = 15 V, PW
< 10 µs
2.8
IGPK+ (1)
HO, LO output high short circuit
pulsed current
HI = LI = 5 V, HO = LO = 0 V, PW <
10 µs
–1.8
mV
Ω
A
7.6 Dynamic Electrical Characteristics
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DYNAMIC CHARACTERISTICS
tPDLH
Turn-on propagation delay (without
deadtime)
LI to LO, HI to HO, HS = COM = 0 V
100
160
tPDHL
Turn-off propagation delay
LI to LO, HI to HO, HS = COM = 0 V
100
160
tPDRM
Low-to-high delay matching
5
30
tPDFM
High-to-low delay matching
12
30
16
50
tRISE
Turn-on rise time
10% to 90%, HO/LO with 1000-pF
load
tFALL
Turn-off fall time
10% to 90%, HO/LO with 1000-pF
load
10
30
tON
Minimum HI/LI ON pulse that
changes output state
0-V to 5-V input signal on HI and LI
pins
25
45
tOFF
Minimum HI/LI OFF pulse that
changes output state
5-V to 0-V input signal on HI and LI
pins
35
45
DT
Deadtime
Internal deadtime for Interlock
150
200
ns
100
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HI
50%
50%
50%
50%
LI
HO
tFALL
tPDLH
90%
10%
10%
90%
90%
LO
tRISE
90%
tPDHL
10%
tRISE
tPDHL
tFALL
10%
Deadtime
(set by controller if > DT)
Interlock
(DT)
Figure 1. Typical Test Timing Diagram
6
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7.7 Typical Characteristics
130
130
VDD = 10V
VDD = 12V
VDD = 15V
110
100
90
-20
0
20
40
60
Temperature (oC)
80
100
90
130
120
120
110
100
90
80
VDD=10V
VDD=12V
VDD=15V
70
-20
0
20
40
60
Temperature (oC)
80
100
20
40
60
Temperature (oC)
80
100
120
D002
110
100
90
VDD=10V
VDD=12V
VDD=15V
80
70
-40
120
-20
0
D003
Figure 4. High-Side, Turn-On Propagation Delay vs
Temperature
20
40
60
Temperature (oC)
80
100
120
D004
Figure 5. High-Side, Turn-Off Propagation Delay vs
Temperature
30
30
24
Turn Off Delay Matching t PDFM (ns)
VDD=10V
VDD=12V
VDD=15V
27
21
18
15
12
9
6
3
0
-40
0
Figure 3. Low-Side, Turn-Off Propagation Delay vs
Temperature
130
60
-40
-20
D001
High Side tPDHL (ns)
High Side tPDLH (ns)
100
70
-40
120
Figure 2. Low-Side, Turn-On Propagation Delay vs
Temperature
Turn On Delay Matching tPDRM (ns)
110
80
80
70
-40
VDD=10V
VDD=12V
VDD=15V
120
Low Side tPDHL (ns)
Low Side tPDLH (ns)
120
-20
0
20
40
60
Temperature (oC)
80
100
120
24
21
18
15
12
9
6
3
0
-40
D005
Figure 6. Turn-On Delay Matching vs Temperature
VDD=10V
VDD=12V
VDD=15V
27
-20
0
20
40
60
Temperature (oC)
80
100
120
D006
Figure 7. Turn-Off Delay Matching vs Temperature
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Typical Characteristics (continued)
130
30
Turn On
Turn Off
125
120
VDD=10V
VDD=12V
VDD=15V
25
110
LO tRISE (ns)
High Side tPD (ns)
115
105
100
95
20
15
10
90
85
5
80
75
0
-40
70
0
60
120
180
240
300 360
VHS (V)
420
480
540
600
-20
0
20
40
60
Temperature (oC)
D007
Figure 8. High-Side Propagation Delay vs HS
80
100
120
D008
Figure 9. LO Rise Time with 1000-pF Load vs Temperature
20
30
VDD=10V
VDD=12V
VDD=15V
25
HO tRISE (ns)
LO tFALL (ns)
15
10
20
15
10
5
VDD=10V
VDD=12V
VDD=15V
5
0
-40
-20
0
20
40
60
Temperature (oC)
80
100
0
-40
120
Figure 10. LO Fall Time with 1000-pF Load vs Temperature
0
20
40
60
Temperature (oC)
80
100
120
D001
Figure 11. HO Rise Time with 1000-pF Load vs Temperature
10
20
UVLO On
UVLO Off
VDD=10V
VDD=12V
VDD=15V
9.5
VVDD ON, VVDD OFF (V)
15
HO tFALL (ns)
-20
D009
10
5
9
8.5
8
0
-40
-20
0
20
40
60
Temperature (oC)
80
100
120
D001
Figure 12. HO Fall Time with 1000-pF Load vs Temperature
8
7.5
-40
-20
0
20
40
60
Temperature (oC)
80
100
120
D001
Figure 13. VDD UVLO Thresholds vs Temperature
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Typical Characteristics (continued)
9
1.5
HB UVLO On
HB UVLO Off
VVDD HYS, VVHB HYS (V)
VVHB ON, VVHB OFF (V)
8
7.5
7
6.5
-40
VDD Hysteresis
VHB Hysteresis
1.25
8.5
1
0.75
0.5
0.25
-20
0
20
40
60
Temperature (oC)
80
100
0
-40
120
-20
0
D001
Figure 14. VHB-VHS UVLO Thresholds vs Temperature
20
40
60
Temperature (oC)
80
100
120
D001
Figure 15. VDD and VHB-VHS UVLO Hysteresis vs
Temperature
2.4
1.5
HI High Thresh
LI High Thresh
2.3
HI Low Thresh
LI Low Thresh
1.4
2.2
1.3
VINL (V)
VINH (V)
2.1
2
1.2
1.1
1.9
1
1.8
0.9
1.7
1.6
-40
-20
0
20
40
60
Temperature (oC)
80
100
0.8
-40
120
Figure 16. HI/LI Pin High Threshold vs Temperature
0
20
40
60
Temperature (oC)
80
100
120
D001
Figure 17. HI/LI Pin Low Threshold vs Temperature
1
4
HI Hysteresis
LI Hysteresis
VDD=10V
VDD=15V
3.5
3
RLOL (:)
0.9
VINHYS (V)
-20
D001
0.8
2.5
2
1.5
0.7
1
0.5
0.6
-40
-20
0
20
40
60
Temperature (oC)
80
100
120
0
-40
D001
Figure 18. HI/LI Pin Hysteresis vs Temperature
-20
0
20
40
60
Temperature (oC)
80
100
120
D001
Figure 19. LO Output Pull-Down Resistance vs Temperature
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Typical Characteristics (continued)
6
4
VDD=10V
VDD=15V
3.5
5.5
5
3
2.5
RLOH (:)
RHOL (:)
4.5
2
1.5
4
3.5
3
2.5
1
2
0.5
0
-40
-20
0
20
40
60
Temperature (oC)
80
100
1
-40
120
-20
0
D001
Figure 20. HO Output Pull-Down Resistance vs Temperature
20
40
60
Temperature (oC)
80
100
120
D002
Figure 21. LO Output Pull-Up Resistance vs Temperature
6
400
VDD=10V
VDD=15V
5.5
HI, LI 0V
HI, LI 5V
350
5
4.5
300
4
IQ (uA)
RHOH (:)
VDD=10V
VDD=15V
1.5
3.5
250
3
200
2.5
2
150
1.5
1
-40
VDD=VHB=15V
-20
0
20
40
60
Temperature (oC)
80
100
100
-40
120
-20
0
D002
Figure 22. HO Output Pull-Up Resistance vs Temperature
20
40
60
Temperature (oC)
80
100
120
D002
Figure 23. Total Quiescent VDD plus HB Supply Current vs
Temperature
5
100
VHB=VHS=400V
VHB=VHS=600V
IQ HB to HS
90
4
70
IBL (uA)
IQBS (uA)
80
60
3
2
50
1
40
VDD=VHB=15V
30
-40
-20
0
20
40
60
Temperature (oC)
80
100
120
Figure 24. Quiescent HB to HS Supply Current vs
Temperature
10
0
-40
D002
-20
0
20
40
60
Temperature (oC)
80
100
120
D002
Figure 25. HB to COM Bootstrap Supply Leakage Current vs
Temperature
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Typical Characteristics (continued)
4
10
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
3.5
8
IVDD, IVHB (mA)
IVDD, IVHB (mA)
3
9
2.5
2
1.5
7
6
5
4
3
1
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
2
0.5
1
0
0
0
50
100
150
200 250 300
Fsw (kHz)
350
400
450
500
0
50
100
D002
Figure 26. VDD and HB Operating Current with No Load vs
Switching Frequency
150
200 250 300
Fsw kHz
350
400
450
500
D002
Figure 27. VDD and HB Operating Current with 1000-pF
Load vs Switching Frequency
40
35
IVDD, IVHB (mA)
30
25
20
15
10
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
5
0
0
50
100
150
200 250 300
Fsw (kHz)
350
400
450
500
D002
Figure 28. VDD and HB Operating Current with 4700-pF Load vs Switching Frequency
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8 Detailed Description
8.1 Overview
The UCC27712-Q1 consists of one ground-referenced channel (LO) and one floating channel (HO) which is
designed for operating with bootstrap or isolated power supplies. The device features fast propagation delays
and excellent delay matching between both channels. On the UCC27712-Q1, each channel is controlled by its
respective input pins,
Developed with TI’s state of the art high-voltage technology, the device features robust drive with excellent noise
and transient immunity including large negative voltage tolerance on its inputs, high dv/dt tolerance, and wide
negative transient safe operating area (NTSOA) on the switch node (HS).
The UCC27712-Q1 includes protection features where the outputs are held low when the inputs are floating or
when the minimum input pulse width specification is not met. Interlock and deadtime functions prevent both
outputs from being turned on simultaneously. In addition, the device accepts a wide range bias supply range
from 10 V ~ 22 V, and offers UVLO protection for both the VDD and HB bias supply.
High-current, gate-driver devices are required in switching power applications for a variety of reasons. In order to
implement fast switching of power devices and reduce associated switching power losses, a powerful gate-driver
device is employed between the PWM output of control devices and the gates of the power semiconductor
devices. Further, gate-driver devices are indispensable when having the PWM controller device directly drive the
gates of the switching devices is sometimes not feasible. In the case of digital power supply controllers, this
situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal
which is not capable of effectively turning on a power switch.
In bridge topologies, like hard-switch half bridge, hard-switch full bridge, half-bridge and full-bridge LLC, and
phase-shift full bridge, the source and emitter pin of the top-side power MOSFET and IGBT switch is referenced
to a node whose voltage changes dynamically; that is, not referenced to a fixed potential, so floating-driver
devices are necessary in these topologies.
The UCC27712-Q1 is a high-side and low-side driver dedicated for offline AC-to-DC power supplies and
inverters. The high side is a floating driver that can be biased effectively using a bootstrap circuit, and can handle
up to 600-V. The driver can be used with 100% duty cycle as long as HB-HS can be above UVLO of the high
side.
The device features industry best-in-class propagation delay and delay matching between both channels aimed
at minimizing pulse width distortion in high-frequency switching applications. Each channel is controlled by its
respective input pins (HI and LI), allowing independent flexibility to control on and off state of the output but does
not allow the HO and LO outputs to be on at the same time. The UCC27712-Q1 includes an interlock feature
which guarantees a 150ns dead time between the HO and LO outputs if the HI and LI inputs are complimentary.
The UCC27712-Q1 includes protection features wherein the outputs are held low when inputs are floating or
when the minimum input pulse width specification is not met. The driver inputs are CMOS and TTL compatible
for easy interface to digital power controllers and analog controllers alike.
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8.2 Functional Block Diagram
8
HB
7
HO
6
HS
3
VDD
5
LO
4
COM
VHB UVLO
Level Shifter
R
Pulse
Filter
HI
2
Deglitch
Filter
1
Q
S
Pulse
Generator
Shoot Through
Prevention
LI
R
VDD UVLO
Delay
Deglitch
Filter
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Figure 29. UCC27712-Q1 Block Diagram
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8.3 Feature Description
8.3.1 VDD and Under Voltage Lockout
The UCC27712-Q1 has an internal under voltage-lockout (UVLO) protection feature on the supply circuit blocks
between VDD and VSS pins, as well as between HB and HS pins. When VDD bias voltage is lower than the
VVDD(on) threshold at device start-up or lower than VVDD(off) after start-up, the VDD UVLO feature holds both the
LO and HO outputs low, regardless of the status of the HI and LI inputs. On the other hand, if HB-HS bias supply
voltage is lower than the VVHB(on) threshold at start-up or VVHB(off) after start-up, the HB-HS UVLO feature only
holds HO to low, regardless of the status of the HI. The LO output status is not affected by the HB-HS UVLO
feature (see Table 1 and Table 2). This allows the LO output to turn-on and re-charge the HB-HS capacitor using
the boot-strap circuit and thus allows HB-HS bias voltage to surpass the VVHB(on) threshold.
Both the VDD and VHB UVLO protection functions are provided with a hysteresis feature. This hysteresis
prevents chatter when there is ground noise from the power supply. Also this allows the device to accept a small
drop in the bias voltage which is bound to happen when the device starts switching and quiescent current
consumption increases instantaneously, as well as when the boot-strap circuit charges the HB-HS capacitor
during the first instance of LO turn-on causing a drop in VDD voltage.
The UVLO circuit of VDD-VSS and HB-HS in UCC27712-Q1 generate internal signals to enable/disable the
outputs after UVLO_ON/UVLO_OFF thresholds are crossed respectively (please refer to Figure 30). Design
considerations indicate that the UVLO propagation delay before the outputs are enabled and disabled can vary
from 20 μs to 50 μs.
Table 1. VDD UVLO Feature Logic Operation
CONDITION (VHB-VHS>VVHB, ON FOR ALL CASES
BELOW)
HI
LI
HO
LO
VDD-VSS < VVDD(on) during device start up
H
L
L
L
VDD-VSS < VVDD(on) during device start up
L
H
L
L
VDD-VSS < VVDD(on) during device start up
H
H
L
L
VDD-VSS < VVDD(on) during device start up
L
L
L
L
VDD-VSS < VVDD(off) after device start up
H
L
L
L
VDD-VSS < VVDD(off) after device start up
L
H
L
L
VDD-VSS < VVDD(off) after device start up
H
H
L
L
VDD-VSS < VVDD(off) after device start up
L
L
L
L
LI
HO
LO
Table 2. VHB UVLO Feature Logic Operation
CONDITION (VDD-VSS > VVDD,ON FOR ALL CASES
BELOW)
HI
VHB-VHS < VVHB(on) during device start up
H
L
L
L
VHB-VHS < VVHB(on) during device start up
L
H
L
H
VHB-VHS < VVHB(on) during device start up
H
H
L
L
VHB-VHS < VVHB(on) during device start up
L
L
L
L
VHB-VHS < VVHB(off) after device start up
H
L
L
L
VHB-VHS < VVHB(off) after device start up
L
H
L
H
VHB-VHS < VVHB(off) after device start up
H
H
L
L
VHB-VHS < VVHB(off) after device start up
L
L
L
L
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VVDD(on)
VVDD(off)
4V
VDD
LI
tDelay
tDelay
LO
VVHB(on)
HB-HS
HI
tDelay
HO
Figure 30. Power-Up Driver
8.3.2 Input and Output Logic Table
UCC27712-Q1 features separate inputs, HI and LI, for controlling the state of the outputs, HO and LO,
respectively. The device does include internal cross-conduction prevention logic and does not allow both HO and
LO outputs to be turned on simultaneously (refer to Table 3). This feature prevents cross conduction in bridge
topologies in the case of incorrect timing from the controller.
Table 3. Input/Output Logic Table
(Assuming no UVLO fault condition exists for VDD and VHB)
HI
LI
HO
LO
L
L
L
L
L
H
L
H
H
L
H
L
H
H
L
L
Left Open
Left Open
L
L
Note
Output transitions occur after the
dead time expires
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8.3.3 Input Stage
The input pins of UCC27712-Q1 are based on a TTL and CMOS compatible input-threshold logic that is
independent of the VDD supply voltage. With typical high threshold (VINH) of 2.0 V and typical low threshold
(VINL) of 1.2 V, along with very little temperature variation as summarized in Figure 16 and Figure 17, the input
pins are conveniently driven with logic level PWM control signals derived from 3.3-V and 5-V digital powercontroller devices. Wider hysteresis (typically 0.8 V) offers enhanced noise immunity compared to traditional TTL
logic implementations, where the hysteresis is typically less than 0.5 V. UCC27712-Q1 also features tight control
of the input pin threshold voltage levels which eases system design considerations and ensures stable operation
across temperature.
The UCC27712-Q1 includes an important feature: wherein, whenever any of the input pins is in a floating
condition, the output of the respective channel is held in the low state. This is achieved using COM pull-down
resistors on all the input pins (HI, LI).
The UCC27712-Q1 input pins are capable of sustaining voltages higher than the bias voltage applied on the
VDD pin of the device, as long as the absolute magnitude is less than the recommended operating condition's
maximum ratings. This features offers the convenience of driving the PWM controller at a higher VDD bias
voltage than the UCC27712-Q1 helping to reduce gate charge related switching losses. This capability is
envisaged in UCC27712-Q1 by way of two ESD diodes tied back-to-front as shown in Figure 31.
Additionally, the input pins are also capable of sustaining negative voltages below COM, as long as the
magnitude of the negative voltage is less than the recommended operating condition minimum ratings. A similar
diode arrangement exists between the input pins and COM as illustrated in Figure 31.
The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied
in typical power supply applications, when the input signals are provided by a PWM controller or logic gates with
fast transition times. With a slow changing input voltage, the output of driver may switch repeatedly at a high
frequency. While the wide hysteresis offered in UCC27712-Q1 definitely alleviates this concern over most other
TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall times to
the power device is the primary goal, then an external resistance is highly recommended between the output of
the driver and the power device. This external resistor has the additional benefit of reducing part of the gatecharge related power dissipation in the gate-driver device package and transferring it into the external resistor
itself. If an RC filter is to be added on the input pins for reducing the impact of system noise and ground bounce,
the time constant of the RC filter is recommended to be 20 ns or less, for example, 50 Ω with 220 pF is an
acceptable choice.
LI
1
22 V
HI
2
5V
4
COM
Figure 31. Diode Structure of Input Stage
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8.3.4 Output Stage
The UCC27712-Q1 device output stage pull-up structure features a P-Channel MOSFET to provide source
current until the output is saturated to VDD or HB. The ROH parameter (see Figure 21) is a DC measurement and
it is representative of the on-resistance of the P-Channel device.
The pull-down structure in UCC27712-Q1 is composed of a N-Channel MOSFET. The ROL parameter (see
Figure 19), which is also a DC measurement, is representative of the impedance of the pull-down stage in the
device.
Each output stage in UCC27712-Q1 is capable of supplying 1.8-A peak source and 2.8-A peak sink current
pulses. The output voltage swings between (VDD and COM) / (HB and HS) providing rail-to-rail operation, thanks
to the MOSFET output stage which delivers very low drop-out.
VDD
3
ROH
Input
Voltage
Body
Diodes
Anti ShootThrough
Circuitry
5
ROL
LO
Body
Diodes
4
COM
Figure 32. Output Stage Structure
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8.3.5 Level Shift
The level shift circuit (refer to the Functional Block Diagram) is the interface from the high-side input to the highside driver stage which is referenced to the switch node (HS). It is a pulsed generated level shifter. With an input
signal the pulse generator generates "on" pulses based on the rising edge of the signal and "off" pulses based
on the falling edge. On pulses and off pulses turn on each branch of the level shifter so that current flows in each
branch to generate different voltages, which is transferred to the set and reset signal in the high side. The signal
is rebuilt by the RS latch in the high side domain. The level shift allows control of the HO output referenced to the
HS pin and provides excellent delay matching with the low-side driver. The delay matching of UCC27712-Q1 is
summarized in Figure 6 and Figure 7.
The level shifter in UCC27712-Q1 offers best-in-class capability while operating under negative voltage
conditions on HS pin. The level shifter is able to transfer signals from the HI input to HO output with only 4-V
headroom between HB and COM. Refer to Operation Under Negative HS Voltage Condition for detailed
explanations.
8.3.6 Low Propagation Delays and Tightly Matched Outputs
The UCC27712-Q1 features a best in class, 100-ns (typical) propagation delay (refer to Figure 2, Figure 3,
Figure 4 and Figure 5 ) between input and output in high voltage 600-V driver, which goes to offer a low level of
pulse width distortion for high frequency switching applications.
Figure 33. Turn-On Propagation Delay
18
Figure 34. Turn-Off Propagation Delay
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8.3.7 Parasitic Diode Structure
Figure 35 illustrates the multiple parasitic diodes involved in the ESD protection components of UCC27712-Q1
device. This provides a pictorial representation of the absolute maximum rating for the device.
8
HB
7
HO
6
HS
3
VDD
5
LO
4
COM
22V
700V
LI
1
22V
HI
2
22V
5V
Figure 35. ESD Structure
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8.4 Device Functional Modes
8.4.1 Minimum Input Pulse Operation
The UCC27712-Q1 device has a minimum turn-on, turn-off pulse transfer function to the output pin from the input
pin. This function ensures UCC27712-Q1 is in the correct state when the input signal is very narrow. The
function is summarized in Figure 36 and Figure 37. The tON which is 25 ns typical is shown in Figure 36 and tOFF
which is 35ns typical is shown in Figure 37
<25 ns
HI, LI
•25 ns
HI, LI
tPDLH
HO, LO
Low State
HO, LO
Figure 36. Minimum Turn-On Pulse
HI, LI
HI, LI
<35 ns
•35 ns
tPDHL
HO, LO
High State
HO, LO
Figure 37. Minimum Turn-Off Pulse
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Device Functional Modes (continued)
8.4.2 Output Interlock and Dead Time
The UCC27712-Q1 has cross-conduction prevention logic, which is a feature that does not allow both the highside and low-side outputs to be in high state simultaneously. In bridge power supply topologies, such as halfbridge or full-bridge, the UCC27712-Q1 interlock feature will prevent the high-side and low-side power switches
to be turned on simultaneously. The UCC27712-Q1 generates a fixed minimum dead time of tDT which is 150ns
nominal in the case of LI and HI overlap or no dead time. Figure 38 illustrates the mode of operation where LI
and HI have no dead time and HO and LO outputs have the minimum dead time of tDT.
Figure 38. HO and LO Minimum Dead Time with LI HI Complementary
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Device Functional Modes (continued)
An input signal's falling edge activates the dead time for the other signal. The output signal's dead time is always
set to the longer of either the driver's minimum dead time, tDT, or the input signal's own dead time. If both inputs
are high simultaneously, both outputs will immediately be set low. This feature is used to prevent cross
conduction, and it does not affect the programmed dead time setting for normal operation. Various driver dead
time logic operating conditions are illustrated and explained in Figure 39.
HI
LI
HO
LO
B
A
C
D
E
F
Figure 39. Input and Output Logic Relationship
Condition A: HI goes high, LI goes low. LI sets LO low immediately and assigns tDT to HO. HO is allowed to go
high after tDT.
Condition B: LI goes high, HI goes low. HI sets HO low immediately and assigns tDT to HO. LO is allowed to go
high after tDT.
Condition C: LI goes low, HI is still low. LI sets LO low immediately and assigns tDT to HO. In this case, the
input signal's own dead time is longer than tDT. Thus when HI goes high HO is set high immediately.
Condition D: HI goes low, LI is still low. HI sets HO low immediately and assigns tDT to LO. In this case, the
input signal's own dead time is longer than tDT. Thus when LI goes high LO is set high immediately.
Condition E: HI goes high, while LI and LO are still high. To avoid cross-conduction, HI immediately sets LO low
and keeps HO low. After some time LI goes low and assigns tDT to HO. LO is already low. After tDT HO is allowed
to go high.
Condition F: LI goes high, while HI and HO are still high. To avoid cross-conduction, LI immediately sets HO low
and keeps LO low. After some time HI goes low and assigns tDT to LO. HO is already low. After tDT LO is allowed
to go high.
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Device Functional Modes (continued)
8.4.3 Operation Under 100% Duty Cycle Condition
The UCC27712-Q1 allows constant on or constant off operation (0% and/or 100% duty cycle) as long as the
VDD and VHB bias supplies are maintained above the UVLO thresholds. This is a challenge when boot-strap
supplies are used for VHB. However, when a dedicated bias supply is used, constant on or constant off
conditions can be supported. Also consider the HI and LI interlock function prevents both outputs from being
high.
8.4.4 Operation Under Negative HS Voltage Condition
A typical half-bridge configuration with UCC27712-Q1 is shown in Figure 40. There are parasitic inductances in
the power circuit from die bonding and pinning in QT/QB and PCB tracks of power circuit, the parasitic
inductances are labeled LK1,2,3,4.
During switching of HS caused by turning off HO, the current path of power circuit is changed to current path 2
from current path 1. This is known as current commutation. The current across LK3, LK4 and body diode of QB
pulls HS lower than COM. The negative voltage of HS with respect to COM causes a logic error of HO if the
driver cannot handle negative voltage of HS. However, the UCC27712-Q1 offers robust operation under these
conditions of negative voltage on HS.
VBUS+
LK1
QT
HO
7
Current Path 1
LK2
HS
6
LK3
QB
LO
Current
Path 2
5
Load
LK4
COM
4
Figure 40. HS Negative Voltage In Half-Bridge Configuration
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Device Functional Modes (continued)
The level shifter circuit is with respect to COM (refer to Functional Block Diagram), the voltage from HB to COM
is the supply voltage of level shifter. Under the condition of HS is negative voltage with respect to COM, the
voltage of HB-COM is decreased, as shown in Figure 41. There is a minimum operational supply voltage of level
shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HI signal to HO. The
minimum supply voltage of level shifter of UCC27712-Q1 is 4 V, so the recommended HS specification is
dependent on HB-HS. The specification of recommended HS is –11 V at HB – HS = 15 V.
In general, HS can operate until -11 V when HB – HS = 15 V as the ESD structure in Figure 35 allows a
maximum voltage difference of 22 V between both pins. If HB-HS voltage is different, the minimum HS voltage
changes accordingly.
HB
HS
HB-COM
COM
Figure 41. Level Shifter Supply Voltage with Negative HS
NOTE
Logic operational for HS of –11 V to 600 V at HB – HS = 15 V
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Device Functional Modes (continued)
The capability of a typical UCC27712-Q1 device to operate under a negative voltage condition in HS pin is
reported in Figure 43. The test method is shown in Figure 42.
Bias
RBIAS
15 V
CVDD
3
VDD
HB
8
CBOOT
2 HI
HO
7
1
HS
6
LO
5
COM
4
LI
+
±
Probe
15 V
Single Phase
Negative
Voltage
Generator
Figure 42. Negative Voltage Test Method
0
HS Negative Voltage (V)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
100
200
300
400 500 600
Time (ns)
700
800
900 1000
NTSO
Figure 43. Negative Voltage Chart
Pulse Width vs Negative Voltage
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9 Application and Implementation
NOTE
Information in the following Applications section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers
are responsible for determining suitability of components for their purposes.
Customers should validate and test their design implementation to confirm system
functionality.
9.1 Application Information
To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other
needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver
physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates,
reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the
controller into the driver.
9.2 Typical Application
The circuit in Figure 44 shows a reference design example with UCC27712-Q1 driving a typical half-bridge
configuration which could be used in several common power converter topologies such as synchronous buck,
synchronous boost, half-bridge/full bridge isolated topologies, and motor drive applications.
For more information, please refer to Figure 44.
Bias
RBIAS
RBOOT
DBOOT
HV
CVDD
3
HB
8
2 HI
HO
7
LI
HS
6
VDD
ROFF
RON
RHI
PWM1
CBOOT
CHI
RLI
1
PWM2
DGATE
ROFF
CLI
Q1
RGS
SW
DGATE
RON
GND
LO
Q2
5
RGS
COM
4
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Figure 44. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 4 shows the reference design parameters for the example application: UCC27712-Q1 driving 650-V
MOSFETs in a high side-low side configuration.
Table 4. UCC27712-Q1 Design Requirements
PARAMETER
VALUE
UNIT
Power transistor
IPB65R190CFD
V
VDD
12
Input signal amplitude
3.3
V
Switching frequency (fSW)
100
kHz
DC link voltage (VHV)
400
V
9.2.2 Detailed Design Procedure
This procedure outlines the steps to design a 600-V high-side, low-side gate driver with 1.8-A source and 2.8-A
sink current capability, targeted to drive power MOSFETs or IGBTs using the UCC27712-Q1. Refer to Figure 44
for component names and network locations. For additional design help see the UCC27712EVM-287 User
Guide, SLUUBO1.
9.2.2.1
Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
It is recommended that users avoid shaping the input signals to the gate driver in an attempt to slow down (or
delay) the signal at the driver output. However it is good practice to have a small RC filter added between PWM
controller and input pin of UCC27712-Q1 to filter the high frequency noise, like RHI/CHI and RLI/CLI which is
shown in Figure 44.
Such a filter should use a RHI/RLI in the range of 10 Ω to 100 Ω and a CHI/CLI between 10 pF and 220 pF. In the
example, a RHI/RLI = 49.9 Ω and a CHI/CLI = 33 pF are selected.
9.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
The bootstrap capacitor should be sized to have more than enough energy to drive the gate of FET Q1 high, and
maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with:
IQBS
65 PA
QTotal QG
68nC
68.65nC
fSW
fSW
(1)
This design example targets a boot capacitor ripple voltage of 0.5 V. Therefore, the absolute minimum CBOOT
requirement is:
QTOTAL 68.65nC
CBOOT
| 137nF
'VBOOT
0.5 V
(2)
In practice, the value of CBOOT needs to be greater than the calculated value. This allows for capacitance shift
from DC bias and temperature, and also skipped cycles that occur during load transients. For this design
example 2x 220-nF capacitors were chosen for the bootstrap capacitor.
CBOOT 440nF
(3)
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9.2.2.3
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Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
The VDD capacitor (CVDD) should be chosen to be at least 10 times larger than CBOOT so there is minimal voltage
drop on the VDD capacitor when charging the boot capacitor . For this design example a 4.7-µF capacitor was
selected.
CVDD t 10 u CBOOT 4.7 PF
(4)
A 10-Ω resistor RBIAS in series with bias supply and VDD pin is recommended to make the VDD ramp up time
larger than 20 µs to minimize LO and HO rising as shown in Figure 45
LO
HO
Figure 45. VDD/HB-HS Fast Ramp Up
9.2.2.4
Selecting Bootstrap Resistor (RBOOT)
Resistor RBOOT is selected to limit the current in DBOOT and limit the ramp up slew rate of voltage of HB-HS to
avoid the phenomenon shown in Figure 45. It is recommended when using the UCC27712-Q1 that RBOOT is
between 2 Ω and 20 Ω. For this design we selected an RBOOT current limiting resistor of 2.2 Ω. The bootstrap
diode current (IDBOOT(pk)) was limited to roughly 5.0 A.
VDD VDBOOT 12 V 1V
IDBOOT(pk)
5.0 A
RBOOT
2.2
(5)
The power dissipation capability of the bootstrap resistor is important. The bootstrap resistor must be able to
withstand the short period of high power dissipation during the initial charging sequence of the boot-strap
capacitor. This energy is equivalent to 1/2 × CBOOT × V2. This energy is dissipated during the charging time of
the bootstrap capacitor (~3 × RBOOT × CBOOT). Special attention must be paid to use a bigger size RBOOT when a
bigger value of CBOOT is chosen.
28
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9.2.2.5 Selecting Gate Resistor RON/ROFF
Resistor RON and ROFF are sized to achieve the following:
•
•
•
•
Limit ringing caused by parasitic inductances and capacitances.
Limit ringing caused by high voltage/current switching dV/dt, dI/dt, and body diode reverse recovery.
Fine-tune gate drive strength to optimize switching loss.
Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC27712-Q1 has a pull up structure with a P-channel MOSFET providing a
peak source current of 1.8A.
For this example 3.3-Ω resistors for RON and 2.2-Ω resistors for ROFF were selected to provide damping for
ringing and ample gate drive current.
RON 3.3 5OFF
(6)
Therefore the peak source current can be predicted with:
IHO
ILO
VDD VDBOOT
§
·
MIN ¨ 1.8 A,
RHOH RON RGFET_Int ¸¹
©
(7)
VDD
§
·
MIN ¨ 1.8 A,
RLOH RON RGFET_Int ¸¹
©
(8)
where
•
•
•
RON: External turn-on resistance
RGFET_Int: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current. The maximum values between 1.8 A, the UCC27712-Q1 peak source current, and
the calculated value based on the gate drive loop resistance.
In this example:
IHO
ILO
VDD VDBOOT
RHOH RON RGFET_Int
VDD
RLOH RON RGFET_Int
12 V-0.6 V
3.0
12 V
3.0
| 1.6 A
(9)
| 1.6 A
(10)
Therefore, the high-side and low side peak source current is 1.6 A. Similarly, the peak sink current can be
calculated with:
IHO
ILO
VDD VDBOOT VDGATE ·
§
MIN ¨ 2.8 A,
¸
R
HOL ROFF RGFET_Int ¹
©
(11)
VDD VDGATE
§
·
MIN ¨ 2.8 A,
¸
R
LOL
R
OFF
R
GFET_Int
©
¹
(12)
where
•
•
•
ROFF: External turn-off resistance
VDGATE: The diode forward voltage drop which is in series with ROFF. The diode in this example is an
MBRM130L.
IO- = Peak sink current. The maximum values between 2.8 A, the UCC27712-Q1 peak sink current, and the
calculated value based on the gate drive loop resistance.
In this example:
VDD VDBOOT VDGATE
12 V-0.6 V-0.6 V
IHO
| 2.3 A
RHOL RON RGFET_Int 1.5
VDD VDGATE
12 V-0.6 V
ILO
| 2.4 A
RLOL RON RGFET_Int 1.5
(13)
(14)
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9.2.2.6 Selecting Bootstrap Diode
A fast recovery diode should be chosen to avoid charge being taken away from the bootstrap capacitor. Thus, a
fast reverse recovery time tRR, low forward voltage VF and low junction capacitance is recommended.
Suggested parts include MURA160T3G and BYG20J.
9.2.2.7
Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
The power losses of UCC27712-Q1 (PUCC27712-Q1) are estimated by calculating losses from several components.
The gate drive loss in the UCC27712-Q1 is typically dominated by gate drive losses associated with charging
and discharging the power device gate charge. There are other losses to consider especially if operating at high
switching frequencies outlined below.
To determine the UCC27712-Q1 operating with no driver load, refer to the Typical Characteristics Figure 26 for
IDD and IHB to determine the operating current at the appropriate fSW. The operating current power losses with
no driver load are calculated in Equation 15:
PQ VVDD u IVDD,100kHz IHB,100kHz 12 V u 310 PA 350 PA | 8mW
(15)
Static losses due to leakage current (IBL) are calculated from the HB high-voltage node as shown in Equation 16:
PIBL VHB u IBL u D 400 V u 20 PA u 0.5 4mW
(16)
Equation 17 calculates dynamic losses during the operation of the level shifter at HO turn-off edge. QP, typically
0.6 nC, is the charge absorbed by the level shifter during operation at each edge. Please note that if high-voltage
switching occurs during HO turn-on as well (as in the case of ZVS topologies), then the power loss due to this
component must be effectively doubled.
PLevelShift ¬ª VHV (VHB VHS)¼º u QP u fSW 411.4 V u 0.6nC u 100kHz 24.7mW
(17)
where
• VHV: DC link high voltage input in V
• fSW: Switching frequency of converter in Hz.
Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated Equation 18.
Please note that this component typically dominates over the dynamic losses related to the internal VDD and
VHB switching logic circuitry in UCC27712-Q1. The losses incurred driving the gate charge are not all dissipated
in the gate driver device, this includes losses in the external gate resistance and internal power switch gate
resistance.
PQG1,QG2 2 u VVDD u QG u fSW 2 u 12 V u 68nC u 100kHz 163mW
(18)
The UCC27712-Q1 gate driver loss on the output stage ,PGDO, is part of PQG1,QG2. If the external gate resistances
are zero most of the PQG1,QG2 will be dissipated in the UCC27712-Q1. If there are external gate resistances, the
total loss will be distributed between the gate driver pull-up/down resistances and the external gate resistances.
The gate drive power dissipated within the UCC27712-Q1 driver can be determined by Equation 19:
PGDO
PQG1,QG2 §
RHOH
u¨
2
© RHOH RON RGFET_Int
RHOL
RHOL ROFF
·
RGFET_Int ¹¸
(19)
In this example the gate drive related losses are approximately 60mW as shown in Equation 20:
·
163mW §
3:
1.5 :
PGDO
u¨
¸ | 60mW
2
© 3 : 3.3 : 1: 1.5 : 2.2 : 1: ¹
(20)
For the conditions, VDD=12V, VHB = 400V, HO On-state Duty cycle D = 50%, QG = 68nC, fSW = 100kHz, the
total power loss in UCC27712-Q1 driver for a half bridge power supply topology can be estimated as follows:
PUCC27712 PQ PIBL PLevelShift PGDO 8mW 4mW 25mW 60mW 97mW
(21)
30
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9.2.2.8 Estimating Junction Temperature
The junction temperature can be estimated with:
TJ TC <JT u PUCC27712
(22)
where
• TC is the UCC27712-Q1 case-top temperature measured with a thermocouple or some other instrument.
and
• ѰJT is the junction-to-top characterization parameter from the Thermal Information table. Importantly.
Using the junction-to-top characterization parameter (ѰJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of estimating the junction temperature. The majority of the power
dissipation of most devices is released into the PCB through the package leads, whereas only a small
percentage of the total dissipation is released through the top of the case (where thermocouple measurements
are usually taken). RθJC can only be used effectively when most of the thermal energy is released through the
case, such as with metal packages or a heatsink is applied to the device package. In other cases RθJC will
inaccurately estimate the true junction temperature of the device. ѰJT is experimentally derived by assuming the
amount of thermal energy dissipated through the top of the device will be similar in both the testing environment
and the application environment. As long as the recommended layout guidelines are observed, junction
temperature can be estimated accurately to within a few degrees Celsius. For more information, see the
Semiconductor and IC Package Thermal Metrics application report.
Additional Considerations: In the application example schematic there are 10-kΩ resistors across the gate and
source terminals of FET Q1 and Q2. These resistors are placed across these nodes to ensure FETs Q1 and Q2
are not turned on if the UCC27712-Q1 is not in place or properly soldered to the circuit board or if UCC27712-Q1
is in an unbiased state.
9.2.2.9 Operation With IGBT's
The UCC27712-Q1 is well suited for driving IGBT's in various applications including motor drive and inverters.
The design procedure is as the previous MOSFET example but the VDD voltage is typically 15-V to drive IGBT
devices. Use the power transistor parameters and application specifications to determine the detail design and
component values. See Figure 46 below for a typical IGBT application.
Bias
RBIAS
RBOOT
DBOOT
HV
CVDD
3
VDD
HB
8
HO
7
HS
6
ROFF
2 HI
CBOOT
CHI
1
PWM2
LI
ROFF
CLI
GND
Q1
RON
RHI
PWM1
RLI
DGATE
RGS
Q2
RON
LO
SW
DGATE
5
RGS
COM
4
Copyright © 2017, Texas Instruments Incorporated
Figure 46. Typical IGBT Application Schematic
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Refer to Figure 47 below for the UCC27712-Q1 driving 40-A, 650-V IGBT's in a high voltage sync buck
configuration. The input voltage is 400 V, output 100 V with a 150-W output load. Channel 1 is the inductor
current, Channel 2 is high-side IGBT VGE, Channel 3 is low-side IGBT VGE, and Channel 4 is the switch node
or HS voltage.
IL
HS
GH
GL
Figure 47. IGBT Sync-Buck Operating at 400 V and 150 W
32
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9.2.3 Application Curves
Figure 48 and Figure 49 show the measured LI to LO turn-on and turn-off delay of one UCC27712-Q1 device.
Channel 3 depicts LI and Channel 4 LO.
Figure 48. LI to LO Turn-On Propagation Delay
Figure 49. LI to LO Turn-Off Propagation Delay
Figure 50 and Figure 51 show the measured HI to HO turn-on and turn-off delay of one UCC27712-Q1 device.
Channel 1 depicts HI and Channel 2 HO.
Figure 50. HI to HO Turn-On Propagation Delay
Figure 51. HI to HO Turn-Off Propagation Delay
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IL
HS
GH
GL
Figure 52. MOSFET Sync-Buck Operating at 400 V and 150 W
Figure 52 shows UCC27712-Q1 operating in a high voltage sync-buck. Channel 1 depicts inductor current,
Channel 2 high side MOSFET VGS, Channel 3 low side MOSFET VGS, and Channel 4 high voltage switch
node.
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10 Power Supply Recommendations
The VDD power terminal for the device requires the placement of an energy storage capacitor, because of
UCC27712-Q1 is 1.8-A, peak-current driver. And requires the placement of low-esr noise-decoupling capacitance
as directly as possible from the VDD terminal to the COM terminal, ceramic capacitors with stable dielectric
characteristics over temperature are recommended, such as X7R or better.
The recommended storage capacitor is an X7R, 50-V capacitor. The recommended decoupling capacitors
are a 1-µF 0805-sized 50-V X7R capacitor, ideally with (but not essential) a second smaller parallel 100-nF
0603-sized 50-V X7R capacitor.
Similarly, a low-esr X7R capacitance is recommended for the HB-HS power terminals which must be placed
as close as possible to device pins.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Locate UCC27712-Q1 as close as possible to the MOSFETs in order to minimize the length of high-current
traces between the HO/LO and the Gate of MOSFETs, as well as the return current path to the driver HS and
COM.
A resistor in series with bias supply and VDD pin is recommended.
Locate the VDD capacitor (CVDD) and VHB capacitor (CBOOT) as close as possible to the pins of
UCC27712-Q1.
A 2-Ω to 20-Ω resistor series with bootstrap diode is recommended to limit bootstrap current.
A RC filter with 10 Ω to 100 Ω and 10 pF to 220 pF for HI/LI is recommended.
Separate power traces and signal traces, such as output and input signals.
Maintain as much separation as possible from the from the low voltage pins and floating drive HB, HO and
HS pins.
Ensure there is not high switching current flowing in the control ground (input signal reference) from the
power train ground.
11.2 Layout Example
Figure 53. UCC27712-Q1 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
User Guide, Using the UCC27712EVM-287, (SLUUBO1)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC27712-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC27712QDQ1
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27712Q
UCC27712QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27712Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Aug-2017
OTHER QUALIFIED VERSIONS OF UCC27712-Q1 :
• Catalog: UCC27712
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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