Texas Instruments | CSD87351ZQ5D Synchronous Buck NexFET™ Power Block (Rev. A) | Datasheet | Texas Instruments CSD87351ZQ5D Synchronous Buck NexFET™ Power Block (Rev. A) Datasheet

Texas Instruments CSD87351ZQ5D Synchronous Buck NexFET™ Power Block (Rev. A) Datasheet
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CSD87351ZQ5D
SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
CSD87351ZQ5D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The CSD87351ZQ5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 5-mm × 6-mm outline.
Optimized for 5-V gate drive applications, this product
offers a flexible solution capable of offering a highdensity power supply when paired with any 5-V gate
drive from an external controller/driver.
Half-Bridge Power Block
90% System Efficiency at 20 A
Up to 32-A Operation
High-Frequency Operation (up to 1.5 MHz)
High-Density SON 5-mm × 6-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Improved ESD Protection
Top View
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
2 Applications
•
•
•
•
BG
P0116-01
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
Device Information(1)
DEVICE
MEDIA
CSD87351ZQ5D
13-Inch Reel
QTY
PACKAGE
SHIP
2500
SON
5.00-mm × 6.00-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Power Block Efficiency
and Power Loss
Efficiency (%)
Typical Circuit
95
6
92
5
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
89
86
83
4
3
2
80
77
Power Loss (W)
1
1
0
5
10
15
Output Current (A)
20
25
0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87351ZQ5D
SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Power Block Performance ........................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 10
6.1 Application Information............................................ 10
6.2 Typical Application .................................................. 13
7
Layout ................................................................... 15
7.1 Layout Guidelines ................................................... 15
7.2 Layout Example ...................................................... 16
8
Device and Documentation Support.................. 17
8.1
8.2
8.3
8.4
8.5
9
Receiving Notification of Documentation Updates.. 17
Community Resources............................................ 17
Trademarks ............................................................. 17
Electrostatic Discharge Caution .............................. 17
Glossary .................................................................. 17
Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1
9.2
9.3
9.4
Q5D Package Dimensions......................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
Q5D Tape and Reel Information .............................
18
19
19
20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2012) to Revision A
Page
•
Added note 2 to the Absolute Maximum Ratings table .......................................................................................................... 3
•
Changed Recommended PCB Design Overview section to Layout section ........................................................................ 15
•
Added the Device and Documentation Support section....................................................................................................... 17
•
Changed Mechanical Data section to Mechanical, Packaging, and Orderable Information section.................................... 18
2
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SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
PARAMETER
CONDITIONS
Voltage
MIN
MAX
VIN to PGND
–0.8
30
TG to TGR
–0.8
10
–8
10
BG to PGND
IDM
Pulsed current rating (2)
PD
Power dissipation
UNIT
V
96
A
12
W
Sync FET, ID = 87 A, L = 0.1 mH
378
Control FET, ID = 44 A, L = 0.1 mH
87
EAS
Avalanche energy
TJ
Operating junction
–55
150
°C
TSTG
Storage temperature
–55
150
°C
(1)
(2)
mJ
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µs. Duty cycle ≤ 0.01%.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
PARAMETER
VGS
Gate drive voltage
VIN
Input supply voltage
ƒSW
Switching frequency
CONDITIONS
MIN
4.5
UNIT
8
V
27
CBST = 0.1 μF (min)
200
Operating current
TJ
MAX
Operating temperature
1500
V
kHz
32
A
125
°C
5.3 Power Block Performance
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
PLOSS
Power loss (1)
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 20 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25°C
IQVIN
VIN quiescent current
TG to TGR = 0 V
BG to PGND = 0 V
(1)
MIN
TYP
MAX
UNIT
2.5
W
10
µA
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5 V driver IC.
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
Junction-to-ambient thermal resistance (min Cu)
(1) (2)
Junction-to-ambient thermal resistance (max Cu) (1) (2)
MIN
TYP
MAX
119
62
Junction-to-case thermal resistance (top of package) (2)
25
Junction-to-case thermal resistance (PGND pin) (2)
2.3
UNIT
°C/W
°C/W
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
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5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
Q1 Control FET
TEST CONDITIONS
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-source leakage
current
30
30
V
VGS = 0 V, VDS = 24 V
IGSS
Gate-to-source leakage
current
VDS = 0 V, VGS = +10 / –8
VGS(th)
Gate-to-source threshold
voltage
VDS = VGS, IDS = 250 μA
ZDS(on) (1)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 20 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH,
7.4
1.6
mΩ
gfs
Transconductance
VDS = 15 V, IDS = 20 A
75
142
S
1
1
μA
100
100
nA
1.15
V
1.0
2.1
0.75
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
966
1255
2410
3133
pF
382
497
1130
1469
CRSS
Reverse transfer
capacitance
pF
19
25
45
59
pF
RG
Qg
Series gate resistance
0.9
1.8
1
2
Ω
Gate charge total (4.5 V)
5.9
7.7
17
22
nC
Qgd
Gate charge gate-to-drain
1.1
3.1
nC
Qgs
VDS = 15 V,
Gate charge gate-to-source IDS = 20 A
2.1
3.7
nC
Qg(th)
Gate charge at Vth
1.1
2
nC
QOSS
Output charge
6.5
23
nC
td(on)
Turnon delay time
6.1
7.7
ns
tr
Rise time
16
10
ns
td(off)
Turnoff delay time
10
31
ns
tf
Fall time
2.1
4.2
ns
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
VDS = 9.8 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
(1)
IDS = 20 A, VGS = 0 V
0.86
Vdd = 9.8 V, IF = 20 A,
di/dt = 300 A/μs
8.6
1
0.78
23
1
nC
V
16
24
ns
Equivalent system performance based on application testing. See Application and Implementation section for details.
HD
LD
HD
LG
HG
5x6 QFN TTA MIN Rev1
5x6 QFN TTA MIN Rev1
Max RθJA = 62°C/W
when mounted on
1 in2 (6.45 cm2) of 2oz (0.071-mm) thick
Cu.
LD
Max RθJA = 119°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
HS
LG
LS
HG
HS
LS
M0189-01
M0190-01
4
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5.6 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise
10
1.6
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
Power Loss (W)
8
7
6
5
4
3
1.3
1.2
1.1
1
0.9
0.8
1
0.7
0
5
10
15
20
Output Current (A)
25
30
0.6
−50
35
Figure 1. Power Loss vs Output Current
40
35
35
30
30
25
20
400LFM
200LFM
100LFM
Nat Conv
15
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
10
5
0
0
10
20
70
25
50
75
100
Junction Temperature (ºC)
125
150
20
90
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
400LFM
200LFM
100LFM
Nat Conv
15
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
10
80
0
25
5
30
40
50
60
Ambient Temperature (ºC)
−25
Figure 2. Normalized Power Loss vs Temperature
40
Output Current (A)
Output Current (A)
1.4
2
0
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
1.5
Power Loss, Normalized
9
0
0
10
20
30
40
50
60
Ambient Temperature (ºC)
70
80
90
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
40
35
Output Current (A)
30
25
20
15
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
10
5
0
0
20
40
60
80
100
Board Temperature (ºC)
120
140
Figure 5. Typical Safe Operating Area(1)
(1)
The typical power block system characteristic curves are based on measurements made on a PCB design with
dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and
Implementation section for detailed explanation.
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Typical Power Block Device Characteristics (continued)
1.3
1.6
14.5
12.1
1.5
12.1
9.7
1.4
9.7
1.3
7.2
1.2
4.8
1.1
2.4
7.2
1.2
4.8
1.1
2.4
1
0.0
1
0.9
−2.4
0.8
−4.8
0.7
−7.2
0.7
−9.7
500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
0.6
0.6
200
350
0.0
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
IOUT = 35A
0.9
0.8
3
Figure 6. Normalized Power Loss vs Switching Frequency
Power Loss, Normalized
1.4
1.3
1.6
12.1
1.5
9.7
1.4
7.3
1.2
4.8
1.1
2.4
1
0
0.9
−2.4
0.8
−4.8
0.7
0.6
0.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
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−7.2
9
11
13
15
Input Voltage (V)
17
19
21
23
−9.7
14.5
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
IOUT = 35A
1.3
12.1
9.7
7.2
1.2
4.8
1.1
2.4
1
0
0.9
−2.4
0.8
−4.8
−7.3
0.7
−7.2
−9.7
0.6
Figure 8. Normalized Power Loss vs Output Voltage
6
Power Loss, Normalized
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 0.3µH
IOUT = 35A
1.5
7
−4.8
Figure 7. Normalized Power Loss vs Input Voltage
14.5
SOA Temperature Adj (ºC)
1.6
5
−2.4
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
SOA Temperature Adj (ºC)
Power Loss, Normalized
1.4
14.5
Power Loss, Normalized
VIN = 12V
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
IOUT = 35A
1.5
SOA Temperature Adj (ºC)
1.6
SOA Temperature Adj (ºC)
TJ = 125°C, unless stated otherwise
−9.7
1.1
Figure 9. Normalized Power Loss vs Output Inductance
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5.7 Typical Power Block MOSFET Characteristics
80
80
70
70
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
TA = 25°C, unless stated otherwise
60
50
40
30
20
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
60
50
40
30
20
0
0.8
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
10
0
0.05
VDS - Drain-to-Source Voltage - V
Figure 10. Control MOSFET Saturation
0.25
0.3
VDS = 5V
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
0.2
100
VDS = 5V
10
1
0.1
0.01
TC = 125°C
TC = 25°C
TC = −55°C
0.001
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
3
10
1
0.1
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
0
Figure 12. Control MOSFET Transfer
0.5
1
1.5
2
VGS - Gate-to-Source Voltage - V
2.5
Figure 13. Sync MOSFET Transfer
8
8
ID = 20A
VDD = 15V
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.15
Figure 11. Sync MOSFET Saturation
100
6
5
4
3
2
1
0
0.1
VDS - Drain-to-Source Voltage - V
0
2
4
6
8
Qg - Gate Charge - nC (nC)
Figure 14. Control MOSFET Gate Charge
Copyright © 2012–2017, Texas Instruments Incorporated
10
ID = 20A
VDD = 15V
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
Qg - Gate Charge - nC (nC)
Figure 15. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
10
10
1
1
C − Capacitance − nF
C − Capacitance − nF
TA = 25°C, unless stated otherwise
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.001
0
5
10
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
15
20
25
30
0.001
0
5
10
VDS - Drain-to-Source Voltage - V
f = 1MHz
VGS = 0V
15
20
25
Figure 16. Control MOSFET Capacitance
Figure 17. Sync MOSFET Capacitance
2
1.6
1.8
ID = 250µA
VGS(th) - Threshold Voltage - V
VGS(th) - Threshold Voltage - V
ID = 250µA
1.6
1.4
1.2
1
0.8
0.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0.4
−75
−50
−25
0
25
50
75
100
125
150
0
−75
175
−50
−25
TC - Case Temperature - ºC
Figure 18. Control MOSFET VGS(th)
50
75
100
125
150
175
Figure 19. Sync MOSFET VGS(th)
25
20
15
10
5
TC = 125°C
TC = 25ºC
0
1
2
3
4
5
6
7
8
9
VGS - Gate-to- Source Voltage - V
Figure 20. Control MOSFET RDS(on) vs VGS
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RDS(on) - On-State Resistance - mΩ
RDS(on) - On-State Resistance - mΩ
25
10
ID = 20A
8
0
TC - Case Temperature - ºC
30
0
30
VDS - Drain-to-Source Voltage - V
ID = 20A
9
8
7
6
5
4
3
2
TC = 125°C
TC = 25ºC
1
0
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to- Source Voltage - V
Figure 21. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise
1.8
1.8
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
−50
−25
0
25
50
75
100
125
150
ID = 20A
VGS = 8V
1.6
Normalized On-State Resistance
ID = 20A
VGS = 8V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
175
−50
−25
TC - Case Temperature - ºC
Figure 22. Control MOSFET Normalized RDS(on)
ISD − Source-to-Drain Current - A
ISD − Source-to-Drain Current - A
50
75
100
125
150
175
100
10
1
0.1
0.01
0.001
TC = 125°C
TC = 25°C
0
0.2
0.4
0.6
0.8
1
10
1
0.1
0.01
0.001
0.0001
TC = 125°C
TC = 25°C
0
VSD − Source-to-Drain Voltage - V
Figure 24. Control MOSFET Body Diode
0.4
0.6
0.8
1
Figure 25. Sync MOSFET Body Diode
I(AV) - Peak Avalanche Current - A
1000
100
10
TC = 25°C
TC = 125°C
1
0.01
0.2
VSD − Source-to-Drain Voltage - V
1000
I(AV) - Peak Avalanche Current - A
25
Figure 23. Sync MOSFET Normalized RDS(on)
100
0.0001
0
TC - Case Temperature - ºC
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 26. Control MOSFET Unclamped Inductive Switching
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100
10
TC = 25°C
TC = 125°C
1
0.01
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 27. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Figure 28. Equivalent System Schematic
The CSD87351ZQ5D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
10
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Application Information (continued)
Figure 29. Elimination of Parasitic Inductances
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87351ZQ5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87351ZQ5D clearly highlights the importance of considering the effective AC on-impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
96
6
94
5
4.5
90
Power Loss (W)
Efficiency (%)
92
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
88
86
84
2
6
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
4
3.5
3
2.5
2
1.5
PowerBlock HS/LS RDS(ON) = 7.4mΩ/2.6mΩ
Discrete HS/LS RDS(ON) = 7.4mΩ/2.6mΩ
Discrete HS/LS RDS(ON) = 7.4mΩ/1.6mΩ
82
80
PowerBlock HS/LS RDS(ON) = 7.4mΩ/2.6mΩ
Discrete HS/LS RDS(ON) = 7.4mΩ/2.6mΩ
Discrete HS/LS RDS(ON) = 7.4mΩ/1.6mΩ
5.5
10
14
18
Output Current (A)
Figure 30. Efficiency
Copyright © 2012–2017, Texas Instruments Incorporated
22
1
0.5
26
0
0
5
10
15
20
Output Current (A)
25
30
Figure 31. Power Loss
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Application Information (continued)
The chart below compares the traditional DC measured RDS(ON) of CSD87351ZQ5D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87351ZQ5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
PARAMETER
HS
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
7.4
—
1.6
—
DC measured RDS(ON) (VGS = 4.5 V)
7.4
8.8
2.6
3.1
The CSD87351ZQ5D NexFET™ power block is an optimized design for synchronous buck applications using 5V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87351ZQ5D as a function of load current. This
curve is measured by configuring and running the CSD87351ZQ5D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87351ZQ5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
Power loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
The SOA curves in the CSD87351ZQ5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.1.4 Normalized Curves
The normalized curves in the CSD87351ZQ5D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
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6.2 Typical Application
Figure 32. Typical Application
6.2.1 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
6.2.1.1 Design Example
Operating conditions:
• Output current = 25 A
• Input voltage = 7 V
• Output voltage = 1 V
• Switching frequency = 800 kHz
• Inductor = 0.2 µH
6.2.1.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 25 A = 3.5 W (Figure 1)
Normalized power loss for input voltage ≈ 1.07 (Figure 7)
Normalized power loss for output voltage ≈ 0.95 (Figure 8)
Normalized power loss for switching frequency ≈ 1.11 (Figure 6)
Normalized power loss for output inductor ≈ 1.07 (Figure 9)
Final calculated power loss = 3.5 W × 1.07 × 0.95 × 1.11 × 1.07 ≈ 4.23 W
6.2.1.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 2°C (Figure 7)
SOA adjustment for output voltage ≈ –1.3°C (Figure 8)
SOA adjustment for switching frequency ≈ 2.8°C (Figure 6)
SOA adjustment for output inductor ≈ 1.6°C (Figure 9)
Final calculated SOA adjustment = 2 + (–1.3) + 2.8 + 1.6 ≈ 5.1°C
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Typical Application (continued)
In the design example above, the estimated power loss of the CSD87351ZQ5D would increase to 4.23 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1°C. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.1°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
50
45
Output Current (A)
40
35
30
1
25
20
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3 mH
15
10
5
2
3
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
G028
Figure 33. Power Block SOA
14
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7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8
should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, and so on). The bootstrap
capacitor for the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to reduce the peak ring
level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the output
characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from
0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Refer to Snubber Circuits: Theory , Design and
Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber
should be placed as close as possible to the Vsw node and PGND, see Figure 34. (1)
7.1.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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CSD87351ZQ5D
SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
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7.2 Layout Example
Figure 34. Recommended PCB Layout (Top Down View)
16
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SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD87351ZQ5D
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www.ti.com
9 Mechanical, Packaging, and Orderable Information
9.1 Q5D Package Dimensions
E2
K
d2
c1
d1
L
4
5
4
q
5
E1
L
6
3
6
3
b
9
D2
2
7
7
D1
2
E
e
8
1
8
1
d
d3
f
Top View
Bottom View
Side View
Pinout
Position
Exposed Tie Bar May Vary
q
a
c
E1
Front View
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
M0187-01
DIM
INCHES
MAX
MIN
MAX
a
1.400
1.500
0.055
0.059
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
1.630
1.730
0.064
0.068
d1
0.280
0.380
0.011
0.015
d2
0.200
0.300
0.008
0.012
d3
0.291
0.391
0.012
0.015
D1
4.900
5.100
0.193
0.201
D2
4.269
4.369
0.168
0.172
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.106
3.206
0.122
0.126
e
1.270 TYP
0.050
f
0.396
0.496
0.016
0.020
L
0.510
0.710
0.020
0.028
θ
0.000
—
—
K
18
MILLIMETERS
MIN
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0.812
—
0.032
Copyright © 2012–2017, Texas Instruments Incorporated
CSD87351ZQ5D
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SLPS426A – DECEMBER 2012 – REVISED FEBRUARY 2017
9.2 Land Pattern Recommendation
3.480 (0.137)
0.530 (0.021)
0.415 (0.016)
0.345 (0.014)
0.650 (0.026)
5
4
0.650 (0.026)
4.460
(0.176)
0.620
(0.024)
0.620 (0.024)
4.460
(0.176)
1.270
(0.050)
1
1.920
(0.076)
8
0.850 (0.033)
0.400 (0.016)
0.850 (0.033)
6.240 (0.246)
M0188-01
NOTE: Dimensions are in mm (in).
9.3 Stencil Recommendation
0.250 (0.010)
0.300 (0.012)
0.610 (0.024)
0.341 (0.013)
5
4
0.410 (0.016)
Stencil Opening
0.300 (0.012)
0.300 (0.012)
1.710
(0.067)
8
1
1.680
(0.066)
0.950 (0.037)
1.290 (0.051)
PCB Pattern
M0208-01
NOTE: Dimensions are in mm (in).
For recommended circuit layout for PCB designs, see application note Reducing Ringing Through PCB Layout
Techniques (SLPA005).
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CSD87351ZQ5D
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9.4 Q5D Tape and Reel Information
4.00 ±0.10 (See Note 1)
K0
0.30 ±0.05
+0.10
2.00 ±0.05
Ø 1.50 –0.00
1.75 ±0.10
5.50 ±0.05
12.00 ±0.30
B0
R 0.20 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 5.30 ±0.10
B0 = 6.50 ±0.10
K0 = 1.90 ±0.10
M0191-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF reflow compatible.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD87351ZQ5D
ACTIVE
Package Type Package Pins Package
Drawing
Qty
LSON-CLIP
DQY
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
87351ZD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CSD87351ZQ5D
LSONCLIP
DQY
8
2500
330.0
12.4
5.3
6.3
1.8
8.0
12.0
Q2
CSD87351ZQ5D
LSONCLIP
DQY
8
2500
330.0
15.4
5.3
6.3
1.2
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD87351ZQ5D
LSON-CLIP
DQY
8
2500
367.0
367.0
35.0
CSD87351ZQ5D
LSON-CLIP
DQY
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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